WO2020173175A1 - 一种时间戳的修正方法、时钟同步方法及系统 - Google Patents

一种时间戳的修正方法、时钟同步方法及系统 Download PDF

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WO2020173175A1
WO2020173175A1 PCT/CN2019/124995 CN2019124995W WO2020173175A1 WO 2020173175 A1 WO2020173175 A1 WO 2020173175A1 CN 2019124995 W CN2019124995 W CN 2019124995W WO 2020173175 A1 WO2020173175 A1 WO 2020173175A1
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clock
information
time stamp
processor
clock information
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PCT/CN2019/124995
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English (en)
French (fr)
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许雷
魏明
张博
方继通
李剑峰
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烽火通信科技股份有限公司
武汉飞思灵微电子技术有限公司
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Publication of WO2020173175A1 publication Critical patent/WO2020173175A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements

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  • the present invention relates to the field of communication technology, in particular to a method for correcting a time stamp, a method and a system for clock synchronization.
  • Telecom operators have a strong demand for 5G commercialization in 2020.
  • the Optical Internet Forum OIF
  • International Telecommunication Union ITU
  • the international telecommunications organization successively released flexible Ethernet (Flexible Ethernet, FlexE), flexible optical transport network (Flexible Optical Transport Network, FlexO), optical transport unit (Optical Transport Unit, OTU), etc. for 5G bearer networks.
  • Flexible Ethernet Flexible Ethernet
  • FlexO flexible optical transport network
  • OTU optical transport unit
  • 5G bearer networks 100G transmission standard.
  • the IEEE1588 protocol is a precision time protocol (Precision Time Protocol, PTP), based on the pairing of PTP messages and timestamps.
  • PTP Precision Time Protocol
  • the frequency and phase of the clock are adjusted to achieve clock synchronization between different devices.
  • factors such as transmission of data frames on each physical layer channel, insertion and deletion of alignment markers (Alignment Marker, AM), and cross-clock domains can cause frame header jitter.
  • the period at which the transmitter inserts or deletes the AM codeword in the FlexE physical layer channel is not an integer multiple of the FlexE frame period, which results in ⁇ 12ns jitter in the frame header of the FlexE frame at the receiver, which seriously affects the clock synchronization accuracy.
  • the purpose of the embodiments of the present invention is to provide a time stamp correction method, clock synchronization method and system, which can improve the accuracy of the time stamp.
  • an embodiment of the present invention provides a method for correcting a time stamp, which includes:
  • the clock information is the duration or the number of clock cycles
  • the time stamp of the frame header of the current data frame is shifted in the opposite direction of the deviation to obtain a revised time stamp, where N>1, and the amount of time offset It is obtained by counting multiple clock information.
  • the method further includes: when the difference between the current clock information and the average value of the previous N clock information exceeds a threshold range, the first N Each clock information is set as the initial average value.
  • the first N clock information is stored in a pre-created queue in a recording order.
  • an embodiment of the present invention provides a clock synchronization method, which includes:
  • the multiple physical layer channels of the first processor send and receive data frames carrying synchronization information and response information, and record the time stamp of the frame header of the data frame and the clock information between adjacent frame headers;
  • the second processor uses the time stamp correction method as described in the first aspect to modify the time stamp of the frame header of the data frame to obtain a modified time stamp; generate the response information; and generate the response information according to the modified time stamp and
  • the synchronization information and its response information perform clock adjustment.
  • the synchronization information and its response information are transmitted between the first processor and the second processor through data packets.
  • an embodiment of the present invention provides a time stamp correction system, which includes:
  • the detection module is used to record the time stamp of the frame header of the data frame received by the physical layer channel and the clock information between adjacent frame headers, where the clock information is the duration or the number of clock cycles;
  • a correction module which is used to shift the time stamp of the current data frame header to the opposite direction of the deviation if the current clock information deviates from the average value of the previous N clock information to obtain a revised time stamp, where N>1, And the amount of time offset is obtained by counting multiple clock information.
  • the correction module is further configured to: when the difference between the current clock information and the average value of the previous N clock information exceeds a threshold range, the previous The N clock information are all set as the initial average value.
  • the first N clock information is stored in a pre-created queue in a recording order.
  • an embodiment of the present invention provides a clock synchronization system.
  • the system includes a first processor and a second processor. Multiple physical layer channels of the first processor transmit and receive data frames that carry synchronization information and response information. ;
  • the first processor is configured to record the time stamp of the frame header of the data frame and the clock information between adjacent frame headers;
  • the second processor is configured to use the time stamp correction method as described in the first aspect to modify the time stamp of the frame header of the data frame to obtain the modified time stamp; also to generate the response information; and The modified time stamp and the synchronization information and its response information are clocked.
  • the synchronization information and its response information are transmitted between the first processor and the second processor through data packets.
  • the embodiment of the present invention provides a method for correcting the time stamp, recording the time stamp of the frame header of the data frame received by the physical layer channel and the clock information between adjacent frame headers.
  • the clock information is the duration or the number of clock cycles. ; If the current clock information deviates from the average value of the previous N clock information, the time stamp of the frame header of the current data frame is shifted in the opposite direction of the deviation to obtain a revised time stamp, where N>1, and the offset time The quantity is obtained by counting multiple clock information.
  • the method for correcting the time stamp in the embodiment of the present invention can improve the accuracy of the time stamp.
  • FIG. 1 is a flowchart of a method for correcting a time stamp according to an embodiment of the present invention
  • FIG. 2 is a schematic diagram of a system for correcting time stamps according to an embodiment of the present invention
  • FIG. 3 is a flowchart of a clock synchronization method according to an embodiment of the present invention.
  • FIG. 4 is a schematic diagram of a clock synchronization system according to an embodiment of the present invention.
  • Figure 5 is a schematic diagram of the frame structure of an Ethernet data packet
  • FIG. 6 is a flowchart of extracting PTP messages in a clock synchronization method according to an embodiment of the present invention
  • Fig. 7 is a flowchart of inserting a PTP message in a clock synchronization method according to an embodiment of the present invention.
  • an embodiment of the present invention provides a method for correcting a time stamp, and the method for correcting a time stamp includes:
  • S110 records the time stamp of the frame header of the data frame received by the physical layer channel and the number of clock cycles between adjacent frame headers.
  • the number of N clock cycles before the current number of clock cycles are stored in a pre-created queue in the order of recording, where N>1 , and N is a positive integer .
  • S120 calculates the average value of the previous N clock cycles, and the average value of the previous N clock cycles is M ave .
  • step S130 judges whether the current number of clock cycles deviates from the average value, if yes, go to step S140; if not, go to step S150.
  • the current number of clock cycles is the number of clock cycles between the frame header of the current data frame and the previous data frame, namely M N+1
  • the current number of clock cycles is the number of recorded N+1th clock cycles
  • the average of the number of the first N clock cycles is the estimated number of N+1 clock cycles.
  • the time stamp of the frame header of the current data frame is shifted to the opposite direction of the deviation to obtain the corrected time stamp, which is used as the time stamp of the frame header of the current data frame.
  • the time stamp of the header of the current data frame is t N+1
  • the modified time stamp t c_N+1 t N+1 - ⁇ t, where ⁇ t is the amount of time offset.
  • the modified time stamp t c_N+1 t N+1 + ⁇ t, ⁇ t is the amount of time offset.
  • the standard deviation obtained by the statistics is an integer.
  • the clock period T is the length of each clock period T.
  • S150 saves the time stamp of the header of the current data frame, removes the data at the head of the queue, adds the current number of clock cycles to the tail of the queue, and returns to step S110.
  • the frame header of the data frame is smoothed to improve the accuracy of the time stamp.
  • N the closer the average M ave of the number of previous N clock cycles to the theoretical value obtained by counting the number of multiple clock cycles, the better the smoothing effect, but the pre-created queue and The greater the resource consumption such as the adder used to find M ave . You can make a trade-off between smoothing performance and resource consumption according to actual needs.
  • the time stamp correction method includes:
  • S200 stores the initial average value of the number of N clock cycles in the queue.
  • counting the number of multiple clock cycles can obtain the threshold range of the number of clock cycles and the initial average value.
  • S210 records the time stamp of the frame header of the data frame received by the physical layer channel and the number of clock cycles between adjacent frame headers.
  • Step S210 is the same as step S110 and will not be repeated here.
  • S220 calculates the average of the number of N clock cycles, where N>1, the current number of clock cycles is the number of clock cycles between the frame header of the current data frame and the previous data frame.
  • Step S220 is the same as step S120, and will not be repeated here.
  • step S230 it is judged whether the difference between the current number of clock cycles and the average value exceeds the threshold range, if yes, return to step S200; if not, proceed to step S240.
  • the previous N clock cycles are all set to the initial average value to avoid the influence of the failure of the receiving end of the data frame on the time stamp.
  • step S240 it is judged whether the current number of clock cycles deviates from the average value, if yes, go to step S250; if not, go to step S260.
  • Step S240 is the same as step S130, and will not be repeated here.
  • S250 shifts the time stamp of the current data frame header to the opposite direction of the deviation to obtain the corrected time stamp, which is used as the time stamp of the current data frame header.
  • Step S250 is the same as step S140, and will not be repeated here.
  • S260 saves the time stamp of the header of the current data frame, removes the data at the head of the queue, and adds the current number of clock cycles to the tail of the queue.
  • Step S260 is the same as step S150 and will not be repeated here.
  • This embodiment provides a method for modifying the time stamp, recording the time stamp of the data frame header received by the physical layer channel and the clock information between adjacent frame headers.
  • the clock information is the duration or the number of clock cycles; if the current clock information deviates from the previous
  • the average value of N clock information shifts the time stamp of the current data frame header to the opposite direction of the deviation to obtain a modified time stamp, where N>1 and the amount of time offset is performed on multiple clock information Statistics. If the current clock information is equal to the average value of the previous N clock information, the time stamp of the header of the current data frame does not need to be modified.
  • the frame header is smoothed, which can improve the accuracy of the time stamp.
  • an embodiment of the present invention also provides a time stamp correction system, which is used to implement the time stamp correction method of the foregoing embodiment.
  • the time stamp correction system includes a detection module 110 a and a correction module 210 a.
  • the detection module 110a is used to record the time stamp of the frame header of the data frame received by the physical layer channel and the clock information between adjacent frame headers.
  • the clock information is the duration or the number of clock cycles.
  • the first N clock information is stored in a pre-created queue in the order of recording.
  • the correction module 210a is used to if the current clock information deviates from the average value of the previous N clock information, shift the time stamp of the frame header of the current data frame to the opposite direction of the deviation to obtain the revised time stamp, where N>1, and The amount of time offset is obtained by counting multiple clock information.
  • the correction module 210a is also used to set the first N clock information as the initial average value when the current clock information deviates from the average value of the previous N clock information and exceeds the threshold value range, and the threshold value range and the initial average value are multiple The clock information is calculated.
  • an embodiment of the present invention also provides a clock synchronization method, and the clock synchronization method includes:
  • the multiple physical layer channels of the first processor receive the data frame carrying synchronization information, and record the time stamp of the frame header of the data frame and the clock information between adjacent frame headers.
  • the second processor uses the time stamp correction method of the foregoing embodiment to modify the time stamp of the frame header of the data frame to obtain the modified time stamp.
  • the time stamp of the header of the data frame after the correction process is used as the time stamp of the header of the data frame.
  • the second processor generates response information and sends it to the first processor.
  • the first processor inserts the response information into the data frame and sends it out.
  • the second processor adjusts the clock according to the modified time stamp and synchronization information and its response information.
  • Steps S330 and S340 and step S350 can be performed at the same time or sequentially, and are not limited.
  • the synchronization information and its response information are transmitted between the first processor and the second processor through data packets.
  • Both the first processor and the second processor may be independent integrated circuit chips, for example, a digital signal processor (Digital Signal Processing, DSP), an application specific integrated circuit (ASIC), and a ready-made programmable gate array ( Field-Programmable Gate Array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.
  • the first processor and the second processor transmit data packets carrying synchronization information and its response information through a Serial Gigabit Media Independent Interface (SGMII) interface.
  • SGMII Serial Gigabit Media Independent Interface
  • the first processor and the second processor may also be integrated in the same integrated circuit chip.
  • the first processor extracts the synchronization information or the overhead containing the synchronization information from the header of the data frame received by each physical layer channel and caches it to a set amount, generates a packet request, and generates it according to the header of the data frame to be sent Send instructions synchronously.
  • the first processor encapsulates the buffered data into data packets according to the synchronous sending instruction and the packet grouping request, and then sends them to the second processor through the SGMII interface.
  • the first processor generates a synchronization transmission indication according to the overhead multiframe indication information of the data frame to be transmitted on the i-th physical layer channel, and uses a weighted round robin scheduling algorithm to schedule n synchronization transmission indications, 1 ⁇ i ⁇ n .
  • the first processor uses a weighted round-robin scheduling algorithm to schedule n packet grouping requests.
  • the second processor parses out the synchronization information from the received data packet, and sends a data packet carrying response information to the first processor.
  • the second processor encapsulates the response information according to the sending frequency of the synchronous sending instruction and the response information to obtain a data packet, and transmits it to the first processor through the SGMII interface.
  • the first processor extracts the response information from the data packet, and inserts the response information into the data frame to be sent according to the synchronous sending instruction.
  • the synchronization information may be a precise time protocol PTP message, which is not limited.
  • PTP messages include a synchronization message (Sync), a follow message (Follow_up), a delay request message (Delay_Req), and a delay response message (Delay_Resp).
  • the master clock periodically sends synchronization messages Sync. If it is in the two-step mode, it will then send a follow-up message Follow_Up, and announce the actual sending time T1 of the synchronization message Sync in the follow-up message Follow_Up message.
  • the actual sending time T1 of the message is included in the synchronization message Sync, and then the arrival time T2 of the synchronization message Sync is recorded from the clock, and the delay request message Delay_Req is sent from the clock at T3.
  • the master clock records the arrival time T4 of the delay request message Delay_Req, and sends the time T4 to the slave clock through the delay response message Delay_Resp.
  • the synchronization information may be a synchronization message Sync, and the response information is a delay request message Delay_Req; or, the synchronization information may be a delay request message Delay_Req, and the response information is a delay response message Delay_Resp.
  • the synchronization information and the response information are respectively a PTP message and a response PTP message.
  • the first processor when the 5G bearer network performs clock synchronization, 1) After receiving the PTP message, the first processor uniformly encapsulates the information in the overhead, the information in the overhead includes the PTP message, and at the same time, records the data frame header The time stamp and the clock information between the adjacent frame headers, and the encapsulated overhead, time stamp and clock information are sent to the second processor.
  • the second processor parses the PTP message, corrects the time stamp of the PTP message, and completes the clock frequency and phase adjustment functions.
  • Send out the response PTP message encapsulate the response PTP message uniformly, and send it to the first processor.
  • the first processor inserts it into the overhead according to the multi-frame field information and the PTP message sending frequency. The data frame is sent out.
  • the frame header is equalized, which can improve the accuracy of the time stamp, effectively suppress the impact of AM codewords or cross clock domains in FlexO and OTU on the jitter of the frame header, greatly improving
  • the clock synchronization accuracy is up to ⁇ 4ns, which meets the requirements of 5G bearer networks such as FlexE, FlexO, and OTU.
  • the embodiment of the present invention transmits PTP messages according to the synchronous transmission instruction, and transmits other message information at the PTP message transmission interval, which greatly improves the bandwidth utilization rate of the overhead; the PTP message transmission frequency can be accurately controlled without Causes bandwidth jitter in the data stream.
  • the PTP message can be flexibly configured, and even if a new standard is defined in the future, it can be expanded by modifying the second processor, which effectively improves the applicability of the chip and reduces the risk of filming.
  • an embodiment of the present invention also provides a clock synchronization system.
  • the clock synchronization system includes a first processor 100 and a second processor 200. Multiple physical layer channels of the first processor 100 transmit and receive synchronization information and carry synchronization information. The data frame of the response message.
  • the first processor 100 is used to record the time stamp of the frame header of the data frame and the clock information between adjacent frame headers.
  • the second processor 200 is configured to use the time stamp correction method of the foregoing embodiment to modify the time stamp of the frame header of the data frame to obtain a modified time stamp; also to generate response information; and according to the modified time stamp and synchronization information And its response information to adjust the clock.
  • the first processor 100 and the second processor 200 transmit synchronization information and its response information through data packets.
  • the first processor 100 includes a receiving side detection module 110b, an overhead extraction module 120, an encapsulation module 130, an analysis module 140, an overhead insertion module 150, and a frame header generation module 160.
  • the second processor includes a correction module 210b, an overhead analysis module 220, a PTP message analysis module 230, a clock adjustment module 240, a PTP message generation module 250, and an encapsulation module 260.
  • the receiving-side detection module 110b is used to record the time stamp of the frame header of the data frame received by the physical layer channel and the clock information between adjacent frame headers.
  • the clock information is the duration or the number of clock cycles.
  • the receiving side detection module 110b is used to detect the frame header characteristic code pattern from the data frame to obtain frame header information.
  • the frame header generating module 160 is configured to read the corresponding response message from the buffer according to the i-th channel of the sending side control signal, and insert it into the data frame to send out.
  • the frame header generating module 160 is used to generate the local FlexE/FlexO frame header and envelope information.
  • the overhead insertion module 150 is configured to generate a PTP message sending instruction according to the overhead multiframe indication information, and insert a response message of the PTP message into the overhead.
  • the overhead extraction unit 120 is configured to extract and buffer a set amount of overhead from the received data frame, and then generate a packet grouping request to realize unified cache control of the overhead.
  • the encapsulation unit 130 of the first processor is configured to encapsulate the overhead data packet into an overhead data packet according to the packet group request and the PTP message sending instruction and send it to the parsing unit of the second processor through the SGMII interface.
  • Multiple ports can time-division multiplex the same serial interface.
  • the overhead data packet is an Ethernet data packet
  • the frame format of the overhead data packet is shown in FIG. 5A.
  • the frame structure of FIG. 5A includes a preamble, destination address, source address, length, requested multi-frame number, status indication, starting multi-frame number, overhead payload and check code.
  • the source address is the PHY related information of the received data frame.
  • the status indication is the first designated identifier
  • the status indication is the second designated identifier
  • it means that the data packet is the extracted overhead data packet and multiframe information, and the multiframe information and buffer Up to the set amount of overhead data is assembled into data packets.
  • the encapsulation unit 130 of the first processor is also used to assemble the PTP message sending instruction into a PTP message sending instruction data packet, such as the Ethernet data packet of FIG. 5B.
  • the frame structure of FIG. 5B includes a preamble, a destination address, and a source address. , Length, request multi-frame number, status indication, padding byte and check code.
  • the parsing module 140 of the first processor is configured to receive a data packet from the encapsulation module 260, and use the destination address and request multiframe information in the data packet to analyze the response PTP packet.
  • the overhead insertion module 150 is configured to adopt a chain control method to perform buffer control on the received response message.
  • the parsing unit 220 of the second processor is configured to receive the overhead data packet and the PTP message transmission instruction data packet from the encapsulation unit 130 of the first processor, and extract the overhead and the PTP message transmission instruction from them.
  • the parsing unit 220 of the second processor extracts the PTP packet according to the destination address and the request multiframe number in the received data packet.
  • the PTP message parsing module 230 is configured to extract the PTP message from the overhead and send it to the clock adjustment module 240.
  • the correction module 210b is used to receive the time stamp of the frame header and the clock information between adjacent frame headers from the receiving side detection module 110b. If the current clock information deviates from the average value of the previous N clock information, the current data frame header The time stamp shifts in the opposite direction of the deviation, and the corrected time stamp is obtained and sent to, where N>1, and the amount of time offset is a clock adjustment module obtained by counting multiple clock information. Smooth the frame header of the received data frame to make the frame header evenly distributed and correct the time stamp.
  • the correction module 210b is also used to set the first N clock information as the initial average value when the current clock information deviates from the average value of the previous N clock information beyond the threshold value range, and the threshold value range and the initial average value are multiple The clock information is calculated.
  • the clock adjustment module 240 is configured to perform clock frequency and phase synchronization according to the timestamp of the PTP message and the data frame header, thereby achieving high-precision clock synchronization.
  • the frequency and phase of the local clock are adjusted.
  • the PTP message generating module 250 is configured to generate a response message according to the PTP message and the timestamp, and cache it.
  • the encapsulation module 260 of the second processor is configured to encapsulate the buffered response message into a data packet according to the PTP message sending instruction and the sending frequency of the PTP message, and then transmit it to the parsing module 140 of the first processor through the SGMII interface.
  • the data packet is an Ethernet data packet as shown in FIG. 5C.
  • the frame structure of FIG. 5C includes a preamble, destination address, source address, length, request multi-frame number, overhead payload, and check code.
  • the S400 first processor generates a PTP message sending instruction, including:
  • the overhead insertion module 150 of the first processor generates a PTP packet sending instruction according to the data frame multiframe instruction.
  • the encapsulation module 130 of the first processor uses a weighted round-robin scheduling algorithm to schedule n PTP packet transmission instructions.
  • the i-th receiving side detection module 110b of the first processor detects the frame header characteristic code pattern from the data frame.
  • the overhead extraction module 120 of the first processor extracts and caches a certain amount of overhead and generates a package request.
  • the packaging module 130 of the first processor uses a weighted round-robin scheduling algorithm to schedule n-way grouping requests.
  • the encapsulation module 130 of the first processor sends an instruction to encapsulate the data packet according to the packet group request and the PTP message.
  • the parsing module 220 of the second processor parses the data packet.
  • the PTP packet parsing module 230 of the second processor parses the PTP packet.
  • the clock adjustment module 240 of the second processor performs clock frequency and phase synchronization according to the PTP message and the time stamp.
  • the PTP message generating module 250 of the second processor generates a response message according to the PTP message and the timestamp, and caches it.
  • the encapsulation module 260 of the second processor encapsulates the PTP message into a data packet according to the PTP message transmission at least and the transmission frequency of the PTP message, and then transmits the PTP message to the analysis module of the first processor through the SGMII interface.
  • the parsing module 140 of the first processor parses the response message according to the destination address and the requested multiframe information in the data packet.
  • the overhead insertion module 150 of the first processor adopts a chain control method to perform buffer control on the received response message.
  • the S550 frame header generating module 160 reads the corresponding response message from the buffer according to the i-th transmission side control signal, and inserts it into the data frame and sends it out.

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Abstract

本发明公开了一种时间戳的修正方法、时钟同步方法及系统，涉及通信技术领域。时间戳的修正方法包括：记录物理层通道接收的数据帧帧头的时间戳以及相邻帧头之间的时钟信息，时钟信息为时长或者时钟周期数量；如果当前的时钟信息偏离前N个时钟信息的平均值，将当前数据帧帧头的时间戳向偏离的相反方向偏移，得到修正的时间戳，其中，N>1，且偏移的时间量是对多个时钟信息进行统计得到的。本发明可以提高时间戳的精度。

Description

一种时间戳的修正方法、时钟同步方法及系统 技术领域
本发明涉及通信技术领域，具体是涉及一种时间戳的修正方法、时钟同步方法及系统。
背景技术
电信运营商在2020年实现5G商用需求强烈，为了满足5G在带宽、监测和时钟同步等方面的新要求，光互联网论坛(Optical Internet Forum，OIF)、国际电信联盟(International Telecommunication Union，ITU)等国际电信组织于2016年底先后发布了灵活以太网(Flexible Ethernet，FlexE)、灵活光传送网(Flexible Optical Transport Network，FlexO)、光传输单元(Optical Transport Unit，OTU)等用于5G承载网络的超100G传输标准。
目前，这些国际标准都定义了用于承载IEEE1588协议的物理层通道(Physical Layer，PHY)，其中，IEEE1588协议是一种精确时间协议(Precision Time Protocal，PTP)，基于PTP报文以及时间戳对时钟的频率和相位进行调整，进而实现不同设备之间的时钟同步。但是，各物理层通道上数据帧的传输、对齐码字(Alignment Marker，AM)的插入与删除、以及跨时钟域等因素会引起帧头抖动。例如，发送端在FlexE的物理层通道中插入或删除AM码字的周期与FlexE的帧周期不是整数倍关系，导致接收端FlexE帧的帧头存在±12ns的抖动，严重影响时钟同步精度。
发明内容
针对现有技术中存在的缺陷，本发明实施例的目的在于提供一种时间戳的修正方法、时钟同步方法及系统，可以提高时间戳的精度。
第一方面，本发明实施例提供一种时间戳的修正方法，其包括：
记录物理层通道接收的数据帧帧头的时间戳以及相邻帧头之间的时钟信息，时钟信息为时长或者时钟周期数量；
如果当前的时钟信息偏离前N个时钟信息的平均值，将当前数据帧帧头的时间戳向偏离的相反方向偏移，得到修正的时间戳，其中，N>1，且偏移的时间量是对多个时钟信息进行统计得到的。
结合第一方面，在第一种可选的实现方式中，所述方法还包括：所述当前的时钟信息与前N个时钟信息的平均值的差值超出阈值范围时，将所述前N个时钟信息均设置为初始平均值。
结合第一方面，在第二种可选的实现方式中，所述前N个时钟信息按照记录顺序存储在预先创建的队列中。
结合第一方面，在第三种可选的实现方式中，所述时长为相邻帧头的所述时间戳之差；或者，所述时长＝所述时钟周期数量×时钟周期。
第二方面，本发明实施例提供一种时钟同步方法，其包括：
第一处理器的多个物理层通道收发携带同步信息及其响应信息的数据帧，并记录数据帧帧头的时间戳和相邻帧头之间的时钟信息；
第二处理器使用如第一方面所述的时间戳的修正方法对所述数据帧帧头的时间戳进行修正，得到修正的时间戳；生成所述响应信息；根据所述修正的时间戳和所述同步信息及其响应信息进行时钟调整。
结合第二方面，在第一种可选的实现方式中，所述第一处理器和所述第二处理器之间通过数据包传输所述同步信息及其响应信息。
第三方面，本发明实施例提供一种时间戳的修正系统，其包括：
检测模块，其用于记录物理层通道接收的数据帧帧头的时间戳以及相邻帧头之间的时钟信息，时钟信息为时长或者时钟周期数量；
修正模块，其用于如果当前的时钟信息偏离前N个时钟信息的平均值，将当前数据帧帧头的时间戳向偏离的相反方向偏移，得到修正的时间戳，其中，N>1，且偏移的时间量是对多个时钟信息进行统计得到的。
结合第三方面，在第一种可选的实现方式中，所述修正模块还用于所述当前的时钟信息与前N个时钟信息的平均值的差值超出阈值范围时，将所述前N个时钟信息均设置为初始平均值。
结合第三方面，在第二种可选的实现方式中，所述前N个时钟信息按照记录顺序存储在预先创建的队列中。
结合第三方面，在第三种可选的实现方式中，所述时长为相邻帧头的所述时间戳之差；或者，所述时长＝所述时钟周期数量×时钟周期。
第四方面，本发明实施例提供一种时钟同步系统，所述系统包括第一处理器和第二处理器，第一处理器的多个物理层通道收发携带同步信息及其响应信息的数据帧；
所述第一处理器用于记录所述数据帧帧头的时间戳以及相邻帧头之间的时钟信息；
所述第二处理器用于使用如第一方面所述的时间戳的修正方法对所述数据帧帧头的时间戳进行修正，得到修正的时间戳；还用于生成所述响应信息；以及根据所述修正的时间戳和所述同步信息及其响应信息进行时钟调整。
结合第四方面，在第一种可选的实现方式中，所述第一处理器和所述第二处理器之间通过数据包传输所述同步信息及其响应信息。
与现有技术相比，本发明实施例提供时间戳的修正方法，记录物理层通道接收的数据帧帧头的时间戳以及相邻帧头之间的时钟信息，时钟信息为时长或者时钟周期数量；如果当前的时钟信息偏离前N个时钟信息的平均值，将当前数据帧帧头的时间戳向偏离的相反方向偏移，得到修正的时间戳，其中，N>1，且偏移的时间量是对多个时钟信息进行统计得到的。通过本发明实施例时间戳的修正方法，可以提高时间戳的精度。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明实施例时间戳的修正方法流程图；
图2是本发明实施例时间戳的修正系统示意图；
图3是本发明实施例时钟同步方法流程图；
图4是本发明实施例时钟同步系统示意图；
图5是以太网数据包的帧结构示意图；
图6是本发明实施例时钟同步方法中，提取PTP报文的流程图；
图7是本发明实施例时钟同步方法中，插入PTP报文的流程图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属 于本发明保护的范围。
下面结合附图及具体实施例对本发明作进一步的详细描述。
参见图1所示，本发明实施例提供一种时间戳的修正方法，时间戳的修正方法包括：
S110记录物理层通道接收的数据帧帧头的时间戳以及相邻帧头之间的时钟周期数量。
具体的，当前的时钟周期数量之前的N个时钟周期数量按照记录顺序存储在预先创建的队列中，其中，N>1 ，N为正整数。
S120计算前N个时钟周期数量的平均值，前N个时钟周期数量的平均值为M ave。
S130判断当前的时钟周期数量是否偏离平均值，若是，进入步骤S140；若否，进入步骤S150。
具体的，当前的时钟周期数量为当前数据帧与前一个数据帧的帧头之间的时钟周期数量，即M N+1，当前的时钟周期数量即记录的第N+1个时钟周期数量，前N个时钟周期数量的平均值即预计的第N+1个时钟周期数量。
S140将当前数据帧帧头的时间戳向偏离的相反方向偏移，得到修正的时间戳，作为当前数据帧帧头的时间戳。
例如，当前数据帧帧头的时间戳为t N+1，当M N+1>M ave时，修正的时间戳t c_N+1＝t N+1-Δt，Δt为偏移的时间量。当M N+1<M ave时，修正的时间戳t c_N+1＝t N+1+Δt，Δt为偏移的时间量。
具体的，偏移的时间量Δt＝时钟周期的偏移量ΔM×时钟周期T，其中，时钟周期的偏移量ΔM可以是对多个时钟周期数量进行统计得到的，例如对多个时钟信息进行统计得到的标准差取整数。时钟周期T为每个时钟周期T的长度。
S150保存当前数据帧帧头的时间戳，并移除队列头部的数据，将当前的时钟周期数量加入队列尾部，返回步骤S110。
通过本实施例时间戳的修正方法，对数据帧帧头进行平滑处理，以提高时间戳的精度。需要说明的是，N值越大，则前N个时钟周期数量的平均值M ave越接近对多个时钟周期数量进行统计得到的理论值，平滑处理的效果越好，但是预先创建的队列和用于求取M ave的加法器等资源消耗越大。可以根据实际需要在平滑处理性能和资源消耗之间进行取舍。
考虑到上电初始化以及数据帧的接收端故障对时间戳的影响，在其他的实施方式中，时间戳的修正方法包括：
S200在队列中存入N个时钟周期数量的初始平均值。
具体的，对多个时钟周期数量进行统计可以得到时钟周期数量的阈值范围和初始平均值。
S210记录物理层通道接收的数据帧帧头的时间戳以及相邻帧头之间的时钟周期数量。
步骤S210与步骤S110相同，此处不再赘述。
S220计算N个时钟周期数量的平均值，其中，N>1，当前的时钟周期数量为当前数据帧与前一个数据帧的帧头之间的时钟周期数量。
步骤S220与步骤S120相同，此处不再赘述。
S230判断当前的时钟周期数量与平均值之差是否超出阈值范围，若是，返回步骤S200；若否，进入步骤S240。
如果当前的时钟周期数量偏离前N个时钟周期数量的平均值超出阈值范围时，将前N个时钟周期数量均设置为初始平均值，可以避免数据帧的接收端故障对时间戳的影响。
S240判断当前的时钟周期数量是否偏离平均值，若是，进入步骤S250；若否，进入步骤S260。
步骤S240与步骤S130相同，此处不再赘述。
S250将当前数据帧帧头的时间戳向偏离的相反方向偏移，得到修正的时间戳，并作为当前数据帧帧头的时间戳。
步骤S250与步骤S140相同，此处不再赘述。
S260保存当前数据帧帧头的时间戳，并移除队列头部的数据，将当前的时钟周期数量加入队列尾部。
步骤S260与步骤S150相同，此处不再赘述。
在其他的实施方式中，时长为相邻帧头的时间戳之差；或者，时长＝时钟周期数量×时钟周期。
本实施例提供时间戳的修正方法，记录物理层通道接收的数据帧帧头的时间戳以及相邻帧头之间的时钟信息，时钟信息为时长或者时钟周期数量；如果当前的时钟信息偏离前N个时钟信息的平均值，将当前数据帧帧头的时间戳向偏离的相反方向偏移，得到修正的时间戳，其中，N>1，且偏移的时间量是对多个时钟信息进行统计得到的。如果当前的时钟信息等于前N个时钟信息的平均值，则当前数据帧帧头的时间戳无需进行修正。通过本实施例时间戳的修正方法，对帧头进行平滑处理，可以提高时间戳的精度。
参见图2所示，本发明实施例还提供一种时间戳的修正系统，用于实现前述实施例的时间戳的修正方法，时间戳的修正系统包括检测模块110a和修正模块210a。
检测模块110a用于记录物理层通道接收的数据帧帧头的时间戳以及相邻帧头之间的时钟信息，时钟信息为时长或者时钟周期数量。
具体的，时长为相邻帧头的时间戳之差；或者，时长＝时钟周期 数量×时钟周期。前N个时钟信息按照记录顺序存储在预先创建的队列中。
修正模块210a用于如果当前的时钟信息偏离前N个时钟信息的平均值，将当前数据帧帧头的时间戳向偏离的相反方向偏移，得到修正的时间戳，其中，N>1，且偏移的时间量是对多个时钟信息进行统计得到的。
具体的，修正模块210a还用于当当前的时钟信息偏离前N个时钟信息的平均值超出阈值范围时，将前N个时钟信息均设置为初始平均值，阈值范围和初始平均值是对多个时钟信息进行统计得到的。
参见图3所示，本发明实施例还提供一种时钟同步方法，时钟同步方法包括：
S310第一处理器的多个物理层通道接收携带同步信息的数据帧，并记录数据帧帧头的时间戳和相邻帧头之间的时钟信息。
S320第二处理器使用前述实施例的时间戳的修正方法对数据帧帧头的时间戳进行修正，得到修正的时间戳。
经过修正处理的数据帧帧头的时间戳作为数据帧帧头的时间戳。
S330第二处理器生成响应信息并发送给第一处理器。
S340第一处理器将响应信息插入数据帧并向外发送。
S350第二处理器根据修正的时间戳和同步信息及其响应信息进行时钟调整。
步骤S330和S340与步骤S350可以同时进行，也可以先后进行，不作限定。
进一步的，第一处理器和第二处理器之间通过数据包传输同步信息及其响应信息。
第一处理器和第二处理器均可以是独立的集成电路芯片，例如， 数字信号处理器(Digital Signal Processing，DSP)、专用集成电路(Application Specific Integrated Circuit，ASIC)、现成可编程门阵列(Field-Programmable Gate Array，FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件等。第一处理器和第二处理器之间通过串行千兆媒体独立(Serial Gigabit Media Independent Interface，SGMII)接口传输携带同步信息及其响应信息的数据包。第一处理器和第二处理器也可以集成在同一个集成电路芯片内。
具体的，第一处理器从每物理层通道接收的数据帧帧头提取同步信息或者包含同步信息的开销并缓存到设定数量后，生成组包请求，并根据待发送的数据帧帧头生成同步发送指示。
第一处理器根据同步发送指示和组包请求将缓存的数据封装成数据包后，通过SGMII接口发送给第二处理器。
具体的，第一处理器根据第i个物理层通道待发送的数据帧的开销复帧指示信息生成同步发送指示，采用加权轮循调度算法对n个同步发送指示进行调度，1≤i≤n。同时，第一处理器采用加权轮循调度算法对n个组包请求进行调度。
第二处理器从收到的数据包中解析出同步信息，并向第一处理器发送携带响应信息的数据包。
具体的，第二处理器根据同步发送指示和响应信息的发送频率，对响应信息进行封装得到数据包，并通过SGMII接口传输到第一处理器。
第一处理器从数据包中提取响应信息，并根据同步发送指示将响应信息插入到待发送的数据帧中。
具体的，同步信息可以是精确时间协议PTP报文，不作限定。根据IEEE1588协议，PTP报文包括同步报文(Sync)、跟随报文 (Follow_up)、延迟请求报文(Delay_Req)和延迟应答报文(Delay_Resp)。主时钟定期发送同步报文Sync，如果为两步模式，则会随后发送跟随报文Follow_Up，并在跟随报文Follow_Up报文中通告同步报文Sync的实际发送时间T1。如果为单步模式，则在发送的同步报文Sync中即包含了报文实际发送时间T1，然后从时钟记录同步报文Sync的到达时间T2，从时钟在T3时刻发送时延请求报文Delay_Req，主时钟记录时延请求报文Delay_Req到达时间T4，并将时间T4通过延迟应答报文Delay_Resp发送给从时钟。
在本实施例中，同步信息可以是同步报文Sync，则响应信息是时延请求报文Delay_Req；或者，同步信息可以是时延请求报文Delay_Req，则响应信息是延迟应答报文Delay_Resp。为了便于说明，同步信息和响应信息分别为PTP报文和响应的PTP报文。
本发明实施例在5G承载网络进行时钟同步时，1)接收PTP报文后，第一处理器对开销中的信息进行统一封装，开销中的信息包括PTP报文，同时，记录数据帧帧头的时间戳和相邻帧头之间的时钟信息，将封装的开销、时间戳和时钟信息发送至第二处理器。第二处理器解析出PTP报文，对PTP报文的时间戳进行修正处理，完成时钟频率和相位调整功能。2)向外发送作为响应的PTP报文，将响应的PTP报文进行统一封装，发送给第一处理器，第一处理器根据复帧字段信息和PTP报文发送频率插入到开销中，随数据帧向外发送。
通过本实施例时间戳的修正方法，对帧头进行均衡化处理，可以提高时间戳的精度，有效抑制AM码字或者FlexO和OTU中跨时钟域等因素对帧头抖动的影响，极大地提高了时钟同步精度，同步精度可达±4ns，满足FlexE、FlexO和OTU等5G承载网络的需求。
另外，本发明实施例根据同步发送指示发送PTP报文，在PTP报文传送间隔传送其他的报文信息，极大提高开销的带宽利用率；可以精确地控制PTP报文发送频率，同时不会引起数据流中的带宽抖动。可以灵活配置PTP报文，即便将来定义新的标准，也可以通过修改第二处理器进行扩展，有效提高芯片适用性，降低投片风险。
参见图4所示，本发明实施例还提供一种时钟同步系统，时钟同步系统包括第一处理器100和第二处理器200，第一处理器100的多个物理层通道收发携带同步信息及其响应信息的数据帧。
第一处理器100用于记录数据帧帧头的时间戳以及相邻帧头之间的时钟信息。
第二处理器200用于使用前述实施例的时间戳的修正方法对数据帧帧头的时间戳进行修正，得到修正的时间戳；还用于生成响应信息；以及根据修正的时间戳和同步信息及其响应信息进行时钟调整。
具体的，第一处理器100和第二处理器200之间通过数据包传输同步信息及其响应信息。
参见图4所示，第一处理器100包括接收侧检测模块110b、开销提取模块120、封装模块130、解析模块140、开销插入模块150和帧头生成模块160。第二处理器包括修正模块210b、开销解析模块220、PTP报文解析模块230、时钟调整模块240、PTP报文生成模块250和封装模块260。
接收侧检测模块110b用于记录物理层通道接收的数据帧帧头的时间戳以及相邻帧头之间的时钟信息，时钟信息为时长或者时钟周期数量。
例如，对于FLEXO帧，多种不同的报文信息可以时分复用开销中的同一个物理层通道。接收侧检测模块110b用于从数据帧中检测 帧头特征码型得到帧头信息。
帧头生成模块160用于根据第i路的发送侧控制信号，从缓存中读取相应的响应报文，并将其插入到数据帧中向外发送。
具体的，帧头生成模块160用于生成本地FlexE/FlexO帧头和包络信息。
开销插入模块150用于根据开销复帧指示信息生成PTP报文发送指示，以及将PTP报文的响应报文插入到开销中。
开销提取单元120用于从接收的数据帧中提取并缓存设定数量的开销后，生成组包请求，实现对开销的统一缓存控制。
第一处理器的封装单元130用于根据组包请求和PTP报文发送指示，封装成开销数据包后通过SGMII接口发送到第二处理器的解析单元。多个端口可以时分复用同一个串行接口。
具体的，开销数据包为以太网数据包，开销数据包的帧格式如图5A所示。图5A的帧结构包括前导码、目的地址、源地址、长度、请求复帧号、状态指示、起始复帧号、开销净荷和校验码。源地址为接收的数据帧的PHY的相关信息。状态指示为第一指定标识时，表示该数据包为提取的开销数据包，状态指示为第二指定标识时，表示该数据包为提取的开销数据包和复帧信息，将复帧信息以及缓存达到设定数量的开销数据组装成数据包。
第一处理器的封装单元130还用于将PTP报文发送指示组装成PTP报文发送指示数据包，如图5B的以太网数据包，图5B的帧结构包括前导码、目的地址、源地址、长度、请求复帧号、状态指示、填充字节和校验码。
第一处理器的解析模块140用于从封装模块260接收数据包，利用数据包中的目的地址和请求复帧信息等字段对响应的PTP报文进 行解析。
开销插入模块150用于采用链式控制方法，对接收到的响应报文进行缓存控制。
第二处理器的解析单元220用于从第一处理器的封装单元130接收开销数据包和PTP报文发送指示数据包，并从中分别提取开销和PTP报文发送指示。
具体的，第二处理器的解析单元220根据接收到的数据包中的目的地址和请求复帧号提取PTP报文。
PTP报文解析模块230用于从开销中提取PTP报文并发送到时钟调整模块240。
修正模块210b用于从接收侧检测模块110b接收帧头的时间戳以及相邻帧头之间的时钟信息，如果当前的时钟信息偏离前N个时钟信息的平均值，将当前数据帧帧头的时间戳向偏离的相反方向偏移，得到修正的时间戳并发送到，其中，N>1，且偏移的时间量是对多个时钟信息进行统计得到的时钟调整模块。对接收的数据帧帧头进行平滑处理，使得帧头分布均匀，并对时间戳进行修正。
具体的，修正模块210b还用于当当前的时钟信息偏离前N个时钟信息的平均值超出阈值范围时，将前N个时钟信息均设置为初始平均值，阈值范围和初始平均值是对多个时钟信息进行统计得到的。
时钟调整模块240用于根据PTP报文和数据帧帧头的时间戳进行时钟频率和相位同步，进而实现高精度时钟同步。
具体的，根据IEEE1588协议，对本地时钟进行频率和相位的调整。
PTP报文生成模块250用于根据PTP报文和时间戳生成响应报文，并进行缓存。
第二处理器的封装模块260用于根据PTP报文发送指示以及PTP报文的发送频率，将缓存的响应报文封装为数据包后通过SGMII接口传输到第一处理器的解析模块140。该数据包如图5C所示的以太网数据包，图5C的帧结构包括前导码、目的地址、源地址、长度、请求复帧号、开销净荷和校验码。
基于图4所示的时钟同步系统，以FLEXO帧为例，提取PTP报文的过程参见图6所示，包括：
S400第一处理器生成PTP报文发送指示，包括：
S401第一处理器的开销插入模块150根据数据帧复帧指示生成PTP报文发送指示。
S402第一处理器的封装模块130采用加权轮循调度算法调度n路PTP报文发送指示。
S410第一处理器的第i路接收侧检测模块110b从数据帧中检测帧头特征码型。
S420第一处理器的开销提取模块120提取并缓存特定数量的开销后生成组包请求。
S430第一处理器的封装模块130采用加权轮循调度算法调度n路组包请求。
S440第一处理器的封装模块130根据组包请求和PTP报文发送指示封装数据包。
S450第二处理器的解析模块220对数据包进行解析。
S460第二处理器的PTP报文解析模块230解析出PTP报文。
S470第二处理器的时钟调整模块240根据PTP报文和时间戳进行时钟频率和相位同步。
基于图4所示的时钟同步系统，以FLEXO帧为例，插入PTP报 文的过程参见图7所示，包括：
S510第二处理器的PTP报文生成模块250根据PTP报文和时间戳生成响应报文，并进行缓存。
S520第二处理器的封装模块260根据PTP报文发送至少以及PTP报文的发送频率，将PTP报文封装为数据包后通过SGMII接口传输到第一处理器的解析模块。
S530第一处理器的解析模块140根据数据包中的目的地址和请求复帧信息等字段对响应报文进行解析。
S540第一处理器的开销插入模块150采用链式控制方法，对接收到的响应报文进行缓存控制。
S550帧头生成模块160根据第i路的发送侧控制信号，从缓存中读取相应的响应报文，并将其插入到数据帧中向外发送。
本发明不局限于上述实施方式，对于本技术领域的普通技术人员来说，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也视为本发明的保护范围之内。本说明书中未作详细描述的内容属于本领域专业技术人员公知的现有技术。

Claims (12)

  1. 一种时间戳的修正方法，其特征在于，其包括：
    记录物理层通道接收的数据帧帧头的时间戳以及相邻帧头之间的时钟信息，时钟信息为时长或者时钟周期数量；
    如果当前的时钟信息偏离前N个时钟信息的平均值，将当前数据帧帧头的时间戳向偏离的相反方向偏移，得到修正的时间戳，其中，N>1，且偏移的时间量是对多个时钟信息进行统计得到的。
  2. 如权利要求1所述的时间戳的修正方法，其特征在于，所述方法还包括：所述当前的时钟信息与前N个时钟信息的平均值的差值超出阈值范围时，将所述前N个时钟信息均设置为初始平均值。
  3. 如权利要求1所述的时间戳的修正方法，其特征在于：
    所述前N个时钟信息按照记录顺序存储在预先创建的队列中。
  4. 如权利要求1所述的时间戳的修正方法，其特征在于：
    所述时长为相邻帧头的所述时间戳之差；或者，
    所述时长＝所述时钟周期数量×时钟周期。
  5. 一种时钟同步方法，其特征在于，其包括：
    第一处理器的多个物理层通道收发携带同步信息及其响应信息的数据帧，并记录数据帧帧头的时间戳和相邻帧头之间的时钟信息；
    第二处理器使用如权利要求1至4任一项所述的时间戳的修正方法对所述数据帧帧头的时间戳进行修正，得到修正的时间戳；生成所述响应信息；根据所述修正的时间戳和所述同步信息及其响应信息进行时钟调整。
  6. 如权利要求5所述的时钟同步方法，其特征在于：
    所述第一处理器和所述第二处理器之间通过数据包传输所述同步信息及其响应信息。
  7. 一种时间戳的修正系统，其特征在于，其包括：
    检测模块，其用于记录物理层通道接收的数据帧帧头的时间戳以及相邻帧头之间的时钟信息，时钟信息为时长或者时钟周期数量；
    修正模块，其用于如果当前的时钟信息偏离前N个时钟信息的平均值，将当前数据帧帧头的时间戳向偏离的相反方向偏移，得到修正的时间戳，其中，N>1，且偏移的时间量是对多个时钟信息进行统计得到的。
  8. 如权利要求7所述的时间戳的修正系统，其特征在于：所述修正模块还用于所述当前的时钟信息与前N个时钟信息的平均值的差值超出阈值范围时，将所述前N个时钟信息均设置为初始平均值。
  9. 如权利要求7所述的时间戳的修正系统，其特征在于：
    所述前N个时钟信息按照记录顺序存储在预先创建的队列中。
  10. 如权利要求7所述的时间戳的修正系统，其特征在于：
    所述时长为相邻帧头的所述时间戳之差；或者，
    所述时长＝所述时钟周期数量×时钟周期。
  11. 一种时钟同步系统，其特征在于：所述系统包括第一处理器和第二处理器，第一处理器的多个物理层通道收发携带同步信息及其响应信息的数据帧；
    所述第一处理器用于记录所述数据帧帧头的时间戳以及相邻帧头之间的时钟信息；
    所述第二处理器用于使用如权利要求1至4任一项所述的时间戳的修正方法对所述数据帧帧头的时间戳进行修正，得到修正的时间戳；还用于生成所述响应信息；以及根据所述修正的时间戳和所述同步信息及其响应信息进行时钟调整。
  12. 如权利要求11所述的时钟同步系统，其特征在于：
    所述第一处理器和所述第二处理器之间通过数据包传输所述同步信息及其响应信息。
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