WO2020170970A1 - 蛍光体基板、発光基板、照明装置、蛍光体基板の製造方法及び発光基板の製造方法 - Google Patents
蛍光体基板、発光基板、照明装置、蛍光体基板の製造方法及び発光基板の製造方法 Download PDFInfo
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- phosphor
- light emitting
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- light
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/80—Constructional details
- H10H20/85—Packages
- H10H20/851—Wavelength conversion means
- H10H20/8514—Wavelength conversion means characterised by their shape, e.g. plate or foil
-
- F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
- F21—LIGHTING
- F21S—NON-PORTABLE LIGHTING DEVICES; SYSTEMS THEREOF; VEHICLE LIGHTING DEVICES SPECIALLY ADAPTED FOR VEHICLE EXTERIORS
- F21S2/00—Systems of lighting devices, not provided for in main groups F21S4/00 - F21S10/00 or F21S19/00, e.g. of modular construction
-
- F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
- F21—LIGHTING
- F21S—NON-PORTABLE LIGHTING DEVICES; SYSTEMS THEREOF; VEHICLE LIGHTING DEVICES SPECIALLY ADAPTED FOR VEHICLE EXTERIORS
- F21S2/00—Systems of lighting devices, not provided for in main groups F21S4/00 - F21S10/00 or F21S19/00, e.g. of modular construction
- F21S2/005—Systems of lighting devices, not provided for in main groups F21S4/00 - F21S10/00 or F21S19/00, e.g. of modular construction of modular construction
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/01—Manufacture or treatment
- H10H20/036—Manufacture or treatment of packages
- H10H20/0364—Manufacture or treatment of packages of interconnections
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/80—Constructional details
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/80—Constructional details
- H10H20/85—Packages
- H10H20/8506—Containers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/80—Constructional details
- H10H20/85—Packages
- H10H20/857—Interconnections, e.g. lead-frames, bond wires or solder balls
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
-
- F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
- F21—LIGHTING
- F21Y—INDEXING SCHEME ASSOCIATED WITH SUBCLASSES F21K, F21L, F21S and F21V, RELATING TO THE FORM OR THE KIND OF THE LIGHT SOURCES OR OF THE COLOUR OF THE LIGHT EMITTED
- F21Y2115/00—Light-generating elements of semiconductor light sources
- F21Y2115/10—Light-emitting diodes [LED]
Definitions
- the present invention relates to a phosphor substrate, a light emitting substrate, a lighting device, a phosphor substrate manufacturing method, and a light emitting substrate manufacturing method.
- Patent Document 1 discloses an LED lighting fixture including a substrate on which a light emitting element (LED element) is mounted.
- a light-reflecting material is provided on the surface of the substrate to improve the luminous efficiency. Further, in the case of the configuration disclosed in Patent Document 1, it is not possible to adjust the light emitted by the LED lighting fixture to a light of a different emission color from the light emitted by the light emitting element by using the reflective material.
- Patent Document 1 discloses a phosphor substrate having a phosphor layer, a light emitting substrate, and a manufacturing method thereof. There is no disclosure.
- the present invention aims to provide a phosphor substrate provided with a phosphor layer having a multilayer structure.
- a phosphor substrate is a phosphor substrate on which at least one light emitting element is mounted on one surface, and the phosphor substrate is disposed on an insulating substrate and one surface of the insulating substrate, and is outside in a thickness direction of the insulating substrate.
- a circuit pattern layer that has a flat surface that faces toward, and that joins at least one joining surface that joins at least one electronic component to the at least one electronic component, and at least a portion of the plane other than the at least one joining surface.
- a phosphor layer including a phosphor disposed on at least one non-bonding surface and having an emission peak wavelength in a visible light region when the emission of the at least one light-emitting element is used as excitation light.
- the body layer has a laminated structure.
- a phosphor substrate of a second aspect of the present invention is the phosphor substrate of the first aspect, wherein the at least one light emitting element is a plurality of light emitting elements, and the at least one bonding surface is a plurality of bonding surfaces. And the at least one non-bonding surface is a plurality of non-bonding surfaces, and the plurality of light emitting elements are arranged on one surface of the insulating substrate and are bonded to the plurality of bonding surfaces and mounted, respectively. ..
- a phosphor substrate according to a third aspect of the present invention is the phosphor substrate according to the first aspect, wherein the circuit pattern layer includes a portion other than the at least one joint surface in the at least one joint surface. At least one groove separating at least one non-bonding surface to be formed.
- a phosphor substrate according to a fourth aspect of the present invention is the phosphor substrate according to the third aspect, wherein the at least one light emitting element is a plurality of light emitting elements, and the at least one bonding surface is a plurality of bonding surfaces. And the at least one non-bonding surface is a plurality of non-bonding surfaces, the at least one groove is a plurality of grooves, the plurality of light emitting elements are arranged on one surface of the insulating substrate, respectively. , Are mounted by being bonded to the plurality of bonding surfaces.
- the light emitting substrate according to the first aspect of the present invention includes the phosphor substrate according to any one of the first to fourth aspects, and at least one light emitting element bonded to the at least one bonding surface.
- a light emitting substrate according to a second aspect of the present invention is the light emitting substrate according to the first aspect, wherein a position in the thickness direction of a surface of the phosphor layer facing outward in the thickness direction is the thickness of the at least one light emitting element. It is located on the inside in the thickness direction with respect to the position of the surface facing outward in the direction.
- a light emitting substrate according to a third aspect of the present invention is the light emitting substrate according to the first aspect, wherein a position in the thickness direction of a surface of the phosphor layer facing outward in the thickness direction is a thickness direction of the at least one light emitting element. Is located at the center position or inside of the position in the thickness direction.
- the lighting device of the present invention includes the light emitting substrate according to any one of the first to third aspects, and a power supply that supplies electric power for causing the light emitting element to emit light.
- the method for producing a phosphor substrate according to the first aspect of the present invention provides an insulating substrate, a circuit pattern layer, and a phosphor having an emission peak wavelength in the visible light region when the emission light of at least one light emitting element is used as excitation light.
- a method for manufacturing a phosphor substrate according to a second aspect of the present invention is the method for manufacturing a phosphor substrate according to the first aspect, wherein in the phosphor layer forming step, 1/n(n The phosphor layer having a thickness of ⁇ 2) is laminated n times to form the phosphor layer.
- a phosphor substrate manufacturing method is the phosphor substrate manufacturing method according to the first aspect, wherein in the phosphor layer forming step, an ejecting unit for ejecting a liquid is provided relative to the insulating substrate.
- the liquid containing the phosphor is ejected to the ejection part so that the phosphor pattern having a thickness of 1/n (n ⁇ 2) of the phosphor layer is laminated n times while moving to the phosphor. Form the layers.
- a phosphor substrate manufacturing method is the phosphor substrate manufacturing method according to the first aspect, wherein in the phosphor layer forming step, an ejecting unit that ejects liquid droplets is provided on the insulating substrate.
- the liquid containing the phosphor is ejected as droplets to the ejection part so that the phosphor pattern having a thickness of 1/n (n ⁇ 2) of the phosphor layer is laminated n times while being moved automatically. Forming the phosphor layer.
- a phosphor substrate manufacturing method of a fifth aspect of the present invention is the phosphor substrate manufacturing method of the first aspect, wherein in the phosphor layer forming step, 1/n(n) of the phosphor layer is printed by printing.
- the phosphor layer having a thickness of ⁇ 2) is laminated n times to form the phosphor layer.
- the method for producing a phosphor substrate according to the sixth aspect of the present invention is the method for producing a phosphor substrate according to the fifth aspect, wherein the printing is screen printing.
- a method for manufacturing a phosphor substrate according to a seventh aspect of the present invention is the method for manufacturing a phosphor substrate according to any one of the first to sixth aspects, wherein in the phosphor layer forming step, the phosphor layer is A phosphor pattern having a thickness smaller than the thickness is laminated to form the phosphor layer having a thickness not more than half the thickness of the phosphor layer.
- An eighth aspect of the present invention is a method for producing a phosphor substrate according to any one of the first to seventh aspects, wherein the phosphor substrate is formed after the pattern layer forming step.
- the groove forming step of forming at least one groove in a plane of the circuit pattern layer facing outward in the thickness direction of the insulating substrate.
- a solder arranging step of arranging a solder for joining at least one light emitting element to one portion with the at least one groove in the plane interposed therebetween.
- a method for manufacturing a light emitting substrate according to a first aspect of the present invention is the method for manufacturing a phosphor substrate according to any one of the first to eighth aspects, wherein the at least one light emitting element is bonded to a part of the wiring pattern layer. And a joining step of
- a method for manufacturing a light-emitting substrate according to a second aspect of the present invention is different from the method for manufacturing a phosphor substrate according to the eighth aspect in that the other part of the circuit pattern layer is sandwiched between the at least one groove in the plane.
- the method for manufacturing a light emitting substrate according to the third aspect of the present invention is the method for manufacturing a light emitting substrate according to the first or second aspect, wherein the joining step is performed after the phosphor layer forming step.
- a method for manufacturing a light-emitting substrate according to a fourth aspect of the present invention is the method for manufacturing a light-emitting substrate according to the first or second aspect, wherein in the joining step, flux is applied to the solder and then the solder is melted. The at least one light emitting element is joined to the other portion.
- the present invention can provide a light emitting substrate including a phosphor layer having a multilayer structure.
- FIG. 1B is a partial cross-sectional view of the light emitting substrate taken along the line 1C-1C in FIG. 1A.
- FIG. 3 is a plan view of a phosphor substrate (a phosphor layer is omitted) of the present embodiment. It is a top view of the fluorescent substance board of this embodiment. It is explanatory drawing of the 1st process in the manufacturing method of the light emitting substrate of this embodiment. It is explanatory drawing of the 2nd process in the manufacturing method of the light emitting substrate of this embodiment. It is explanatory drawing of the 3rd process in the manufacturing method of the light emitting substrate of this embodiment.
- 1A is a plan view of the light emitting substrate 10 of the present embodiment (view seen from the front surface 31), and FIG. 1B is a bottom view of the light emitting substrate 10 of the present embodiment (view seen from the back surface 33).
- 1C is a partial cross-sectional view of the light emitting substrate 10 taken along the line 1C-1C in FIG. 1A.
- the light emitting substrate 10 of the present embodiment has a rectangular shape as an example when viewed from the front surface 31 and the back surface 33.
- the light emitting substrate 10 of the present embodiment includes a plurality of light emitting elements 20 (an example of electronic components), a phosphor substrate 30, and electronic components (not shown) such as a connector and a driver IC. That is, the light emitting substrate 10 of the present embodiment is configured such that the plurality of light emitting elements 20 and the electronic components are mounted on the phosphor substrate 30.
- the light emitting substrate 10 of the present embodiment has a function of emitting light when power is supplied from an external power source (not shown) by directly attaching a lead wire or via a connector. Therefore, the light emitting substrate 10 of this embodiment is used as a main optical component in, for example, a lighting device (not shown).
- each of the plurality of light emitting elements 20 is a CSP (Chip Scale Package) in which a flip chip LED 22 (hereinafter, referred to as LED 22) is incorporated (see FIG. 1C).
- the CSP As the CSP, as shown in FIG. 1C, it is preferable that the entire periphery (five sides) of the LED 22 except the bottom surface is covered with the phosphor sealing layer 24.
- the phosphor sealing layer 24 contains a phosphor, and the light of the LED 22 is color-converted by the phosphor of the phosphor sealing layer 24 and emitted to the outside. As shown in FIG.
- the plurality of light emitting elements 20 are regularly arranged on the front surface 31 (an example of one surface) of the phosphor substrate 30 over the entire surface 31 of the phosphor substrate 30. It is installed.
- the correlated color temperature of the light emitted by each light emitting element 20 of the present embodiment is set to 3,018K as an example.
- the plurality of light emitting elements 20 use a heat sink (not shown) and a cooling fan (not shown) during the light emitting operation to radiate heat so that the phosphor substrate 30 is kept at room temperature from 50° C. to 100° C. as an example. Cooling).
- “50° C. to 100° C.” means “50° C. or more and 100° C. or less”.
- the term "-" used in the numerical range in the present specification means "more than the part described before "" and less than the part described after "”.
- FIG. 2A is a diagram of the phosphor substrate 30 of the present embodiment, and is a plan view (a view from the front surface 31) in which the phosphor layer 36 is omitted.
- FIG. 2B is a plan view (view from the front surface 31) of the phosphor substrate 30 of the present embodiment.
- the bottom view of the phosphor substrate 30 of the present embodiment is the same as the view of the light emitting substrate 10 viewed from the back surface 33.
- the partial cross-sectional view of the phosphor substrate 30 of the present embodiment is the same as the drawing when the light emitting element 20 is removed from the partial cross-sectional view of FIG. 1C. That is, the phosphor substrate 30 of the present embodiment has a rectangular shape as viewed from the front surface 31 and the back surface 33, for example.
- the phosphor substrate 30 of the present embodiment includes an insulating layer 32 (an example of an insulating substrate), a circuit pattern layer 34, a phosphor layer 36, and a back surface pattern layer 38 (FIGS. 1B, 1C, and 1C). 2A and FIG. 2B).
- the phosphor layer 36 is omitted in FIG. 2A, as shown in FIG. 2B, the phosphor layer 36 is, as an example, a plurality of phosphor layers 36 described later on the surface 31 of the insulating layer 32 and the circuit pattern layer 34. It is arranged in a portion other than the electrode pair 34A.
- through holes 39 are formed in the phosphor substrate 30 at four locations near the four corners and two locations near the center.
- the six through holes 39 are used as positioning holes when manufacturing the phosphor substrate 30 and the light emitting substrate 10.
- the six through holes 39 are used as mounting screw holes for securing a heat-extracting effect (preventing substrate warpage and floating) to the (light emitting) lamp housing.
- the phosphor substrate 30 of the present embodiment is processed (etched or the like) by processing a double-sided plate (hereinafter referred to as a mother board MB; see FIG. 3A) in which copper foil layers are provided on both surfaces of an insulating plate.
- a mother board MB see FIG. 3A
- CS-3305A manufactured by Risho Industry Co., Ltd. is used as an example.
- the main features of the insulating layer 32 of this embodiment will be described below.
- the shape is rectangular as viewed from the front surface 31 and the back surface 33, as an example.
- the material is an insulating material including bismaleimide resin and glass cloth as an example. Further, the insulating material does not contain halogen and phosphorus (halogen-free, phosphorus-free).
- the thickness is, for example, 100 ⁇ m to 200 ⁇ m.
- the coefficient of thermal expansion (CTE) in the machine direction and the coefficient of thermal expansion (CTE) in the machine direction are each 10 ppm/° C. or less in the range of 50° C. to 100° C., for example.
- the coefficient of thermal expansion (CTE) in the longitudinal direction and the coefficient of thermal expansion (CTE) in the lateral direction are 6 ppm/K, respectively, as an example. This value is almost the same as the case of the light emitting element 20 of the present embodiment (90% to 110%, that is, within ⁇ 10%).
- the glass transition temperature is, for example, higher than 300°C.
- the storage elastic modulus is larger than 1.0 ⁇ 10 10 Pa and smaller than 1.0 ⁇ 10 11 Pa in the range of 100° C. to 300° C.
- the bending elastic moduli in the machine direction and the transverse direction are 35 GPa and 34 GPa in the normal state, respectively.
- the hot bending elastic modulus in the machine direction and the transverse direction is 19 GPa at 250° C., for example.
- the water absorption is 0.13% when left for 24 hours in a temperature environment of 23°C.
- the relative permittivity is 4.6 in a 1 MHz normal state as an example.
- the dielectric loss tangent is 0.010 in the normal state of 1 MHz.
- the circuit pattern layer 34 of the present embodiment is a metal layer provided on the surface 31 side of the insulating layer 32.
- the circuit pattern layer 34 of the present embodiment is, for example, a copper foil layer (a layer made of Cu).
- at least the surface (the surface facing the outer side in the thickness direction of the insulating layer 32) of the circuit pattern layer 34 of the present embodiment is a flat surface including copper.
- the circuit pattern layer 34 is a pattern provided on the insulating layer 32, and is electrically connected to a terminal (not shown) to which a connector (not shown) is joined.
- the circuit pattern layer 34 supplies electric power supplied from an external power source (not shown) via the connector to the plurality of light emitting elements 20 when the light emitting substrate 10 is configured. Therefore, a part of the circuit pattern layer 34 is a plurality of electrode pairs 34A to which the plurality of light emitting elements 20 are respectively joined. That is, the circuit pattern layer 34 of the light emitting substrate 10 of the present embodiment is arranged on the insulating layer 32 and connected to each light emitting element 20.
- the circuit pattern layer 34 of the phosphor substrate 30 of the present embodiment is arranged on the insulating layer 32 and is connected to each light emitting element 20 by each electrode pair 34A.
- the surface of each electrode pair 34A is referred to as a bonding surface 34A1.
- each joint surface 34A1 is a surface on one side with each groove 34E on the surface (flat surface) of the circuit pattern layer.
- each non-bonding surface 34B1 is, as shown in FIG. 1C, FIG. 2A, FIG.
- each bonding surface 34A1 with each groove 34E on the surface (flat surface) of the circuit pattern layer is formed.
- a plurality of grooves 34E that separate the plurality of bonding surfaces 34A1 and the plurality of non-bonding surfaces 34B1 are formed.
- the region where the circuit pattern layer 34 is arranged on the surface 31 of the insulating layer 32 (the area occupied by the circuit pattern layer 34) is, for example, 60% or more of the surface 31 of the insulating layer 32 (area). (See FIG. 2A).
- the bonding surfaces 34A1 and the non-bonding surfaces 34B1 are located at the same position in the thickness direction of the insulating layer 32 (see FIG. 1C, FIG. 3F, etc.).
- the phosphor layer 36 of the present embodiment is arranged in a portion other than the plurality of electrode pairs 34A and the groove 34E on the surface 31 of the insulating layer 32 and the circuit pattern layer 34. .. That is, the phosphor layer 36 is arranged in a region other than the plurality of electrode pairs 34A and the groove 34E in the circuit pattern layer 34. In other words, at least a part of the phosphor layer 36 is arranged on the surface 31 around the plurality of grooves 34E and the bonding surfaces 34A1 adjacent to the grooves 34E (see FIGS. 1C and 2B).
- the phosphor layer 36 is arranged so as to surround the entire joint surface 34A1 when viewed from the surface 31 side.
- the region where the phosphor layer 36 is arranged on the surface 31 of the insulating layer 32 is, for example, 80% or more of the surface 31 of the insulating layer 32.
- the surface of the phosphor layer 36 on the outer side in the thickness direction of the insulating layer 32 is located on the outer side in the thickness direction than the joint surface 34A1 of the circuit pattern layer 34 (see FIG. 1C).
- the phosphor layer 36 of the present embodiment has a facing surface 36A facing the light emitting element 20 at the boundary with the groove 34E in each non-bonding surface 34B1 (see FIG.
- the position in the thickness direction of the thickness direction outer surface (the surface facing the outside) of the insulating layer 32 in the phosphor layer 36 is the center position in the thickness direction of each light emitting element 20. (See FIG. 1C).
- the position in the thickness direction of the surface of the phosphor layer 36 on the outer side in the thickness direction of the insulating layer 32 is preferably located at a position on the inner side in the thickness direction than the center of each light emitting element 20 in the thickness direction. .. The above reason is to ensure the light emitting effect of each light emitting element 20.
- the phosphor layer 36 of the present embodiment is, for example, an insulating layer containing a phosphor and a binder described later.
- the phosphor contained in the phosphor layer 36 is fine particles held in a state of being dispersed in a binder, and has a property of exciting the light emission of the LED 22 of each light emitting element 20 as excitation light.
- the phosphor of the present embodiment has a property that the emission peak wavelength when the light emitted from the LED 22 of the light emitting element 20 is used as excitation light is in the visible light region.
- the binder may be, for example, an epoxy type, an acrylate type, a silicone type, or the like, as long as it has an insulating property equivalent to that of the binder contained in the solder resist.
- examples of the phosphor contained in the phosphor layer 36 of the present embodiment include an ⁇ -sialon phosphor containing Eu, a ⁇ -sialon phosphor containing Eu, a CASN phosphor containing Eu, and Eu.
- the phosphor is at least one phosphor selected from the group consisting of SCASN phosphors containing
- the above-mentioned phosphor is an example of this embodiment, and may be a phosphor other than the above-mentioned phosphor, such as YAG, LuAG, BOS, and other phosphors excited by visible light.
- examples of the nitride phosphor include a Eu-containing CASN phosphor and a Eu-containing SCASN phosphor.
- a CASN phosphor containing Eu (an example of a nitride phosphor) is represented by, for example, the formula CaAlSiN 3 :Eu 2+ , has Eu 2+ as an activator, and has a crystal composed of an alkaline earth silicon nitride as a matrix. A red phosphor.
- the Eu-containing CASN phosphor in the present specification the Eu-containing SCASN phosphor is excluded.
- the SCASN phosphor containing Eu (an example of a nitride phosphor) is represented by, for example, the formula (Sr,Ca)AlSiN 3 :Eu 2+ , uses Eu 2+ as an activator, and is made of an alkaline earth silicon nitride.
- the back surface pattern layer 38 of the present embodiment is a metal layer provided on the back surface 33 side of the insulating layer 32.
- the back pattern layer 38 of the present embodiment is, for example, a copper foil layer (Cu layer).
- the back surface pattern layer 38 is arranged such that a plurality of rectangular portion blocks arranged in a straight line along the longitudinal direction of the insulating layer 32 are adjacent to each other with their phases shifted in the lateral direction. It is supposed to be a layer.
- the back pattern layer 38 is, for example, an independent floating layer.
- the back surface pattern layer 38 overlaps, for example, 80% or more of the area of the circuit pattern layer 34 arranged on the front surface 31 in the thickness direction of the insulating layer 32 (phosphor substrate 30).
- the method for manufacturing the light emitting substrate 10 of this embodiment includes a first step, a second step, a third step, a fourth step and a fifth step, and each step is performed in the order described.
- FIG. 3A is a diagram showing the start time and the end time of the first step.
- the first step is a step of forming the same pattern 34C (an example of a conductive pattern layer) as the circuit pattern layer 34 on the front surface 31 of the motherboard MB when viewed from the thickness direction, and the back surface pattern layer 38 on the back surface 33. This step is performed by etching using a mask pattern (not shown), for example. Note that this step is an example of the pattern layer forming step.
- FIG. 3B is a diagram showing the start time and the end time of the second step.
- the second step is a step of forming a plurality of grooves 34E on the surface of the pattern 34C. This step is performed by etching using a mask pattern (not shown), for example.
- the circuit pattern layer 34 is formed. That is, when this step is completed, the joint surface 34A1 and the non-joint surface 34B1 are formed on both sides of each groove 34E, respectively. Note that this step is an example of the groove forming step.
- FIG. 3C is a diagram showing the start time and the end time of the third step.
- the third step is a step of disposing the solder SP on each joint surface 34A1 of the circuit pattern layer 34 (in other words, applying the solder SP). This step is performed by printing as an example. Note that this step is an example of the solder placement step.
- FIG. 3D is a diagram showing the start of the fourth step and the application of the first layer.
- FIG. 3E is a diagram showing the second step and the third layer in the fourth step.
- the fourth step is a step of forming the phosphor layer 36 over the entire non-bonding surface 34B1 of the circuit pattern layer 34.
- the phosphor layer 36 is arranged by stacking the phosphor patterns 361, 362, and 363 having a thickness of 1/3 of the phosphor layer 36 three times by transfer.
- the position in the thickness direction of the surface of the phosphor layer 36 facing the thickness direction outside of the insulating layer 32 is the center position in the thickness direction of each light emitting element 20 bonded to the circuit pattern layer 34.
- the phosphor layer 36 is applied so as to be located at. In other words, in this step, the phosphor layer 36 is applied such that the thickness of the phosphor layer 36 is not more than half the thickness of each light emitting element 20. However, for the reasons described above, the thickness of the phosphor layer 36 is preferably half or less of the thickness of each light emitting element 20. Note that this step is an example of the phosphor layer arranging step.
- FIG. 3F is a diagram showing the start time and the end time of the fifth step.
- the fifth step is a step of mounting the plurality of light emitting elements 20 on the phosphor substrate 30.
- the solder SP is melted in a state in which the electrodes of the plurality of light emitting elements 20 are aligned with the joint surfaces 34A1 on which the solder SP is arranged in the third step.
- each light emitting element 20 is bonded to each electrode pair 34A (each bonding surface 34A1). That is, this process is performed by a reflow process as an example.
- FIG. 4 is a diagram for explaining the light emitting operation of the light emitting substrate 10 of the present embodiment.
- a part of the light L emitted from each light emitting element 20 is emitted to the outside without entering the phosphor layer 36.
- the wavelength of the light L remains the same as the wavelength of the light L emitted from each light emitting element 20.
- the light of the LED 22 itself which is a part of the light L emitted from each light emitting element 20, is incident on the phosphor layer 36.
- the above-mentioned “light of the LED 22 itself in a part of the light L” means color conversion by the phosphor (phosphor sealing layer 24) of each light emitting element 20 (CSP itself) in the emitted light L.
- Light that is not emitted that is, light of the LED 22 itself (for example, light of blue color (wavelength near 470 nm)) is meant. Then, when the light L of the LED 22 itself collides with the phosphor dispersed in the phosphor layer 36, the phosphor is excited and emits excitation light.
- the reason why the phosphor is excited is that the phosphor dispersed in the phosphor layer 36 is a phosphor having an excitation peak in blue light (visible light excitation phosphor). Along with this, a part of the energy of the light L is used to excite the phosphor, so that a part of the energy of the light L is lost. As a result, the wavelength of the light L is converted (wavelength conversion is performed). For example, depending on the type of phosphor of the phosphor layer 36 (for example, when red-based CASN is used for the phosphor), the wavelength of the light L becomes long (for example, 650 nm or the like).
- the wavelength of the excitation light by the phosphor of the phosphor layer 36 is 600 nm or more, the reflection effect can be expected even if the circuit pattern layer 34 is Cu.
- the wavelength of the light L differs from that in the above example depending on the type of the fluorescent material of the fluorescent material layer 36, the wavelength conversion of the light L is performed in any case.
- the reflection effect can be expected if the circuit pattern layer 34 or its surface is made of Ag (plating), for example.
- a white reflective layer may be provided below the phosphor layer 36 (on the side of the insulating layer 32).
- the reflective layer is provided by, for example, white paint such as titanium oxide filler.
- the light L emitted from each light emitting element 20 (the light L radially emitted from each light emitting element 20) is emitted to the outside together with the excitation light via the plurality of optical paths as described above. .. Therefore, when the emission wavelength of the phosphor included in the phosphor layer 36 is different from the emission wavelength of the phosphor (phosphor sealing layer 24) that seals (or covers) the LED 22 in the light emitting element 20 (CSP),
- the bundle of light L emitted by each light emitting element 20 is a bundle of light L including the light L having a wavelength different from the wavelength of the light L emitted by each light emitting element 20.
- the light emitting substrate 10 of the present embodiment includes a light L including a bundle of light L emitted by each light emitting element 20 and a light L having a wavelength longer than the wavelength of the light L emitted by each light emitting element 20.
- the emission wavelength of the phosphor contained in the phosphor layer 36 and the emission wavelength of the phosphor (phosphor sealing layer 24) that seals (or covers) the LED 22 in the light emitting element 20 (CSP) are In the same case (in the case of the same correlated color temperature), in the light emitting substrate 10 of the present embodiment, the bundle of light L emitted by each light emitting element 20 is the same as the wavelength of the light L emitted by each light emitting element 20. A bundle of light L including a light L having a wavelength is emitted together with the excitation light.
- FIG. 5 is a diagram for explaining the light emitting operation of the light emitting substrate 10A of the comparative form.
- the light emitting substrate 10A of the comparative form (the substrate 30A on which the plurality of light emitting elements 20 are mounted) has the same configuration as the light emitting substrate 10 (phosphor substrate 30) of the present embodiment, except that the phosphor layer 36 is not provided. ing.
- the light emitting substrate 10A of the comparative form In the case of the light emitting substrate 10A of the comparative form, the light L emitted from each light emitting element 20 and incident on the surface 31 of the substrate 30A is reflected or scattered without the wavelength being converted. Therefore, in the case of the comparative substrate 30A, when the light emitting element 20 is mounted, it is not possible to adjust the light emission color different from the light emitted by the light emitting element 20. That is, in the case of the light emitting substrate 10A of the comparative form, it is not possible to adjust the light emission color different from the light emitted by the light emitting element 20.
- the phosphor layer 36 when viewed from the thickness direction of the insulating layer 32, the phosphor layer 36 is provided on the surface 31 of the insulating layer 32 and around each bonding surface 34A1 with each light emitting element 20. It is arranged. Therefore, a part of the light L emitted from each light emitting element 20 in a hemispherical shape is incident on the phosphor layer 36, the wavelength thereof is converted by the phosphor layer 36, and the light is irradiated to the outside. In this case, part of the light L radially emitted from each light emitting element 20 enters the phosphor layer 36 to excite the phosphor contained in the phosphor layer 36 and generate excitation light.
- the phosphor substrate 30 of the present embodiment when the light emitting element 20 is mounted, the light L emitted from the phosphor substrate 30 is changed to the light of the emission color different from the light L emitted by the light emitting element 20. Can be adjusted. Accordingly, according to the light emitting substrate 10 of the present embodiment, the light L emitted from the phosphor substrate 30 can be adjusted to the light L having a different emission color from the light L emitted by the light emitting element 20.
- the light emitting substrate 10 converts the bundle of the light L emitted by each light emitting element 20 into the light having the same wavelength as the wavelength of the light L emitted by each light emitting element 20.
- a bundle of light L containing L is irradiated together with the excitation light.
- the phosphor layer 36 can also reduce the chromaticity variation of the mounted light emitting element 20.
- the present embodiment it is possible to reduce glare as compared with the comparative example.
- this effect is obtained when the phosphor layer 36 is provided over the entire surface of the insulating layer 32, specifically, the region of the surface 31 of the insulating layer 32 where the phosphor layer 36 is arranged is the surface 13. It is effective in the case of 80% or more of the area.
- the phosphor layer 36 of the present embodiment has a facing surface 36A corresponding to the adjacent light emitting element 20, as shown in FIG. 1C. Therefore, in the present embodiment, for example, glare can be reduced compared to the case where the light emitting element 20 is arranged on the phosphor layer 36 (not shown).
- the phosphor contained in the phosphor layer 36 is a CASN phosphor containing Eu, and the phosphor layer 36 is provided on the Cu wiring portion 34B. Therefore, for example, when each light emitting element 20 emits white light L, for example, the excitation light from the CASN phosphor contained in the phosphor layer 36 is emitted by reflection by Cu forming the lower electrode. The efficiency is improved (the structure of the present embodiment has a Cu light reflection effect). Then, in the present embodiment, due to the effect, the white light L can be adjusted to the warmer color light L (color in which the correlated color temperature is shifted to the low temperature side). In this case, warm-colored light can be added to the white-based light of the light emitting element 20, and the special color rendering coefficient R9 value can be increased. This effect is particularly effective for pseudo white light using YAG-based white light (yellow phosphor).
- the phosphor layers 36 are arranged by stacking the phosphor patterns 361, 362, and 363 each having a thickness of 1/3 of the phosphor layer 36 three times. To do. Therefore, according to the present embodiment, it is possible to manufacture the phosphor substrate 30 including the phosphor layer 36 having a multilayer structure. From another point of view, according to the present embodiment, the film thickness of the phosphor layer 36 can be adjusted by adjusting the number of times the phosphor patterns 361 and the like are stacked in the third step.
- the fourth step is performed after the third step (solder arranging step) (see FIGS. 3C to 3E).
- the timing of arranging the solder SP may be, for example, the time of the fifth step (the step of mounting the plurality of light emitting elements 20) after the fourth step.
- the solder SP can be easily arranged by printing.
- each groove 34E formed on the surface of the circuit pattern layer 34 is effective in that it functions as a solder flow stop for the solder SP.
- the phosphor layer 36 is formed by transferring, for example, three phosphor patterns 361, 362, 363 each having a thickness of 1/3 of the phosphor layer 36. It has been described that the phosphor layer 36 is formed by stacking the layers once. However, the phosphor layer 36 may be formed by a method different from this embodiment. For example, as in the modified example (first modified example) shown in FIG.
- the phosphor layer 36 may be formed by discharging the liquid LQ containing the phosphor to the dispenser DP such that the phosphor patterns having a thickness of /n (n ⁇ 2) are stacked n times.
- the droplet discharge head IJH an example of the discharge section
- the phosphor layer 36 is formed by causing the liquid droplet ejection head IJH to eject the liquid droplet DL containing the phosphor so that the phosphor pattern having a thickness of 1/n (n ⁇ 2) of the body layer 36 is stacked n times. You may do so. Further, unlike the first modification and the second modification, in the fourth step, 1/n so that the phosphor patterns having a thickness of 1/n (n ⁇ 2) of the phosphor layer 36 are laminated n times.
- the phosphor layer 36 may be formed by printing a phosphor pattern having a thickness of n times. As a printing method in the case of this modification, for example, there is a screen printing method. However, if the phosphor layer 36 can be formed by printing the phosphor pattern n times, the specific printing method is not limited to the screen printing method.
- the fifth step (the joining step of the light emitting element 20) is performed after the fourth step (the phosphor layer arranging step).
- the fourth step may be performed after the fifth step.
- the second modified example is effective in that the fourth step can be performed at any timing before and after the fifth step.
- this point can be said in the case of the first modification.
- the film thickness of the phosphor layer 36 can be partially adjusted. It can be said that it is effective.
- the example of the light emitting element 20 is the CSP.
- an example of the light emitting element 20 may be other than the CSP.
- a flip chip may be simply mounted. It can also be applied to the substrate of the COB device itself.
- the phosphor substrate 30 has a plurality of light emitting elements 20 mounted thereon, and the light emitting substrate 10 has a plurality of light emitting elements 20.
- the number of the light emitting elements 20 mounted on the phosphor substrate 30 may be at least one.
- the number of the light emitting elements 20 mounted on the light emitting substrate 10 may be at least one.
- the number of the bonding surfaces 34A1 and the non-bonding surfaces 34B1 may be at least one or more.
- the back surface 33 of the phosphor substrate 30 is provided with the back surface pattern layer 38 (see FIG. 1B).
- the first effect is achieved even if the back surface 33 of the phosphor substrate 30 is not provided with the back surface pattern layer 38. Therefore, even if the back surface 33 does not have the back surface pattern layer 38, which is different from the phosphor substrate 30 and the light emitting substrate 10 of the present embodiment, the embodiment can be said to belong to the technical scope of the present invention.
- the phosphor substrate 30 has a plurality of light emitting elements 20 mounted thereon.
- the example of the electronic component may not be the light emitting element 20.
- the phosphor substrate 30, which is an example of the circuit board includes the phosphor layer 36.
- the phosphor layer 36 may not be provided on the circuit board.
- the phosphor layer 36 is arranged on the surface 31 of the insulating layer 32 and the circuit pattern layer 34 other than the plurality of electrode pairs 34A (see FIG. 2B).
- the first and the fourth effects can be obtained even if they are not arranged over the entire area of the surface 31 of the phosphor substrate 30 other than the plurality of electrode pairs 34A. It is clear that the effect of 4 is produced. Therefore, even if the phosphor substrate 36 and the light emitting substrate 10 of the present embodiment are different from each other only in that the phosphor layer 36 is arranged in the range of the surface 31 different from the case of the present embodiment, the embodiment is the present invention.
- the phosphor layer 36 is provided between the adjacent light emitting elements 20 (FIG. 2B). Further, the binder of the phosphor layer 36 has the same insulating property as the binder contained in the solder resist, for example. That is, in the case of the present embodiment, the phosphor layer 36 functions as a solder resist.
- CS-3305A manufactured by Risho Industry Co., Ltd. is used as the motherboard MB.
- the light emitting substrate 10 of the present embodiment (including its modification) can be applied to a lighting device by combining with other components.
- the other components in this case are a power supply for supplying electric power for causing the light emitting element 20 of the light emitting substrate 10 to emit light.
- Light emitting board (an example of mounting board) 20 Light-Emitting Element 30 Phosphor Substrate (Example of Circuit Board) 31 surface (one example of one side) 32 insulating layer (an example of an insulating substrate) 33 back surface 34 circuit pattern layer 34A electrode pair 34A1 bonding surface 34B wiring portion 34B1 non-bonding surface 34E groove 36 phosphor layer 36E facing surface 38 back surface pattern layer DP dispenser (an example of a discharge part) IJH droplet discharge head (an example of a discharge unit) L Hikari MB Motherboard SP Solder ball, solder
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- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Led Device Packages (AREA)
- Fastening Of Light Sources Or Lamp Holders (AREA)
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
Description
以下、本実施形態の発光基板10(実装基板の一例)の構成及び機能について図1A~図1Cを参照しながら説明する。次いで、本実施形態の発光基板10の製造方法について図3A~図3Fを参照しながら説明する。次いで、本実施形態の発光基板10の発光動作について図4を参照しながら説明する。次いで、本実施形態の効果について図4等を参照しながら説明する。なお、以下の説明において参照するすべての図面において、同様な構成要素には同様の符号を付し、適宜説明を省略する。
図1Aは本実施形態の発光基板10の平面図(表面31から見た図)、図1Bは本実施形態の発光基板10の底面図(裏面33から見た図)である。図1Cは、図1Aの1C-1C切断線により切断した発光基板10の部分断面図である。
本実施形態の発光基板10は、表面31及び裏面33から見て、一例として矩形とされている。また、本実施形態の発光基板10は、複数の発光素子20(電子部品の一例)と、蛍光体基板30と、コネクタ、ドライバIC等の電子部品(図示省略)とを備えている。すなわち、本実施形態の発光基板10は、蛍光体基板30に、複数の発光素子20及び上記電子部品が搭載されたものとされている。
本実施形態の発光基板10は、リード線の直付けにより又はコネクタを介して外部電源(図示省略)から給電されると、発光する機能を有する。そのため、本実施形態の発光基板10は、例えば照明装置(図示省略)等における主要な光学部品として利用される。
複数の発光素子20は、それぞれ、一例として、フリップチップLED22(以下、LED22という。)が組み込まれたCSP(Chip Scale Package)とされている(図1C参照)。CSPとして、図1Cに示すように、LED22の底面を除く全周囲(5面)が蛍光体封止層24により覆われていることが好ましい。蛍光体封止層24には蛍光体が含まれ、LED22の光は蛍光体封止層24の蛍光体により色変換されて外部に出射する。複数の発光素子20は、図1Aに示されるように、蛍光体基板30の表面31(一面の一例)に、表面31の全体に亘って規則的に並べられた状態で、蛍光体基板30に搭載されている。なお、本実施形態の各発光素子20が発光する光の相関色温度は、一例として3,018Kとされている。また、複数の発光素子20は、発光動作時に、ヒートシンク(図示省略)や冷却ファン(図示省略)を用いることで、蛍光体基板30を一例として常温から50℃~100℃に収まるように放熱(冷却)されるようになっている。
ここで、本明細書で数値範囲に使用する「~」の意味について補足すると、例えば「50℃~100℃」は「50℃以上100℃以下」を意味する。そして、本明細書で数値範囲に使用する「~」は、「『~』の前の記載部分以上『~』の後の記載部分以下」を意味する。
図2Aは、本実施形態の蛍光体基板30の図であって、蛍光体層36を省略して図示した平面図(表面31から見た図)である。図2Bは、本実施形態の蛍光体基板30の平面図(表面31から見た図)である。なお、本実施形態の蛍光体基板30の底面図は、発光基板10を裏面33から見た図と同じである。また、本実施形態の蛍光体基板30の部分断面図は、図1Cの部分断面図から発光素子20を除いた場合の図と同じである。すなわち、本実施形態の蛍光体基板30は、表面31及び裏面33から見て、一例として矩形とされている。
以下、本実施形態の絶縁層32の主な特徴について説明する。
形状は、前述のとおり、一例として表面31及び裏面33から見て矩形である。
材質は、一例としてビスマレイミド樹脂及びガラスクロスを含む絶縁材である。また、当該絶縁材にはハロゲン及びリンは含まれていない(ハロゲンフリー、リンフリー)。
厚みは、一例として100μm~200μmである。
縦方向及び横方向の熱膨張係数(CTE)は、それぞれ、一例として、50℃~100℃の範囲において10ppm/℃以下である。また、別の見方をすると、縦方向及び横方向の熱膨張係数(CTE)は、それぞれ、一例として、6ppm/Kである。この値は、本実施形態の発光素子20の場合とほぼ同等(90%~110%、すなわち±10%以内)である。
ガラス転移温度は、一例として、300℃よりも高い。
貯蔵弾性率は、一例として、100℃~300℃の範囲において、1.0×1010Paよりも大きく1.0×1011Paよりも小さい。
縦方向及び横方向の曲げ弾性率は、一例として、それぞれ、常態において35GPa及び34GPaである。
縦方向及び横方向の熱間曲げ弾性率は、一例として、250℃において19GPaである。
吸水率は、一例として、23℃の温度環境で24時間放置した場合に0.13%である。
比誘電率は、一例として、1MHz常態において4.6である。
誘電正接は、一例として、1MHz常態において、0.010である。
本実施形態の回路パターン層34は、絶縁層32の表面31側に設けられた金属層とされている。本実施形態の回路パターン層34は一例として銅箔層(Cu製の層)とされている。別言すれば、本実施形態の回路パターン層34は、少なくともその表面(絶縁層32の厚み方向外側に向く面)が銅を含んで形成された平面とされている。
なお、絶縁層32の表面31における回路パターン層34が配置されている領域(回路パターン層34の専有面積)は、一例として、絶縁層32の表面31の60%以上の領域(面積)とされている(図2A参照)。また、本実施形態では、各接合面34A1と各非接合面34B1とは、絶縁層32の厚み方向における同じ位置に位置している(図1C、図3F等参照)。
本実施形態の蛍光体層36は、図2Bに示されるように、一例として、絶縁層32及び回路パターン層34の表面31における、複数の電極対34A及び溝34E以外の部分に配置されている。すなわち、蛍光体層36は、回路パターン層34における複数の電極対34A及び溝34E以外の領域に配置されている。別言すると、蛍光体層36の少なくとも一部は、表面31における、複数の溝34E及び各溝34Eに隣接する各接合面34A1の周囲に配置されている(図1C及び図2B参照)。さらに、別の見方をすると、蛍光体層36の少なくとも一部は、表面31側から見て、各接合面34A1の周りを全周に亘って囲むように配置されている。そして、本実施形態では、絶縁層32の表面31における蛍光体層36が配置されている領域は、一例として、絶縁層32の表面31における80%以上の領域とされている。
なお、蛍光体層36における絶縁層32の厚み方向外側の面は、回路パターン層34の接合面34A1よりも当該厚み方向外側に位置している(図1C参照)。また、本実施形態の蛍光体層36は、各非接合面34B1における溝34Eとの境界において、発光素子20に対向する対向面36Aを有する(図1C参照)。また、本実施形態では、一例として、蛍光体層36における絶縁層32の厚み方向外側の面(外側に向く面)の前記厚み方向の位置は、各発光素子20の前記厚み方向の中央の位置に位置している(図1C参照)。ただし、蛍光体層36における絶縁層32の厚み方向外側の面の前記厚み方向の位置は、各発光素子20の前記厚み方向の中央よりも前記厚み方向内側の位置に位置していることが好ましい。以上の理由は、各発光素子20による発光効果を確保するためである。
ここで、本実施形態の蛍光体層36に含まれる蛍光体は、一例として、Euを含有するα型サイアロン蛍光体、Euを含有するβ型サイアロン蛍光体、Euを含有するCASN蛍光体及びEuを含有するSCASN蛍光体からなる群から選ばれる少なくとも一種以上の蛍光体とされている。なお、前述の蛍光体は、本実施形態の一例であり、YAG、LuAG、BOSその他の可視光励起の蛍光体のように、前述の蛍光体以外の蛍光体であってもよい。
本実施形態の裏面パターン層38は、絶縁層32の裏面33側に設けられた金属層とされている。本実施形態の裏面パターン層38は一例として銅箔層(Cu製の層)とされている。
裏面パターン層38は、図1Bに示されるように、絶縁層32の長手方向に沿って直線状に並べられている複数の矩形部分の塊が短手方向において位相をずらしたよう隣接して並べられている層とされている。
なお、裏面パターン層38は、一例として、独立フローティング層とされている。また、裏面パターン層38は、絶縁層32(蛍光体基板30)の厚み方向において、一例として、表面31に配置されている回路パターン層34の80%以上の領域と重なっている。
次に、本実施形態の発光基板10の製造方法について図3A~図3Fを参照しながら説明する。本実施形態の発光基板10の製造方法は第1工程、第2工程、第3工程、第4工程及び第5工程を含んでおり、各工程はこれらの記載順で行われる。
図3Aは、第1工程の開始時及び終了時を示す図である。第1工程は、マザーボードMBの表面31に厚み方向から見て回路パターン層34と同じパターン34C(導電性パターン層の一例)を、裏面33に裏面パターン層38を形成する工程である。本工程は、例えばマスクパターン(図示省略)を用いたエッチングにより行われる。なお、本工程は、パターン層形成工程の一例である。
図3Bは、第2工程の開始時及び終了時を示す図である。第2工程は、パターン34Cの表面に複数の溝34Eを形成する工程である。本工程は、例えばマスクパターン(図示省略)を用いたエッチングにより行われる。本工程が終了すると、回路パターン層34が形成される。すなわち、本工程が終了すると、各溝34Eを挟んで両側にそれぞれ接合面34A1及び非接合面34B1が形成される。なお、本工程は、溝形成工程の一例である。
図3Cは、第3工程の開始時及び終了時を示す図である。第3工程は、回路パターン層34の各接合面34A1にはんだSPを配置する(別言すると、はんだSPを塗布する)工程である。本工程は、一例として印刷により行われる。なお、本工程は、はんだ配置工程の一例である。
図3Dは、第4工程の開始時及び1層目塗布時を示す図である。図3Eは、第4工程の2層目塗布時及び3層目塗布時を示す図である。第4工程は、回路パターン層34における各非接合面34B1の全域に蛍光体層36を形成する工程である。本工程は、例えば、転写により、蛍光体層36の1/3の厚みの蛍光体パターン361、362、363を3回積層させて蛍光体層36を配置する。本工程では、一例として、蛍光体層36における絶縁層32の厚み方向外側に向く面の前記厚み方向の位置が、回路パターン層34に接合される各発光素子20の前記厚み方向の中央の位置に位置するように、蛍光体層36を塗布する。別言すると、本工程では、蛍光体層36の厚みが各発光素子20の厚みの半分以下となるように、蛍光体層36を塗布する。ただし、前述した理由により、蛍光体層36の厚みは、各発光素子20の厚みの半分以下であることが好ましい。なお、本工程は、蛍光体層配置工程の一例である。
図3Fは、第5工程の開始時及び終了時を示す図である。第5工程は、蛍光体基板30に複数の発光素子20を搭載する工程である。本工程は、第3工程においてはんだSPが配置された各接合面34A1に複数の発光素子20の各電極を位置合わせした状態ではんだSPを溶かす。その後、はんだSPが冷却されて固化すると、各電極対34A(各接合面34A1)に各発光素子20が接合される。すなわち、本工程は、一例としてリフロー工程により行われる。なお、本工程では、各接合面34A1のはんだSPにフラックスを塗布してから各電極対34Aに各発光素子20を接合させる。このようにすることで、第4工程の前に第3工程を行う本実施形態の場合に、フラックスは各発光素子20にはんだSPを粘着させるように作用する。本工程は、接合工程の一例である。
次に、本実施形態の発光基板10の発光動作について図4を参照しながら説明する。ここで、図4は、本実施形態の発光基板10の発光動作を説明するための図である。
これに対して、蛍光体層36に含まれる蛍光体の発光波長と、発光素子20(CSP)におけるLED22を封止した(又は覆う)蛍光体(蛍光体封止層24)の発光波長とが同じ場合(同じ相関色温度の場合)、本実施形態の発光基板10は、各発光素子20が出射した際の光Lの束を、各発光素子20が出射した際の光Lの波長と同じ波長の光Lを含む光Lの束として上記励起光とともに照射する。
次に、本実施形態の効果について図面を参照しながら説明する。
第1の効果については、本実施形態を以下に説明する比較形態(図5参照)と比較して説明する。ここで、比較形態の説明において、本実施形態と同じ構成要素等を用いる場合は、その構成要素等に本実施形態の場合と同じ名称、符号等を用いることとする。図5は、比較形態の発光基板10Aの発光動作を説明するための図である。比較形態の発光基板10A(複数の発光素子20を搭載する基板30A)は、蛍光体層36を備えていない点以外は、本実施形態の発光基板10(蛍光体基板30)と同じ構成とされている。
なお、蛍光体層36に含まれる蛍光体の発光波長と、発光素子20(CSP)におけるLED22を封止した(又は覆う)蛍光体(蛍光体封止層24)の発光波長とが同じ場合(同じ相関色温度の場合)、本実施形態の発光基板10は、各発光素子20が出射した際の光Lの束を、各発光素子20が出射した際の光Lの波長と同じ波長の光Lを含む光Lの束として上記励起光とともに照射する。この場合、搭載される発光素子20の色度ばらつきを蛍光体層36により緩和する効果も発現できる。
比較形態の場合、図5に示されるように、各発光素子20の配置間隔に起因して外部に照射される光Lに斑が発生する。ここで、光Lの斑が大きいほど、グレアが大きいという。
これに対して、本実施形態の場合、図2Bに示されるように、各接合面34A1の周囲が(全周に亘って)蛍光体層36に囲まれたうえで、さらに隣接する発光素子20同士の間にも蛍光体層36が設けられている。そのため、各接合面34A1の周囲(各発光素子20の周囲)からも励起光が発光される。
したがって、本実施形態によれば、比較形態に比べて、グレアを小さくすることができる。
特に、本効果は、蛍光体層36が絶縁層32の全面に亘って設けられている場合、具体的には、絶縁層32の表面31における蛍光体層36が配置されている領域が表面13の80%以上の領域のような場合に有効である。
また、本実施形態の蛍光体層36は、図1Cに示されるように、隣接する発光素子20に対応する対向面36Aを有する。そのため、本実施形態は、例えば、蛍光体層36上に発光素子20が配置されている場合(図示省略)に比べて、グレアを低減することができる。
また、本実施形態の場合、例えば、蛍光体層36に含まれる蛍光体をEuを含有するCASN蛍光体とし、蛍光体層36をCu製の配線部分34B上に設けている。そのため、例えば、各発光素子20が白色系の光Lを出射した場合に、例えば、蛍光体層36に含まれるCASN蛍光体からの励起光は、下層電極を構成しているCuによる反射により発光効率が向上している(本実施形態の構成では、Cuの光反射効果がある)。そして、本実施形態では、当該効果により、白色系の光Lをより暖かい色系の光L(相関色温度が低温側にシフトした色)に調整することができる。この場合、発光素子20の白色系光に暖色系光を加味することができ、特殊演色係数R9値を上げることができる。本効果は、YAG系白色光(黄色蛍光体)を用いた擬似白色に特に有効となる。
また、本実施形態の第3工程(図3C参照)では、一例として、蛍光体層36の1/3の厚みの蛍光体パターン361、362、363を3回積層させて蛍光体層36を配置する。
したがって、本実施形態によれば、多層構造の蛍光体層36を備える蛍光体基板30を製造することができる。また、別の見方をすると、本実施形態によれば、第3工程での蛍光体パターン361等の積層回数を調整することで、蛍光体層36の膜厚を調整することができる。
また、本実施形態の発光基板10の製造方法では、第4工程(蛍光体層配置工程)は、第3工程(はんだ配置工程)の後に行われる(図3C~図3E参照)。ここで、はんだSPの配置のタイミングは、例えば、第4工程の後の第5工程時(複数の発光素子20を搭載する工程時)も考えられる。
しかしながら、本実施形態のように、第4工程が第3工程の後に行われるため、はんだSPを印刷により簡単に配置することができる。また、回路パターン層34の表面に形成された各溝34Eは、はんだSPのはんだ流れ止めとして機能する点で有効である。
例えば、図6Aに示される変形例(第1変形例)のように、第4工程において、ディスペンサーDP(吐出部の一例)を絶縁層32に相対的に移動させながら、蛍光体層36の1/n(n≧2)の厚みの蛍光体パターンがn回積層するように、ディスペンサーDPに蛍光体を含む液体LQを吐出させて、蛍光体層36を形成するようにしてもよい。
また、例えば、図6Bに示される変形例(第2変形例)のように、第4工程において、液滴吐出ヘッドIJH(吐出部の一例)を絶縁層32に相対的に移動させながら、蛍光体層36の1/n(n≧2)の厚みの蛍光体パターンがn回積層するように、液滴吐出ヘッドIJHに蛍光体を含む液滴DLを吐出させて、蛍光体層36を形成するようにしてもよい。
また、第1変形例及び第2変形例とは異なり、第4工程において、蛍光体層36の1/n(n≧2)の厚みの蛍光体パターンがn回積層するように、1/nの厚みの蛍光体パターンをn回印刷することにより、蛍光体層36を形成するようにしてもよい。この変形例の場合の印刷方法としては、例えばスクリーン印刷による方法がある。ただし、上記蛍光体パターンをn回印刷することにより蛍光体層36を形成することができれば、具体的な印刷方法はスクリーン印刷による方法でなくてもよい。
なお、図6Aの第1変形例のディスペンサーDP又は図6Bの第2変形例の液滴吐出ヘッドIJHを用いて第3工程を場合、例えば、部分的に蛍光体層36の膜厚を調整できる点で有効といえる。
なお、本実施形態の場合、隣接する発光素子20同士の間に蛍光体層36が設けられている(図2B)。また、蛍光体層36のバインダーは、例えばソルダーレジストに含まれるバインダーと同等の絶縁性を有する。すなわち、本実施形態の場合、蛍光体層36がソルダーレジストの機能を果たす。
20 発光素子
30 蛍光体基板(回路基板の一例)
31 表面(一面の一例)
32 絶縁層(絶縁基板の一例)
33 裏面
34 回路パターン層
34A 電極対
34A1 接合面
34B 配線部分
34B1 非接合面
34E 溝
36 蛍光体層
36E 対向面
38 裏面パターン層
DP ディスペンサー(吐出部の一例)
IJH 液滴吐出ヘッド(吐出部の一例)
L 光
MB マザーボード
SP はんだボール、はんだ
Claims (20)
- 一面に少なくとも1つの発光素子が搭載される蛍光体基板であって、
絶縁基板と、
前記絶縁基板の一面に配置され、前記絶縁基板の厚み方向外側に向く平面を有し、前記平面の一部を前記少なくとも1つの電子部品と接合する少なくとも1つの接合面として接合される回路パターン層と、
少なくとも前記平面における前記少なくとも1つの接合面以外の部分とされる少なくとも1つの非接合面に配置され、前記少なくとも1つの発光素子の発光を励起光としたときの発光ピーク波長が可視光領域にある蛍光体を含む蛍光体層と、
を備え、
前記蛍光体層は、積層構造とされている、
蛍光体基板。 - 前記少なくとも1つの発光素子は、複数の発光素子とされ、
前記少なくとも1つの接合面は、複数の接合面とされ、
前記少なくとも1つの非接合面は、複数の非接合面とされ、
前記複数の発光素子は、前記絶縁基板の一面に並べられ、それぞれ、前記複数の接合面に接合されて搭載される、
請求項1に記載の蛍光体基板。 - 前記回路パターン層には、前記少なくとも1つの接合面と前記平面における前記少なくとも1つの接合面以外の部分とされる少なくとも1つの非接合面とを隔てる少なくとも1つの溝が形成されている、
請求項1に記載の蛍光体基板。 - 前記少なくとも1つの発光素子は、複数の発光素子とされ、
前記少なくとも1つの接合面は、複数の接合面とされ、
前記少なくとも1つの非接合面は、複数の非接合面とされ、
前記少なくとも1つの溝は、複数の溝とされ、
前記複数の発光素子は、前記絶縁基板の一面に並べられ、それぞれ、前記複数の接合面に接合されて搭載される、
請求項3に記載の蛍光体基板。 - 請求項1~4のいずれか1項に記載の蛍光体基板と、
前記少なくとも1つの接合面に接合されている少なくとも1つの発光素子と、
を備える発光基板。 - 前記蛍光体層における前記厚み方向外側に向く面の前記厚み方向の位置は、前記少なくとも1つの発光素子における前記厚み方向外側に向く面の位置よりも前記厚み方向内側に位置している、
請求項5に記載の発光基板。 - 前記蛍光体層における前記厚み方向外側に向く面の前記厚み方向の位置は、前記少なくとも1つの発光素子の厚み方向の中央の位置又は当該位置よりも前記厚み方向内側に位置している、
請求項5に記載の発光基板。 - 請求項5~7のいずれか1項に記載の発光基板と、
前記発光素子を発光させるための電力を供給する電源と、
を備える照明装置。 - 絶縁基板、回路パターン層、及び、少なくとも1つの発光素子の発光を励起光としたときの発光ピーク波長が可視光領域にある蛍光体を含む蛍光体層を備える蛍光体基板の製造方法であって、
前記絶縁基板の一面に、配線パターン層を形成するパターン層形成工程と、
前記配線パターン層の一部に前記蛍光体層を形成する蛍光体層形成工程と、
を含み、
前記蛍光体層形成工程では、前記蛍光体層の厚みよりも薄い蛍光体パターンを積層させて、前記蛍光体層を形成する、
蛍光体基板の製造方法。 - 前記蛍光体層形成工程では、転写により、前記蛍光体層の1/n(n≧2)の厚みの蛍光体パターンをn回積層させて前記蛍光体層を形成する、
請求項9に記載の蛍光体基板の製造方法。 - 前記蛍光体層形成工程では、液体を吐出する吐出部を前記絶縁基板に相対的に移動させながら、前記蛍光体層の1/n(n≧2)の厚みの蛍光体パターンがn回積層するように、前記吐出部に前記蛍光体を含む液体を吐出させて、前記蛍光体層を形成する、
請求項9に記載の蛍光体基板の製造方法。 - 前記蛍光体層形成工程では、液滴を吐出する吐出部を前記絶縁基板に相対的に移動させながら、前記蛍光体層の1/n(n≧2)の厚みの蛍光体パターンがn回積層するように、前記吐出部に前記蛍光体を含む液体を液滴として吐出させて、前記蛍光体層を形成する、
請求項9に記載の蛍光体基板の製造方法。 - 前記蛍光体層形成工程では、印刷により、前記蛍光体層の1/n(n≧2)の厚みの蛍光体パターンをn回積層させて前記蛍光体層を形成する、
請求項9に記載の蛍光体基板の製造方法。 - 前記印刷は、スクリーン印刷とされる、
請求項13に記載の蛍光体基板の製造方法。 - 前記蛍光体層形成工程では、前記蛍光体層の厚みよりも薄い蛍光体パターンを積層させて、前記蛍光体層の厚みの半分以下の厚みの前記蛍光体層を形成する、
請求項9~14のいずれか1項に記載の蛍光体基板の製造方法。 - 前記パターン層形成工程の後、かつ、前記蛍光体層形成工程の前に行われる工程であって、前記回路パターン層における前記絶縁基板の厚み方向外側に向く平面に少なくとも1つの溝を形成する溝形成工程と、
前記蛍光体層形成工程の前に行われる工程であって、前記平面における前記少なくとも1つの溝を挟んで一方の部分に少なくとも一つの発光素子を接合させるためのはんだを配置するはんだ配置工程と
を含む請求項9~15のいずれか1項に記載の蛍光体基板の製造方法。 - 請求項9~16のいずれか1項に記載の蛍光体基板の製造方法と、
前記回路パターン層の一部に前記少なくとも1つの発光素子を接合する接合工程と、
を含む発光基板の製造方法。 - 請求項16に記載の蛍光体基板の製造方法と、
前記回路パターン層の一部であって、前記平面における前記少なくとも1つの溝を挟んで他方の部分に前記少なくとも1つの発光素子を接合する接合工程と、
を含む発光基板の製造方法。 - 前記接合工程は、前記蛍光体層形成工程の後に行われる、
請求項17又は18に記載の発光基板の製造方法。 - 前記接合工程では、前記はんだにフラックスを塗布してから前記はんだを溶融させて前記他方の部分に前記少なくとも1つの発光素子を接合させる、
請求項18又は19に記載の発光基板の製造方法。
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| KR102739550B1 (ko) * | 2023-12-04 | 2024-12-05 | 진성호 | 윈도우 기판에 범프를 포함한 led 패키지 및 이의 제조방법 |
| WO2026079404A1 (ja) * | 2024-10-11 | 2026-04-16 | デンカ株式会社 | 蛍光体基板および発光装置 |
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- 2020-02-14 KR KR1020217026685A patent/KR20210131338A/ko not_active Withdrawn
- 2020-02-14 JP JP2021501942A patent/JP7449271B2/ja active Active
- 2020-02-14 CN CN202080015201.2A patent/CN113491017B/zh active Active
- 2020-02-19 TW TW109105245A patent/TWI825278B/zh active
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| US20170084799A1 (en) * | 2014-06-02 | 2017-03-23 | 3M Innovative Properties Company | Led with remote phosphor and shell reflector |
| WO2017077739A1 (ja) * | 2015-11-04 | 2017-05-11 | シャープ株式会社 | 発光体、発光装置、照明装置、および発光体の製造方法 |
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| WO2024063045A1 (ja) * | 2022-09-21 | 2024-03-28 | デンカ株式会社 | 蛍光体基板の製造方法及び発光基板の製造方法 |
| JPWO2024063045A1 (ja) * | 2022-09-21 | 2024-03-28 | ||
| JP7818712B2 (ja) | 2022-09-21 | 2026-02-20 | デンカ株式会社 | 蛍光体基板の製造方法及び発光基板の製造方法 |
| KR102739550B1 (ko) * | 2023-12-04 | 2024-12-05 | 진성호 | 윈도우 기판에 범프를 포함한 led 패키지 및 이의 제조방법 |
| WO2025121768A1 (ko) * | 2023-12-04 | 2025-06-12 | 진성호 | 윈도우 기판에 범프를 포함한 led 패키지 및 이의 제조방법 |
| WO2026079404A1 (ja) * | 2024-10-11 | 2026-04-16 | デンカ株式会社 | 蛍光体基板および発光装置 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPWO2020170970A1 (ja) | 2021-12-16 |
| KR20210131338A (ko) | 2021-11-02 |
| JP7449271B2 (ja) | 2024-03-13 |
| CN113491017B (zh) | 2024-11-15 |
| TW202039791A (zh) | 2020-11-01 |
| CN113491017A (zh) | 2021-10-08 |
| TWI825278B (zh) | 2023-12-11 |
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