WO2020168520A1 - 编码器、编码系统和编码方法 - Google Patents

编码器、编码系统和编码方法 Download PDF

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WO2020168520A1
WO2020168520A1 PCT/CN2019/075746 CN2019075746W WO2020168520A1 WO 2020168520 A1 WO2020168520 A1 WO 2020168520A1 CN 2019075746 W CN2019075746 W CN 2019075746W WO 2020168520 A1 WO2020168520 A1 WO 2020168520A1
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image
circuit
encoded
encoding
image block
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PCT/CN2019/075746
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English (en)
French (fr)
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张健华
韩彬
赵文军
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深圳市大疆创新科技有限公司
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Priority to PCT/CN2019/075746 priority Critical patent/WO2020168520A1/zh
Priority to CN201980005009.2A priority patent/CN111264062A/zh
Priority to JP2020021387A priority patent/JP7063925B2/ja
Publication of WO2020168520A1 publication Critical patent/WO2020168520A1/zh
Priority to US17/198,105 priority patent/US20210203952A1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/102—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or selection affected or controlled by the adaptive coding
    • H04N19/124—Quantisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/134—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or criterion affecting or controlling the adaptive coding
    • H04N19/146—Data rate or code amount at the encoder output
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/134—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or criterion affecting or controlling the adaptive coding
    • H04N19/146—Data rate or code amount at the encoder output
    • H04N19/147—Data rate or code amount at the encoder output according to rate distortion criteria
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/169—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding
    • H04N19/17—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object
    • H04N19/174—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a slice, e.g. a line of blocks or a group of blocks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/169—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding
    • H04N19/17—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object
    • H04N19/176—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/169—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding
    • H04N19/184—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being bits, e.g. of the compressed video stream
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/70—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by syntax aspects related to video coding, e.g. related to compression standards

Definitions

  • This application relates to the field of image decoding, and more specifically, to an encoder, an encoding system, and an encoding method.
  • JPEG Joint Photographic Experts Group
  • JPEG 2000 Joint Photographic Experts Group 2000 are commonly used image coding standards.
  • JPEG 2000 adopts wavelet transform and performs entropy coding based on optimized intercepted block coding with optimized truncation (EBCOT), which has a higher compression ratio than JPEG, and supports progressive download and display.
  • EBCOT optimized intercepted block coding with optimized truncation
  • the code rate control algorithm of the traditional JPEG 2000 encoder performs a global optimization algorithm for the entire frame of image, which requires high system bandwidth.
  • the present application provides an encoder, an encoding system, and an encoding method, which can reduce the requirement for system bandwidth in the encoding process.
  • an encoder including: a first interface circuit for reading pre-generated statistical information of an image to be encoded from an external memory; a code rate control circuit for Statistical information, determining the target code rate of the image block in the image to be encoded; a first encoding circuit, configured to perform tier-1 encoding on the code block of the image block to obtain the code stream of the image block; second The encoding circuit is configured to perform tier-2 encoding on the bit stream of the image block according to the target bit rate, so as to cut the bit stream of the image block.
  • an encoding system including: a preprocessing circuit for calculating statistical information of the image to be encoded; a memory for storing the image to be encoded and the statistical information; as described in the first aspect
  • the encoder for reading the image to be encoded and the statistical information from the memory.
  • an encoding method which includes: reading pre-generated statistical information of an image to be encoded from an external memory; and determining the size of image blocks in the image to be encoded according to the statistical information of the image to be encoded Target code rate; perform tier-1 encoding on the code block of the image block to obtain the code stream of the image block; perform tier-2 encoding on the code stream of the image block according to the target code rate to cut off all The code stream of the image block.
  • a computer-readable storage medium is provided, and instructions are stored in the computer-readable storage medium, which when run on a computer, cause the computer to execute the method described in the third aspect.
  • a computer program product containing instructions, which when run on a computer, causes the computer to execute the method described in the third aspect.
  • the statistical information of the image blocks in the image to be encoded is pre-calculated, and the bit stream of the image block is truncated according to the statistical information, thereby relatively independent bit rate control of each image block to reduce the encoder's requirement on system bandwidth.
  • Figure 1 is a coding framework diagram of JPEG 2000.
  • Fig. 2 is a schematic structural diagram of an encoding system provided by an embodiment of the present application.
  • Fig. 3 is a schematic structural diagram of a preprocessing circuit provided by an embodiment of the present application.
  • Fig. 4 is a schematic structural diagram of an encoder provided by an embodiment of the present application.
  • Figure 5 is a schematic diagram of the principle of wavelet transform of image blocks.
  • Fig. 6 is a schematic structural diagram of a decoder provided by an embodiment of the present application.
  • Fig. 7 is a schematic flowchart of an encoding method provided by an embodiment of the present application.
  • This application can be applied to the field of image coding and decoding, video coding and decoding, hardware video coding and decoding, dedicated circuit video coding and decoding, and real-time video coding and decoding.
  • the encoder provided in this application can be used to perform lossy compression (lossy compression) on images, and can also be used to perform lossless compression (lossless compression) on images.
  • the lossless compression can be a visually lossless compression (visually lossless compression) or a mathematically lossless compression (mathematically lossless compression).
  • the coding framework of JPEG 2000 may include a preprocessing module 12, a transformation module 14, a quantization module 16, and an EBCOT module 18.
  • the preprocessing module 12 may include a component transformation (component transformation) module 122 and a direct current level shift module 124.
  • the component transformation module 122 may perform a certain transformation on the components of the image to reduce the correlation between the components. For example, the component transformation module 122 can transform each component of the image from the current color domain to another color domain.
  • the component transformation module 122 may support multiple color transformation modes. Therefore, the component transformation module 122 may sometimes be referred to as a multi-mode color transform (MCT) module.
  • MCT multi-mode color transform
  • the component transform module 122 may support irreversible color transform (ICT) or reversible color transform (RCT). It should be noted that the component transformation module 122 is optional. In the actual encoding process, it is also possible to directly perform subsequent processing without performing component transformation on the image.
  • the DC level shifting module 124 can be used to shift the center of the component values so that the component values are symmetrically distributed with respect to 0, so as to facilitate subsequent transformation operations.
  • the transform module 14 uses wavelet transform to transform each tile in the image to obtain wavelet coefficients of subbands.
  • the embodiment of the present application does not specifically limit the size of the image block, for example, it may be 512 ⁇ 512 (unit is pixel).
  • the quantization module 16 may be used to quantize the wavelet coefficients of the subbands to obtain the quantized wavelet coefficients of the subbands.
  • the EBCOT module 18 is the entropy coding module of JEPG 2000, and belongs to the core module of JEPG 2000.
  • the EBCOT module 18 may include a tier-1 encoding module 182, a tier-2 encoding module 184, and a rate control module 186.
  • the tier-1 encoding module 182 can be used to perform tier-1 encoding on a code block (the subband can be further divided into multiple independent code blocks).
  • Tier-1 coding can include bit-plane coding and arithmetic coding.
  • the tier-2 encoding module 184 is mainly responsible for the organization of the code stream. For example, the code stream of the code block can be truncated according to the target code rate provided by the code rate control module 186.
  • JPEG 2000 mainly uses post-compression rate-distortion optimization (PCRD) for rate control.
  • PCD post-compression rate-distortion optimization
  • the traditional JPEG 2000 technology calculates the optimal set of cut-off points of the code stream of all code blocks in a frame of image by traversal.
  • the traditional JPEG 2000 technology performs bit rate control for the entire frame of image.
  • the hardware encoder if you want to control the rate of the entire frame of image, a large amount of intermediate data will be generated. In the case of limited on-chip cache, it will inevitably require a large amount of data between the encoder and external memory (such as memory). Data interaction requires high system bandwidth.
  • the encoding system 2 includes a preprocessing circuit 4, a signal processing device 6 and an encoder 7.
  • the preprocessing circuit 4 may include a calculation circuit 42.
  • the calculation circuit 42 can be used to calculate the statistical information of the image to be encoded.
  • the image to be encoded may be an image collected by the sensor 3 or an image input by other devices.
  • the format of the image to be encoded can be RAW or other formats, such as RGB.
  • the function of the preprocessing circuit 4 may be performed by an image signal processing (ISP) subsystem (the ISP subsystem is represented by the dashed box on the left in FIG. 2).
  • ISP image signal processing
  • the statistical information of the image to be encoded may be information that can be used to control the rate of the tile in the image to be encoded. Therefore, in some embodiments, the statistical information of the image to be encoded may also be referred to as the image to be encoded. Block rate control information.
  • the statistical information of the image to be encoded may include one or more of the following information of the image blocks in the image to be encoded: complexity, activity, and texture.
  • the complexity of the image block may be defined or calculated based on the amplitude of the high-frequency components of the pixels in the image block.
  • the complexity of the image block may be the cumulative sum of the amplitudes of the high frequency components of each pixel in the image block area.
  • the coded code stream (or the number of bits consumed for coding) corresponding to the image block area with higher complexity will be correspondingly larger.
  • high frequency components can be obtained through filtering operations, and then the complexity of the image block can be calculated.
  • the complexity of the image block can be defined or calculated based on the mean-square error (MSE) of the pixel value in the image block.
  • MSE mean-square error
  • the complexity of the image block can also be defined in other ways, or a combination of the above definition ways, which is not limited in the embodiment of the present application.
  • the preprocessing circuit 4 may further include a component transformation circuit 44.
  • the component transformation circuit 44 can be used to perform the component transformation operations described above. In the process of calculating the statistical information of the image to be coded, the component transformation of the image to be coded is equivalent to stripping out the operations originally required in the encoder 7 and putting it in the preprocessing circuit 4 for execution, thereby reducing the complexity of the encoder 7 degree.
  • the preprocessing circuit 4 may not perform the component transformation operation, but the encoder 7 still performs it.
  • the processing result of the preprocessing circuit 4 (which may include the preprocessed image to be encoded and the statistical information of the image to be encoded) can be stored in the external memory 5.
  • the memory 5 may be a double data rate (DDR) memory.
  • the encoder 7 may be a hardware encoder supporting the JPEG 2000 standard. As shown in FIG. 4, the encoder 7 may include a first interface circuit 71, a conversion circuit 72, a quantization circuit 73, a first encoding circuit 74, a rate control circuit 75, a second encoding circuit 76 and a code stream writing circuit 77.
  • the first interface circuit 71 can be used to read the pre-generated statistical information of the image to be encoded from the external memory 5.
  • the first interface circuit 71 can also be used to read the image block of the image to be encoded (the tile may be any image block in the image to be encoded).
  • the first interface circuit 71 can use a specific addressing mode to directly read the image blocks of the image to be coded stored in the memory 5 without segmenting the image to be coded.
  • the image to be encoded may be stored in row order in the memory 5.
  • the first interface circuit 71 may calculate the storage location of each image block according to the position of the image to be encoded in the memory 5, and then read the corresponding Image block; or, the image to be encoded can be stored in the memory 5 as image blocks, and the first interface circuit 71 can read the image blocks according to the storage order of the image blocks.
  • the first interface circuit 71 may read image blocks from the memory 5 in a direct memory access (DMA) manner.
  • DMA direct memory access
  • the first interface circuit 71 may transmit the statistical information of the image to be encoded as rate control information to the rate control circuit 75 for the rate control circuit 75 to perform rate control on the encoding process.
  • the first interface circuit 71 may also be used to perform a DC level shift on the image block, that is, to implement the function of the above-mentioned DC level shift module 124.
  • the transform circuit 72 can be used to perform the operation performed by the transform module 14 above, that is, perform wavelet transform on the image block. After the image block undergoes wavelet transformation, many subbands can be obtained. After wavelet transformation, the wavelet coefficients of the image block can be obtained, which can refer to the wavelet coefficients of these sub-bands.
  • the quantization circuit 73 can be used to quantize the wavelet coefficients to obtain quantized fractional coefficients or quantized subband wavelet coefficients.
  • part or all of operations such as transformation and quantization may be delivered to the signal processing device 6 shown in FIG. 2 for execution.
  • the embodiment of the present application does not specifically limit the type of the signal processing device 6, for example, it may be a digital signal processor (digital signal processor, DSP), or a graphics processing unit (graphics processing unit, GPU).
  • DSP digital signal processor
  • GPU graphics processing unit
  • part of the operations in the transform operation can be handed over to the signal processing device 6 for execution.
  • the quantization circuit 73 in the encoder 7 can either receive the transform coefficients (wavelet coefficients) output by the transform circuit 72 or the signal processing device 6
  • the output transform coefficients (wavelet coefficients) can not only simplify the structure of the encoder 7 but also improve the parallelism of the encoding process.
  • all transform operations can be performed by the signal processing device 6 and the encoder 7 can perform quantization operations.
  • the signal processing device 6 may also be responsible for all transformation and quantization operations, and the encoder 7 may directly use the quantized result for encoding.
  • the signal processing device 6 can directly read the image blocks of the image to be encoded stored in the memory 5 by using a specific addressing mode, without segmenting the image to be encoded.
  • the image to be encoded can be stored in the memory 5 in row order, and the signal processing device 6 can calculate the storage location of each image block according to the position of the image to be encoded in the memory 5, and then read the corresponding image in a jump address mode
  • the image to be encoded can be stored in image blocks in the memory 5, and the signal processing device 6 can read the image blocks according to the storage order of the image blocks.
  • the signal processing device 6 can read the image block from the memory 5 in a DMA manner.
  • the signal processing device 6 participates in the encoding process of the image block
  • the signal processing device 6 and the encoder 7 can be regarded as the encoding subsystem of the entire system on chip (SOC) (the encoding subsystem is represented by the right side in Figure 2). The dashed box indicates).
  • SOC system on chip
  • the first encoding circuit 74 can be used to perform tier-1 encoding on the code block of the image block to obtain the code stream of the image block.
  • the wavelet coefficients of the subbands are obtained after transformation and quantization.
  • a subband can be divided into one or more code blocks that can be independently coded. Therefore, the code block of the image block refers to the image block.
  • the code block of the subband is not limited to the code block.
  • the first encoding circuit 74 may be used to perform operations performed by the tier-1 encoding module 182 in FIG. 1, such as bit-plane encoding and arithmetic encoding on the code block.
  • the code block may also be preprocessed, for example, the sign bit and the absolute value of the wavelet coefficient are separated.
  • the first encoding circuit 74 encodes the code block into a code stream, it can also perform post-processing on the code block. For example, the code stream can be spliced together for use by the second encoding circuit 75.
  • the code rate control circuit 75 may be used to determine the target code rate (target size) of the image block in the image to be encoded according to the statistical information of the image to be encoded.
  • the rate control circuit 75 may assign weights to each image block according to the complexity of each image block. The higher the complexity of the image block, the greater the weight.
  • the code rate control circuit 75 can calculate the target code rate of the image block according to the weight of each image block and current network conditions (such as network bandwidth), so that the larger the weight of the image block, the higher the target code rate.
  • the statistical information of the image to be encoded output by the preprocessing circuit 4 may include the weight of each image block, and the code rate control circuit 75 may directly use the weight of the image block to calculate the target code rate.
  • the second encoding circuit 76 can be used to implement the function of the tier-2 encoding module 184 mentioned above.
  • the second encoding circuit 76 may be used to perform tier-2 encoding on the bit stream of the image block according to the target bit rate, so as to cut the bit stream of the image block.
  • the second encoding circuit 76 may include a rate-distortion calculation circuit 762 (or slopemaker) and a truncation circuit 764 (or truncator).
  • the rate-distortion calculation circuit 762 can be used to calculate the rate-distortion slope of the code stream output by the first encoding circuit 74.
  • the rate-distortion calculation circuit 762 may calculate the rate-distortion slope (distortion) based on the rate and distortion of each code stream (that is, the code stream (pass) of each code block) output by the first encoding circuit 74. slope).
  • the rate-distortion slope can be used to evaluate the contribution of the current code block to the entire image block.
  • the rate-distortion slope can be used for subsequent code stream organization, such as code stream layering and truncation.
  • the truncation circuit 764 can be used to process the bit stream of the image block according to the target bit rate and the rate-distortion slope. For example, the truncation circuit 764 can be used to cut the bit stream of the image block according to the target bit rate and the rate-distortion slope. Further, the truncation circuit 764 can also be used to reorganize the code stream, layer the code stream, and so on. In addition, in some embodiments, the truncation circuit 764 may also be used to generate header information of the code stream, and transmit the header information together with the code stream to the subsequent code stream write circuit 77.
  • the code stream write circuit 77 can be used to receive the organized code stream output by the truncation circuit 764 and write the code stream to an external memory. For example, it can be written to an external memory via the bus.
  • the bus may be, for example, an advanced extensive interface (AXI) bus.
  • the code stream writing circuit 77 may also add information such as a tile header to the code stream.
  • the rate control circuit 75 may also be used to generate state information of the rate control buffer (or buffer size) according to the statistical information of the image block.
  • the first encoding circuit 74 can also be used to control the tier-1 encoding according to the state information of the code rate control buffer.
  • the status information of the buffer can be used by the first encoding circuit 74 to pre-truncate the code stream. For example, the first encoding circuit 74 may delete code streams that exceed a predetermined size according to the status information of the buffer, or delete code streams that do not meet the requirements. Therefore, the status information of the buffer can sometimes be called pre-truncation information.
  • the rate control circuit 75 may also receive feedback on the size of the code stream actually encoded by the first encoding circuit 74, and update the pre-truncation information of the image block at each resolution.
  • the encoder 7 may also include an interface circuit (not shown in the figure) for software configuration, through which the information in the register inside the encoder 7 can be configured or changed, thereby Control the encoding mode of the encoder 7.
  • the embodiment of the present application pre-calculates the statistical information of the image blocks in the image to be encoded, and cuts the bit stream of the image block according to the statistical information, so that each image block is relatively independent of the rate control, without all the codes in the image to be encoded
  • the overall optimization of the block will not generate a large amount of intermediate data. Therefore, the embodiment of the present application can reduce the requirement of the encoder on the system bandwidth. The entire encoding process of the image to be encoded can even be carried out completely on the chip.
  • the traditional JPEG 2000 encoding system can be understood as an online encoding system.
  • the online encoding system will directly input the image to be encoded (the image collected by the sensor 3 in FIG. 2) into the encoder, and store it in the memory 5 after the encoding is completed.
  • the encoding system provided by the embodiments of this application first preprocesses the image to be encoded, obtains the statistical information of the image to be encoded (which can be used for rate control), and stores the image to be encoded after preprocessing Memory 5. Then, the encoder 7 can read and relatively independently process each image block in the image to be encoded in units of image blocks.
  • the encoding system provided in this embodiment of the present application may be referred to as an offline encoding system.
  • a buffer (on-chip buffer) may be set inside or at the output end of the conversion circuit 72 to buffer the intermediate results output by the conversion circuit 72.
  • a buffer (on-chip buffer) may be provided inside or at the output end of the truncation circuit 764 for buffering the intermediate results output by the truncation circuit 764.
  • the image blocks in the embodiments of the present application can be relatively independently coded, so a large amount of intermediate data will not be generated, and the above-mentioned buffer can be used to buffer some intermediate results generated on the chip.
  • the two adjacent stages in the encoder 7 may be rate matched.
  • the circuits with slower processing speeds in adjacent two-stage circuits can be set to a multi-channel parallel structure; then, a certain mechanism can be used to control the data transmission between the two, so that the two-stage circuits are fully pipelined.
  • the rates of the quantization circuit 73 and the first encoding circuit 74 may be matched.
  • the first encoding circuit 74 may include a plurality of encoding units 742.
  • the multiple coding units 742 can be used to perform tier-1 coding in parallel on each code block output by the quantization circuit 73, that is, the first coding circuit 74 can use a multi-path parallel structure to perform tier-1 coding.
  • the quantization circuit 73 and the plurality of encoding units 742 may adopt a group arbitration or free arbitration method to determine the encoding unit 742 corresponding to the intermediate result output by the quantization circuit 73.
  • Group arbitration refers to always assigning the code block of a certain frequency component output by the quantization circuit 73 to a fixed set of coding units (each group of coding units can be composed of several coding units), while free arbitration refers to the output of the quantization circuit 73
  • Each code block of may be received by one of the multiple parallel coding units.
  • the advantage of the packet arbitration method is that the circuit connection is relatively simple in hardware implementation, while the free arbitration method can improve the utilization efficiency of the coding unit in some cases.
  • the rates of the first encoding circuit 74 and the rate-distortion slope calculation circuit 762 may be matched.
  • the rate-distortion calculation circuit 762 may include a plurality of rate-distortion slope calculation modules.
  • the multiple rate-distortion slope calculation modules can be used to calculate the rate-distortion slope of the code stream output by the first encoding circuit 74 in parallel.
  • the first encoding circuit 74 and the rate-distortion calculation circuit 762 may also adopt a group arbitration or free arbitration method to determine the rate-distortion calculation module corresponding to the intermediate result output by the first encoding circuit 74.
  • one rate-distortion calculation module may correspond to a group of coding units in the first coding circuit 74.
  • a rate-distortion calculation module corresponding to a group of encoding units can make the design of the entire circuit easier.
  • the transform circuit 72 usually divides the image block into a number of 64x64 blocks for transformation. After each transformation, four 32x32 intermediate results are generated, namely 4 Code blocks. Among them, if it is the last transformation, 4 code blocks will be output at the same time. In other cases, 3 code blocks will be output (that is, the code blocks corresponding to the frequency components of HL, LH, and HH).
  • the encoding unit 742 corresponding to each code block can be determined by the group arbitration method.
  • the first encoding circuit 74 includes three groups of encoding units: group0, group1, and group2.
  • group0 includes encoders u0-u3;
  • group1 includes encoders u4-u7;
  • group2 includes encoders u8-u11.
  • Each image block can include 4 components (such as R, Gr, Gb, B).
  • the mapping between the code block of each component and the above 3 groups of coding units can be mapped as shown in the following table:
  • the code blocks to be coded at t6 can be sent to the coding units u2 and u3 of group 0 in advance; at t5, the coding units in group 1 Coding units u5-u7 are in the idle state. At this time, the code blocks to be coded at t6 can be sent to the coding units u5-u7 of group1 in advance; at t5, the coding units u9-u11 in group2 are in the idle state.
  • the code blocks to be coded at t6 can be sent to the coding units u9-u11 of group2 in advance; in this way, the code blocks between components 0 and 2 and components 1, 3 can be efficiently coded in a ping-pong manner.
  • three rate-distortion calculation modules can be set in the rate-distortion slope calculation circuit 762, and a group arbitration mechanism can be adopted between the 12 coding units and the three rate-distortion calculation modules: u0 ⁇ u3 can be combined with the first rate-distortion calculation module Interconnection, u4 ⁇ u7 can be interconnected with the second rate-distortion calculation module, and u8 ⁇ u11 can be interconnected with the third rate-distortion calculation module.
  • the structure of the encoder 7 provided in the embodiment of the present application has been exemplified above in conjunction with FIG. 4.
  • the structure of the decoder 8 provided in the embodiment of the present application will be described below with reference to FIG. 6 as an example.
  • the decoder 8 may include one or more of the following circuits: code stream reading circuit 81, code stream analysis circuit 82, decoding circuit 83, inverse quantization circuit 84, inverse transform circuit 85, output circuit 86.
  • the code stream reading circuit 81 can be used to read the code stream to be decoded.
  • the code stream reading circuit 81 can, for example, use an advanced extensible interface (AXI) to read the code stream to be decoded from an external memory (such as a memory).
  • AXI advanced extensible interface
  • the code stream parsing circuit 82 may also be referred to as a code stream header parser circuit (header parser).
  • the code stream analysis circuit 82 can parse various types of header information in the code stream, and separate parameters and code stream data related to decoding therefrom for use by the decoding circuit 83 at a later stage.
  • the decoding circuit 83 may include one decoding unit or parallel multiple decoding units (the specific number can be configured according to actual needs, for example, 8 parallel decoding units can be configured). Each decoding unit in the decoding circuit 83 can independently decode a code block.
  • a preprocessing circuit may be provided before the decoding circuit 83.
  • the preprocessing circuit can be used to distribute the decoding parameters, code stream data, etc. output by the code stream analysis circuit 82 to parallel multiple decoding units.
  • a post-processing circuit may also be provided.
  • the post-processing circuit can be used to reorganize the decoded data output by the decoding circuit 83 and output the organized data to the subsequent circuit.
  • the inverse quantization circuit 84 can be used to inverse quantize the data decoded by the decoding circuit 83.
  • the inverse transform circuit 85 can be used to inversely transform the data output by the inverse quantization circuit 84.
  • the inverse transform can be discrete wavelet inverse transform.
  • the output circuit 86 can be used to write the data output by the inverse conversion circuit 85 into an external memory.
  • the data output from the inverse conversion circuit 85 can be written into an external memory through AXI.
  • the decoder 8 may also include a software configuration interface.
  • the software configuration interface can configure or change the information in the internal registers of the decoder 8 to control the decoding mode of the decoder 8.
  • the decoder 8 provided in the embodiment of the present application may perform decoding in units of tiles. After the decoder 8 reads the code stream from the external memory, the entire decoding process can be performed on the chip (because the embodiment of the present application performs decoding in units of image blocks, the intermediate data is not too large and can be temporarily stored through the on-chip buffer), No interaction with external memory to save system bandwidth. In addition, all levels of circuits in the decoder 8 can work in a pipeline manner to improve decoding efficiency.
  • the embodiment of the present application also provides an encoding method.
  • the encoding method can be executed by the encoder 7 or encoding system mentioned above. As shown in Figure 7, the encoding method includes steps S72-S78.
  • step S72 the pre-generated statistical information of the image to be encoded is read from the external memory.
  • step S74 the target code rate of the image block in the image to be encoded is determined according to the statistical information of the image to be encoded.
  • step S76 tier-1 coding is performed on the code block of the image block to obtain the code stream of the image block.
  • step S78 the code stream of the image block is tier-2 encoded according to the target code rate, so as to cut the code stream of the image block.
  • the method in FIG. 7 may further include: generating state information of the rate control buffer according to the statistical information of the image block; and controlling the tier-1 encoding according to the state information of the rate control buffer.
  • the method in FIG. 7 may further include: reading the image block from the memory.
  • the method in FIG. 7 may further include: performing a DC level shift on the image block.
  • the method in FIG. 7 may further include: quantizing the wavelet coefficients of the image block.
  • step S76 may include: using multiple coding units to perform tier-1 coding on the code blocks of the image block in parallel.
  • the multiple coding units include multiple groups of coding units, wherein the coding units of different groups are used to perform tier-1 coding on code blocks of different frequency components of the image block.
  • the method in FIG. 7 may further include: performing wavelet transform on the image block.
  • step S78 may include: calculating the rate-distortion slope of the tier-1 encoded bitstream; and truncating the bitstream of the image block according to the target bitrate and the rate-distortion slope.
  • calculating the rate-distortion slope of the tier-1 encoded code stream may include: using a plurality of rate-distortion slope calculation modules to calculate the rate-distortion slope of the tier-1 encoded code stream in parallel.
  • At least part of the transform coefficients or quantized coefficients of the image to be encoded is generated based on an external signal processing device.
  • the method in FIG. 7 may further include: receiving the transform coefficients or quantized coefficients generated by the signal processing device.
  • the statistical information of the image to be encoded includes the complexity of image blocks in the image to be encoded.
  • the method of FIG. 7 may further include: calculating the statistical information of the image to be encoded; storing the statistical information of the image to be encoded in the memory .
  • the method in FIG. 7 may further include: performing component transformation on the image to be coded.
  • the computer program product includes one or more computer instructions.
  • the computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices.
  • the computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from a website, computer, server, or data center.
  • the computer-readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server or a data center integrated with one or more available media.
  • the usable medium may be a magnetic medium (for example, a floppy disk, a hard disk, a magnetic tape), an optical medium (for example, a digital video disc (DVD)), or a semiconductor medium (for example, a solid state disk (SSD)), etc.
  • the disclosed system, device, and method may be implemented in other ways.
  • the device embodiments described above are merely illustrative.
  • the division of the units is only a logical function division, and there may be other divisions in actual implementation, for example, multiple units or components can be combined or It can be integrated into another system, or some features can be ignored or not implemented.
  • the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, and may be in electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the solutions of the embodiments.
  • the functional units in the various embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit.

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Abstract

一种编码器、编码系统和编码方法。该编码器包括：第一接口电路（71），用于从外部的存储器中读取预先生成的待编码图像的统计信息；码率控制电路（75），用于根据待编码图像的统计信息，确定待编码图像中的图像块的目标码率；第一编码电路（74），用于对图像块的码块进行tier-1编码，得到图像块的码流；第二编码电路（76），用于根据目标码率对图像块的码流进行tier-2编码，以截断图像块的码流。该系统预先计算待编码图像中的图像块的统计信息，并根据该统计信息截断图像块的码流，可以降低编码器对系统带宽的要求。

Description

编码器、编码系统和编码方法
版权申明
本专利文件披露的内容包含受版权保护的材料。该版权为版权所有人所有。版权所有人不反对任何人复制专利与商标局的官方记录和档案中所存在的该专利文件或者该专利披露。
技术领域
本申请涉及图像解码领域，更为具体地，涉及一种编码器、编码系统和编码方法。
背景技术
联合图像专家小组(joint photographic experts group，JPEG)、JPEG 2000是常用的图像编码标准。
JPEG 2000采用小波变换，并基于优化截取内嵌码块编码(embedded block coding with optimized truncation，EBCOT)进行熵编码，具有比JPEG更高的压缩比，并支持渐进式下载和显示。
传统JPEG 2000的编码器的码率控制算法针对整帧图像进行全局优化算法，对系统带宽的要求较高。
发明内容
本申请提供一种编码器、编码系统和编码方法，能够降低编码过程对系统带宽的要求。
第一方面，提供一种编码器，包括：第一接口电路，用于从外部的存储器中读取预先生成的待编码图像的统计信息；码率控制电路，用于根据所述待编码图像的统计信息，确定所述待编码图像中的图像块的目标码率；第一编码电路，用于对所述图像块的码块进行tier-1编码，得到所述图像块的码流；第二编码电路，用于根据所述目标码率对所述图像块的码流进行tier-2编码，以截断所述图像块的码流。
第二方面，提供一种编码系统，包括：预处理电路，用于计算所述待编码图像的统计信息；存储器，用于存储所述待编码图像和所述统计信息；如 第一方面所述的编码器，用于从所述存储器中读取所述待编码图像和所述统计信息。
第三方面，提供一种编码方法，包括：从外部的存储器中读取预先生成的待编码图像的统计信息；根据所述待编码图像的统计信息，确定所述待编码图像中的图像块的目标码率；对所述图像块的码块进行tier-1编码，得到所述图像块的码流；根据所述目标码率对所述图像块的码流进行tier-2编码，以截断所述图像块的码流。
第四方面，提供一种计算机可读存储介质，所述计算机可读存储介质中存储有指令，当其在计算机上运行时，使得计算机执行第三方面所述的方法。
第五方面，提供一种包含指令的计算机程序产品，当其在计算机上运行时，使得计算机执行第三方面所述的方法。
预先计算待编码图像中的图像块的统计信息，并根据该统计信息截断图像块的码流，从而对各个图像块进行相对独立地码率控制，以降低编码器对系统带宽的要求。
附图说明
图1是JPEG 2000的编码框架图。
图2是本申请实施例提供的编码系统的结构示意图。
图3是本申请实施例提供的预处理电路的结构示意图。
图4是本申请实施例提供的编码器的结构示意图。
图5是图像块的小波变换的原理示意图。
图6是本申请实施例提供的解码器的结构示意图。
图7是本申请实施例提供的编码方法的示意性流程图。
具体实施方式
本申请可应用于图像编解码领域、视频编解码领域、硬件视频编解码领域、专用电路视频编解码领域、实时视频编解码领域。
本申请提供的编码器可用于对图像进行有损压缩(lossy compression)，也可用于对图像进行无损压缩(lossless compression)。该无损压缩可以是视觉无损压缩(visually lossless compression)，也可以是数学无损压缩(mathematically lossless compression)。
为了便于理解，先对JPEG 2000的编码框架进行简单介绍。
如图1所示，JPEG 2000的编码框架可以包括预处理模块12、变换模块14、量化模块16、EBCOT模块18。
预处理模块12可以包括分量变换(component transformation)模块122和直流电平平移(direct current level shift)模块124。
分量变换模块122可以对图像的分量进行某种变换以降低各分量之间的相关性。例如，分量变换模块122可以将图像的各个分量从当前颜色域转换至另一颜色域。
分量变换模块122可以支持多种颜色变换模式，因此，分量变换模块122有时也可称为多模颜色变换(multi-mode color transform，MCT)模块。例如，分量变换模块122可支持不可逆颜色变换(irreversible color transform，ICT)或可逆颜色变换(reversible color transform，RCT)。需要说明的是，分量变换模块122是可选的，实际编码过程中，也可以不对图像进行分量变换，直接进行后续处理。
直流电平平移模块124可用于对分量值进行中心平移，使得分量值关于0对称分布，以便于后续的变换操作。
变换模块14采用小波变换对图像中的各个图像块(tile)进行变换，得到子带的小波系数。本申请实施例对图像块的尺寸不做具体限定，例如可以是512×512(单位为像素)。
量化模块16可用于对子带的小波系数进行量化，得到量化后的子带的小波系数。
EBCOT模块18是JEPG 2000的熵编码模块，属于JEPG 2000的核心模块。
EBCOT模块18可以包括tier-1编码模块182、tier-2编码模块184和码率控制模块186。tier-1编码模块182可用于对码块(子带可以进一步划分成独立的多个码块(codeblock))进行tier-1编码。tier-1编码可以包括比特平面编码和算术编码。tier-2编码模块184主要负责码流的组织工作，如可以根据码率控制模块186提供的目标码率对码块的码流进行截断等处理。
JPEG 2000主要采用压缩后率失真优化算法(post-compression rate-distortion optimization，PCRD)进行码率控制。传统JPEG 2000技术在进行码率控制时，通过遍历的方式计算一帧图像中的所有码块的码流的最优 截断点集合。换句话说，传统JPEG 2000技术针对整帧图像进行码率控制。对于硬件编码器而言，如果希望针对整帧图像进行码率控制，会产生大量的中间数据，在片上缓存有限的情况下，势必需要编码器与外部的存储器(如内存)之间进行大量的数据交互，对系统带宽的要求较高。
下面将结合图2至图6，对本申请中的技术方案进行描述。
本申请实施例提供一种编码系统。如图2所示，该编码系统2包括预处理电路4、信号处理装置6以及编码器7。
如图3所示，预处理电路4可以包括计算电路42。计算电路42可用于计算待编码图像的统计信息。该待编码图像可以是由传感器3采集到的图像，也可以是其他设备输入的图像。该待编码图像的格式可以是RAW，也可以是其他格式，如RGB。预处理电路4的功能可以由图像信号处理(image signal processing，ISP)子系统执行(该ISP子系统由图2中的位于左侧的虚框表示)。
待编码图像的统计信息可以是能够用于对待编码图像中的图像块(tile)进行码率控制的信息，因此，在某些实施例中，待编码图像的统计信息也可以称为待编码图像块的码率控制信息。待编码图像的统计信息可以包括待编码图像中的图像块的以下信息中的一种或多种：复杂度、活动性、纹理。
待编码图像的统计信息的计算方式可以有多种。以待编码图像的统计信息为待编码图像中的图像块的复杂度为例，可以基于图像块内像素点的高频分量的幅值定义或计算图像块的复杂度。比如，图像块的复杂度可以为图像块区域内每个像素点的高频分量的幅值的累加和。当图像块的纹理较复杂，那么相应的高频分量的幅值的累加和也会相应较大，可以认为该图像块的复杂度较高。根据图像的编码理论，复杂度较高的图像块区域对应的编码后的码流(或编码所需消耗的比特数)也会相应较大。具体地，可以基于图像块区域内的像素点的像素值，通过滤波操作，得到高频分量，进而计算图像块的复杂度。
又如，可以基于图像块中的像素值的均方误差(mean-square error，MSE)定义或计算图像块的复杂度，图像块的像素值的MSE越大，可以认为该图像块的复杂度越高。
当然，图像块的复杂度也可以采用其他定义方式，或上述定义方式的组合，本申请实施例对此并不限定。
可选地，在一些实施例中，预处理电路4还可以包括分量变换电路44。分量变换电路44可用于执行前文描述的分量变换操作。在计算待编码图像的统计信息的过程中对待编码图像进行分量变换，相当于将原本需要在编码器7中执行的操作剥离出来，放到预处理电路4执行，从而可以降低编码器7的复杂度。当然，在另一些实施例中，预处理电路4也可以不执行分量变换操作，仍由编码器7执行。
继续参见图2，预处理电路4的处理结果(可以包括预处理后的待编码图像以及该待编码图像的统计信息)可以存入外部的存储器5。存储器5可以是双倍速率(double data rate，DDR)内存。
编码器7可以是支持JPEG 2000标准的硬件编码器。如图4所示，编码器7可以包括第一接口电路71、变换电路72、量化电路73、第一编码电路74、码率控制电路75、第二编码电路76以及码流写出电路77。
第一接口电路71可用于从外部的存储器5中读取预先生成的待编码图像的统计信息。第一接口电路71还可用于读取待编码图像的图像块(该图像块(tile)可以是待编码图像中的任一图像块)。第一接口电路71可以采用特定的寻址模式直接读取存储器5中存储的待编码图像的图像块，而无需对待编码图像进行分割。例如，待编码图像在存储器5中可以是按行顺序存储，第一接口电路71可以根据待编码图像在存储器5中的位置，计算出各个图像块的存储位置，然后按照跳地址方式读取相应图像块；或者，待编码图像在存储器5中可以按图像块存储，第一接口电路71按照图像块的存储顺序读取图像块即可。第一接口电路71可以按照直接内存存取(direct memory access，DMA)的方式从存储器5中读取图像块。
第一接口电路71可以将待编码图像的统计信息作为码率控制信息传输至码率控制电路75，供码率控制电路75对编码过程进行码率控制。
可选地，在一些实施例中，第一接口电路71还可用于对图像块进行直流电平平移，即实现上述直流电平平移模块124的功能。
变换电路72可用于执行上文中的变换模块14执行的操作，即对图像块进行小波变换。图像块经过小波变换之后可以得到许多子带。经过小波变换，可以得到图像块的小波系数可以指这些子带(sub-band)的小波系数。
量化电路73可用于对小波系数进行量化，得到量化后的小数系数或量化后的子带的小波系数。
值得注意的是，为了简化编码器7的复杂度，可以将变换、量化等操作中的部分或全部交给如图2所示的信号处理装置6执行。本申请实施例对信号处理装置6的类型不做具体限定，例如可以是数字信号处理器(digital signal processor，DSP)，也可以是图形处理单元(graphics processing unit，GPU)。作为一个示例，可以将变换操作中的部分操作交给信号处理装置6执行，编码器7中的量化电路73既可以接收变换电路72输出的变换系数(小波系数)，也可以接收信号处理装置6输出的变换系数(小波系数)，这样不但能够简化编码器7的结构，还可以提高编码过程的并行度。作为另一个示例，可以由信号处理装置6执行所有的变换操作，编码器7执行量化操作即可。作为又一示例，也可以由信号处理装置6负责全部的变换和量化操作，编码器7直接利用量化后的结果进行编码即可。在信号处理装置6参与运算的实施例中，信号处理装置6可以采用特定的寻址模式直接读取存储器5中存储的待编码图像的图像块，而无需对待编码图像进行分割。例如，待编码图像在存储器5中可以是按行顺序存储，信号处理装置6可以根据待编码图像在存储器5中的位置，计算出各个图像块的存储位置，然后按照跳地址方式读取相应图像块；或者，待编码图像在存储器5中可以按图像块存储，信号处理装置6按照图像块的存储顺序读取图像块即可。信号处理装置6可以按照DMA的方式从存储器5中读取图像块。
当信号处理装置6参与图像块的编码过程时，可以将信号处理装置6和编码器7视为整个片上系统(system on chip，SOC)的编码子系统(编码子系统由图2中的右侧的虚框表示)。
第一编码电路74可用于对图像块的码块进行tier-1编码，得到图像块的码流。参见前文的描述可知，变换和量化后得到的是子带的小波系数，一个子带又可以被划分成可独立编码的一个或多个码块，因此，图像块的码块指的是图像块的子带的码块。
第一编码电路74可用于执行图1中的tier-1编码模块182执行的操作，如对码块进行比特平面编码和算术编码。可选地，第一编码电路74对码块进行编码之前，还可以对码块进行预处理，例如，将小波系数的符号位和绝对值分离。此外，在一些实施例中，第一编码电路74将码块编码成码流之后，还可以对码块进行后处理，如可以将码流拼接在一起，供第二编码电路75使用。
码率控制电路75可用于根据待编码图像的统计信息确定待编码图像中的图像块的目标码率(target size)。
以待编码图像的统计信息为待编码图像中的图像块的复杂度为例，码率控制电路75可以根据各个图像块的复杂度，为各个图像块分配权值。图像块的复杂度越高，权值越大。码率控制电路75可以根据各个图像块的权值以及当前网络状况(如网络带宽)，计算图像块的目标码率，使得图像块的权值越大，目标码率越高。可选地，预处理电路4输出的待编码图像的统计信息可以包括各个图像块的权值，码率控制电路75直接利用图像块的权值计算目标码率即可。
第二编码电路76可用于实现上文提及的tier-2编码模块184的功能。例如，第二编码电路76可用于根据目标码率对图像块的码流进行tier-2编码，以截断图像块的码流。
第二编码电路76可以包括率失真计算电路762(或称slope maker)和截断电路764(或称truncator)。
率失真计算电路762可用于计算第一编码电路74输出的码流的率失真斜率。例如，率失真计算电路762可以根据第一编码电路74输出的每片码流(即每个码块的码流(pass))的码率(rate)和失真度(distortion)计算率失真斜率(slope)。率失真斜率可用于评估当前码块的码流在整个图像块的贡献度。该率失真斜率可用于后续的码流组织，如码流的分层、截断等。
截断电路764可用于根据目标码率以及率失真斜率对图像块的码流进行处理。例如，截断电路764可用于根据目标码率以及率失真斜率截断图像块的码流。进一步地，截断电路764还可用于对码流进行重新组织，码流分层等。此外，在某些实施例中，截断电路764还可用于生成码流的header信息，并将header信息与码流一块传输至后级的码流写出电路77。
码流写出电路77可用于接收截断电路764输出的已经组织好的码流，并将码流写到外部的存储器中。例如，可以通过总线写到外部的存储器中。该总线例如可以是高级扩展接口(advanced extensible interface，AXI)总线。码流写出电路77还可以为码流追加图像块头部(tile header)等信息。
可选地，在某些实施例中，码率控制电路75还可用于根据图像块的统计信息，生成码率控制缓冲区的状态信息(或称缓冲区大小，buffer size)。第一编码电路74还可用于根据码率控制缓冲区的状态信息，对tier-1编码进 行控制。缓冲区的状态信息可用于第一编码电路74对码流进行预截断。例如，第一编码电路74可以根据缓冲区的状态信息删除超出预定大小的码流，或者删除不符合要求的码流。因此，缓冲区的状态信息有时也可称为预截断信息。进一步地，在一些实施例中，码率控制电路75还可以接收第一编码电路74实际编码的码流大小的反馈，并更新图像块在每个分辨率下的预截断信息。
可选地，在一些实施例中，编码器7还可以包括用于软件配置的接口电路(图中未示出)，通过该接口电路可以配置或改变编码器7内部的寄存器中的信息，从而控制编码器7的编码方式。
本申请实施例预先计算待编码图像中的图像块的统计信息，并根据该统计信息截断图像块的码流，从而对各个图像块进行相对独立地码率控制，无需对待编码图像中的所有码块进行整体优化，也就不会产生大量的中间数据，因此，本申请实施例可以降低编码器对系统带宽的要求。整个待编码图像的编码过程甚至完全可以在片上进行。
传统JPEG 2000编码系统可以理解为一种在线编码系统。在线编码系统会将待编码图像(如图2中的传感器3采集到的图像)直接输入至编码器，等编码结束之后再存入存储器5。不同于传统JPEG 2000编码系统，本申请实施例提供的编码系统先对待编码图像进行预处理，得到待编码图像的统计信息(可用于码率控制)，并将预处理之后的待编码图像存入存储器5。然后，编码器7可以以图像块为单位读取并相对独立处理待编码图像中的每个图像块。由于待编码图像在编码之前已经被存入存储器5，因此，编码器的后续编码操作并非实时地在线进行，因此，本申请实施例提供的编码系统可以称为一种离线编码系统。
可选地，在某些实施例中，变换电路72内部或输出端可以设置缓存(片上缓存)，用于缓存变换电路72输出的中间结果。
可选地，在某些实施例中，截断电路764内部或输出端可以设置缓存(片上缓存)，用于缓存截断电路764输出的中间结果。
本申请实施例中的图像块可以相对独立编码，因此不会产生大量中间数据，上述缓存可用于缓存片上生成的一些中间结果。
为了提高编码器7编码效率，在某些实施例中，可以对编码器7中的相邻两级电路进行速率匹配。例如，可以将相邻两级电路中的处理速度较慢的 电路设置成多路并行结构；然后，可以采用一定的机制控制二者之间的数据传输，使得两级电路充分流水。
作为一个示例，可以对量化电路73与第一编码电路74的速率进行匹配。具体地，如图4所示，第一编码电路74可以包括多个编码单元742。该多个编码单元742可用于对量化电路73输出的各个码块并行地进行tier-1编码，即第一编码电路74可以采用多路并行结构进行tier-1编码。
量化电路73和多个编码单元742之间可以采用分组仲裁或自由仲裁的方式确定量化电路73输出的中间结果所对应的编码单元742。分组仲裁指的是将量化电路73输出的某个频率分量的码块始终分配给固定的一组编码单元(每组编码单元可以由若干个编码单元组成)，而自由仲裁是指量化电路73输出的每个码块均有可能被多路并行编码单元中的一路接收。分组仲裁方式的优点在于硬件实现时电路连接较为简单，而自由仲裁方式则在某些情况下能提高编码单元的利用效率。
作为另一示例，可以对第一编码电路74和率失真斜率计算电路762的速率进行匹配。例如，率失真计算电路762可以包括多个率失真斜率计算模块。该多个率失真斜率计算模块可用于并行地计算第一编码电路74输出的码流的率失真斜率。第一编码电路74与率失真计算电路762之间也可以采用分组仲裁或自由仲裁的方式确定第一编码电路74输出的中间结果所对应的率失真计算模块。以分组仲裁为例，一个率失真计算模块可以对应第一编码电路74中的一组编码单元。一个率失真计算模块对应一组编码单元可以使得整个电路的设计更加简单。
以图5所示的512×512大小的图像块为例，变换电路72通常会将该图像块分为若干个64x64的块进行变换，每次变换后会产生4个32x32的中间结果，即4个码块。其中，如果是最后一次变换，4个码块将同时输出，其他情况下，会输出3个码块(即频率分量为HL、LH、HH对应的码块)。
变换电路72输出的3个或4个码块经过量化电路73，连接到多路并行的第一编码电路74时，并可以采用分组仲裁方式确定每个码块对应的编码单元742。
假设第一编码电路74包括3组编码单元：group0，group1，group2。group0包括编码器u0-u3；group1包括编码器u4-u7；group2包括编码器u8-u11。每个图像块可以包括4个分量(如R，Gr，Gb，B)。其中每个分量的码块 与上述3组编码单元之间的映射可以采用下表所示的映射方式：
Figure PCTCN2019075746-appb-000001
上表中，在t5时刻，group0中的编码单元u2和u3处于空闲状态，此时，可以将t6时刻要编码的码块提前送入group0的编码单元u2和u3；在t5时刻，group1中的编码单元u5-u7处于空闲状态，此时，可以将t6时刻要编码的码块提前送入group1的编码单元u5-u7；在t5时刻，group2中的编码单元u9-u11处于空闲状态，此时，可以将t6时刻要编码的码块提前送入group2的编码单元u9-u11；这样一来，可以使得分量0、2和分量1、3之间的码块按照乒乓的方式高效编码。
此外，可以在率失真斜率计算电路762中设置3个率失真计算模块，12个编码单元与3个率失真计算模块之间可以采用分组仲裁机制：u0～u3可以与第1个率失真计算模块互联，u4～u7可以与第2率失真计算模块互联，u8～u11可以与第3个率失真计算模块互联。
上文结合图4，对本申请实施例提供的编码器7的结构进行了举例说明。 下文结合图6，对本申请实施例提供的解码器8的结构进行举例说明。
如图6所示，解码器8可以包括以下电路中的一种或多种：码流读取电路81，码流解析电路82，解码电路83，逆量化电路84，逆变换电路85，输出电路86。
码流读取电路81可用于读取待解码的码流。该码流读取电路81例如可以利用高级可扩展接口(advanced eXtensible interface，AXI)从外部存储器(如内存)中读取该待解码的码流。
码流解析电路82也可称为码流头部解析电路(header parser)。码流解析电路82可以解析码流中的各种类型的头部信息，并从中分离出与解码相关的参数和码流数据，供后级的解码电路83使用。
解码电路83可以包括一个解码单元，也可以包括并行的多路解码单元(具体数量可以根据实际需要配置，如可以配置并行地8路解码单元)。解码电路83中的每个解码单元可以独立地对一个码块进行解码。
可选地，在某些实施例中，在解码电路83之前，还可以设置预处理电路。预处理电路可用于将码流解析电路82输出的解码参数、码流数据等分配给并行的多路解码单元。
可选地，在某些实施例中，在解码电路83之后，还可以设置后处理电路。后处理电路可用于对解码电路83输出的解码数据进行重新组织，并将组织好的数据输出给后级电路。
逆量化电路84可用于对解码电路83解码得到的数据进行逆量化。
逆变换电路85可用于对逆量化电路84输出的数据进行逆变换。逆变换的方式可以是离散小波逆变换。
输出电路86可用于将逆变换电路85输出的数据写入到外部的存储器中。例如，可以通过AXI将逆变换电路85输出的数据写入到外部的存储器中。
可选地，在某些实施例中，解码器8还可以包括软件配置接口。通过该软件配置接口可以配置或改变解码器8内部的寄存器中的信息，从而控制解码器8的解码方式。
本申请实施例提供的解码器8可以以图像块(tile)为单位进行解码。解码器8从外部的存储器读入码流之后，整个解码过程可以在片上进行(由于本申请实施例以图像块为单位进行解码，中间数据不会太大，可以通过片上缓存进行临时存储)，不与外部存储器进行交互，以节省系统带宽。此外， 解码器8中的各级电路可以采用流水线的方式工作，以提高解码效率。
本申请实施例还提供一种编码方法。该编码方法可以由上文提及的编码器7或编码系统执行。如图7所示，该编码方法包括步骤S72-S78。
在步骤S72中，从外部的存储器中读取预先生成的待编码图像的统计信息。
在步骤S74中，根据待编码图像的统计信息，确定待编码图像中的图像块的目标码率。
在步骤S76中，对图像块的码块进行tier-1编码，得到图像块的码流。
在步骤S78中，根据目标码率对图像块的码流进行tier-2编码，以截断图像块的码流。
可选地，图7的方法还可包括：根据图像块的统计信息，生成码率控制缓冲区的状态信息；根据码率控制缓冲区的状态信息，对tier-1编码进行控制。
可选地，图7的方法还可包括：从存储器中读取图像块。
可选地，图7的方法还可包括：对图像块进行直流电平平移。
可选地，图7的方法还可包括：对图像块的小波系数进行量化。
可选地，步骤S76可包括：采用多个编码单元对图像块的码块并行地进行tier-1编码。
可选地，多个编码单元包括多组编码单元，其中不同组的编码单元用于对图像块的不同频率分量的码块进行tier-1编码。
可选地，图7的方法还可包括：对图像块进行小波变换。
可选地，步骤S78可包括：计算tier-1编码后的码流的率失真斜率；根据目标码率以及率失真斜率截断图像块的码流。
可选地，计算tier-1编码后的码流的率失真斜率可包括：采用多个率失真斜率计算模块并行地计算tier-1编码后的码流的率失真斜率。
可选地，待编码图像的至少部分变换系数或量化系数是基于外部的信号处理装置生成的，图7的方法还可包括：接收信号处理装置生成的变换系数或量化系数。
可选地，待编码图像的统计信息包括待编码图像中的图像块的复杂度。
可选地，在从外部的存储器中读取预先生成的待编码图像的统计信息之前，图7的方法还可包括：计算待编码图像的统计信息；将待编码图像的统 计信息存储至存储器中。
可选地，在将待编码图像的统计信息存储至存储器之前，图7的方法还可包括：对待编码图像进行分量变换。
在上述实施例中，可以全部或部分地通过软件、硬件、固件或者其他任意组合来实现。当使用软件实现时，可以全部或部分地以计算机程序产品的形式实现。所述计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行所述计算机程序指令时，全部或部分地产生按照本发明实施例所述的流程或功能。所述计算机可以是通用计算机、专用计算机、计算机网络、或者其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一个计算机可读存储介质传输，例如，所述计算机指令可以从一个网站站点、计算机、服务器或数据中心通过有线(例如同轴电缆、光纤、数字用户线(digital subscriber line，DSL))或无线(例如红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。所述计算机可读存储介质可以是计算机能够存取的任何可用介质或者是包含一个或多个可用介质集成的服务器、数据中心等数据存储设备。所述可用介质可以是磁性介质(例如，软盘、硬盘、磁带)、光介质(例如数字视频光盘(digital video disc，DVD))、或者半导体介质(例如固态硬盘(solid state disk，SSD))等。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作 为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (31)

  1. 一种编码器，其特征在于，包括：
    第一接口电路，用于从外部的存储器中读取预先生成的待编码图像的统计信息；
    码率控制电路，用于根据所述待编码图像的统计信息，确定所述待编码图像中的图像块的目标码率；
    第一编码电路，用于对所述图像块的码块进行tier-1编码，得到所述图像块的码流；
    第二编码电路，用于根据所述目标码率对所述图像块的码流进行tier-2编码，以截断所述图像块的码流。
  2. 根据权利要求1所述的编码器，其特征在于：
    所述码率控制电路还用于根据所述图像块的统计信息，生成码率控制缓冲区的状态信息；
    所述第一编码电路还用于根据所述码率控制缓冲区的状态信息，对所述tier-1编码进行控制。
  3. 根据权利要求1或2所述的编码器，其特征在于，所述第一接口电路还用于从所述存储器中读取所述图像块。
  4. 根据权利要求1-3中任一项所述的编码器，其特征在于，所述第一接口电路还用于对所述图像块进行直流电平平移。
  5. 根据权利要求1-4中任一项所述的编码器，其特征在于，还包括：
    量化电路，用于对所述图像块的小波系数进行量化。
  6. 根据权利要求5所述的编码器，其特征在于，所述第一编码电路包括：
    多个编码单元，用于对所述图像块的码块并行地进行tier-1编码。
  7. 根据权利要求6所述的编码器，其特征在于，所述多个编码单元包括多组编码单元，其中不同组的编码单元用于对所述图像块的不同频率分量的码块进行tier-1编码。
  8. 根据权利要求1-7中任一项所述的编码器，其特征在于，还包括：
    变换电路，用于对所述图像块进行小波变换。
  9. 根据权利要求8所述的编码器，其特征在于，还包括：
    第一缓存，用于缓存所述变换电路输出的中间结果。
  10. 根据权利要求1-9中任一项所述的编码器，其特征在于，所述第二编码电路包括：
    率失真计算电路，用于计算所述第一编码电路输出的码流的率失真斜率；
    截断电路，用于根据所述目标码率以及所述率失真斜率截断所述图像块的码流。
  11. 根据权利要求10所述的编码器，其特征在于，所述率失真计算电路包括：
    多个率失真斜率计算模块，用于并行地计算所述第一编码电路输出的码流的率失真斜率。
  12. 根据权利要求11所述的编码器，其特征在于，所述多个率失真斜率计算模块与所述第一编码电路中的多组编码单元一一对应，其中一个所述率失真斜率计算模块用于计算一组所述编码单元输出的码流的率失真斜率。
  13. 根据权利要求10-12中任一项所述的编码器，其特征在于，还包括：
    第二缓存，用于缓存所述截断电路输出的中间结果。
  14. 根据权利要求1-13中任一项所述的编码器，其特征在于，所述待编码图像的至少部分变换系数或量化系数是基于外部的信号处理装置生成的，
    所述编码器还包括：
    第二接口电路，用于接收所述信号处理装置生成的变换系数或量化系数。
  15. 根据权利要求1-14中任一项所述的编码器，其特征在于，所述待编码图像的统计信息包括所述待编码图像中的图像块的复杂度。
  16. 一种编码系统，其特征在于，包括：
    预处理电路，用于计算所述待编码图像的统计信息；
    存储器，用于存储所述待编码图像和所述统计信息；
    如权利要求1-15中任一项所述的编码器，用于从所述存储器中读取所述待编码图像和所述统计信息。
  17. 根据权利要求16所述的编码系统，其特征在于，所述预处理电路还包括分量变换电路，所述存储器中存储的所述待编码图像是经所述分量变换电变换之后的图像。
  18. 一种编码方法，其特征在于，包括：
    从外部的存储器中读取预先生成的待编码图像的统计信息；
    根据所述待编码图像的统计信息，确定所述待编码图像中的图像块的目标码率；
    对所述图像块的码块进行tier-1编码，得到所述图像块的码流；
    根据所述目标码率对所述图像块的码流进行tier-2编码，以截断所述图像块的码流。
  19. 根据权利要求18所述的编码方法，其特征在于，还包括：
    根据所述图像块的统计信息，生成码率控制缓冲区的状态信息；
    根据所述码率控制缓冲区的状态信息，对所述tier-1编码进行控制。
  20. 根据权利要求18或19所述的编码方法，其特征在于，还包括：
    从所述存储器中读取所述图像块。
  21. 根据权利要求18-20中任一项所述的编码方法，其特征在于，还包括：
    对所述图像块进行直流电平平移。
  22. 根据权利要求18-21中任一项所述的编码方法，其特征在于，还包括：
    对所述图像块的小波系数进行量化。
  23. 根据权利要求22所述的编码方法，其特征在于，所述对所述图像块的码块进行tier-1编码，包括：
    采用多个编码单元对所述图像块的码块并行地进行tier-1编码。
  24. 根据权利要求23所述的编码方法，其特征在于，所述多个编码单元包括多组编码单元，其中不同组的编码单元用于对所述图像块的不同频率分量的码块进行tier-1编码。
  25. 根据权利要求18-24中任一项所述的编码方法，其特征在于，还包括：
    对所述图像块进行小波变换。
  26. 根据权利要求18-25中任一项所述的编码方法，其特征在于，所述根据所述目标码率对所述图像块的码流进行tier-2编码，以截断所述图像块的码流，包括：
    计算所述tier-1编码后的码流的率失真斜率；
    根据所述目标码率以及所述率失真斜率截断所述图像块的码流。
  27. 根据权利要求26所述的编码方法，其特征在于，所述计算所述tier-1 编码后的码流的率失真斜率，包括：
    采用多个率失真斜率计算模块并行地计算所述tier-1编码后的码流的率失真斜率。
  28. 根据权利要求18-27中任一项所述的编码方法，其特征在于，所述待编码图像的至少部分变换系数或量化系数是基于外部的信号处理装置生成的，
    所述编码方法还包括：
    接收所述信号处理装置生成的变换系数或量化系数。
  29. 根据权利要求18-28中任一项所述的编码方法，其特征在于，所述待编码图像的统计信息包括所述待编码图像中的图像块的复杂度。
  30. 根据权利要求18-29中任一项所述的编码方法，其特征在于，在所述从外部的存储器中读取预先生成的待编码图像的统计信息之前，还包括：
    计算所述待编码图像的统计信息；
    将所述待编码图像的统计信息存储至所述存储器中。
  31. 根据权利要求18-30中任一项所述的编码方法，其特征在于，在所述将所述待编码图像的统计信息存储至所述存储器之前，还包括：
    对所述待编码图像进行分量变换。
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