WO2020164200A1 - 像素电极 - Google Patents

像素电极 Download PDF

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Publication number
WO2020164200A1
WO2020164200A1 PCT/CN2019/086660 CN2019086660W WO2020164200A1 WO 2020164200 A1 WO2020164200 A1 WO 2020164200A1 CN 2019086660 W CN2019086660 W CN 2019086660W WO 2020164200 A1 WO2020164200 A1 WO 2020164200A1
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WIPO (PCT)
Prior art keywords
sub
branch
pixel electrode
width
electrode according
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PCT/CN2019/086660
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English (en)
French (fr)
Inventor
曹武
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to US16/493,305 priority Critical patent/US10877323B2/en
Publication of WO2020164200A1 publication Critical patent/WO2020164200A1/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement

Definitions

  • the present invention relates to the field of display technology, in particular to a pixel electrode.
  • a pixel electrode includes a main stem and a branch structure. As shown in FIG. 1, the main stem includes a central stem 11 having a cross shape, a lateral stem 13 located on the periphery of the central stem 11, and pixel electrode branches 12. After the pixel electrode is energized, an inclined electric field can be generated, thereby inducing the liquid crystal molecules in different regions to fall to different directions.
  • FIG. 2 is an enlarged schematic diagram of a part of the structure of the central trunk portion 11 (or side trunk portion 13) and the pixel electrode branches 12 in the prior art.
  • the pattern width of the pixel electrode branches 12 is L, and two adjacent ones are
  • the gap between the pixel electrode branches 12 is S, and the sum of the two is P.
  • P the smaller the transmittance of the display panel.
  • the P value reaches the critical process limit, the effect of improving the transmittance is not obvious.
  • the relationship between the ratio of L and S is very subtle. From a theoretical point of view, the larger the L, the stronger the vertical electric field, the more obvious the improvement of the tilt angle, and the higher the penetration rate.
  • the present invention provides a pixel electrode to solve the problem that the existing pixel electrode deteriorates dark lines due to the influence of the complex electric field at the boundary between the main stem and the branches, which affects the efficiency of the liquid crystal, and further affects the transmittance of the liquid crystal display panel.
  • the present invention provides a pixel electrode, including: a first pixel electrode and a plurality of second pixel electrodes; the second pixel electrode branch includes a first sub branch and at least one second sub branch, and the first sub branch includes On the first side, the second sub-branch includes a second side, one end of the second sub-branch is connected to the first sub-branch, and the opposite end is connected to the first pixel electrode, wherein The first width of the first sub-branch is different from the second width of the second sub-branch.
  • the second sub-branch is an axisymmetric pattern or a center symmetric pattern; the first pixel electrode divides a sub-pixel area into multiple A plurality of second pixel electrodes arranged in parallel are located in each chip.
  • the first width of the first sub-branch is smaller than the second width of the second sub-branch.
  • the second sub-branch is an isosceles trapezoid, and the direction of the second sub-branch is close to the first pixel electrode along the symmetry axis of the second sub-branch.
  • the width gradually increases.
  • the second sub-branch has a parallelogram shape, and the second side of the second sub-branch coincides with a straight line on which the second side of the first sub-branch is located.
  • the first width of the first sub-branch is greater than the second width of the second sub-branch.
  • the second sub-branch is an isosceles trapezoid, and the direction of the second sub-branch is close to the first pixel electrode along the symmetry axis of the second sub-branch.
  • the width gradually decreases.
  • the second sub-branch is a parallelogram, and the second side of the second sub-branch is parallel to the first side of the first sub-branch.
  • the vertical distance between the first side edges of two adjacent first sub-branch portions in a chip is 6-4.5 microns.
  • the present invention also provides another pixel electrode, including a first pixel electrode and a plurality of second pixel electrodes; the second pixel electrode branch includes a first sub branch and at least one second sub branch, the first sub branch It includes a first side, the second sub-branch includes a second side, one end of the second sub-branch is connected to the first sub-branch, and the opposite end is connected to the first pixel electrode, wherein, The first width of the first sub-branch is different from the second width of the second sub-branch.
  • the second sub-branch is an axisymmetric figure or a center symmetric figure.
  • the first width of the first sub-branch is smaller than the second width of the second sub-branch.
  • the second sub-branch is an isosceles trapezoid, and the direction of the second sub-branch is close to the first pixel electrode along the symmetry axis of the second sub-branch.
  • the width gradually increases.
  • the second sub-branch has a parallelogram shape, and the second side of the second sub-branch coincides with a straight line on which the second side of the first sub-branch is located.
  • the first width of the first sub-branch is greater than the second width of the second sub-branch.
  • the second sub-branch is an isosceles trapezoid, and the direction of the second sub-branch is close to the first pixel electrode along the symmetry axis of the second sub-branch.
  • the width gradually decreases.
  • the second sub-branch is a parallelogram, and the second side of the second sub-branch is parallel to the first side of the first sub-branch.
  • the first pixel electrode divides a sub-pixel area into a plurality of chips, and the plurality of second pixel electrodes arranged in parallel at intervals are located in each chip.
  • the horizontal distance between the second side edges of two adjacent second sub-branches is equal to the first side of two adjacent first sub-branches. The horizontal distance between the sides.
  • the vertical distance between the first side edges of two adjacent first sub-branch portions in a chip is 6-4.5 microns.
  • the first pixel electrode includes a central stem portion and a lateral stem portion, the central stem portion is in a cross shape, and the lateral stem portion is disposed on the central stem portion. Two opposite sides.
  • the beneficial effects of the present invention are: by setting the first sub-branch at the junction of the main stem and the branch of the pixel electrode to change the width of the branch at the junction, the dark lines can be effectively controlled, and the liquid crystal efficiency and the penetration of the liquid crystal display panel can be improved. Transmittance.
  • 1 and 2 are schematic diagrams of the structure of pixel electrodes in the prior art
  • 3 and 4 are schematic diagrams of the structure of the pixel electrode according to the first embodiment of the present invention.
  • FIG. 5 is a schematic diagram of the structure of the pixel electrode of the second embodiment of the present invention.
  • FIG. 6 and 7 are schematic diagrams of the structure of the pixel electrode according to the third embodiment of the present invention.
  • FIG. 8 is a schematic diagram of the structure of the pixel electrode of the fourth embodiment of the present invention.
  • FIG. 9 is a schematic diagram of the structure of a pixel electrode according to the fifth embodiment of the present invention.
  • FIG. 10 is a schematic diagram of the structure of a pixel electrode according to the sixth embodiment of the present invention.
  • FIG. 11 is a schematic diagram of the structure of the pixel electrode in the seventh embodiment of the present invention.
  • the present invention addresses the problem of the existing pixel electrode, which deteriorates dark lines due to the influence of the complex electric field at the borders of the main stem and the branches of the pixel electrode, which affects the efficiency of the liquid crystal, and thus the transmittance of the liquid crystal display panel.
  • This embodiment can Solve the defect.
  • this embodiment provides a pixel electrode 100, which includes a first pixel electrode 20 and a plurality of second pixel electrodes 30.
  • the first pixel electrode 20 divides a sub-pixel area into a plurality of chips. In each chip, the second pixel electrode 30 extends from the first pixel electrode 20 in different directions. The extension directions of the two pixel electrodes 30 are different.
  • the first pixel electrode 20 has a cross-shaped structure, and a sub-pixel area is divided into four chips, and the second pixel electrodes 30 in each chip are spaced apart and arranged in parallel.
  • the second pixel electrode 30 includes a first sub-branch portion 31 and a second sub-branch portion 32. One end of the second sub-branch portion 32 is connected to the first sub-branch portion 31, and the opposite end is connected to the first pixel.
  • the electrode 20 is connected; one end of the first sub-branch portion 31 is connected to the second sub-branch portion 32, and the opposite end extends outward.
  • the angle between the extension direction of the first sub-branch portion 31 and the horizontal direction presents a certain angle.
  • the angle between the extension direction of the first sub-branch portion 31 and the horizontal direction in the four chips is 45 degrees. , 135 degrees, minus 135 degrees, minus 45 degrees. This is because theoretically when the azimuth angle of the liquid crystal molecules is 45 degrees (the long axis is arranged along the extension direction of the sub-branch), the tilt angle is 90 degrees, and the transmittance of the pixel area is the highest.
  • the first sub-branch portion 31 includes a first side 311, the first side 311 is the same side as the first sub-branch extending direction (left side of the first sub-branch) Side or right side), the horizontal connecting distance between the first side 311 of two adjacent first sub-branch portions 31 in a chip is P1.
  • the second sub-branch portion 32 includes a second side edge 321, which is the same side as the first sub-branch portion 31, and two adjacent second sub-branch portions within one chip
  • the horizontal distance between the second side edges 321 of 32 is P2, P2 is equal to P1
  • the vertical distance between the first side edges 311 of two adjacent first sub-branch portions 31 in a chip is P
  • the P value is between 6 and 4.5 microns, and the P value in this embodiment is 5 microns.
  • the first sub-branch portion 31 is a striped pattern
  • the second sub-branch portion 32 is an axisymmetrical pattern
  • the symmetry axis 322 of the second sub-branch portion 32 is the same as the extension direction of the first sub-branch portion 31.
  • the first width L1 of the first sub-branch portion 31 is smaller than the second width L2 of the second sub-branch portion 32, and both the first width L1 and the second width L2 are in line with the second sub-branch portion 32.
  • the symmetry axis 322 is measured in the vertical direction.
  • the second sub-branch 32 is an isosceles trapezoid.
  • the second sub-branch 32 is a regular trapezoid, that is, the second sub-branch 32 approaches the first sub-branch along its axis of symmetry.
  • the width in the direction of the pixel electrode 20 gradually increases.
  • the first sub-branch portion 31 may be rectangular, the first width L1 of the first sub-branch portion 31 is 2 microns, and the distance between two adjacent first sub-branch portions 31 in one chip is The vertical distance (vertical gap) is 3 microns. According to theoretical analysis and experimental simulation test, when the vertical distance P of the same side of the first sub-branch remains unchanged, to a certain extent, the penetration rate increases with the The first width L1 of the first sub-branch decreases and increases, but the optimal design value of the first width L1 of the first sub-branch corresponding to each P value is different, and the optimal design value of L has a peak value (maximum ), once L1 is less than or greater than the peak value, the penetration rate will decrease.
  • the second pixel electrode 30 in this embodiment includes one first sub-branch 31 and one second sub-branch 32.
  • the first pixel electrode 20 and the second At the junction (connection) of the pixel electrode 30, a plurality of the second sub-branch portions 32 may be superimposed.
  • the first pixel electrode 20 is the main part of the pixel electrode 100
  • the second pixel electrode 30 is a branch of the pixel electrode 100.
  • the present invention increases the width of the branch at the junction of the branch and the trunk. By thickening the branch at the junction of the trunk, the area of the pixel electrode is increased here, and the local electric field is enhanced, so that the liquid crystal molecules It is easier to fall down, increase the angle factor of the dump, and reduce the dark lines.
  • the difference from the first embodiment is that the first width L1 of the first sub-branch portion 31 in this embodiment is greater than the second width L2 of the second sub-branch portion 32.
  • the second sub-branch portion 32 has an inverted trapezoid shape, and the width of the second sub-branch portion gradually decreases along the direction of the symmetry axis 322 of the second sub-branch portion 32 approaching the first pixel electrode 20.
  • the second sub-branch 32 in the inverted trapezoidal shape can be arranged near the cross center of the first pixel electrode 20, and the other junctions far away from the cross center can be arranged in a positive trapezoidal shape as shown in FIG. 4
  • the main reason for the low efficiency of the azimuth factor is that the liquid crystal molecules are affected by the three-sided electric field. It is difficult to achieve a deflection with an azimuth angle of 45 degrees.
  • the width of the second pixel electrode 30 here, the gap between the adjacent second pixel electrodes 30 is increased, and the trilateral electric field is reduced. Influence each other to increase the azimuth factor, thereby increasing the penetration rate.
  • the first pixel electrode 20 in this embodiment includes a central stem portion 21 and a lateral stem portion 22, the central stem portion 21 and the lateral stem portion 22.
  • the sub-pixel area is divided into four chips together.
  • the central backbone 21 is cross-shaped.
  • the lateral backbones 22 are respectively arranged on two opposite sides of the central backbone 21.
  • the outer boundary of the two pixel electrodes 30 is surrounded.
  • FIG. 7 is a schematic diagram of the structure at the boundary between the second pixel electrode 30 and the first pixel electrode 20 in this embodiment, and the first and last two ends of the second pixel electrode 30 are part of a chip.
  • a second sub-branch 32 is provided, that is, part
  • the second pixel electrode 30 includes a first sub-branch portion 31 and two second sub-branch portions 32, and two opposite ends of the first sub-branch portion 31 are respectively connected to the two second sub-branch portions 32, One end of the second sub-branch portion 32 is connected to the central trunk portion 21 (or lateral trunk portion 22), and the opposite end thereof is connected to the first sub-branch portion 31.
  • the structure of the second sub-branch portion 32 is the same as that of the first embodiment.
  • the structure of the second sub-branch in is the same, which is not repeated here.
  • a second sub-branch portion 32 is also provided at the junction of the lateral main stem portion 22 and the second pixel electrode 30 to improve dark lines and improve liquid crystal efficiency.
  • the lateral main portion 22 encloses a frame structure that surrounds the central main portion 21 and the second pixel electrode 30, so
  • the lateral main portion 22 may also be arranged at three sides of the central main portion, and the specific structure may be determined according to actual design requirements.
  • a second sub-branch 32 is provided at the junction of the lateral main stem portion 22 and the second pixel electrode 30, and the junction between the central stem portion 21 and the second pixel electrode 30, so as to ensure that the junction is
  • the width of the second sub-branch portion 32 is different from the width of the first sub-branch portion 31.
  • the difference from the first embodiment is that the second sub-branch 32 in this embodiment is a centrally symmetrical figure, specifically a parallelogram. In other embodiments, the second sub-branch 32 may be diamond.
  • the first width L1 of the first sub-branch portion 31 is smaller than the second width L2 of the second sub-branch portion 32, and both the first width L1 and the second width L2 are measured in the same direction as the horizontal direction. Got.
  • the first side 311 of the first sub-branch portion 31 coincides with the line where the second side 321 of the second sub-branch portion 32 is located.
  • the horizontal distance P1 between the first side edges 311 of two adjacent first sub-branches 31 in one chip is equal to the level between the second side edges 321 of two adjacent second sub-branches 32 Distance P2.
  • the difference from the fourth embodiment is that the first side 311 of the first sub-branch portion 31 and the second side 321 of the second sub-branch portion 32 do not overlap, and the first side 311 and the The second side 321 is parallel, and other structures are the same as the fourth embodiment.
  • the difference from the fourth embodiment is that the first width L1 of the first sub-branch portion 31 in this embodiment is greater than the second width L2 of the second sub-branch portion 32, and other structures are the same as those in the fourth embodiment. the same.
  • the difference from the sixth embodiment is that the first side 311 of the first sub-branch portion 31 and the second side 321 of the second sub-branch portion 32 in this embodiment do not overlap.
  • the The first side 311 is parallel to the second side 321, and other structures are the same as the sixth embodiment.
  • the pixel electrode provided by the present invention can be applied to a display panel.
  • the liquid crystal display panel includes a TFT array substrate, a color film substrate, a liquid crystal layer, a pixel electrode, and a common electrode.
  • the TFT array substrate is arranged opposite to the color filter substrate, the pixel electrode is arranged on the side of the TFT array substrate facing the color filter substrate, and the common electrode is arranged on the color filter substrate facing the TTF On one side of the array substrate, the liquid crystal layer is disposed between the pixel electrode and the common electrode.
  • the pixel electrode provided by the present invention can effectively control dark lines by changing the width of the pixel electrode branch at the junction of the pixel electrode backbone, and improve the liquid crystal efficiency and the transmittance of the liquid crystal display panel.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Geometry (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Liquid Crystal (AREA)

Abstract

一种像素电极（100），包括第一像素电极（20）和多个第二像素电极（30），第二像素电极（30）包括第一子支部（31）和第二子支部（32），第二子支部（32）的一端与第一像素电极连接（20），相对的另一端与第一子支部（31）连接，第一子支部（31）的第一宽度（L1）与第二子支部（32）的第二宽度（L2）不相同。通过改变支部在其与主干部交界处的宽度，可以有效控制暗纹，提高液晶效率和液晶显示面板的穿透率。

Description

像素电极 技术领域
本发明涉及显示技术领域，尤其涉及一种像素电极。
 背景技术
液晶显示面板的穿透率主要受到三个物理因子的影响，分别为穿透区膜层的总吸收透射率、绝对开口率、以及液晶效率。产品技术精进时，如何在不改变膜层吸收和开口区大小的前提下，利用像素电极图案的设计来提高液晶效率成为提升穿透率的重要途径。一般像素电极包括主干部和分支结构，如图1所示，主干部包括具有“十”字形状的中心主干部11和位于中心主干部11外围的侧向主干部13、以及像素电极分支12，像素电极通电后能够产生倾斜的电场，从而诱导不同区域内的液晶分子倒向不同的方向。
如图2所示，图2为现有技术中的中心主干部11（或侧主干部13）与像素电极分支12的部分结构放大示意图，像素电极分支12的图案宽度为L，相邻两个像素电极分支12的间隙为S，两者之和为P，一般而言，P越小，显示面板的穿透率越佳，当P值达到临界工艺极限，穿透率提升的效果不明显，而对于固定的P值不变时，L与S的比值关系很微妙，从理论上看，L越大，给予的垂直电场越强，倾角改善越明显，穿透率越高，但是从模拟结果看，由于主干部与像素电极分支12的边界处受复杂电场影响，边界处不遵从此规律，在主干部与像素电极分支12的边界区域内，容易恶化暗纹，影响穿透率。
 技术问题
本发明提供一种像素电极，以解决现有的像素电极由于主干部和分支的边界处受到复杂电场的影响而恶化暗纹，影响液晶效率，进而影响液晶显示面板的穿透率的问题。
 技术解决方案
为解决上述问题，本发明提供的技术方案如下：
本发明提供一种像素电极，包括：第一像素电极和多个第二像素电极；所述第二像素电极支部包括一个第一子支部和至少一个第二子支部，所述第一子支部包括第一侧边，所述第二子支部包括第二侧边，所述第二子支部的一端与所述第一子支部连接，相对的另一端与所述第一像素电极连接，其中，所述第一子支部的第一宽度与所述第二子支部的第二宽度不相同所述第二子支部为轴对称图形或中心对称图形；所述第一像素电极将一个子像素区域分成多个筹，多个间隔平行设置的所述第二像素电极位于每一个筹内。
在本发明的至少一种实施例中，所述第一子支部的第一宽度小于所述第二子支部的第二宽度。
在本发明的至少一种实施例中，所述第二子支部为等腰梯形，沿着所述第二子支部的对称轴靠近所述第一像素电极的方向，所述第二子支部的宽度逐渐增大。
在本发明的至少一种实施例中，所述第二子支部为平行四边形，所述第二子支部的第二侧边与所述第一子支部的第二侧边所在的直线重合。
在本发明的至少一种实施例中，所述第一子支部的第一宽度大于所述第二子支部的第二宽度。
在本发明的至少一种实施例中，所述第二子支部为等腰梯形，沿着所述第二子支部的对称轴靠近所述第一像素电极的方向，所述第二子支部的宽度逐渐减小。
在本发明的至少一种实施例中，所述第二子支部为平行四边形，所述第二子支部的第二侧边与所述第一子支部的第一侧边平行。
在本发明的至少一种实施例中，一个筹内的相邻两个所述第一子支部的第一侧边之间的垂直距离为6~4.5微米。
本发明还提供另一种像素电极，包括第一像素电极和多个第二像素电极；所述第二像素电极支部包括一个第一子支部和至少一个第二子支部，所述第一子支部包括第一侧边，所述第二子支部包括第二侧边，所述第二子支部的一端与所述第一子支部连接，相对的另一端与所述第一像素电极连接，其中，所述第一子支部的第一宽度与所述第二子支部的第二宽度不相同。
在本发明的至少一种实施例中，所述第二子支部为轴对称图形或中心对称图形。
在本发明的至少一种实施例中，所述第一子支部的第一宽度小于所述第二子支部的第二宽度。
在本发明的至少一种实施例中，所述第二子支部为等腰梯形，沿着所述第二子支部的对称轴靠近所述第一像素电极的方向，所述第二子支部的宽度逐渐增大。
在本发明的至少一种实施例中，所述第二子支部为平行四边形，所述第二子支部的第二侧边与所述第一子支部的第二侧边所在的直线重合。
在本发明的至少一种实施例中，所述第一子支部的第一宽度大于所述第二子支部的第二宽度。
在本发明的至少一种实施例中，所述第二子支部为等腰梯形，沿着所述第二子支部的对称轴靠近所述第一像素电极的方向，所述第二子支部的宽度逐渐减小。
在本发明的至少一种实施例中，所述第二子支部为平行四边形，所述第二子支部的第二侧边与所述第一子支部的第一侧边平行。
在本发明的至少一种实施例中，所述第一像素电极将一个子像素区域分成多个筹，多个间隔平行设置的所述第二像素电极位于每一个筹内。
在本发明的至少一种实施例中，在一个筹内，相邻两个所述第二子支部的第二侧边之间的水平距离等于相邻两个所述第一子支部的第一侧边之间的水平距离。
在本发明的至少一种实施例中，一个筹内的相邻两个所述第一子支部的第一侧边之间的垂直距离为6~4.5微米。
在本发明的至少一种实施例中，所述第一像素电极包括中心主干部和侧向主干部，所述中心主干部为十字形状，所述侧向主干部设置于所述中心主干部的两相对侧。
 有益效果
本发明的有益效果为：通过在像素电极的主干部与支部的交界处设置第一子支部，用以改变支部在交界处的宽度，可以有效控制暗纹，提高液晶效率和液晶显示面板的穿透率。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1、图2为现有技术的像素电极的结构示意图；
图3、图4为本发明的实施例一的像素电极的结构示意图；
图5为本发明的实施例二的像素电极的结构示意图；
图6、图7为本发明的实施例三的像素电极的结构示意图；
图8为本发明的实施例四的像素电极的结构示意图；
图9为本发明的实施例五的像素电极的结构示意图；
图10为本发明的实施例六的像素电极的结构示意图；
图11为本发明的实施例七的像素电极的结构示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是用以相同标号表示。
本发明针对现有的像素电极，由于像素电极的主干部和分支的边界处受到复杂电场的影响而恶化暗纹，影响液晶效率，进而影响液晶显示面板的穿透率的问题，本实施例能够解决该缺陷。
实施例一
如图3、图4所示，本实施例提供一种像素电极100，包括第一像素电极20、和多个第二像素电极30，所述第二像素电极30与所述第一像素电极20连接。
所述第一像素电极20将一个子像素区域分成多个筹，在各个筹内，所述第二像素电极30自所述第一像素电极20沿不同方向延伸，相邻筹内的所述第二像素电极30的延伸方向不同。
本实施例中的所述第一像素电极20为“十”字形结构，将一个子像素区域分成四个筹，每个筹内的所述第二像素电极30间隔且平行设置。
所述第二像素电极30包括第一子支部31和第二子支部32，所述第二子支部32的一端与所述第一子支部31连接，其相对的另一端与所述第一像素电极20连接；所述第一子支部31的一端与所述第二子支部32连接，相对的另一端向外侧延伸。
所述第一子支部31的延伸方向与水平方向的夹角呈现一定的角度，本实施例中四个筹内的所述第一子支部31的延伸方向与水平方向的夹角分别为45度、135度、负135度、负45度。这是由于理论上当液晶分子的方位角为45度时 (长轴沿子支部延伸方向排列)，倾倒角为90度，像素区域的穿透率最高。
如图4所示，所述第一子支部31包括第一侧边311，所述第一侧边311为与所述第一子支部延伸方向相同的一侧（所述第一子支部的左侧边或右侧边），一个筹内的相邻的两个所述第一子支部31的第一侧边311之间的水平连线距离为P1。
所述第二子支部32包括第二侧边321，所述第二侧边321为与所述第一子支部31相同的一侧，一个筹内的相邻的两个所述第二子支部32的第二侧边321之间的水平连线距离为P2，P2等于P1，一个筹内的相邻的两个所述第一子支部31的第一侧边311之间的垂直距离为P，P值为6~4.5微米之间，本实施例中的P值为5微米。
所述第一子支部31为条状图形，所述第二子支部32为轴对称图形，所述第二子支部32的对称轴322与所述第一子支部31的延伸方向相同。
所述第一子支部31的第一宽度L1小于所述第二子支部32的第二宽度L2，所述第一宽度L1和所述第二宽度L2均是在与所述第二子支部32的对称轴322垂直的方向上测得。
具体地，所述第二子支部32为等腰梯形，本实施例中的所述第二子支部32为正梯形，即所述第二子支部32在沿着其对称轴靠近所述第一像素电极20的方向上的宽度逐渐增大。
本实施例中的所述第一子支部31可为矩形，所述第一子支部31的第一宽度L1为2微米，一个筹内的相邻两个所述第一子支部31之间的垂直距离（垂直间隙）为3微米，由理论分析和实验模拟测试知，所述第一子支部的同侧边的垂直距离P保持不变时，在一定程度上，穿透率随着所述第一子支部的第一宽度L1的减小而增大，但每个P值对应的第一子支部的第一宽度L1的最佳设计值不同，L的最佳设计值存在峰值（最大值），一旦L1小于或大于该峰值后，穿透率会降低。
本实施例中的所述第二像素电极30包括一个所述第一子支部31和一个所述第二子支部32，在其他实施例中，在所述第一像素电极20与所述第二像素电极30的交界处（连接处），可叠加多个所述第二子支部32。
本实施例中的所述第一像素电极20为像素电极100的主干部，第二像素电极30为像素电极100的支部。与现有技术相比，本发明在支部与主干的交界处，增加了支部的宽度，通过加粗在主干交界处的支部，增大像素电极在此处的面积，增强局部电场，使得液晶分子更易倒伏，提高倾倒角因子，缩小暗纹。
实施例二
如图5所示，与实施例一不同的是，本实施例中的所述第一子支部31的第一宽度L1大于所述第二子支部32的第二宽度L2。所述第二子支部32为倒梯形，沿着所述第二子支部32的对称轴322靠近所述第一像素电极20的方向，所述第二子支部的宽度逐渐减小。
在其他实施例中，倒梯形状的所述第二子支部32可设置所述第一像素电极20的十字中心附近，其他远离十字中心的交界处可设置成如图4所示的正梯形状的第二子支部，这是由于位于所述第一像素电极20的十字中心附近处的液晶分子效率低的主要原因是其方位角因子效率较低，液晶分子受到三边电场的互相影响，较难实现方位角为45度的偏转，通过减小在此处的所述第二像素电极30的宽度，进而增大相邻的所述第二像素电极30之间的间隙，降低三边电场的互相影响，提升方位角因子，进而提高穿透率。
实施例三
如图6所示，与实施例一相比，本实施例中的所述第一像素电极20包括中心主干部21和侧向主干部22，所述中心主干部21和所述侧向主干部22一起将一个子像素区域分成四个筹，所述中心主干部21为十字形，所述侧向主干部22分别设置于所述中心主干部21的两相对侧，将四个筹内的第二像素电极30的外侧边界包围。
如图7所示，图7为本实施例中的第二像素电极30与第一像素电极20的边界处的结构示意图，一个筹内的部分所述第二像素电极30的首尾两个端部分别与所述中心主干部21、所述侧向主干部22连接，在与所述中心主干部21和所述侧向主干部22的连接边界处，均设置有第二子支部32，即部分所述第二像素电极30包括一个第一子支部31和两个第二子支部32，所述第一子支部31的两个相对的端部分别与两个所述第二子支部32连接，所述第二子支部32的一端连接所述中心主干部21（或侧向主干部22），其相对的另一端连接所述第一子支部31，第二子支部32的结构与实施例一中的第二子支部的结构相同，这里不再赘述。
由于在所述侧向主干部22与所述第二像素电极30形成的边界处受到Data line（数据线）与公共电极电场的影响，致使该边界处的液晶效率相较于中心主干部21边界处更为低下，因此在所述侧向主干部22与所述第二像素电极30的交界处也设置有第二子支部32的结构，以用于改善暗纹，提高液晶效率。
在其他实施例中，设置于所述十字中心主干部21的四侧，所述侧向主干部22围成一框架结构，将所述中心主干部21及所述第二像素电极30包围，所述侧向主干部22也可设置在所述中心主干部的三个边侧处，具体结构可视实际设计需要而定。但需保证的是，侧向主干部22与所述第二像素电极30的交界处、中心主干部21与所述第二像素电极30的交界处均设置有第二子支部32，保证交界处的第二子支部32的宽度与第一子支部31的宽度不同。
实施例四
如图8所示，与实施例一不同的是，本实施例中的所述第二子支部32为中心对称图形，具体为平行四边形，在其他实施例中所述第二子支部32可为菱形。
所述第一子支部31的第一宽度L1小于所述第二子支部32的第二宽度L2，所述第一宽度L1和所述第二宽度L2均是在与水平方向相同的方向上测得。
所述第一子支部31的第一侧边311与所述第二子支部32的第二侧边321所在的直线重合。
一个筹内的相邻两个所述第一子支部31的第一侧边311之间的水平距离P1等于相邻的两个所述第二子支部32的第二侧边321之间的水平距离P2。通过减小在边界处的第二像素电极30之间的间隙，增大在边界处的第二像素电极30的宽度，提升了液晶在交界处的倾倒角因子，进而提高穿透率。
实施例五
如图9所示，与实施例四不同的是，第一子支部31的第一侧边311与第二子支部32的第二侧边321不重合，所述第一侧边311与所述第二侧边321平行，其他结构均与实施例四相同。
实施例六
如图10所示，与实施例四不同的是，本实施例中的第一子支部31的第一宽度L1大于所述第二子支部32的第二宽度L2，其他结构均与实施例四相同。
实施例七
如图11所示，与实施例六不同的是，本实施例中的第一子支部31的第一侧边311与第二子支部32的第二侧边321不重合，具体地，所述第一侧边311平行于所述第二侧边321，其他结构均与实施例六相同。
本发明提供的像素电极可应用于显示面板中，以液晶显示面板为例，所述液晶显示面板包括TFT阵列基板、彩膜基板、液晶层、像素电极以及公共电极。
所述TFT阵列基板与所述彩膜基板相对设置，所述像素电极设置于所述TFT阵列基板面向所述彩膜基板的一侧，所述公共电极设置于所述彩膜基板面向所述TTF阵列基板的一侧，所述液晶层设置于所述像素电极与所述公共电极之间。
有益效果：本发明提供的像素电极通过改变像素电极支部在像素电极主干部交界处的宽度，可以有效控制暗纹，提高液晶效率和液晶显示面板的穿透率。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种像素电极，其中，包括：
    第一像素电极；
    多个第二像素电极，所述第二像素电极包括：
    一第一子支部，所述第一子支部包括第一侧边；
    至少一第二子支部，所述第二子支部包括第二侧边，所述第二子支部的一端与所述第一子支部连接，相对的另一端与所述第一像素电极连接，其中，
    所述第一子支部的第一宽度与所述第二子支部的第二宽度不相同；
    所述第二子支部为轴对称图形或中心对称图形；
    所述第一像素电极将一个子像素区域分成多个筹，多个间隔平行设置的所述第二像素电极位于每一个筹内。
  2. 根据权利要求1所述的像素电极，其中，所述第一子支部的第一宽度小于所述第二子支部的第二宽度。
  3. 根据权利要求2所述的像素电极，其中，所述第二子支部为等腰梯形，沿着所述第二子支部的对称轴靠近所述第一像素电极的方向，所述第二子支部的宽度逐渐增大。
  4. 根据权利要求2所述的像素电极，其中，所述第二子支部为平行四边形，所述第二子支部的第二侧边与所述第一子支部的第二侧边所在的直线重合。
  5. 根据权利要求1所述的像素电极，其中，所述第一子支部的第一宽度大于所述第二子支部的第二宽度。
  6. 根据权利要求4所述的像素电极，其中，所述第二子支部为等腰梯形，沿着所述第二子支部的对称轴靠近所述第一像素电极的方向，所述第二子支部的宽度逐渐减小。
  7. 根据权利要求5所述的像素电极，其中，所述第二子支部为平行四边形，所述第二子支部的第二侧边与所述第一子支部的第一侧边平行。
  8. 根据权利要求1所述的像素电极，其中，一个筹内的相邻两个所述第一子支部的第一侧边之间的垂直距离为6~4.5微米。
  9. 一种像素电极，其中，包括：
    第一像素电极；
    多个第二像素电极，所述第二像素电极包括：
    一第一子支部，所述第一子支部包括第一侧边；
    至少一第二子支部，所述第二子支部包括第二侧边，所述第二子支部的一端与所述第一子支部连接，相对的另一端与所述第一像素电极连接，其中，
    所述第一子支部的第一宽度与所述第二子支部的第二宽度不相同。
  10. 根据权利要求9所述的像素电极，其中，所述第二子支部为轴对称图形或中心对称图形。
  11. 根据权利要求10所述的像素电极，其中，所述第一子支部的第一宽度小于所述第二子支部的第二宽度。
  12. 根据权利要求11所述的像素电极，其中，所述第二子支部为等腰梯形，沿着所述第二子支部的对称轴靠近所述第一像素电极的方向，所述第二子支部的宽度逐渐增大。
  13. 根据权利要求11所述的像素电极，其中，所述第二子支部为平行四边形，所述第二子支部的第二侧边与所述第一子支部的第二侧边所在的直线重合。
  14. 根据权利要求10所述的像素电极，其中，所述第一子支部的第一宽度大于所述第二子支部的第二宽度。
  15. 根据权利要求13所述的像素电极，其中，所述第二子支部为等腰梯形，沿着所述第二子支部的对称轴靠近所述第一像素电极的方向，所述第二子支部的宽度逐渐减小。
  16. 根据权利要求14所述的像素电极，其中，所述第二子支部为平行四边形，所述第二子支部的第二侧边与所述第一子支部的第一侧边平行。
  17. 根据权利要求9所述的像素电极，其中，所述第一像素电极将一个子像素区域分成多个筹，多个间隔平行设置的所述第二像素电极位于每一个筹内。
  18. 根据权利要求17所述的像素电极，其中，在一个筹内，相邻两个所述第二子支部的第二侧边之间的水平距离等于相邻两个所述第一子支部的第一侧边之间的水平距离。
  19. 根据权利要求17所述的像素电极，其中，一个筹内的相邻两个所述第一子支部的第一侧边之间的垂直距离为6~4.5微米。
  20. 根据权利要求9所述的像素电极，其中，所述第一像素电极包括中心主干部和侧向主干部，所述中心主干部为十字形状，所述侧向主干部设置于所述中心主干部的两相对侧。
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