WO2020155544A1 - 一种ssd主控中的raid被动加速装置和加速方法 - Google Patents

一种ssd主控中的raid被动加速装置和加速方法 Download PDF

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WO2020155544A1
WO2020155544A1 PCT/CN2019/093559 CN2019093559W WO2020155544A1 WO 2020155544 A1 WO2020155544 A1 WO 2020155544A1 CN 2019093559 W CN2019093559 W CN 2019093559W WO 2020155544 A1 WO2020155544 A1 WO 2020155544A1
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bus
data
sram
raid
interface
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French (fr)
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王运哲
刘大铕
刘奇浩
刘尚
朱苏雁
孙中琳
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山东华芯半导体有限公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
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    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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  • the invention relates to a RAID acceleration device and an acceleration method, in particular to a RAID passive acceleration device and an acceleration method in an SSD master control, which uses hardware to help a CPU accelerate the realization of RAID in the SSD storage.
  • the existing RAID technology is generally aimed at HDD disks, using an operating system or a RAID card to implement RAID.
  • the present invention provides a RAID passive acceleration device and acceleration method in the SSD master control, which implements RAID in the SSD master control, improves the speed of the RAID, and improves the system efficiency.
  • a RAID passive acceleration device in the SSD master control is: a passive acceleration device directly hung on the bus and includes the following modules:
  • Bus configuration interface responsible for receiving configuration information from the CPU
  • the bus slave interface is responsible for receiving broadcast data from the bus.
  • the bus can also read the calculation result data through this interface;
  • the exclusive OR module is responsible for the exclusive OR operation of the intermediate exclusive OR result read from SRAM and the newly read data from the Master port and write the new result into SRAM;
  • the control module is responsible for generating the state process of fetching calculation and writing results according to the configuration information obtained from the configuration bus interface, and the bus deployment slave interface and the exclusive OR calculation module realize the whole process, and then feedback the state to the bus configuration interface.
  • the configuration information received by the bus configuration interface from the CPU includes startup information, address information, and data length.
  • the state flow generated by the control module includes four parallel operations, which are: enable the slave interface to receive bus data; enable SRAM and read the data corresponding to the current bus from the SRAM; enable the exclusive OR calculation module The data from the bus and the data from the SRAM are XORed to get the corresponding result; the result of the operation is replaced with the corresponding data in the SRAM and is reserved for the next round of the big cycle to read out.
  • dual-port SRAM is used in parallel operation, the data corresponding to the current bus cycle is read, and the XOR calculation result corresponding to the previous bus cycle is written.
  • the invention also discloses a RAID passive acceleration method in SSD master control, which includes the following steps:
  • the bus configuration interface receives configuration information from the CPU, the configuration information includes startup information, address information, and page data length;
  • control module enters the data storage state according to the above configuration information, and starts the slave interface to receive the data broadcast by the bus until it receives the data of the data length specified in the configuration information.
  • control module sends an enable to the SRAM in the NFC Signal, store the data in SRAM buffer;
  • the control module enters the calculation state and starts the internal large loop counter and small loop counter.
  • the large loop is responsible for counting each page of the entire read stripe
  • the small loop is responsible for counting each cycle of a page on the bus.
  • the steps include four parallel operations: enable the slave interface to receive bus data; enable SRAM and read the data corresponding to the current bus from the SRAM; enable the exclusive OR calculation module to perform processing between the data from the bus and the data from the SRAM XOR operation to get the corresponding result; replace the operation result with the corresponding data in SRAM and save it for reading and using in the next big cycle;
  • the control module enters the idle state and updates the status register in the configuration interface.
  • dual-port SRAM is used in parallel operation, the data corresponding to the current bus cycle is read, and the XOR calculation result corresponding to the previous bus cycle is written.
  • the acceleration device of the present invention is a hardware module integrated in the SSD main control, and realizes RAID by combining with the CPU configuration command queue, that is, the present invention realizes RAID through the combination of software and hardware, and has strong flexibility.
  • the raid acceleration module is hung on the bus as a slave, and the broadcast mode of the bus is used to facilitate the system to perform data scheduling, so that the raid acceleration and ECC and scrambling in the NFC can be performed at the same time without affecting the process, improving the data flow s efficiency. Time sharing of SRAM with NFC improves the utilization of SRAM.
  • FIG. 1 is a schematic block diagram of the acceleration device described in Embodiment 1.
  • This embodiment discloses a RAID passive acceleration device in the SSD master control.
  • this device is a passive acceleration device (slave) directly hung on the bus AXI_INTERCONNECT.
  • the CPU uses the broadcast mode of the bus to program
  • the data is sent from the DRAM to the XOR module and NFC at the same time.
  • this device includes the following modules:
  • Bus configuration interface AXI_RGF responsible for receiving configuration information from the CPU
  • the bus slave interface AXI_SLV is responsible for receiving the broadcast data from the bus.
  • the bus can also read the calculation result data through this interface;
  • the exclusive OR module RAID CAL is responsible for the exclusive OR operation between the intermediate exclusive OR result read from SRAM and the newly read data from the Master port and write the new result into SRAM;
  • the RAID CTL control module is responsible for generating the status process of fetching calculation and writing results according to the configuration information obtained from the configuration bus interface, and the bus deployment slave interface and the exclusive OR calculation module implement the entire process, and then feedback the status to the bus configuration interface.
  • the configuration information received by the bus configuration interface from the CPU includes startup information, address information, and data length.
  • the state flow generated by the control module includes four parallel operations, which are: enable slave interface to receive bus data; enable SRAM and read data corresponding to the current bus from SRAM; enable XOR
  • the calculation module performs an exclusive OR operation on the data from the bus and the data from the SRAM to obtain the corresponding result; the operation result replaces the corresponding data in the SRAM and saves it for reading in the next round of the big cycle.
  • dual-port SRAM is used in parallel operation, the data corresponding to the current bus cycle is read, and the XOR calculation result corresponding to the previous bus cycle is written.
  • the parallel operation continues until each cycle of each page in the entire read stripe on the bus ends, and the final XOR result will be stored in the SRAM for NFC processing.
  • the passive acceleration device described in this embodiment is a hardware module integrated in the SSD controller, which uses hardware to help the CPU accelerate the implementation of RAID in the SSD storage. Compared with pure software implementation, it is faster and more flexible.
  • This embodiment discloses a RAID passive acceleration method in SSD master control, which includes the following steps:
  • the bus configuration interface receives configuration information from the CPU, the configuration information includes startup information, address information, and page data length;
  • control module enters the data storage state according to the above configuration information, and starts the slave interface to receive the data broadcast by the bus until it receives the data of the data length specified in the configuration information.
  • control module sends an enable to the SRAM in the NFC Signal, store the data in SRAM buffer;
  • the control module enters the calculation state and starts the internal large loop counter and small loop counter.
  • the large loop is responsible for counting each page of the entire read stripe
  • the small loop is responsible for counting each cycle of a page on the bus.
  • the steps include parallel four-part operations: enable the slave interface to receive bus data; enable SRAM and read the data corresponding to the current bus from the SRAM; enable the exclusive OR calculation module to perform processing between the data from the bus and the data from the SRAM XOR operation to get the corresponding result; replace the operation result with the corresponding data in SRAM and save it for reading and using in the next big cycle;
  • the data read from the SRAM is the initial value or the result of the previous XOR, which is different from the data from the bus.
  • the corresponding data read from the SRAM and the corresponding data on the current bus refers to the data of the same strip. Because there are a lot of data on the bus, including different data in flash units such as multiple channels, multiple luns, and multiple planes, but for RAID, only the data of the same strip is used for XOR, and how much is stored in SRAM The intermediate XOR result of each strip, so the data in the SRAM and the data on the bus have a corresponding relationship based on the same strip.
  • the Slave port is connected to the bus, and the intermediate XOR result is stored in the SRAM, so the intermediate XOR result is the corresponding data read from the SRAM, and the new data received by the Slave port is the corresponding data on the bus.
  • the data from the bus and the data from the SRAM are data on the same strip.
  • the control module enters the idle state and updates the status register in the configuration interface.
  • dual-port SRAM is used in parallel operation, the data corresponding to the current bus cycle is read, and the XOR calculation result corresponding to the previous bus cycle is written. The parallel operation continues until the large and small loops are over, and the final XOR result will be stored in the SRAM for NFC processing.
  • the raid acceleration module is hung on the bus as a slave, and the broadcast mode of the bus is used to facilitate the system to perform data scheduling, so that the raid acceleration and ECC and scrambling in NFC can be performed simultaneously without affecting the process.
  • the efficiency of data flow Time sharing of SRAM with NFC improves the utilization of SRAM.

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Abstract

一种SSD主控中的RAID被动加速装置和加速方法，所述加速装置包括总线配置接口、总线slave接口、异或运算模块和控制模块，控制模块负责根据从配置总线接口得到的配置信息生成取数计算写结果的状态流程，并且总线调配slave接口、异或计算模块实现整个流程，然后将状态反馈给总线配置接口。加速方法将raid加速模块挂在总线上作为一个slave，利用总线广播模式将program的数据从DRAM同时发给异或运算模块和NFC。该方法和装置在SSD主控中实现RAID，并且提高RAID的速度，可提高系统效率。

Description

一种SSD主控中的RAID被动加速装置和加速方法 技术领域
本发明涉及一种RAID加速装置和加速方法，具体是一种SSD主控中的RAID被动加速装置和加速方法，使用硬件帮助CPU加速SSD存储中的RAID实现。
背景技术
在对SSD的读写当中，从Flash颗粒读出数据时，若ECC纠错失败，且read re-try等操作也无法读出正确数据，此时就需考虑如何进行数据恢复。RAID技术可以充分发挥出存储芯片的阵列优势，提供容错功能来确保数据安全性，在某个存储单元出现问题的情况下仍可以继续工作。
现有的RAID技术一般是针对HDD盘，使用操作系统或者RAID卡两种方式实现RAID。在SSD控制器中实现RAID的方法很少，并且现有的方法大都是单纯通过软件实现，降低了正常使用时的写效率，恢复数据时的读效率。
发明内容
针对现有技术的缺陷，本发明提供一种SSD主控中的RAID被动加速装置和加速方法，在SSD主控中实现RAID，并且提高RAID的速度，提高系统效率。
为了解决所述技术问题，本发明采用的技术方案是：一种SSD主控中的RAID被动加速装置，本装置为直接挂在总线上的被动加速装置，包括以下模块：
总线配置接口，负责接收来自CPU的配置信息；
总线slave接口，负责接收来自总线的广播数据，总线也可以通过此接口读取运算结果数据；
异或运算模块，负责将从SRAM中读取的中间异或结果与从Master口新读入的数据进行异或运算并将所得新结果写入SRAM；
控制模块，负责根据从配置总线接口得到的配置信息生成取数计算写结果的状态流程，并且总线调配slave接口、异或计算模块实现整个流程，然后将状态反馈给总线配置接口。
进一步的，总线配置接口从CPU接收的配置信息包括启动信息、地址信息和数据长度。
进一步的，控制模块生成的状态流程包括并行的四部分操作，分别为：使能slave接口接收总线数据；使能SRAM并从SRAM中读出与当前总线上对应的数据；使能异或计算模块将来自总线的数据和来自SRAM的数据进行异或运算得到相应结果；将运算结果替换 SRAM中对应数据留待下一轮大循环时读出使用。
进一步的，并行操作中使用双口SRAM，读出的是当前总线周期所对应的数据，写入的是上一个总线周期所对应的异或计算结果。
进一步的，并行操作持续至整个读取条带中的每一页在总线上的每个周期都结束，最终的异或结果将存在SRAM中留待NFC处理。
本发明还公开一种SSD主控中的RAID被动加速方法，包括以下步骤：
S01)、总线配置接口接收到来自CPU的配置信息，该配置信息包括启动信息、地址信息和页数据长度；
S02)、控制模块根据上述配置信息进入储数状态，启动slave接口接收总线广播的数据，直至收到配置信息中所指定数据长度的数据，与此同时，控制模块向NFC中的SRAM发送使能信号，将该笔数据存入SRAM当中缓存；
S03)、控制模块进入计算状态，启动内部大循环计数器和小循环计数器，其中大循环负责计数整个读取条带的每一页，小循环负责计数某一页在总线上的每个周期，此步骤包括并行的四部分操作：使能slave接口接收总线数据；使能SRAM并从SRAM中读出与当前总线上对应的数据；使能异或计算模块将来自总线的数据和来自SRAM的数据进行异或运算得到相应结果；将运算结果替换SRAM中对应数据留待下一轮大循环时读出使用；
S04)、控制模块进入空闲状态，更新配置接口中的状态寄存器。
进一步的，并行操作中使用双口SRAM，读出的是当前总线周期所对应的数据，写入的是上一个总线周期所对应的异或计算结果。
进一步的，并行操作持续至大小循环都结束，最终的异或结果将存在SRAM中留待NFC处理。
本发明的有益效果：本发明所述加速装置是集成在SSD主控制内的一个硬件模块，通过与CPU配置命令队列结合实现RAID，也就是说本发明通过软硬件结合实现RAID，灵活性强。将raid加速模块挂在总线上作为一个slave，利用了总线的广播模式，方便系统进行数据调度，使得raid加速与NFC中的ECC和加扰等在不影响流程的情况下同时进行，提高数据流的效率。与NFC分时共享SRAM，提高了SRAM利用率。
附图说明
图1为实施例1所述加速装置的原理框图。
具体实施方式
下面结合附图和具体实施例对本发明做进一步的说明。
实施例1
本实施例公开一种SSD主控中的RAID被动加速装置，如图1所示，本装置是直接挂在总线AXI_INTERCONNECT上的一个被动加速装置(slave)，CPU使用总线的广播模式，将program的数据从DRAM同时发给异或运算模块和NFC。RAID加速模块与NFC之间有传输数据的接口，在完成异或运算后通过接口将结果存放于NFC的SRAM中。
具体的，本装置包括以下模块：
总线配置接口AXI_RGF，负责接收来自CPU的配置信息；
总线slave接口AXI_SLV，负责接收来自总线的广播数据，总线也可以通过此接口读取运算结果数据；
异或运算模块RAID CAL，负责将从SRAM中读取的中间异或结果与从Master口新读入的数据进行异或运算并将所得新结果写入SRAM；
控制模块RAID CTL，负责根据从配置总线接口得到的配置信息生成取数计算写结果的状态流程，并且总线调配slave接口、异或计算模块实现整个流程，然后将状态反馈给总线配置接口。
本实施例中，总线配置接口从CPU接收的配置信息包括启动信息、地址信息和数据长度。
本实施例中，控制模块生成的状态流程包括并行的四部分操作，分别为：使能slave接口接收总线数据；使能SRAM并从SRAM中读出与当前总线上对应的数据；使能异或计算模块将来自总线的数据和来自SRAM的数据进行异或运算得到相应结果；将运算结果替换SRAM中对应数据留待下一轮大循环时读出使用。本过程中，并行操作中使用双口SRAM，读出的是当前总线周期所对应的数据，写入的是上一个总线周期所对应的异或计算结果。并行操作持续至整个读取条带中的每一页在总线上的每个周期都结束，最终的异或结果将存在SRAM中留待NFC处理。
本实施例所述被动加速装置是集成在SSD控制器中一个硬件模块，使用硬件帮助CPU加速SSD存储中的RAID实现。与单纯的软件实现相比，速度更快，更灵活。
实施例2
本实施例公开一种SSD主控中的RAID被动加速方法，包括以下步骤：
S01)、总线配置接口接收到来自CPU的配置信息，该配置信息包括启动信息、地址信息和页数据长度；
S02)、控制模块根据上述配置信息进入储数状态，启动slave接口接收总线广播的数据，直 至收到配置信息中所指定数据长度的数据，与此同时，控制模块向NFC中的SRAM发送使能信号，将该笔数据存入SRAM当中缓存；
S03)、控制模块进入计算状态，启动内部大循环计数器和小循环计数器，其中大循环负责计数整个读取条带的每一页，小循环负责计数某一页在总线上的每个周期，此步骤包括并行的四部分操作：使能slave接口接收总线数据；使能SRAM并从SRAM中读出与当前总线上对应的数据；使能异或计算模块将来自总线的数据和来自SRAM的数据进行异或运算得到相应结果；将运算结果替换SRAM中对应数据留待下一轮大循环时读出使用；
本实施例中，从SRAM中读出的数据是初始值或者之前异或的结果，与来自总线的数据不同。从SRAM中读出与当前总线上对应的数据中的对应是指同一条带的数据。因为总线上有很多数据，包括多channel、多lun、多plane等Flash单元里的不同数据，但就做RAID来讲就是只有同一条带的数据才拿来做异或，并且SRAM中存有多个条带的中间异或结果，所以SRAM中的数据与总线上的数据存在基于同一条带的对应关系。Slave口是与总线相连接的，中间异或结果存在SRAM中，所以中间异或结果即是从SRAM中读出的对应数据，Slave口新接收数据即是总线上的对应数据。来自总线的数据和来自SRAM的数据是同一条带上的数据。
S04)、控制模块进入空闲状态，更新配置接口中的状态寄存器。
具体的，并行操作中使用双口SRAM，读出的是当前总线周期所对应的数据，写入的是上一个总线周期所对应的异或计算结果。并行操作持续至大小循环都结束，最终的异或结果将存在SRAM中留待NFC处理。
本方法将raid加速模块挂在总线上作为一个slave，利用了总线的广播模式，方便系统进行数据调度，使得raid加速与NFC中的ECC和加扰等在不影响流程的情况下同时进行，提高数据流的效率。与NFC分时共享SRAM，提高了SRAM利用率。
以上描述的仅是本发明的基本原理和优选实施例，本领域技术人员根据本发明做出的改进和替换，属于本发明的保护范围。

Claims (8)

  1. 一种SSD主控中的RAID被动加速装置，其特征在于：本装置为直接挂在总线上的被动加速装置，包括以下模块：
    总线配置接口，负责接收来自CPU的配置信息；
    总线slave接口，负责接收来自总线的广播数据，总线也可以通过此接口读取运算结果数据；
    异或运算模块，负责将从SRAM中读取的中间异或结果与从Master口新读入的数据进行异或运算并将所得新结果写入SRAM；
    控制模块，负责根据从配置总线接口得到的配置信息生成取数计算写结果的状态流程，并且总线调配slave接口、异或计算模块实现整个流程，然后将状态反馈给总线配置接口。
  2. 根据权利要求1所述的SSD主控中的RAID被动加速装置，其特征在于：总线配置接口从CPU接收的配置信息包括启动信息、地址信息和数据长度。
  3. 根据权利要求1所述的SSD主控中的RAID被动加速装置，其特征在于；控制模块生成的状态流程包括并行的四部分操作，分别为：使能slave接口接收总线数据；使能SRAM并从SRAM中读出与当前总线上对应的数据；使能异或计算模块将来自总线的数据和来自SRAM的数据进行异或运算得到相应结果；将运算结果替换SRAM中对应数据留待下一轮大循环时读出使用。
  4. 根据权利要求3所述的SSD主控中的RAID被动加速装置，其特征在于：并行操作中使用双口SRAM，读出的是当前总线周期所对应的数据，写入的是上一个总线周期所对应的异或计算结果。
  5. 根据权利要求3所述的SSD主控中的RAID被动加速装置，其特征在于：并行操作持续至读取条带中的每一页在总线上的每个周期都结束，最终的异或结果将存在SRAM中留待NFC处理。
  6. 一种SSD主控中的RAID被动加速方法，其特征在于：包括以下步骤：
    S01)、总线配置接口接收到来自CPU的配置信息，该配置信息包括启动信息、地址信息和页数据长度；
    S02)、控制模块根据上述配置信息进入储数状态，启动slave接口接收总线广播的数据，直至收到配置信息中所指定数据长度的数据，与此同时，控制模块向NFC中的SRAM发送使能信号，将该笔数据存入SRAM当中缓存；
    S03)、控制模块进入计算状态，启动内部大循环计数器和小循环计数器，其中大循环负责计数整个读取条带的每一页，小循环负责计数某一页在总线上的每个周期，此步骤包括并行的 四部分操作：使能slave接口接收总线数据；使能SRAM并从SRAM中读出与当前总线上对应的数据；使能异或计算模块将来自总线的数据和来自SRAM的数据进行异或运算得到相应结果；将运算结果替换SRAM中对应数据留待下一轮大循环时读出使用；
    S04)、控制模块进入空闲状态，更新配置接口中的状态寄存器。
  7. 根据权利要求6所述的SSD主控中的RAID被动加速方法，其特征在于：并行操作中使用双口SRAM，读出的是当前总线周期所对应的数据，写入的是上一个总线周期所对应的异或计算结果。
  8. 根据权利要求6所述的SSD主控中的RAID被动加速方法，其特征在于：并行操作持续至大小循环都结束，最终的异或结果将存在SRAM中留待NFC处理。
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