WO2020153055A1

WO2020153055A1 - Digital-analog conversion device, imaging device, and electronic equipment

Info

Publication number: WO2020153055A1
Application number: PCT/JP2019/049579
Authority: WO
Inventors: 浩希須藤
Original assignee: ソニーセミコンダクタソリューションズ株式会社
Priority date: 2019-01-25
Filing date: 2019-12-18
Publication date: 2020-07-30
Also published as: JP2020120307A

Abstract

A digital-analog conversion device of the present disclosure comprises: an analog signal output unit that outputs an analog signal according to a value of a digital input signal; an analog gain adjustment unit that adjusts the gain of the analog signal; and an initial potential control unit that is connected to an output node of the analog signal output unit and controls the initial potential of the analog signal. The initial potential control unit controls the initial potential of the analog signal to a certain potential regardless of the gain adjusted by the analog gain adjustment unit.

Description

Digital-analog conversion device, imaging device, and electronic device

The present disclosure relates to a digital-analog conversion device, an imaging device, and an electronic device.

In imaging devices, for example, a single-slope analog-digital converter is used as an analog-digital converter that converts an analog pixel signal output from a pixel (pixel circuit) into a digital signal. In the single-slope analog-digital converter, a so-called ramp (RAMP) wave reference signal whose level (voltage) monotonically decreases with time is used as a reference signal in analog-digital conversion. A digital-analog converter (DAC; Digital Analog Converter) is used as a reference signal generation unit that generates a ramp wave reference signal (see, for example, Patent Document 1). Patent Document 1 describes a current control type digital-analog conversion device.

JP, 2007-59991, A

In the digital-analog conversion device described in Patent Document 1, the gain current I _gain in the circuit changes when the analog gain (gain when performing analog-digital conversion) is changed. Along with this, the amplifier output current in the subsequent stage, which receives the gain current I _gain by the current mirror, also changes. As a result, since the DC potential of the output voltage at the output node of the digital-analog converter changes, the initial voltage of the output voltage of the digital-analog converter at the time of changing the analog gain cannot be kept constant.

Therefore, the present disclosure is directed to a digital-analog conversion device capable of maintaining a constant initial voltage of the output voltage of the digital-analog conversion device when an analog gain is changed, an imaging device including the digital-analog conversion device, and An object is to provide an electronic device including an imaging device.

A digital-analog conversion device of the present disclosure (hereinafter, sometimes referred to as a “DA conversion device”) for achieving the above object is
An analog signal output section that outputs an analog signal according to the value of the digital input signal,
An analog gain adjusting section for adjusting the gain of the analog signal, and
An initial potential control unit that is connected to the output node of the analog signal output unit and controls the initial potential of the analog signal is provided. And
The initial potential control unit controls the initial potential of the analog signal to a constant potential regardless of the gain adjusted by the analog gain adjustment unit.

An imaging device of the present disclosure for achieving the above object is
A pixel array section having a pixel circuit including a photoelectric conversion element,
An analog-to-digital converter having a plurality of analog-to-digital converters for converting an analog pixel signal output from each pixel circuit of the pixel array section into a digital signal, and
A reference signal generation unit that generates a ramp wave reference signal and supplies the reference signal to the analog-digital conversion unit;
The reference signal generation unit includes a digital-analog conversion device.
The digital-analog converter is
An analog signal output section that outputs an analog signal according to the value of the digital input signal,
An analog gain adjusting section for adjusting the gain of the analog signal, and
An initial potential control unit that is connected to the output node of the analog signal output unit and controls the initial potential of the analog signal is provided. And
The initial potential control unit controls the initial potential of the analog signal to a constant potential regardless of the gain adjusted by the analog gain adjustment unit.
Further, an electronic device of the present disclosure for achieving the above object includes the image pickup apparatus having the above configuration.

FIG. 1 is a block diagram showing an outline of a basic configuration of a CMOS image sensor which is an example of the image pickup apparatus of the present disclosure. FIG. 2 is a circuit diagram showing an example of the circuit configuration of the pixel circuit. FIG. 3 is a block diagram showing an example of the configuration of a column parallel analog-digital conversion unit mounted on the CMOS image sensor. FIG. 4 is a plan view showing an outline of a flat-type chip structure of a CMOS image sensor. FIG. 5 is an exploded perspective view showing an outline of a stacked semiconductor chip structure of a CMOS image sensor. FIG. 6 is a circuit diagram showing an example of the configuration of a digital-analog converter according to a conventional example. FIG. 7 is an explanatory diagram of fluctuations in the DC potential of the ramp wave output voltage when the analog gain is changed. FIG. 8A is a circuit diagram showing a double-sided auto-zero type comparator, and FIG. 8B is a circuit diagram showing a single-sided auto-zero type comparator. FIG. 9 is an explanatory diagram of the dynamic range of the comparator. FIG. 10 is a circuit diagram showing an example of the configuration of the digital-analog conversion device according to the first embodiment of the present disclosure. FIG. 11 is a waveform diagram showing the output voltage of the digital-analog conversion device according to the first embodiment of the present disclosure. FIG. 12 is a circuit diagram showing an example of the configuration of the digital-analog conversion device according to the second embodiment of the present disclosure. FIG. 13 is a diagram illustrating an application example of the technology according to the present disclosure. FIG. 14 is a block diagram showing an outline of a configuration example of an imaging system which is an example of the electronic device of the present disclosure. FIG. 15 is a block diagram showing a schematic configuration example of a vehicle control system that is an example of a mobile body control system to which the technology according to the present disclosure can be applied. FIG. 16 is a diagram illustrating an example of installation positions of the imaging unit and the vehicle exterior information detection unit in the mobile control system.

Hereinafter, modes for carrying out the technology according to the present disclosure (hereinafter, referred to as “embodiments”) will be described in detail with reference to the drawings. The technology according to the present disclosure is not limited to the embodiment, and various numerical values in the embodiment are examples. In the following description, the same elements or elements having the same function will be denoted by the same reference symbols, without redundant description. The description will be given in the following order.
1. 1. Description of digital-analog conversion device, imaging device, and electronic device according to the present disclosure Imaging device of the present disclosure 2-1. Configuration example of CMOS image sensor 2-2. Configuration example of pixel circuit 2-3. Configuration example of analog-digital conversion unit 2-4. Semiconductor chip structure 2-4-1. Flat type semiconductor chip structure 2-4-2. Stacked semiconductor chip structure 3. Digital-analog conversion device of the present disclosure 3-1. Conventional example 3-2. Example 1 (example using offset current source circuit)
3-3. Example 2 (example using a correction current amplifier circuit)
4. Modification 5. Application example 6. Application example of technology according to the present disclosure 6-1. Electronic device of the present disclosure (example of imaging device)
6-2. Application example to mobile unit 7. Configurations that the present disclosure can take

<Description of DA Converter, Imaging Device, and Electronic Device of the Present Disclosure>
In the DA converter, the imaging device, and the electronic device of the present disclosure, the analog signal output unit receives the gain control signal for adjusting the analog gain and outputs the output current according to the value of the digital input signal. A voltage signal generated by current-voltage converting the generated output current may be output as an analog signal.

Further, in the DA converter, the imaging device, and the electronic device of the present disclosure including the above-described preferable configuration, the gain current and the non-selection side current according to the value of the digital gain control signal are supplied to the analog gain adjusting section. A voltage signal generated and current-voltage converted from the gain current may be supplied to the analog signal output unit as a gain control signal.

Further, in the DA conversion device, the imaging device, and the electronic device of the present disclosure including the above-described preferable configuration, the initial potential control unit has a plurality of current sources, and the offset setting value based on the setting of the analog gain. By supplying a current from the current source corresponding to the above to the output node of the analog signal output section, the initial potential of the analog signal can be controlled to a constant potential.

Further, in the DA converter, the imaging device, and the electronic device of the present disclosure including the above-described preferable configuration, the correction current based on the non-selected side current is output to the output node of the analog signal output unit in the initial potential control unit. By supplying a current to, the initial potential of the analog signal can be controlled to a constant potential.

Further, in the image pickup apparatus and the electronic apparatus of the present disclosure including the above-described preferable configuration, the analog-digital converter is supplied from the analog pixel signal output from the pixel circuit and the reference signal generation unit. A configuration having a comparator having two inputs of the ramp wave reference signal can be adopted. Then, the comparator can be configured such that the initialization operation is performed only on the input side of the analog pixel signal. Further, it is preferable that the analog-digital converter is provided corresponding to each pixel circuit of the pixel array section.

In addition, in the imaging device and the electronic device of the present disclosure including the above-described preferable configuration, each of the first semiconductor chip in which each pixel circuit of the pixel array section is formed and each pixel circuit of the pixel array section It is possible to adopt a configuration having a laminated semiconductor chip structure in which at least two semiconductor chips of the second semiconductor chip in which the analog-digital converter is formed corresponding to the above are laminated.

<Imaging Device of the Present Disclosure>
First, a basic configuration of an imaging device (that is, an imaging device according to the present disclosure) including a DA conversion device to which the technology according to the present disclosure is applied will be described. Here, a CMOS (Complementary Metal Oxide Semiconductor) image sensor, which is a type of an XY addressing type image pickup device, will be described as an example of the image pickup device. The CMOS image sensor is an image sensor manufactured by applying a CMOS process or partially using it.

[Configuration example of CMOS image sensor]
FIG. 1 is a block diagram showing an outline of a basic configuration of a CMOS image sensor which is an example of the image pickup apparatus of the present disclosure.

The CMOS image sensor 1 according to this example is configured to include a pixel array section 11 and a peripheral circuit section of the pixel array section 11. The pixel array unit 11 includes pixel circuits (pixels) 2 including a light receiving unit (photoelectric conversion unit) arranged two-dimensionally in the row direction and the column direction, that is, in a matrix. Here, the row direction means the arrangement direction of the pixel circuits 2 in the pixel row (so-called horizontal direction), and the column direction means the arrangement direction of the pixel circuits 2 in the pixel column (so-called vertical direction). The pixel circuit 2 performs photoelectric conversion to generate and accumulate photocharges according to the amount of received light.

The peripheral circuit section of the pixel array section 11 includes, for example, a row selection section 12, a constant current source section 13, an analog-digital conversion section 14, a reference signal generation section 15, a horizontal transfer scanning section 16, a signal processing section 17, and timing. It is configured by the control unit 18 and the like. Then, as the reference signal generation unit 15, a DA converter to which the technology according to the present disclosure is applied (that is, the DA converter of the present disclosure) is used.

In the pixel array unit 11, pixel control lines 31 ₁ to 31 _m (hereinafter, may be collectively referred to as “pixel control line 31”) are arranged along the row direction for each pixel row in a matrix of pixel arrays. Is wired. Further, vertical signal lines 32 ₁ to 32 _n (hereinafter, may be collectively referred to as “vertical signal line 32”) are arranged along the column direction for each pixel column. The pixel control line 31 transmits a drive signal for driving when reading a signal from the pixel circuit 2. In FIG. 1, the pixel control line 31 is illustrated as one wiring, but the number is not limited to one. One end of the pixel control line 31 is connected to the output end corresponding to each row of the row selection unit 12.

Below, each component of the peripheral circuit section of the pixel array section 11, that is, the row selection section 12, the constant current source section 13, the analog-digital conversion section 14, the reference signal generation section 15, the horizontal transfer scanning section 16, the signal processing. The unit 17 and the timing control unit 18 will be described.

The row selection unit 12 is composed of a shift register, an address decoder, and the like, and controls scanning of pixel rows and addresses of pixel rows when selecting each pixel circuit 2 of the pixel array unit 11. Although not specifically shown, the row selection unit 12 generally has two scanning systems, a read scanning system and a sweep scanning system.

The read scanning system sequentially selects and scans the pixel circuits 2 of the pixel array section 11 in units of rows in order to read pixel signals from the pixel circuits 2. The pixel signal read from the pixel circuit 2 is an analog signal. The sweep-out scanning system performs sweep-out scanning with respect to the read-out row in which the read-out scanning is performed by the read-out scanning system, prior to the read-out scanning by the shutter speed time.

By the sweep-out scanning by this sweep-out scanning system, unnecessary photoelectric charges are swept out from the photoelectric conversion section of the pixel circuit 2 in the readout row, and the photoelectric conversion section is reset. Then, by sweeping out (resetting) unnecessary charges by this sweeping scanning system, a so-called electronic shutter operation is performed. Here, the electronic shutter operation means an operation of discarding the photocharges of the photoelectric conversion unit and newly starting the exposure (starting the accumulation of the photocharges).

The constant current source unit 13 includes a plurality of current sources I each of which is composed of, for example, a MOS transistor and is connected to each of the vertical signal lines 32 ₁ to 32 _n for each pixel column, and is selectively scanned by the row selection unit 12. A bias current is supplied to each pixel circuit 2 in the pixel row through each of the vertical signal lines 32 ₁ to 32 _n .

The analog-digital conversion unit 14 includes a set of a plurality of analog-digital converters provided corresponding to the pixel columns of the pixel array unit 11, for example, provided for each pixel column. The analog-digital conversion unit 14 is a column parallel type analog-digital conversion unit that converts an analog pixel signal output through each of the vertical signal lines 32 ₁ to 32 _n for each pixel column into a digital signal.

As the analog-to-digital converter in the column parallel analog-to-digital converter 14, for example, a single slope analog-to-digital converter which is an example of the reference signal comparison type analog-to-digital converter can be used.

The reference signal generation unit 15 includes a DA converter of the present disclosure to be described later, and generates a reference signal of a ramp (RAMP) wave whose level (voltage) monotonically decreases with time. The reference signal of the ramp wave generated by the reference signal generation unit 15 is supplied to the analog-digital conversion unit 14 and used as a reference signal for analog-digital conversion.

The horizontal transfer scanning unit 16 is composed of a shift register, an address decoder, and the like, and controls the scanning of the pixel column and the address of the pixel column when reading the signal of each pixel circuit (pixel) 2 of the pixel array unit 11. Under the control of the horizontal transfer scanning unit 16, the pixel signal converted into a digital signal by the analog-digital conversion unit 14 is read out to the horizontal transfer line 19 in pixel column units.

The signal processing unit 17 performs predetermined signal processing on the digital pixel signal supplied through the horizontal transfer line 19 to generate two-dimensional image data. For example, the signal processing unit 17 corrects vertical line defects and point defects, clamps signals, and performs digital signal processing such as parallel-serial conversion, compression, encoding, addition, averaging, and intermittent operation. To go. The signal processing unit 17 outputs the generated image data as an output signal of the CMOS image sensor 1 to a device in the subsequent stage.

The timing control unit 18 generates various timing signals, clock signals, control signals, etc., and based on these generated signals, the row selection unit 12, the constant current source unit 13, the analog-digital conversion unit 14, see The drive control of the signal generation unit 15, the horizontal transfer scanning unit 16, the signal processing unit 17, and the like is performed.

[Pixel circuit configuration example]
FIG. 2 is a circuit diagram showing an example of the configuration of the pixel circuit 2. The pixel circuit 2 has, for example, a photodiode 21 as a photoelectric conversion element which is a light receiving element. The pixel circuit 2 has a configuration including a transfer transistor 22, a reset transistor 23, an amplification transistor 24, and a selection transistor 25 in addition to the photodiode 21.

As the four transistors of the transfer transistor 22, the reset transistor 23, the amplification transistor 24, and the selection transistor 25, for example, N-channel MOS type field effect transistors (FETs) are used. However, the combination of the conductivity types of the four transistors 22 to 25 illustrated here is merely an example, and the present invention is not limited to these combinations.

For this pixel circuit 2, as the above-mentioned pixel control line 31, a plurality of pixel control lines are wired in common to each pixel circuit 2 in the same pixel row. The plurality of pixel control lines are connected to the output end of the row selection unit 12 corresponding to each pixel row in pixel row units. The row selection unit 12 appropriately outputs the transfer signal TRG, the reset signal RST, and the selection signal SEL to the plurality of pixel control lines.

The photodiode 21 has an anode electrode connected to a low-potential-side power source (eg, ground), and photoelectrically converts the received light into a photocharge (here, photoelectron) having a charge amount corresponding to the light amount thereof. Accumulates electric charge. The cathode electrode of the photodiode 21 is electrically connected to the gate of the amplification transistor 24 via the transfer transistor 22. Here, the region where the gate of the amplification transistor 24 is electrically connected is the floating diffusion (floating diffusion region/impurity diffusion region) FD. The floating diffusion FD is a charge-voltage converter that converts charges into a voltage.

The gate of the transfer transistor 22 is supplied with a transfer signal TRG that activates a high level (for example, V _DD level) from the row selection unit 12. When the transfer transistor 22 becomes conductive in response to the transfer signal TRG, it is photoelectrically converted by the photodiode 21 and transfers the photocharges accumulated in the photodiode 21 to the floating diffusion FD.

The reset transistor 23 is connected between the node of the high-potential-side power supply voltage V _DD and the floating diffusion FD. To the gate of the reset transistor 23, the reset signal RST whose high level becomes active is given from the row selection unit 12. The reset transistor 23 becomes conductive in response to the reset signal RST, and resets the floating diffusion FD by discarding the charge of the floating diffusion FD to the node of the voltage V _DD .

The gate of the amplification transistor 24 is connected to the floating diffusion FD, and the drain thereof is connected to the node of the high-potential-side power supply voltage V _DD . The amplification transistor 24 serves as an input unit of a source follower that reads out a signal obtained by photoelectric conversion in the photodiode 21. That is, the source of the amplification transistor 24 is connected to the vertical signal line 32 via the selection transistor 25. The amplification transistor 24 and the current source I connected to one end of the vertical signal line 32 constitute a source follower that converts the voltage of the floating diffusion FD into the potential of the vertical signal line 32.

The drain of the selection transistor 25 is connected to the source of the amplification transistor 24, and the source is connected to the vertical signal line 32. A selection signal SEL that activates a high level is applied to the gate of the selection transistor 25 from the row selection unit 12. The selection transistor 25 is rendered conductive in response to the selection signal SEL, and thereby transmits the signal output from the amplification transistor 24 to the vertical signal line 32 by setting the pixel circuit 2 in the selected state.

In the above circuit example, the pixel circuit 2 has the 4Tr configuration including the transfer transistor 22, the reset transistor 23, the amplification transistor 24, and the selection transistor 25, that is, four transistors (Tr). , But not limited to this. For example, the selection transistor 25 may be omitted, and the amplification transistor 24 may have a 3Tr configuration in which the function of the selection transistor 25 is provided. If necessary, the number of transistors may be increased to 5Tr or more. ..

[Configuration example of analog-digital converter]
Next, a configuration example of the column parallel analog-digital conversion unit 14 will be described. An example of the configuration of the column parallel analog-digital conversion unit 14 is shown in FIG. The analog-digital converter 14 in the CMOS image sensor 1 of the present disclosure is composed of a set of a plurality of single slope type analog-digital converters provided corresponding to each pixel circuit 2 of the pixel array unit 11. Here, the single-slope analog-digital converter 140 in the n-th column will be described as an example.

The single-slope analog-digital converter 140 has a circuit configuration including a comparator 141, a counter circuit 142, and a latch circuit 143. The single-slope analog-to-digital converter 140 uses the ramp wave reference signal generated by the reference signal generation unit 19. Specifically, it is given as a reference signal to the comparator 141 provided for each pixel column.

The comparator 141 uses the analog pixel signal read from the pixel circuit 2 as a comparison input and the ramp wave reference signal generated by the reference signal generation unit 19 as a reference input, and compares the two signals. Then, for example, the output of the comparator 141 is in the first state (for example, high level) when the reference signal is larger than the pixel signal, and the output is in the second state (for example, when the reference signal is less than or equal to the pixel signal). , Low level). As a result, the comparator 141 outputs a pulse signal having a pulse width corresponding to the signal level of the pixel signal, specifically, the magnitude of the signal level, as the comparison result.

The clock signal CLK is given to the counter circuit 142 from the timing control unit 18 at the same timing as the timing of starting the supply of the reference signal to the comparator 141. Then, the counter circuit 142 measures the pulse width period of the output pulse of the comparator 141, that is, the period from the start of the comparison operation to the end of the comparison operation by performing the counting operation in synchronization with the clock signal CLK. The count result (count value) of the counter circuit 142 becomes a digital value obtained by digitizing an analog pixel signal.

The latch circuit 143 holds (latches) the digital value that is the count result of the counter circuit 142. Further, the latch circuit 143 is an example of noise removal processing by calculating the difference between the D-phase count value corresponding to the signal level pixel signal and the P-phase count value corresponding to the reset level pixel signal. , CDS (Correlated Double Sampling) processing. Then, under the drive of the horizontal transfer scanning unit 16, the latched digital value is output to the horizontal transfer line 19.

As described above, in the column parallel analog-to-digital conversion unit 14 including the set of the single slope type analog-to-digital converter 140, the reference signal of the linearly changing analog value generated by the reference signal generation unit 15 and the pixel A digital value is obtained from time information until the magnitude relationship with the analog pixel signal output from the circuit 2 changes.

In the above example, the column parallel analog-to-digital conversion unit 14 has the configuration in which the analog-to-digital converter 140 is arranged in a one-to-one relationship with the pixel column. It is also possible to adopt a configuration in which the analog-digital converter 140 is arranged as a unit.

[Semiconductor chip structure]
As the semiconductor chip structure of the CMOS image sensor 1 having the above structure, a flat semiconductor chip structure and a laminated semiconductor chip structure can be exemplified. In addition, the pixel structure may be a back-illuminated pixel structure in which light emitted from the opposite back surface side is taken in when the substrate surface on the side where the wiring layer is formed is the front surface (front surface). However, a front-illuminated pixel structure that takes in light emitted from the front side can also be used.

Below, an outline of the flat type semiconductor chip structure and the laminated type semiconductor chip structure will be explained.

(Flat type semiconductor chip structure)
FIG. 4 is a plan view showing an outline of a flat-type chip structure of the CMOS image sensor 1. As shown in FIG. 4, a flat semiconductor chip structure, that is, a flat structure, has a periphery of the pixel array unit 11 on the same semiconductor chip 41 as the pixel array unit 11 in which the pixel circuits 2 are arranged in a matrix. It has a structure in which each component of the circuit portion is formed. Specifically, on the same semiconductor chip 41 as the pixel array unit 11, the row selection unit 12, the constant current source unit 13, the analog-digital conversion unit 14, the reference signal generation unit 15, the horizontal transfer scanning unit 16, the signal processing unit. 17, a timing controller 18 and the like are formed.

(Stacked semiconductor chip structure)
FIG. 5 is an exploded perspective view showing an outline of a stacked semiconductor chip structure of the CMOS image sensor 1. As shown in FIG. 5, the laminated semiconductor chip structure, so-called laminated structure, has a structure in which at least two semiconductor chips, that is, the first semiconductor chip 42 and the second semiconductor chip 43, are laminated.

In this laminated semiconductor chip structure, the first semiconductor chip 42 of the first layer has a pixel array section 11 in which pixel circuits 2 including photoelectric conversion elements (for example, photodiodes 21) are two-dimensionally arranged in a matrix. It is the formed pixel chip. The second semiconductor chip 43 in the second layer is an analog formed of a set of analog-digital converters (ADC) 140 arranged corresponding to the pixel circuits 2 arranged two-dimensionally in a matrix of the pixel array section 11. A circuit chip in which a circuit section including the digital conversion section 14 is formed.

Each pixel circuit 2 of the first semiconductor chip 42 of the first layer and each analog-digital converter 140 of the second semiconductor chip 43 of the second layer are connected to each other by Cu-Cu connection (copper-copper connection) or the like. Electrically connected through (not shown).

According to this laminated semiconductor chip structure, a process suitable for manufacturing the pixel circuit 2 can be applied to the first semiconductor chip 42 of the first layer, and a circuit portion can be manufactured to the second semiconductor chip 43 of the second layer. Suitable process can be applied. Thereby, in manufacturing the CMOS image sensor 1, the process can be optimized. In particular, when manufacturing a circuit portion, it is possible to apply an advanced process.

<Digital-Analog Converter of the Present Disclosure>
In the CMOS image sensor 1, the digital-analog converter of the present disclosure used as the reference signal generator 15 is a current control type digital-analog converter. Before describing the digital-analog converter of the present disclosure, a conventional example of a current control type digital-analog converter will be described.

[Conventional example]
FIG. 6 is a circuit diagram showing an example of the configuration of a conventional digital-analog conversion device 50A.

The digital-analog conversion device 50A according to the conventional example is configured as a ground-reference DA conversion device, and has a configuration including an analog signal output unit 51, an analog gain adjustment unit 52, a counter decoder 53, and a gain decoder 54. ing.

(Analog signal output section)
The analog signal output unit 51 generates an output current according to the value of the digital input signal DI decoded by the counter decoder 53, and outputs a voltage signal obtained by current-voltage converting the generated output current as an analog signal. In addition, the analog signal output unit 51 adjusts the gain of the analog signal according to the bias voltage V _bias that is the gain control signal supplied from the analog gain adjusting unit 52.

The analog signal output section 51 has the following circuit configuration. That is, the analog signal output unit 51 includes a differential transistor and a plurality of basic current source cells 511 ₁ to 511 including a current source transistor of the differential transistor, and a common bias voltage is supplied to the gate of the current source transistor. It is configured to have _n .

In the case of the ground-referenced DA converter 50A, the plurality of basic current source cells 511 ₁ to 511 _n are formed by P-channel MOS transistors. The analog signal output unit 51 has a plurality of basic current source cells 511 ₁ to 511 _n , a selected output line 512, a non-selected output line 513, and a terminating resistor 514.

The plurality of basic current source cells 511 ₁ to 511 _n of the analog signal output section 51 have a common configuration. That is, each of the basic current source cells 511 ₁ to 511 _n includes a P-channel MOS transistor PT ₁₁ forming a current source transistor, and P-channel MOS transistors PT ₁₂ and PT ₁₃ forming sources which are connected to each other to form a differential transistor. It is composed of.

In the basic current source cells 511 ₁ to 511 _n , the source of the P channel MOS transistor PT ₁₁ is connected to the power source line L ₁ of the power source voltage V _DD , and the drain is connected to the sources of the P channel MOS transistors PT ₁₂ and PT _13. ing.

One end of the non-selected output line 513 is connected to the drain of the P-channel MOS transistor PT ₁₂ . The other end of the non-selected output line 513 is connected to the ground line L ₂ of GND potential. The ground line L ₂ of GND potential has a parasitic wiring resistance 515 having a resistance value R ₀ of about 1Ω.

One end of the selection output line 512 is connected to the drain of the P-channel MOS transistor PT ₁₃ . The other end of the selection output line 512 is connected to one end of a terminating resistor 514. The other end of the terminating resistor 514 is connected to the ground line L ₂ . The terminating resistor 514 has a resistance value R _{1 of} about 100Ω and performs current-voltage conversion.

In the plurality of basic current source cells 511 ₁ to 511 _n , the gate of the P-channel MOS transistor PT ₁₁ is commonly connected to the supply line L ₃ of the bias voltage V _bias which is the gain control signal supplied from the analog gain adjusting section 52. Has been done. The gate of the P-channel MOS transistor PT ₁₂ is used as the input terminal of the digital signal Q _in the gate of the P-channel MOS transistor PT ₁₃ is in the input end of the digital signal Q _in a reverse-phase signal xQ _in.

In the plurality of basic current source cells 511 ₁ to 511 _n , the drain of one P-channel MOS transistor PT ₁₃ of the differential transistors is commonly connected to the selection output line 512, and the drain of the other P-channel MOS transistor PT ₁₂ is non-conductive. It is commonly connected to the selection output line 513. The connection node becomes the output node ND ₅₁ with a selected output line 512 and the terminating resistor 514, from the output node ND _51, the analog signal is derived which is the output signal of the analog signal output section 51. That is, the output node ND ₅₁ is the output node of the analog signal output unit 51 and the output node of the digital-analog conversion device 50A.

In the analog signal output unit 51, one of the plurality of basic current source cells 511 ₁ to 511 _n is selected as a P-channel MOS transistor PT _{13 of the} differential transistor according to the decode information of the counter decoder 53. As a result, the current outputs of the selected basic current source cells are added and the resulting current flows to the selected output line 512 as the lamp output current I _ramp . Then, the lamp output current I _ramp is converted into a voltage signal by the terminating resistor 514 and output as an analog signal from the output node ND ₅₁ .

Further, in the plurality of basic current source cells 511 ₁ to 511 _n , the other P-channel MOS transistor PT ₁₃ is selected according to the decode information of the counter decoder 53. In this case, the current outputs of the selected basic current source cells are added and _flown as the lamp non-output current I _{ramp_minus} to the ground line L ₂ via the non-selected output line 513.

As described above, the analog signal output section 51 generates the _ramp output current I _ramp according to the value of the digital input signal DI decoded by the counter decoder 53. Then, the number of selected basic current source cells is gradually reduced according to the value of the digital input signal DI, and the lamp output current I _ramp at that time is subjected to current-voltage conversion to generate a voltage signal of a ramp wave. And output as a ramp wave analog signal.

(Analog gain adjuster)
The analog gain adjustment unit 52 generates a bias voltage V _bias which is a gain control signal according to the value of the digital gain control signal DGI decoded by the gain decoder 54. Then, the analog gain adjustment unit 52 outputs the generated bias voltage V _bias to the analog signal output unit 51 as a signal for adjusting the gain.

The analog gain adjusting unit 52 includes a differential transistor and a current source transistor of the differential transistor, and a plurality of basic current source cells 521 to which a bias voltage according to a common reference current is supplied to the gate of the current source transistor. _The configuration has ₁ to 521 _n . In the case of the ground-referenced DA converter 50A, the plurality of basic current source cells 521 ₁ to 521 _n are formed by N-channel MOS transistors.

The analog gain adjusting section 52 has a selection line 522, a non-selection line 523, an N-channel MOS transistor DN ₂₁ , and a P-channel MOS transistor DP ₂₁ in addition to the plurality of basic current source cells 521 ₁ to 521 _n. There is. The N-channel MOS transistor DN ₂₁ and the P-channel MOS transistor DP ₂₁ have a diode connection configuration in which the gate and the drain are commonly connected.

The plurality of basic current source cells 521 ₁ to 521 _n of the analog gain adjusting section 52 have a common configuration. That is, each of the basic current source cells 521 ₁ to 521 _n has an N-channel MOS transistor NT ₂₁ forming a current source transistor, and N-channel MOS transistors NT ₂₂ and NT ₃₃ having sources connected to each other to form a differential transistor. It is composed of.

In the basic current source cells 521 ₁ to 521 _n , the source of the N-channel MOS transistor NT ₂₁ is connected to the ground line L ₂ having the GND potential, and the drain is connected to each source of the N-channel MOS transistors NT ₂₂ and NT ₂₃ . ..

One end of the non-select line 523 is connected to the drain of the N-channel MOS transistor NT ₂₂ . The other end of the non-selection line 523 is connected to the power supply line L ₁ of the power supply voltage V _DD . The drain of N-channel MOS transistor NT _23, one end of the selection line 522 are connected.

The other end of the selection line 522 is connected to the drain and gate of the P-channel MOS transistor DP ₂₁ , and the connection node is connected to the gates of the current source transistors of the plurality of basic current source cells 511 ₁ to 511 _n of the analog signal output section 51. It is connected. In other words, the P-channel MOS transistor DP _{21 of} the analog gain adjusting section 52 and the P-channel MOS transistor PT ₂₁ forming the current source transistors of the plurality of basic current source cells 511 ₁ to 511 _n of the analog signal output section 51 are used for the current A mirror circuit is formed.

In the plurality of basic current source cells 521 ₁ to 521 _n , the gate of the N-channel MOS transistor NT ₂₁ is commonly connected to the gate of the N-channel MOS transistor DN _{21 having} a diode connection configuration.

In the N-channel MOS transistor DN ₂₁ , the source is connected to the ground line L ₂ , the drain and gate are connected to the supply line of the reference current I _ref , and the connection point (gate) is a plurality of basic current source cells 521 ₁ to 521 _n is connected to the gate of each N-channel MOS transistor NT ₂₁ .

Then, the N-channel MOS transistor DN ₂₁ converts the reference current I _ref into a voltage and _{supplies it} as a reference voltage V _ref to the gates of the N-channel MOS transistors NT ₂₁ of the plurality of basic current source cells 521 ₁ to 521 _n .

The gate of N-channel MOS transistor NT ₂₂ is connected to the supply line of the signal G _in, the gate of the N-channel MOS transistor NT ₂₃ is connected to the supply line of the signal xG _in the signal G _in opposite phase.

In the plurality of basic current source cells 521 ₁ to 521 _n , the drain of one N-channel MOS transistor NT ₂₃ of the differential transistors is commonly connected to the select line 522, and the drain of the other N-channel MOS transistor NT ₂₂ is unselected. Commonly connected to the line 523.

In the plurality of basic current source cells 521 ₁ to 521 _n , one N channel MOS transistor NT _{23 of the} differential transistors is selected according to the decoding information of the gain decoder 54. As a result, the current outputs of the selected basic current source cells are added and flow to the selection line 522 as the gain current I _gain . Then, the gain current I _gain is converted into a voltage signal by the P-channel MOS transistor DP ₂₁ and output to the analog signal output unit 51.

Further, in the plurality of basic current source cells 521 ₁ to 521 _n , the other N-channel MOS transistor NT ₂₂ is selected according to the decoding information of the gain decoder 54. In this case, the current outputs of the selected basic current source cells are added and the non-selected side current I _{gain_minus} flows through the non-selected line 523.

As described above, the analog gain adjusting section 52 generates the gain current I _gain and the non-selection side current I _{gain_minus} according to the value of the digital gain control signal DGI decoded by the gain decoder 54. Then, the bias voltage V _bias based on the gain current I _gain is generated, the bias voltage V _bias is the analog signal output section 51, is outputted as the gain control signal for adjusting the gain. The analog gain adjusting unit 52 can change the slope of the output voltage of the digital-analog converter 50A by the gain current I _gain .

In the digital-analog converter 50A according to the conventional example having the above configuration, the gain current I _gain in the circuit changes when the analog gain of the analog-digital converter 14 is changed. For example, when the gain current I _{gain of} 0 dB is 2I, the gain current I _{gain of} 6 dB becomes I. Along with this, the lamp output current I _ramp of the analog signal output unit 51 at the _subsequent stage, which receives the gain current I _gain by the current mirror, also changes from 2I (0 dB) to I (6 dB). As a result, the DC potential of the output voltage of the digital-analog converter 50A at the output node ND ₅₁ of the digital-analog converter 50A fluctuates between 0 dB and 6 dB as shown in FIG. The output voltage of the digital-analog converter 50A cannot be kept constant. Further, due to the tolerance of the power supply voltage supplied from the outside of the semiconductor chip, the DC potential of the output voltage of the digital-analog converter 50A has individual differences.

Here, the situation where the output voltage of the digital-analog converter 50A needs to be kept constant when the analog gain is changed will be described.

First, the comparator 141 (see FIG. 3) of the analog-digital converter 140, which receives the pixel signal VSL output from the pixel circuit 2 and the reference signal RAMP of the ramp wave supplied from the reference signal generator 15 as two inputs. Will be described. The comparator 141 includes a double-sided auto-zero type comparator and a single-sided auto-zero type comparator.

(Both side auto zero type comparator)
A circuit diagram of a double-sided auto-zero type comparator is shown in FIG. 8A. The double-sided auto-zero type comparator has a configuration including a differential amplifier 60, a first capacitive element C ₃₁ , a second capacitive element C _{32, a} first switch transistor NT ₃₃ , and a second switch transistor NT _34. There is. Here, for example, N-channel MOS transistors are used as the first switch transistor NT ₃₃ and the second switch transistor NT ₃₄ .

The differential amplifier 60 is composed of a first differential transistor NT ₃₁ , a second differential transistor NT ₃₂ , a current source transistor NT ₃₅ , a first load transistor PT ₃₁ and a second load transistor PT _32. ing. Here, N-channel MOS transistors are used as the first differential transistor NT ₃₁ and the second differential transistor NT ₃₂ , and P-channel MOS transistors are used as the first load transistor PT ₃₁ and the second load transistor PT _32. ing.

In the differential amplifier 60, the sources of the first differential transistor NT ₃₁ and the second differential transistor NT ₃₂ are commonly connected to form a differential pair that performs a differential operation. The current source transistor NT ₃₅ is connected between the source common connection node of the first differential transistor NT ₃₁ and the second differential transistor NT ₃₂ and the ground GND. The first load transistor PT ₃₁ has a diode connection configuration in which the gate and the drain are commonly connected, and is connected in series to the first differential transistor NT ₃₁ . That is, the drains of the first load transistor PT ₃₁ and the first differential transistor NT ₃₁ are commonly connected.

The second load transistor PT ₃₂ is connected in series with the second differential transistor NT ₃₂ . That is, the drains of the second load transistor PT ₃₂ and the second differential transistor NT ₃₂ are commonly connected. The gates of the first load transistor PT ₃₁ and the second load transistor PT ₃₂ are commonly connected to form a current mirror circuit.

The node to which the drain of the second differential transistor NT _{32 and} the drain of the second load transistor PT ₃₂ are connected is the output node N of the differential amplifier 60, and an output signal from the output node N is output. OUT is derived. The sources of the first load transistor PT ₃₁ and the second load transistor PT ₃₂ are connected to the power supply line of the power supply voltage V _DD .

The first capacitive element C ₃₁ is connected between the input terminal of the ramp wave reference signal RAMP and the gate of the first differential transistor NT ₃₁ . Then, the reference signal RAMP becomes one input of the differential amplifier 60 via the first capacitive element C ₃₁ . The second capacitive element C ₃₂ is connected between the input terminal of the pixel signal VSL and the gate of the second differential transistor NT ₃₂ . Then, the pixel signal VSL becomes the other input of the differential amplifier 60 via the second capacitive element C ₃₂ .

The first switch transistor NT ₃₃ is connected between the gate and the drain of the first differential transistor NT ₃₁ . The second switch transistor NT ₃₄ is connected between the gate and the drain of the second differential transistor NT ₃₂ . Then, the first switch transistor NT ₃₃ and the second switch transistor NT ₃₄ are ON (conductive)/OFF (non-conductive) controlled by the auto-zero signal AZ.

That is, by controlling the first switch transistor NT ₃₃ and the second switch transistor NT ₃₄ by the auto-zero signal AZ, the auto-zero operation which is the initialization operation of the differential amplifier 60 is performed. Thus, in the comparator of this circuit example, the auto-zero operation of the differential amplifier 60 is performed on both the input side of the reference signal RAMP of the ramp wave and the input side of the pixel signal VSL.

(One side auto zero type comparator)
A circuit diagram of a one-sided auto-zero type comparator is shown in FIG. 8B. The one-sided auto-zero type comparator is the two-sided auto-zero type comparator shown in FIG. 8A, in which the first capacitive element C ₃₁ and the first switch transistor NT ₃₃ on the input side of the ramp wave reference signal RAMP are omitted. The configuration other than is the same as the case of the double-sided auto-zero type. As a result, in the comparator of this circuit example, the auto-zero operation of the differential amplifier 60 is performed only on one side of the input side of the pixel signal VSL. There is no problem with one-sided auto zero due to the circuit operation of the comparator.

In terms of circuit area, the capacitive element occupies a large proportion. Therefore, in the case of the one-sided auto-zero type comparator, the circuit area can be reduced as compared with the two-sided auto-zero type comparator by the reduction of the first capacitive element C ₃₁ . In particular, in the case of the stacked semiconductor chip structure shown in FIG. 5, a large number of analog-digital converters 140 including a comparator 141 are arranged corresponding to the pixel circuits 2. Therefore, the use of a one-sided auto-zero type comparator as the comparator 141 has a great effect of reducing the circuit scale of the analog-digital converter 140.

By the way, in the case of a two-sided auto-zero type comparator, normally, the potential of the reference signal RAMP of the ramp wave seen from the input of the comparator becomes constant irrespective of the DC potential of the reference signal RAMP itself due to the auto-zero operation of the comparator. , It doesn't matter. However, in the case of a one-sided auto-zero type comparator having no capacitive element on the input side of the reference signal RAMP, the potential of the reference signal RAMP during auto-zero operation becomes important.

For example, in a one-sided auto-zero type comparator, if the overdrive voltage V _ov of the current source transistor NT ₃₅ is 0.2 V and the gate-source voltage V _gs of the differential transistors NT ₃₁ and NT ₃₂ is 0.6 V, this comparator The lower limit of the differential input for moving in the saturation region is 0.8V (=0.2V+0.6V).

Further, for example, if the power supply voltage V _DD is 2.9 V and the gate-source voltage V _gs of the load transistors PT ₃₁ and PT ₃₂ is 0.6 V, the upper limit of the differential input for operating this comparator in the saturation region is set. It becomes 2.7V (=2.9V-0.6V-0.2V+0.6V). An explanatory view of the dynamic range of the comparator is shown in FIG.

In the case of a one-sided auto-zero type comparator, the DC potential of the reference signal RAMP needs to be within the dynamic range of the comparator in FIG. 9, but the output voltage of the digital-analog converter 50A when the analog gain is changed is not constant. In this case, there is a possibility that the value may fall outside the lower limit range especially at high gain. This is a problem when using the digital-analog converter 50A according to the conventional example, and when the analog gain is changed, the output voltage of the digital-analog converter 50A (that is, the voltage of the reference signal of the ramp wave) is kept constant. That is why it is necessary.

The technology according to the present disclosure has been made to solve the above problems. In order to keep the initial voltage of the output voltage of the digital-analog converter when the analog gain is changed, in the embodiment of the present disclosure, the analog signal output unit ₅₁ is connected to the output node ND ₅₁ , and the analog signal An initial potential control unit that controls the initial potential is provided. Then, the initial potential control unit controls the initial potential of the analog signal to be a constant potential regardless of the gain adjusted by the analog gain adjustment unit 52.

Then, the digital-analog converter according to the present embodiment can be used as the analog-digital converter 140 of the analog-digital converter 14 in the above-described image pickup device (specifically, the CMOS image sensor 1). Accordingly, even if the comparator 141 of the analog-digital converter 140 is a one-sided auto-zero type comparator, it can be operated within the dynamic range of the comparator even if the analog gain is increased, so that a high-quality captured image can be obtained. You can

A specific example of the digital-analog converter according to the present embodiment for keeping the initial voltage of the output voltage of the digital-analog converter when the analog gain is changed will be described below.

[Example 1]
FIG. 10 is a circuit diagram showing an example of the configuration of the digital-analog conversion device according to the first embodiment of the present disclosure.

The digital-analog conversion device 50B according to the first embodiment includes an offset current source circuit that is an example of an initial potential control unit in addition to the analog signal output unit 51, the analog gain adjustment unit 52, the counter decoder 53, and the gain decoder 54. 55 and a manual offset decoder 56. The analog signal output unit 51 and the analog gain adjustment unit 52 are the same as those in the case of the digital-analog conversion device 50A according to the conventional example shown in FIG.

The offset current source circuit 55, which is an example of the initial potential control unit, is connected to the output node ND ₅₁ of the analog signal output unit 51 via the signal line S ₁ and is controlled by the gain adjusted by the analog gain adjustment unit 52. Instead, the initial potential of the analog signal output from the output node ND ₅₁ is controlled to be a constant potential.

The offset current source circuit 55 is configured to have a plurality of current source transistors CT ₃₁ and the same number of switch transistors ST ₃₁ . The plurality of current source transistors CT ₃₁ and the switch transistor ST ₃₁ are P-channel MOS transistors, and are connected in series between the power supply line L ₁ of the power supply voltage V _DD and the output node ND ₅₁ of the analog signal output unit 51. There is.

The offset current source circuit 55 further has a P-channel MOS transistor DP ₃₁ and an N-channel MOS transistor DN ₃₁ . The P-channel MOS transistor DP ₃₁ has a diode connection configuration in which a gate and a drain are commonly connected, and a current mirror circuit is formed by commonly connecting a plurality of current source transistors CT ₃₁ and a gate. ing. N-channel MOS transistor DN ₃₁ is connected in series with the P-channel MOS transistor DP _31, and a gate receiving a reference current I _ref of the analog gain adjustment unit 52.

The offset current source circuit 55 having the above configuration is externally applied based on the setting of the analog gain, and on/off-controls the plurality of switch transistors ST ₃₁ according to the offset set value decoded by the manual offset decoder 56. .. As a result, a current flows from the current source transistor CT ₃₁ to the output node ND ₅₁ through the selected switch transistor ST ₃₁ , and is supplied to the terminating resistor 514.

According to the offset current source circuit 55, which is an example of the initial potential control unit, when the lamp output current I _ramp of the analog signal output unit 51 changes due to the change of the analog gain, the offset current corresponding to the correction current is manually set. By flowing into the terminating resistor 514 through the output node ND _51, the output voltage of the digital-analog converter 50B as shown in FIG. 11 can be obtained. As a result, even if the analog gain is changed, the initial voltage of the output voltage of the digital-analog converter 50B can be kept constant. In FIG. 11, R ₀ is the resistance value of the parasitic wiring resistance 515, and R ₁ is the resistance value of the termination resistance 514.

According to the above-described digital-analog converter 50B according to the first embodiment, the initial voltage of the output voltage of the digital-analog converter 50B when the analog gain is changed can be kept constant by the action of the offset current source circuit 55. ..

[Example 2]
FIG. 12 is a circuit diagram showing an example of the configuration of the digital-analog conversion device according to the second embodiment of the present disclosure.

The digital-analog conversion device 50C according to the second embodiment includes a correction current amplification that is an example of an initial potential control unit in addition to the analog signal output unit 51, the analog gain adjustment unit 52, the counter decoder 53, and the gain decoder 54. It has a circuit 57. The analog signal output unit 51 and the analog gain adjustment unit 52 are the same as those in the case of the digital-analog conversion device 50A according to the conventional example shown in FIG.

The correction current amplification circuit 57 is connected to the analog gain adjusting section 52 via the signal line L ₄ and is connected to the output node ND ₅₁ of the analog signal output section 51 via the signal line S ₂ . Correction current amplifying circuit 57, the unselected-side current I _{Gain_minus} the analog gain adjustment unit 52, and input through the signal line L _4, based on the non-select side current I _{Gain_minus,} the gain setting in the analog gain adjuster 52 A correction current I _corct that accurately compensates for the current fluctuation due to the change is generated.

The correction current amplifier circuit 57 _supplies the generated correction current I _corct to the output node ND ₅₁ of the analog signal output unit 51 through the signal line S ₂ . As a result, the correction current I _corct that accurately compensates for the amount of current fluctuation caused by changing the gain setting is added to the lamp output current I _ramp of the analog signal output unit 51. As a result, the total current consumption of the analog signal output unit 51 and the correction current amplification circuit 57 is kept constant regardless of the gain setting. Therefore, the current of the entire digital-analog converter 50C is kept constant regardless of the gain setting.

Further, the correction current I _corct is supplied to the output node ND ₅₁ , is added to the lamp output current I _ramp , and flows into the terminating resistor 514 having the resistance value R ₁ . Thus, at 0 dB, when the gain current I _gain is 2I, the correction current I _corct becomes 0, and the current flowing through the terminating resistor 514 becomes 2I. At 6 dB, when the gain current I _gain is I, the correction current I _corct becomes 1. _corct becomes I, and the current flowing through the terminating resistor 514 becomes 2I. This means that even if the analog gain is changed, the current flowing through the terminating resistor 514 does not change due to the action of the correction current amplification circuit 57. As a result, the initial voltage of the output voltage of the digital-analog converter 50C at the time of changing the analog gain can be kept constant.

The correction current amplification circuit 57 has a configuration including a P-channel MOS transistor DP ₄₁ as an IV conversion circuit, a P-channel MOS transistor PT ₄₁ as a current source, and an output P-channel MOS transistor PT ₄₂ .

The P-channel MOS transistor DP ₄₁ is diode-connected and has the same function as the P-channel MOS transistor DP _{21 of} the analog gain adjusting section 52. The P-channel MOS transistor PT ₄₁ has the same function as the P-channel MOS transistor PT ₁₁ as the current source of the basic current source cells 511 ₁ to 511 _n of the analog signal output section 51. Further, the P-channel MOS transistor PT ₄₂ has the same function as the P-channel MOS transistor PT ₁₂ or PT _{13 which} is a differential transistor of the basic current source cells 511 ₁ to 511 _n of the analog signal output section 51.

In the correction current amplifier circuit 57, the number of parallel P-channel MOS transistors PT ₄₁ and PT ₄₂ is set in the same manner as the number n of the basic current source cells 511 ₁ to 511 _n of the analog signal output section 51.

The P-channel MOS transistor DP ₄₁ has a drain and a gate connected to the signal line L ₅ , and a source connected to the power supply line L ₁ of the power supply voltage V _DD . A bias voltage V _bisa2 is applied to the gate of the P-channel MOS transistor DP ₄₁ through the signal line L ₅ .

The sources of the n P-channel MOS transistors PT ₄₁ are connected to the power supply line L ₁ of the power supply voltage V _DD , and the drains are connected to the sources of the P-channel MOS transistors PT ₄₁ . The bias voltage V _bisa2 is also applied to the gates of the n P-channel MOS transistors PT ₄₁ , similarly to the P-channel MOS transistor DP ₄₁ .

The gates of the n P-channel MOS transistors PT ₄₂ are held at the ground potential and held in the ON state. The drains of the n P-channel MOS transistors PT ₄₂ are connected to the signal line S ₂ for supplying the correction current I _corct to the output node ND ₅₁ of the analog signal output section 51. In other words, the signal line S ₂ of the correction current I _corct is wired between the drains of the n P-channel MOS transistors PT ₄₂ and the output node ND ₅₁ of the analog signal output section 51.

In the correction current amplifier circuit 57, a current mirror circuit is formed by the diode-connected P channel MOS transistor DP ₄₁ and n P channel MOS transistors PT ₄₁ . The correction current amplification circuit 57 includes a P-channel MOS transistor DP ₂₁ of the analog gain adjustment section 52 and a P-channel MOS transistor PT ₁₁ as a current source of the basic current source cells 511 ₁ to 511 _n of the analog signal output section 51. Current amplification is performed at the same ratio as the current mirror ratio of the formed current mirror circuit.

According to the digital-analog converter 50C according to the second embodiment described above, the correction current amplifier circuit 57 can keep the initial voltage of the output voltage of the digital-analog converter 50C constant when the analog gain is changed. Further, compared to the first embodiment, it is not necessary to manually adjust the offset current value, so that the usability for the user can be improved. Further, as compared with the first embodiment, since the non-selection side current I _{gain_minus} and the offset current do not overlap each other, the power consumption can be reduced and the layout area can be _saved .

<Modification>
Although the technology according to the present disclosure has been described above based on the preferred embodiment, the technology according to the present disclosure is not limited to the embodiment. The configurations and structures of the digital-analog conversion device and the imaging device described in the above embodiments are examples, and can be changed as appropriate.

<Application example>
The imaging device of the present disclosure described above can be used in various devices that sense light such as visible light, infrared light, ultraviolet light, and X-rays, as illustrated in FIG. 13, for example. Specific examples of various devices are listed below.

-A device that captures images used for viewing, such as a digital camera or a portable device with a camera function-For driving in front of a vehicle, for safe driving such as automatic stop, and recognition of the driver's condition Devices used for traffic such as in-vehicle sensors that take images of the rear, surroundings, and inside the vehicle, surveillance cameras that monitor running vehicles and roads, ranging sensors that measure distances between vehicles, etc. Devices used for home appliances such as TVs, refrigerators, and air conditioners in order to take images and operate the devices according to the gestures ・Endoscopes, devices that take blood vessels by receiving infrared light, etc. Used for medical care and healthcare ・Security devices such as security surveillance cameras and person authentication cameras ・Skin measuring devices for skin and scalp A device used for beauty, such as a microscope, a device used for sports, such as an action camera or wearable camera for sports purposes, a camera used for monitoring the condition of fields or crops, Equipment used for agriculture

<Application example of technology according to the present disclosure>
The technology according to the present disclosure can be applied to various products. A more specific application example will be described below.

[Electronic device of the present disclosure]
Here, a case where the invention is applied to an image pickup system such as a digital still camera or a video camera, a mobile terminal device having an image pickup function such as a mobile phone, or an electronic device such as a copying machine using an image pickup device as an image reading unit will be described.

(Imaging system)
FIG. 14 is a block diagram illustrating a configuration example of an imaging system which is an example of the electronic device of the present disclosure. As shown in FIG. 14, an imaging system 100 according to this example includes an imaging optical system 101 including a lens group, an imaging unit 102, a DSP (Digital Signal Processor) circuit 103, a frame memory 104, a display device 105, and a recording device 106. An operation system 107, a power supply system 108, and the like. The DSP circuit 103, the frame memory 104, the display device 105, the recording device 106, the operation system 107, and the power supply system 108 are connected to each other via a bus line 109.

The imaging optical system 101 captures incident light (image light) from a subject and forms an image on the imaging surface of the imaging unit 102. The imaging unit 102 converts the light amount of the incident light imaged on the imaging surface by the optical system 101 into an electric signal for each pixel and outputs the electric signal as a pixel signal. The DSP circuit 103 performs general camera signal processing, such as white balance processing, demosaic processing, and gamma correction processing.

The frame memory 104 is used to appropriately store data in the process of signal processing in the DSP circuit 103. The display device 105 includes a panel-type display device such as a liquid crystal display device and an organic EL (electroluminescence) display device, and displays a moving image or a still image captured by the image capturing unit 102. The recording device 106 records the moving image or the still image captured by the image capturing unit 102 in a recording medium such as a portable semiconductor memory, an optical disc, or an HDD (Hard Disk Drive).

The operation system 107 issues operation commands for various functions of the imaging apparatus 100 under the operation of the user. The power supply system 108 appropriately supplies various power supplies serving as operating power supplies of the DSP circuit 103, the frame memory 104, the display device 105, the recording device 106, and the operation system 107 to these supply targets.

In the imaging system 100 having the above configuration, an imaging device (an imaging device of the present disclosure) equipped with a digital-analog conversion device to which the technology according to the present disclosure is applied can be used as the imaging unit 102. According to the digital-analog conversion device to which the technology of the present disclosure is applied, the initial voltage of the output voltage of the digital-analog conversion device when the analog gain is changed can be kept constant, so that a high-quality captured image is obtained. be able to.

[Application example to mobile]
The technology according to the present disclosure can be applied to various products. For example, the technology according to the present disclosure can be applied to any type of movement of an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility, an airplane, a drone, a ship, a robot, a construction machine, an agricultural machine (tractor), and the like. It may be realized as an image sensor mounted on the body.

FIG. 15 is a block diagram showing a schematic configuration example of a vehicle control system 7000 that is an example of a mobile body control system to which the technology according to the present disclosure can be applied. The vehicle control system 7000 includes a plurality of electronic control units connected via a communication network 7010. In the example shown in FIG. 15, the vehicle control system 7000 includes a drive system control unit 7100, a body system control unit 7200, a battery control unit 7300, a vehicle exterior information detection unit 7400, a vehicle interior information detection unit 7500, and an integrated control unit 7600. .. The communication network 7010 connecting these plural control units complies with any standard such as CAN (Controller Area Network), LIN (Local Interconnect Network), LAN (Local Area Network) or FlexRay (registered trademark). It may be an in-vehicle communication network.

Each control unit includes a microcomputer that performs arithmetic processing according to various programs, a storage unit that stores a program executed by the microcomputer or parameters used in various arithmetic operations, and a drive circuit that drives various controlled devices. Equipped with. Each control unit is equipped with a network I/F for communicating with other control units via the communication network 7010, and also by wire communication or wireless communication with devices or sensors inside or outside the vehicle. A communication I/F for performing communication is provided. In FIG. 15, as the functional configuration of the integrated control unit 7600, a microcomputer 7610, a general-purpose communication I/F 7620, a dedicated communication I/F 7630, a positioning unit 7640, a beacon receiving unit 7650, an in-vehicle device I/F 7660, an audio image output unit 7670, An in-vehicle network I/F 7680 and a storage unit 7690 are illustrated. Similarly, the other control units also include a microcomputer, a communication I/F, a storage unit, and the like.

The drive system control unit 7100 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 7100 includes a drive force generation device for generating a drive force of a vehicle such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to wheels, and a steering angle of the vehicle. It functions as a steering mechanism for adjusting and a control device such as a braking device for generating a braking force of the vehicle. The drive system control unit 7100 may have a function as a control device such as ABS (Antilock Brake System) or ESC (Electronic Stability Control).

A vehicle state detection unit 7110 is connected to the drive system control unit 7100. The vehicle state detection unit 7110 includes, for example, a gyro sensor that detects the angular velocity of the shaft rotational movement of the vehicle body, an acceleration sensor that detects the acceleration of the vehicle, an accelerator pedal operation amount, a brake pedal operation amount, or a steering wheel steering operation. At least one of sensors for detecting an angle, an engine speed, a wheel rotation speed, and the like is included. The drive system control unit 7100 performs arithmetic processing using the signal input from the vehicle state detection unit 7110 to control the internal combustion engine, drive motor, electric power steering device, brake device, or the like.

The body system control unit 7200 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 7200 functions as a keyless entry system, a smart key system, a power window device, or a control device for various lamps such as a head lamp, a back lamp, a brake lamp, a winker, or a fog lamp. In this case, the body system control unit 7200 may receive radio waves or signals of various switches transmitted from a portable device that substitutes for a key. The body system control unit 7200 receives the input of these radio waves or signals and controls the vehicle door lock device, the power window device, the lamp, and the like.

The battery control unit 7300 controls the secondary battery 7310 that is the power supply source of the drive motor according to various programs. For example, to the battery control unit 7300, information such as the battery temperature, the battery output voltage, or the remaining capacity of the battery is input from the battery device including the secondary battery 7310. The battery control unit 7300 performs arithmetic processing using these signals to control the temperature adjustment of the secondary battery 7310 or the cooling device provided in the battery device.

The exterior information detection unit 7400 detects information outside the vehicle equipped with the vehicle control system 7000. For example, at least one of the image capturing unit 7410 and the vehicle exterior information detection unit 7420 is connected to the vehicle exterior information detection unit 7400. The imaging unit 7410 includes at least one of a ToF (Time Of Flight) camera, a stereo camera, a monocular camera, an infrared camera, and other cameras. The outside-vehicle information detection unit 7420 detects, for example, an environment sensor for detecting current weather or weather, or another vehicle around the vehicle equipped with the vehicle control system 7000, an obstacle, a pedestrian, or the like. At least one of the ambient information detection sensors of.

The environmental sensor may be, for example, at least one of a raindrop sensor that detects rainy weather, a fog sensor that detects fog, a sunshine sensor that detects the degree of sunshine, and a snow sensor that detects snowfall. The ambient information detection sensor may be at least one of an ultrasonic sensor, a radar device, and a LIDAR (Light Detection and Ranging, Laser Imaging Detection and Ranging) device. The imaging unit 7410 and the vehicle exterior information detection unit 7420 may be provided as independent sensors or devices, or may be provided as a device in which a plurality of sensors or devices are integrated.

Here, FIG. 16 shows an example of installation positions of the imaging unit 7410 and the vehicle exterior information detection unit 7420. The

imaging units

7910, 7912, 7914, 7916, 7918 are provided at at least one of the front nose of the vehicle 7900, the side mirrors, the rear bumper, the back door, and the upper part of the windshield inside the vehicle. The image capturing unit 7910 provided on the front nose and the image capturing unit 7918 provided on the upper part of the windshield in the vehicle interior mainly acquire an image in front of the vehicle 7900. The

imaging units

7912 and 7914 provided in the side mirrors mainly acquire images of the side of the vehicle 7900. The imaging unit 7916 provided on the rear bumper or the back door mainly acquires an image of the rear of the vehicle 7900. The imaging unit 7918 provided on the upper part of the windshield in the vehicle interior is mainly used for detecting a preceding vehicle, a pedestrian, an obstacle, a traffic signal, a traffic sign, a lane, or the like.

Note that FIG. 16 shows an example of the shooting ranges of the respective

image pickup units

7910, 7912, 7914, 7916. The imaging range a indicates the imaging range of the imaging unit 7910 provided on the front nose, the imaging ranges b and c indicate the imaging ranges of the

imaging units

7912 and 7914 provided on the side mirrors, and the imaging range d is The imaging range of the imaging part 7916 provided in the rear bumper or the back door is shown. For example, by overlaying the image data captured by the

image capturing units

7910, 7912, 7914, and 7916, a bird's-eye view image of the vehicle 7900 viewed from above can be obtained.

The vehicle exterior

information detection units

7920, 7922, 7924, 7926, 7928, 7930 provided on the front, rear, sides, corners of the vehicle 7900 and on the windshield inside the vehicle may be ultrasonic sensors or radar devices, for example. The vehicle exterior

information detection units

7920, 7926, 7930 provided on the front nose, rear bumper, back door, and upper windshield of the vehicle 7900 may be LIDAR devices, for example. These vehicle exterior information detection units 7920 to 7930 are mainly used to detect a preceding vehicle, a pedestrian, an obstacle, or the like.

Return to FIG. 15 and continue the explanation. The vehicle exterior information detection unit 7400 causes the image capturing unit 7410 to capture an image of the vehicle exterior and receives the captured image data. In addition, the vehicle exterior information detection unit 7400 receives detection information from the vehicle exterior information detection unit 7420 connected thereto. When the vehicle exterior information detection unit 7420 is an ultrasonic sensor, a radar device, or a LIDAR device, the vehicle exterior information detection unit 7400 transmits ultrasonic waves, electromagnetic waves, or the like, and receives information on the received reflected waves. The vehicle exterior information detection unit 7400 may perform an object detection process or a distance detection process such as a person, a car, an obstacle, a sign, or characters on the road surface based on the received information. The vehicle exterior information detection unit 7400 may perform environment recognition processing for recognizing rainfall, fog, road surface conditions, or the like based on the received information. The vehicle exterior information detection unit 7400 may calculate the distance to an object outside the vehicle based on the received information.

The vehicle exterior information detection unit 7400 may also perform image recognition processing or distance detection processing for recognizing a person, a car, an obstacle, a sign, characters on the road surface, or the like based on the received image data. The vehicle exterior information detection unit 7400 performs processing such as distortion correction or position adjustment on the received image data, combines the image data captured by different image capturing units 7410, and generates an overhead image or a panoramic image. Good. The vehicle exterior information detection unit 7400 may perform viewpoint conversion processing using image data captured by different image capturing units 7410.

The in-vehicle information detection unit 7500 detects in-vehicle information. The in-vehicle information detection unit 7500 is connected with, for example, a driver state detection unit 7510 that detects the state of the driver. The driver state detecting unit 7510 may include a camera for capturing an image of the driver, a biometric sensor for detecting biometric information of the driver, a microphone for collecting voice in the vehicle interior, or the like. The biometric sensor is provided on, for example, a seat surface or a steering wheel, and detects biometric information of an occupant sitting on a seat or a driver who holds the steering wheel. The in-vehicle information detection unit 7500 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 7510, or determine whether the driver is asleep. You may. The in-vehicle information detection unit 7500 may perform processing such as noise canceling processing on the collected audio signal.

The integrated control unit 7600 controls overall operations in the vehicle control system 7000 according to various programs. An input unit 7800 is connected to the integrated control unit 7600. The input unit 7800 is realized by a device that can be input and operated by a passenger, such as a touch panel, a button, a microphone, a switch or a lever. Data obtained by voice recognition of voice input by a microphone may be input to the integrated control unit 7600. The input unit 7800 may be, for example, a remote control device that uses infrared rays or other radio waves, or may be an external connection device such as a mobile phone or a PDA (Personal Digital Assistant) that supports the operation of the vehicle control system 7000. May be. The input unit 7800 may be, for example, a camera, in which case the passenger can input information by gesture. Alternatively, data obtained by detecting the movement of the wearable device worn by the passenger may be input. Furthermore, the input unit 7800 may include, for example, an input control circuit that generates an input signal based on information input by a passenger or the like using the input unit 7800 and outputs the input signal to the integrated control unit 7600. A passenger or the like operates the input unit 7800 to input various data or instruct a processing operation to the vehicle control system 7000.

The storage unit 7690 may include a ROM (Read Only Memory) that stores various programs executed by the microcomputer, and a RAM (Random Access Memory) that stores various parameters, calculation results, sensor values, and the like. The storage unit 7690 may be realized by a magnetic storage device such as an HDD (Hard Disc Drive), a semiconductor storage device, an optical storage device, a magneto-optical storage device, or the like.

The general-purpose communication I/F 7620 is a general-purpose communication I/F that mediates communication with various devices existing in the external environment 7750. The general-purpose communication I/F 7620 is a cellular communication protocol such as GSM (registered trademark) (Global System of Mobile communications), WiMAX, LTE (Long Term Evolution) or LTE-A (LTE-Advanced), or a wireless LAN (Wi-Fi). (Also referred to as a registered trademark), Bluetooth (registered trademark), and other wireless communication protocols may be implemented. The general-purpose communication I/F 7620 is connected to a device (for example, an application server or a control server) existing on an external network (for example, the Internet, a cloud network or a network unique to a business operator) via a base station or an access point, for example. You may. In addition, the general-purpose communication I/F 7620 uses, for example, P2P (Peer To Peer) technology, and is a terminal existing in the vicinity of the vehicle (for example, a driver, a pedestrian or a shop terminal, or an MTC (Machine Type Communication) terminal). May be connected with.

The dedicated communication I/F 7630 is a communication I/F that supports a communication protocol formulated for use in a vehicle. The dedicated communication I/F 7630 uses a standard protocol such as WAVE (Wireless Access in Vehicle Environment), DSRC (Dedicated Short Range Communications), or a cellular communication protocol, which is a combination of a lower layer IEEE 802.11p and an upper layer IEEE 1609, for example. May be implemented. The dedicated communication I/F 7630 is typically a vehicle-to-vehicle communication, a vehicle-to-infrastructure communication, a vehicle-to-home communication, and a vehicle-to-pedestrian communication. ) Perform V2X communications, a concept that includes one or more of the communications.

The positioning unit 7640 receives, for example, a GNSS signal from a GNSS (Global Navigation Satellite System) satellite (for example, a GPS signal from a GPS (Global Positioning System) satellite) to perform positioning, and the latitude, longitude, and altitude of the vehicle. Generate position information including. The positioning unit 7640 may specify the current position by exchanging a signal with the wireless access point, or may acquire the position information from a terminal having a positioning function, such as a mobile phone, PHS, or smartphone.

The beacon receiving unit 7650 receives, for example, a radio wave or an electromagnetic wave transmitted from a wireless station or the like installed on the road, and acquires information such as the current position, traffic jam, traffic closure, or required time. The function of the beacon receiving unit 7650 may be included in the dedicated communication I/F 7630 described above.

The in-vehicle device I/F 7660 is a communication interface that mediates a connection between the microcomputer 7610 and various in-vehicle devices 7760 existing in the vehicle. The in-vehicle device I/F 7660 may establish a wireless connection using a wireless communication protocol such as wireless LAN, Bluetooth (registered trademark), NFC (Near Field Communication) or WUSB (Wireless USB). Further, the in-vehicle device I/F 7660 is connected to a USB (Universal Serial Bus), HDMI (registered trademark) (High-Definition Multimedia Interface), or MHL (Mobile) via a connection terminal (and a cable if necessary) not shown. Wired connection such as High-definition Link) may be established. The in-vehicle device 7760 may include, for example, at least one of a mobile device or a wearable device that the passenger has, or an information device that is carried in or attached to the vehicle. The in-vehicle device 7760 may include a navigation device that searches for a route to an arbitrary destination. The in-vehicle device I/F 7660 exchanges control signals or data signals with these in-vehicle devices 7760.

The in-vehicle network I/F 7680 is an interface that mediates communication between the microcomputer 7610 and the communication network 7010. The in-vehicle network I/F 7680 transmits and receives signals and the like according to a predetermined protocol supported by the communication network 7010.

The microcomputer 7610 of the integrated control unit 7600 passes through at least one of the general-purpose communication I/F 7620, the dedicated communication I/F 7630, the positioning unit 7640, the beacon receiving unit 7650, the in-vehicle device I/F 7660, and the in-vehicle network I/F 7680. The vehicle control system 7000 is controlled according to various programs based on the information acquired by the above. For example, the microcomputer 7610 calculates a control target value of the driving force generation device, the steering mechanism or the braking device based on the acquired information on the inside and outside of the vehicle, and outputs a control command to the drive system control unit 7100. Good. For example, the microcomputer 7610 realizes the functions of ADAS (Advanced Driver Assistance System) including collision avoidance or impact mitigation of a vehicle, follow-up traveling based on an inter-vehicle distance, vehicle speed maintenance traveling, vehicle collision warning, vehicle lane departure warning, etc. You may perform the coordinated control aiming at. In addition, the microcomputer 7610 controls the driving force generation device, the steering mechanism, the braking device, and the like based on the acquired information about the surroundings of the vehicle, so that the microcomputer 7610 automatically travels independently of the driver's operation. You may perform cooperative control for the purpose of driving etc.

Information acquired by the microcomputer 7610 via at least one of a general-purpose communication I/F 7620, a dedicated communication I/F 7630, a positioning unit 7640, a beacon receiving unit 7650, an in-vehicle device I/F 7660, and an in-vehicle network I/F 7680. Based on the above, three-dimensional distance information between the vehicle and surrounding objects such as structures and people may be generated, and local map information including peripheral information of the current position of the vehicle may be created. In addition, the microcomputer 7610 may generate a warning signal by predicting a danger such as a vehicle collision, a pedestrian or the like approaching a road or a closed road, based on the acquired information. The warning signal may be, for example, a signal for generating a warning sound or lighting a warning lamp.

The voice image output unit 7670 transmits an output signal of at least one of a voice and an image to an output device capable of visually or audibly notifying information to a passenger of the vehicle or the outside of the vehicle. In the example of FIG. 15, an audio speaker 7710, a display unit 7720, and an instrument panel 7730 are illustrated as output devices. The display unit 7720 may include at least one of an onboard display and a head-up display, for example. The display unit 7720 may have an AR (Augmented Reality) display function. The output device may be a device other than these devices, such as headphones, a wearable device such as a glasses-type display worn by a passenger, a projector, or a lamp. When the output device is a display device, the display device displays results obtained by various processes performed by the microcomputer 7610 or information received from another control unit in various formats such as text, images, tables, and graphs. Display it visually. When the output device is an audio output device, the audio output device converts an audio signal composed of reproduced audio data, acoustic data, or the like into an analog signal and outputs it audibly.

Note that in the example shown in FIG. 15, at least two control units connected via the communication network 7010 may be integrated as one control unit. Alternatively, each control unit may be composed of a plurality of control units. Further, the vehicle control system 7000 may include another control unit not shown. Further, in the above description, some or all of the functions of one of the control units may be given to another control unit. That is, if the information is transmitted and received via the communication network 7010, the predetermined arithmetic processing may be performed by any of the control units. Similarly, a sensor or device connected to one of the control units may be connected to another control unit, and a plurality of control units may send and receive detection information to and from each other via the communication network 7010. ..

Above, an example of the vehicle control system to which the technology according to the present disclosure can be applied has been described. The technology according to the present disclosure can be applied to, for example, the

imaging units

7910, 7912, 7914, 7916, 7918 and the vehicle exterior

information detection units

7920, 7922, 7924, 7926, 7928, 7930 among the configurations described above. Then, by using the image pickup device equipped with the digital-analog converter to which the technology according to the present disclosure is applied as the image pickup unit or the vehicle exterior information detection unit, for example, a high-quality picked-up image is acquired as the information of the image pickup target. A possible vehicle control system can be constructed.

<Structure that the present disclosure can take>
Note that the present disclosure may also have the following configurations.

<<A. Digital-analog converter>>
[A-1] An analog signal output section that outputs an analog signal according to the value of the digital input signal,
An analog gain adjusting section for adjusting the gain of the analog signal, and
An initial potential control unit that is connected to the output node of the analog signal output unit and controls the initial potential of the analog signal is provided.
The initial potential control unit controls the initial potential of the analog signal to a constant potential regardless of the gain adjusted by the analog gain adjustment unit,
Digital-analog converter.
[A-2] The analog signal output section receives the gain control signal for adjusting the analog gain, generates an output current according to the value of the digital input signal, and performs current-voltage conversion on the generated output current. Output voltage signal as analog signal,
The digital-analog converter according to the above [A-1].
[A-3] The analog gain adjusting section generates a gain current and a non-selection side current according to the value of the digital gain control signal, and outputs a voltage signal obtained by current-voltage converting the gain current to the analog signal output section. Supply as,
The digital-analog converter according to the above [A-2].
[A-4] The initial potential control unit has a plurality of current sources, and supplies a current from the current source corresponding to the offset setting value based on the setting of the analog gain to the output node of the analog signal output unit, Control the initial potential of the analog signal to a constant potential,
The digital-analog converter according to the above [A-3].
[A-5] The initial potential control unit controls the initial potential of the analog signal to a constant potential by supplying a correction current based on the non-selected side current to the output node of the analog signal output unit.
The digital-analog converter according to the above [A-3].

<<B. Imaging device ≫
[B-1] A pixel array section having a pixel circuit including a photoelectric conversion element,
An analog-to-digital converter having a plurality of analog-to-digital converters for converting an analog pixel signal output from each pixel circuit of the pixel array section into a digital signal, and
A reference signal generation unit that generates a ramp wave reference signal and supplies the reference signal to the analog-digital conversion unit;
The reference signal generation unit includes a digital-analog conversion device,
The digital-analog converter is
An analog signal output section that outputs an analog signal according to the value of the digital input signal,
An analog gain adjusting section for adjusting the gain of the analog signal, and
An initial potential control unit that is connected to the output node of the analog signal output unit and controls the initial potential of the analog signal is provided.
The initial potential control unit controls the initial potential of the analog signal to a constant potential regardless of the gain adjusted by the analog gain adjustment unit,
Imaging device.
[B-2] The analog signal output unit receives the gain control signal for adjusting the analog gain, generates an output current according to the value of the digital input signal, and performs current-voltage conversion on the generated output current. Output voltage signal as analog signal,
The imaging device according to the above [B-1].
[B-3] The analog gain adjusting section generates a gain current and a non-selection side current according to the value of the digital gain control signal, and a voltage signal obtained by current-voltage converting the gain current is sent to the analog signal output section. Supply as,
The imaging device according to the above [B-2].
[B-4] The initial potential control unit has a plurality of current sources and supplies a current to the output node of the analog signal output unit from the current source corresponding to the offset setting value based on the setting of the analog gain, Control the initial potential of the analog signal to a constant potential,
The imaging device according to the above [B-3].
[B-5] The initial potential control unit controls the initial potential of the analog signal to a constant potential by supplying a correction current based on the non-selected side current to the output node of the analog signal output unit.
The imaging device according to the above [B-3].
[B-6] The analog-digital converter has a comparator that has two inputs, the analog pixel signal output from the pixel circuit and the reference signal of the ramp wave supplied from the reference signal generation unit,
The comparator is initialized only on the input side of the analog pixel signal,
The imaging device according to any one of [B-1] to [B-5].
[B-7] An analog-digital converter is provided corresponding to each pixel circuit of the pixel array section,
The imaging device according to the above [B-6].
[B-8] A first semiconductor chip in which each pixel circuit of the pixel array section is formed, and a second semiconductor chip in which an analog-digital converter is formed corresponding to each pixel circuit of the pixel array section A stacked semiconductor chip structure in which at least two semiconductor chips are stacked,
The imaging device according to the above [B-7].

<<C. Electronic equipment ≫
[C-1] A pixel array section having a pixel circuit including a photoelectric conversion element,
An analog-to-digital converter having a plurality of analog-to-digital converters for converting an analog pixel signal output from each pixel circuit of the pixel array section into a digital signal, and
A reference signal generation unit that generates a ramp wave reference signal and supplies the reference signal to the analog-digital conversion unit;
The reference signal generation unit includes a digital-analog conversion device,
The digital-analog converter is
An analog signal output section that outputs an analog signal according to the value of the digital input signal,
An analog gain adjusting section for adjusting the gain of the analog signal, and
An initial potential control unit that is connected to the output node of the analog signal output unit and controls the initial potential of the analog signal is provided.
The initial potential control unit controls the initial potential of the analog signal to a constant potential regardless of the gain adjusted by the analog gain adjustment unit,
An electronic device having an imaging device.
[C-2] The analog signal output unit receives the gain control signal for adjusting the analog gain, generates an output current according to the value of the digital input signal, and performs current-voltage conversion on the generated output current. Output voltage signal as analog signal,
The electronic device according to the above [C-1].
[C-3] The analog gain adjustment unit generates a gain current and a non-selected side current according to the value of the digital gain control signal, and a voltage signal obtained by current-voltage converting the gain current is sent to the analog signal output unit. Supply as,
The electronic device according to the above [C-2].
[C-4] The initial potential control unit has a plurality of current sources, and supplies a current from the current source corresponding to the offset setting value based on the setting of the analog gain to the output node of the analog signal output unit, Control the initial potential of the analog signal to a constant potential,
The electronic device according to the above [C-3].
[C-5] The initial potential control unit controls the initial potential of the analog signal to a constant potential by supplying a correction current based on the non-selected side current to the output node of the analog signal output unit.
The electronic device according to the above [C-3].
[C-6] The analog-digital converter has a comparator that has two inputs, the analog pixel signal output from the pixel circuit and the ramp wave reference signal supplied from the reference signal generation unit,
The comparator is initialized only on the input side of the analog pixel signal,
The electronic device according to any one of [C-1] to [C-5].
[C-7] An analog-digital converter is provided corresponding to each pixel circuit of the pixel array section,
The electronic device according to [C-6].
[C-8] A first semiconductor chip in which each pixel circuit of the pixel array section is formed, and a second semiconductor chip in which an analog-digital converter is formed corresponding to each pixel circuit of the pixel array section A stacked semiconductor chip structure in which at least two semiconductor chips are stacked,
The electronic device according to [C-7].

DESCRIPTION OF SYMBOLS 1... CMOS image sensor, 2... Pixel, 11... Pixel array part, 12... Row selection part, 13... Constant current source part, 14... Analog-digital conversion part, 15 Reference signal generation unit, 16 Horizontal transfer scanning unit, 17 Signal processing unit, 18 Timing controller, 19 Horizontal transfer line, 21 Photo diode (light receiving unit) ), 22... Transfer transistor, 23... Reset transistor, 24... Amplification transistor, 25... Selection transistor, 31 (31 ₁ to 31 _m )... Pixel control line, 32 (32 ₁ to 32 _n )... Vertical signal line, 41... Semiconductor chip, 42... First semiconductor chip, 43... Second semiconductor chip, 50A... Digital-analog converter according to conventional example, 50B ... Digital-analog converter according to the first embodiment, 50C ... Digital-analog converter according to the second embodiment, 51... Analog signal output section, 52... Analog gain adjusting section, 53... -Counter decoder, 54... Gain decoder, 55... Offset current source circuit, 56... Manual offset decoder, 57... Correction current amplification circuit, 140... Single slope type analog-digital converter , 141... Comparator, 142... Counter circuit, 143... Latch circuit

Claims

An analog signal output section that outputs an analog signal according to the value of the digital input signal,
An analog gain adjusting section for adjusting the gain of the analog signal, and
An initial potential control unit that is connected to the output node of the analog signal output unit and controls the initial potential of the analog signal is provided.
The initial potential control unit controls the initial potential of the analog signal to a constant potential regardless of the gain adjusted by the analog gain adjustment unit,
Digital-analog converter.
The analog signal output section receives the gain control signal for adjusting the analog gain, generates an output current according to the value of the digital input signal, and converts the generated output current into a voltage signal which is an analog signal. Output as
The digital-analog conversion device according to claim 1.
The analog gain adjustment unit generates a gain current and a non-selected side current according to the value of the digital gain control signal, and supplies a voltage signal obtained by current-voltage converting the gain current to the analog signal output unit as a gain control signal.
The digital-analog conversion device according to claim 2.
The initial potential control unit has a plurality of current sources, and supplies a current to the output node of the analog signal output unit from the current source corresponding to the offset setting value based on the setting of the analog gain, so that the initial potential of the analog signal is To a constant potential,
The digital-analog conversion device according to claim 3.
The initial potential control unit controls the initial potential of the analog signal to a constant potential by supplying a correction current based on the non-selected side current to the output node of the analog signal output unit.
The digital-analog conversion device according to claim 3.
A pixel array section having a pixel circuit including a photoelectric conversion element,
An analog-to-digital converter having a plurality of analog-to-digital converters for converting an analog pixel signal output from each pixel circuit of the pixel array section into a digital signal, and
A reference signal generation unit that generates a ramp wave reference signal and supplies the reference signal to the analog-digital conversion unit;
The reference signal generation unit includes a digital-analog conversion device,
The digital-analog converter is
An analog signal output section that outputs an analog signal according to the value of the digital input signal,
An analog gain adjusting section for adjusting the gain of the analog signal, and
An initial potential control unit that is connected to the output node of the analog signal output unit and controls the initial potential of the analog signal is provided.
The initial potential control unit controls the initial potential of the analog signal to a constant potential regardless of the gain adjusted by the analog gain adjustment unit,
Imaging device.
The analog signal output section receives the gain control signal for adjusting the analog gain, generates an output current according to the value of the digital input signal, and converts the generated output current into a voltage signal which is an analog signal. Output as
The imaging device according to claim 6.
The analog gain adjustment unit generates a gain current and a non-selected side current according to the value of the digital gain control signal, and supplies a voltage signal obtained by current-voltage converting the gain current to the analog signal output unit as a gain control signal.
The image pickup apparatus according to claim 7.
The initial potential control unit has a plurality of current sources, and supplies a current to the output node of the analog signal output unit from the current source corresponding to the offset setting value based on the setting of the analog gain, so that the initial potential of the analog signal is To a constant potential,
The image pickup apparatus according to claim 8.
The initial potential control unit controls the initial potential of the analog signal to a constant potential by supplying a correction current based on the non-selected side current to the output node of the analog signal output unit.
The image pickup apparatus according to claim 8.
The analog-digital converter has a comparator that has two inputs, the analog pixel signal output from the pixel circuit and the reference signal of the ramp wave supplied from the reference signal generation unit,
The comparator is initialized only on the input side of the analog pixel signal,
The imaging device according to claim 6.
The analog-digital converter is provided corresponding to each pixel circuit of the pixel array section,
The imaging device according to claim 11.
At least two semiconductor chips, a first semiconductor chip in which each pixel circuit of the pixel array section is formed and a second semiconductor chip in which an analog-digital converter is formed corresponding to each pixel circuit of the pixel array section Has a stacked semiconductor chip structure in which
The image pickup apparatus according to claim 12.
A pixel array section having a pixel circuit including a photoelectric conversion element,
An analog-to-digital converter having a plurality of analog-to-digital converters for converting an analog pixel signal output from each pixel circuit of the pixel array section into a digital signal, and
A reference signal generation unit that generates a ramp wave reference signal and supplies the reference signal to the analog-digital conversion unit;
The reference signal generation unit includes a digital-analog conversion device,
The digital-analog converter is
An analog signal output section that outputs an analog signal according to the value of the digital input signal,
An analog gain adjusting section for adjusting the gain of the analog signal, and
An initial potential control unit that is connected to the output node of the analog signal output unit and controls the initial potential of the analog signal is provided.
The initial potential control unit controls the initial potential of the analog signal to a constant potential regardless of the gain adjusted by the analog gain adjustment unit,
An electronic device having an imaging device.