JP2009303042A - Digital/analog conversion circuit, solid-state imaging apparatus, camera system and method for analog conversion of digital code - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To propose a D/A conversion technique which is effective for reducing noise in a lateral streak shape in an image, while avoiding increase in current consumption of a D/A converter. <P>SOLUTION: A digital/analog (D/A) conversion circuit includes a regulator which outputs a reference voltage from a driver; and an analog voltage output section, to which the reference voltage output from the regulator is supplied, for outputting an analog voltage corresponding to an input code. Then, control is performed for varying the size of the driver inside the regulator, according to the input code. Thus, a gate voltage of the driver is suppressed from being varied by re-regulation, or the like, and the transient response property required for the regulator can be reduced. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a digital / analog conversion circuit, a digital code analog conversion method, a solid-state imaging device including the digital-analog conversion circuit, and a camera system including the solid-state imaging device.

  A CMOS (Complementary Metal Oxide Semiconductor) type image sensor is known as a solid-state imaging device. Since a CMOS image sensor is manufactured based on a CMOS LSI manufacturing process, functions other than the image sensor can be easily incorporated in the same chip by using this process. Using this characteristic, an analog-digital converter (ADC) is provided for each column of pixels, and conversion processing from pixel values (analog voltage values) output by the pixels to digital data is performed in parallel in each column. Has been done. This method is called a column ADC method.

In the case of the column ADC system, details of the configuration for A / D (Analog / Digital) conversion of pixel values will be described in detail in an embodiment to be described later. That is, the counter is operated at a cycle of reading the pixel value of each pixel, and a slope waveform in which the voltage level changes in order corresponding to the code indicated by the count value of the counter is created. The creation of the slope waveform is a process of obtaining an analog voltage waveform corresponding to the code value, and corresponds to D / A (Digital / Analog) conversion. The created slope waveform repeats up and down levels in conjunction with the cycle of reading each pixel value.
The analog voltage slope waveform thus generated is supplied to one input terminal of the comparator. Further, the pixel value read at that time is supplied to the other input terminal of the comparator, the timing at which the slope waveform exceeds the pixel value is detected, and the count value at that timing is latched. The latched count value is output as digital data of the corresponding pixel.

  FIG. 11 shows an example of the slope waveform supplied to the comparator when such A / D conversion is performed. In this example, the slope waveform voltage Va is a waveform whose level decreases in order each time one A / D conversion is performed, and the level returns to the original each time the next A / D conversion is performed.

Such a solid-state imaging device that performs A / D conversion by the column ADC method is described in Patent Document 1, for example.
JP 2007-59991 A

By the way, in the case of the column ADC system, the output signals of the pixels arranged in the row direction are simultaneously subjected to A / D conversion processing by a plurality of A / D converters, and this is repeated in the column direction, thereby one frame worth. The pixel signals are all digitally converted. For this reason, pixels arranged in the horizontal direction are simultaneously subjected to A / D conversion processing, but pixels arranged vertically in the vertical direction have different timings for A / D conversion processing.
For this reason, if affected by noise during A / D conversion processing, the amount of noise affected by the upper and lower columns may be different. In such a case, horizontal streak noise is used as the digitally converted image. There was a problem that would occur.
In particular, when the reference voltage (DAC reference voltage) of the slope voltage described above is obtained by a series regulator or the like, the power supply noise is superimposed on the DAC reference due to insufficient power supply ripple resistance of the series regulator, and horizontal streak noise is generated. There was a thing.

  Here, for example, the slope voltage is a voltage difference generated between both ends of the resistor by digitally controlling a plurality of constant current sources so that the current value monotonously increases and decreases at a constant rate of change with time. Can be obtained from In addition, when adjusting the gain in A / D conversion, a mechanism is provided to uniformly increase or decrease the values of a plurality of constant current sources controlled at the time of slope voltage generation so that the slope of the slope voltage can be adjusted with high accuracy. A technique for changing is proposed in Japanese Patent Application Laid-Open No. H10-228707.

To improve the power supply ripple resistance of the series regulator, it is easy to connect a capacitor to the output terminal or insert a low-pass filter to the power supply terminal of the regulator itself. From the viewpoint of thermal noise suppression, it is desirable to reduce the bandwidth of the series regulator appropriately. However, when such a means is used, the transient response characteristic with respect to the load fluctuation of the regulator is remarkably impaired. If the transient response characteristics are impaired, there is a problem that the response speed of the regulator is not in time for sudden load fluctuations when gain adjustment occurs between the end of A / D conversion and the next AD conversion or between frames. It was.
For example, in the example of the slope voltage shown in FIG. 11, when the slope voltage Va changes from the lowest state to the highest state, distortion occurs due to insufficient transient response characteristics, such as the voltage Vb indicated by the broken line in FIG. It becomes a slope voltage. This distortion occurs because the load current suddenly decreases and the DAC reference rises above the target value.

  The series regulator inserts a voltage dividing resistor between the output terminal and the power supply terminal, compares the divided component of the output voltage and the reference voltage with an error amplifier, and reduces the error from the target voltage in the direction of the driver gate voltage. Is a negative feedback circuit configured to output a constant voltage. For this reason, it is basically impossible to avoid a delay in response to load fluctuations. Therefore, when applied to a DAC reference of an image sensor, it is necessary to adopt a configuration in which the response delay is suppressed to such an extent that it does not cause an operation problem, and at the same time, a load fluctuation hardly occurs.

For example, in the D / A converter, the current value that flows through the fixed resistor is changed according to the output value of the slope voltage, but in order to suppress the load fluctuation applied to the DAC reference, the reactive current is passed through the path that does not pass through the fixed resistor. In some cases, the load current does not fluctuate as the slope voltage rises or falls.
Similarly, if the reactive current is kept flowing so that the total constant current does not change during gain adjustment, the load will be constant throughout the entire operation, and there will be no problem even if the transient response characteristics of the regulator are lowered. .
However, this increases current consumption and degrades the performance of the entire system.

  The present invention has been made in view of these points, and an object of the present invention is to propose a technique effective for reducing horizontal streak noise in an image while avoiding an increase in current consumption of a D / A converter.

  The present invention includes a regulator that outputs a reference voltage from a driver, and an analog voltage output unit that is supplied with the reference voltage output from the regulator and outputs an analog voltage corresponding to the input code. Then, control is performed to vary the size of the driver in the regulator according to the input code.

  According to the present invention, by changing the size of the driver in the regulator according to the input code, it is possible to suppress the change in the gate voltage of the driver due to readjustment, etc., and to reduce the transient response characteristic required for the regulator. Is possible. By improving the power supply ripple resistance of the regulator in this way, distortion of the slope voltage due to the influence of noise can be eliminated, and digital conversion of the pixel signal using the slope voltage waveform can be performed accurately. As a result, it is possible to prevent horizontal streak noise from occurring in the digitally converted pixel data.

According to the present invention, the relationship between the current supplied by the regulator driver and the load can be kept constant, and the gate voltage of the driver need not be controlled at high speed. As a result, the speed required for the error amplifier of the regulator is reduced. Inserting a low-pass filter into the power supply terminal of the regulator or connecting a large capacitor to the output stage improves noise suppression and ripple removal capability. Can be easily performed.
Further, by using the circuit configuration of the present invention, it is not necessary to flow the reactive current that has been flown in order to suppress the load fluctuation in the past, which greatly contributes to power saving of the entire system.

Examples of embodiments of the present invention will be described below with reference to FIGS. This embodiment will be described in the following order.
1. First embodiment [basic configuration example: FIGS. 1 to 6]
2. 2. Second Embodiment [Configuration Example with Gain DAC in addition to Basic Configuration Example and Linking Gain Control Driver and Regulator Driver: FIGS. 7 and 8]
3. Third Embodiment [Example in which a gain DAC is provided using a basic configuration, and a gain control driver and a regulator driver are linked to each other: FIGS. 9 and 10]
In the following description, digital / analog conversion may be abbreviated as DAC and analog / digital conversion may be abbreviated as ADC.

1. Example of First Embodiment [Configuration of Digital / Analog Conversion Circuit]
FIG. 1 is a configuration example of a digital / analog conversion circuit of the example of the present embodiment.
The digital / analog conversion circuit of the present embodiment includes a DAC reference regulator 100. The DAC reference regulator 100 generates a digital / analog conversion reference voltage (DAC reference voltage). The DAC reference regulator 100 is a negative feedback circuit configured to output a constant voltage, and includes a driver 105 configured by a P-channel field effect transistor for obtaining a DAC reference voltage. The driver 105 of this example is configured to be variable in size in a plurality of stages. As a configuration for changing the driver size, for example, a plurality of field effect transistors are connected in parallel, and the size is changed by selecting a transistor to be operated. A specific configuration example for changing the size will be described later.

The driver 105 of this P-channel type field effect transistor has a source connected to a terminal from which the power supply voltage Vdd can be obtained, and a drain connected to the DAC output terminal 111 via a resistor 112.
The gate of the driver 105 is controlled by the output of the error amplifier 102. The error amplifier 102 compares the output voltage of the regulator 100 divided by the resistor 112 with the reference voltage from the voltage source 101, detects an error from the target voltage, and detects the error from the driver 105. Supply to the gate. One end of the variable resistor 103 and the capacitor 104 is connected to a connection point between the driver 105 and the resistor 112, and the other end of the variable resistor 103 and the capacitor 104 is grounded. Then, the voltage signal divided by the variable resistor 103 is input to the error amplifier 102. With this configuration, the error amplifier 102 compares the output of the DAC reference regulator 100 with the target voltage, and outputs a constant voltage by controlling the gate voltage of the driver in a direction that reduces the error from the target voltage. To come.

  Then, the connection point between the resistor 112 and the DAC output terminal 111 is connected to the drain of the ramp DAC 110 composed of an N-channel field effect transistor. In the following description, the transistor constituting the DAC 110 may be described with reference numeral 110. The field effect transistor constituting the ramp wave DAC 110 has a source connected to the ground potential portion and a gate connected to the gate of the transistor 122. The transistors constituting the ramp-wave DAC 110 are variable, and the voltage output from the DAC output terminal 111 is determined by the variable setting of the transistors. The setting of the transistor 110 and the setting of the size of the driver 105 of the regulator 100 described above are configured in conjunction with each other. As the configuration to be set, for example, a plurality of field effect transistors are connected in parallel, and the size is varied by selecting a transistor to be operated. A specific configuration example for changing the size will also be described later.

A transistor 122 having a gate connected to a field effect transistor constituting the ramp DAC 110 is an N-channel field effect transistor. In this transistor 122, the current from the current source 121 is supplied to the drain, and the source is connected to the ground potential portion. The current source 121 supplies a constant current using the power source Vdd as a power source.
The transistors 110 and 122 are in a current mirror connection.

  With such a configuration, the voltage output from the DAC output terminal 111 is supplied as a reference voltage for digital conversion of the pixel signal. The configuration for digital conversion in the solid-state imaging device will be described later when the overall configuration of the solid-state imaging device is described.

  FIG. 2 shows a detailed configuration example of the driver 105 of the regulator 100 shown in FIG. 1 and the transistors constituting the ramp-wave DAC 110. FIG. 2 shows the configuration of the A portion surrounded by a broken line in FIG.

  In the example shown in FIG. 2, the driver 105 shown in FIG. 1 prepares a plurality of sets of two transistors in series. That is, two P-channel field effect transistors Q11 and Q12 are prepared, the source of the transistor Q11 is connected to the power supply Vdd, and the drain of the transistor Q11 is connected to the source of the transistor Q12. The drain of the transistor Q12 is connected to the DAC output terminal 111 side through the resistor 12.

  The gate of the transistor Q11 is connected to the output terminal 102a of the error amplifier 102 (FIG. 1). Output data of a DAC code generation unit 116, which will be described later, is supplied to the gate of the transistor Q12 via the inverter element 113. The drain of the transistor Q12 is connected to the reference voltage output terminal 106.

  In parallel with the transistors Q11 and Q12, a predetermined number of pairs of transistors Q13 and Q14, Q15 and Q16,. The output terminal 102a of the error amplifier 102 (FIG. 1) is commonly supplied to the gates of the transistors Q11, Q13, and Q15 of each group, and the ON / OFF is commonly controlled. Also, the other transistors Q12, Q14, Q16 of each set are individually supplied with output data at different bit positions of the DAC code generator 116 by different inverter elements 113, 114, 115,. ON / OFF is controlled. The other transistors Q12, Q14, Q16 of each set function as a driver size control unit of the regulator 100.

  As for the transistors constituting the ramp-wave DAC 110, a plurality of parallel sets of two transistors are prepared in parallel. That is, two N-channel field effect transistors Q21 and Q22 are prepared, the drain of the transistor Q21 is connected to the connection point between the resistor 112 and the DAC output terminal 111, and the source of the transistor Q21 is connected to the drain of the transistor Q22. Connect to. The source of transistor Q22 is connected to the ground potential portion.

  The output data of the DAC code generator 116 is supplied to the gate of the transistor Q21 to control on / off. The gate of transistor Q22 is connected to the gate side of transistor 122 (FIG. 1) via terminal 117.

  A predetermined number of pairs of transistors Q23 and Q24, Q25 and Q26,... Having the same connection configuration are prepared in parallel with the transistors Q21 and Q22. The gates of one of the transistors Q21, Q23, Q25 in each set are supplied with output data at different bit positions of the DAC code generator 116, and are individually controlled to be turned on / off. The other transistors Q22, Q24, Q26 of each set are connected to the gate side of the transistor 122 (FIG. 1) via a terminal 117.

  In FIG. 2, welfare in which a 3-bit (three) signal line is output from the DAC code generation unit 116 is shown, but in actuality, it corresponds to the number of bits of the digital value generated by the DAC code generation unit 116. A signal line is output, and a transistor group (transistors Q11, Q12, etc.) corresponding to the driver 105 and a transistor group (transistors Q21, Q22, etc.) constituting the ramp DAC 110 are each in the number of bits (that is, the number of signal lines). Just prepare.

[Circuit operation and effects]
The waveform diagram of FIG. 3 is a diagram showing a control state of each transistor having the configuration of FIG.
In the example of FIG. 3, a transistor set corresponding to the driver 105 and a transistor set constituting the ramp DAC 110 are prepared.
As shown in FIGS. 3A to 3C, a transistor that is turned on among a plurality of transistors Q21, Q23, Q25,... Prepared in parallel according to the output code value of the DAC code generation unit 116. The voltage value corresponding to the ON number is obtained at the DAC output terminal 111. In the case of this example, the output code value of the DAC code generation unit 116 is set so that the voltage value obtained at the DAC output terminal 111 becomes a ramp wave that decreases in order for each pixel signal readout period. It is.

  Then, the transistors Q12, Q14, Q16,... Constituting the driver 105 are turned on in conjunction with the control of the number of transistors that are turned on among the plurality of transistors Q21, Q23, Q25,. It is also configured to control the number of transistors. That is, the transistors Q12, Q14, and Q16 shown in FIGS. 3D to 3F are turned on in conjunction with the transistors Q21, Q23, and Q25 shown in FIGS.

As described above, the transistors constituting the regulator driver are divided into a plurality of sets, and each set of transistors is controlled by the DAC code, whereby appropriate control is performed. That is, even in a transistor not selected by the DAC code, the output of the error amplifier is supplied to the gate, and the voltage between the gate and source of one of the transistors Q11, Q13, and Q15 is always charged to an appropriate voltage. When the other transistors Q12, Q14, and Q16 transition from the off state to the on state due to the code change, it is possible to supply current with the minimum settling time.
In addition, when the value of the constant current source is changed by the DAC code, the current capability of the transistor constituting the driver also increases / decreases at the same rate, and as a result, the gate voltage of the transistor constituting the driver always maintains a constant value. It becomes like this. Therefore, even if the slope voltage fluctuates and a load fluctuates, it is not necessary to greatly increase or decrease the output of the error amplifier.

  For this reason, even if the response speed of the regulator is lowered, the DAC reference voltage can be maintained at the target value without causing any trouble in digital conversion. Further, in the configuration of the present embodiment, it is not necessary to continue the reactive current except for the purpose of directly generating the slope voltage, which greatly contributes to power saving of the entire system. This has a great effect particularly when the solid-state imaging device of the present embodiment is applied to a camera device driven by a battery or the like.

[Example of overall configuration of solid-state imaging device]
Next, an example of the overall configuration of a solid-state imaging device to which the configuration of the present embodiment is applied will be described with reference to FIG.
FIG. 4 is a schematic configuration diagram of a CMOS solid-state imaging device (CMOS image sensor) as an example of the solid-state imaging device to which the configuration of FIGS. 1 and 2 is applied.
The solid-state imaging device 1 includes a pixel unit in which a plurality of pixels including a light receiving element (an example of a charge generation unit) that outputs a signal corresponding to an incident light amount is arranged in rows and columns (that is, in a two-dimensional matrix). . A pixel signal output from each pixel is a voltage signal, and a CDS (Correlated Double Sampling) processing function unit, a digital conversion unit (ADC), and the like are provided in parallel in the pixel signal processing. ing.

  “The CDS processing function unit and the digital conversion unit are provided in parallel with the column” means that a plurality of CDS processing function units and digital conversion units are provided substantially in parallel with the vertical signal line 19 in the vertical column. Means that Each of the plurality of functional units is arranged only on one edge side in the column direction (the output side arranged on the lower side in FIG. 4) with respect to the pixel unit (imaging unit) 10 when the device is viewed in plan view. It may be in the form of being made. Alternatively, the pixel portion 10 is arranged separately on one edge side in the column direction (output side arranged on the lower side in the figure) and the other edge side (upper side in the figure) on the opposite side. It may be in the form. In the latter case, it is preferable that the horizontal scanning unit that performs readout scanning (horizontal scanning) in the row direction is also arranged separately on each edge side so that each can operate independently.

  For example, as a typical example in which a CDS processing function unit and a digital conversion unit are provided in parallel in a column, a CDS processing function unit and a digital conversion unit are arranged for each vertical column in a portion called a column area provided on the output side of the imaging unit. And is a column type that sequentially reads out to the output side. In addition to the column type, a configuration in which one CDS processing function unit or digital conversion unit is assigned to a plurality of adjacent (for example, two) vertical signal lines 19 (vertical columns), or every N (N is It is also possible to adopt a form in which one CDS processing function unit or digital conversion unit is assigned to N vertical signal lines 19 (vertical columns) of a positive integer (with N−1 lines in between). In the following embodiments, this column type will be described unless otherwise specified.

  As illustrated in FIG. 4, the solid-state imaging device 1 includes a pixel unit (imaging unit) 10 in which a plurality of unit pixels 3 having a substantially square pixel shape are arranged in rows and columns (that is, a square lattice), and a pixel unit. 10 includes a drive control unit 7, a column processing unit 26, a reference signal generation unit 27 that supplies a reference voltage for AD conversion to the column processing unit 26, and an output circuit 28.

  The drive control unit 7 has a control circuit function for sequentially reading signals from the pixel unit 10. For example, the drive control unit 7 includes a horizontal scanning circuit (column scanning circuit) 12 that controls column addresses and column scanning, a vertical scanning circuit (row scanning circuit) 14 that controls row addresses and row scanning, and an internal clock. And a communication / timing control unit 20 having a function such as generation.

  In the figure, as indicated by a broken line in the vicinity of the communication / timing control unit 20, the clock conversion unit 23 is an example of a high-speed clock generation unit that generates a pulse having a clock frequency faster than the input clock frequency. May be provided. The communication / timing control unit 20 generates an internal clock based on the input lock (master clock) CLK0 input via the terminal 5a and the high-speed clock generated by the clock conversion unit 23.

  In FIG. 4, some of the rows and columns are omitted for the sake of simplicity, but in reality, several tens to thousands of unit pixels 3 are arranged in each row and each column, and the pixel unit 10 includes Composed. The unit pixel 3 is typically composed of a photodiode as a light receiving element (charge generation unit) and an in-pixel amplifier having an amplifying semiconductor element (for example, a transistor).

  In addition to an effective image region (effective portion) that is an effective region for capturing an image, the pixel unit 10 includes a reference pixel region that provides optical black arranged around the effective image region. As an example, reference pixels that give optical black for several rows (for example, 1 to 10 rows) are arranged above and below in the vertical column direction, and several pixels to several tens in the horizontal direction including the effective image region 10a. Reference pixels that provide optical black for pixels (for example, 3 to 40 pixels) are arranged.

  The reference pixel for providing optical black is shielded on the light receiving surface side so that light does not enter a charge generation unit made of a photodiode or the like. The pixel signal from this reference pixel is used for the black reference of the video signal.

  Further, in the solid-state imaging device 1, the pixel unit 10 is adapted for color imaging. That is, the light receiving surface of each charge generation unit (photodiode or the like) in the pixel unit 10 is provided with any one of color separation filters including a combination of a plurality of color filters for capturing a color image. Yes.

  The example shown in FIG. 4 uses a basic color filter of a so-called Bayer array, and unit pixels 3 arranged in a square lattice are red (R), green (G), and blue (B). The repeating unit of the color separation filter is arranged by 2 pixels × 2 pixels so as to correspond to the three-color color filter, thereby constituting the pixel unit 10.

For example, a first color pixel for sensing a first color (red; R) is arranged in an odd-numbered row and an odd-numbered column, and a second color (green; G; ) Is arranged, and the third color pixel for sensing the third color (blue; B) is arranged in the even-numbered row and the even-numbered column, and is different for each row. Further, two color pixels of R / G or G / B are arranged in a checkered pattern.
In the color arrangement of the basic color filter in such a Bayer arrangement, two colors of R / G or G / B are repeated every two in both the row direction and the column direction.

  Further, as other components of the drive control unit 7, a horizontal scanning circuit 12, a vertical scanning circuit 14, and a communication / timing control unit 20 are provided. The horizontal scanning circuit 12 has a function of a reading scanning unit that reads a count value from the column processing unit 26. Each element of these drive control units 7 is formed integrally with a pixel unit 10 in a semiconductor region such as single crystal silicon using a technique similar to a semiconductor integrated circuit manufacturing technique, and is a solid-state imaging which is an example of a semiconductor system It is configured as an element (imaging device).

  The unit pixel 3 includes a column processing unit 26 in which a vertical scanning circuit 14 is provided via a row control line 15 for row selection, and a column AD circuit 25 is provided for each vertical column via a vertical signal line 19; Each is connected. Here, the row control line 15 indicates the entire wiring that enters the pixel from the vertical scanning circuit 14.

  The horizontal scanning circuit 12 and the vertical scanning circuit 14 include a decoder as will be described later, and start a shift operation (scanning) in response to control signals CN1 and CN2 given from the communication / timing control unit 20. It has become. Therefore, the row control line 15 includes various pulse signals (for example, a reset pulse RST, a transfer pulse TRF, a DRN control pulse DRN, etc.) for driving the unit pixel 3.

  Although not shown, the communication / timing control unit 20 includes a functional block of a timing generator TG (an example of a read address control device) that supplies a clock signal necessary for the operation of each unit and a pulse signal with a predetermined timing. The communication / timing control unit 20 receives a master clock through the terminal 5a, receives data instructing an operation mode and the like through the terminal 5b, and further outputs data including information on the solid-state imaging device 1. Provide functional blocks.

  For example, the horizontal address signal is output to the horizontal decoder 12a and the vertical address signal is output to the vertical decoder 14a, and each decoder 12a, 14a receives it and selects a corresponding row or column.

  At this time, since the unit pixels 3 are arranged in a two-dimensional matrix, analog pixel signals generated by the pixel signal generation unit 5 and output in the column direction via the vertical signal lines 19 are arranged in a row unit (column parallel). ) Access and capture (vertical) scan reading. Thereafter, the pixel signal or pixel is read by performing a (horizontal) scan reading in which the pixel signal (in this example, digitized pixel data) is read out to the output side by accessing the row direction which is the arrangement direction of the vertical columns. Data reading speed can be increased. Of course, not only scanning reading but also random access for reading out only the information of the necessary unit pixel 3 is possible by directly addressing the unit pixel 3 to be read out.

  In the communication / timing control unit 20, a clock CLK1 having the same frequency as the master clock (master clock) CLK0 input through the terminal 5a, a clock obtained by dividing the clock CLK1, or a low-speed clock obtained by further dividing the device are used as devices. For example, the horizontal scanning circuit 12, the vertical scanning circuit 14, and the column processing unit 26. Hereinafter, the clocks divided by two and all clocks having a frequency lower than that are collectively referred to as a low-speed clock CLK2.

  The vertical scanning circuit 14 selects a row of the pixel unit 10 and supplies a necessary pulse to the row. For example, a vertical decoder 14a that defines a readout row in the vertical direction (selects a row of the pixel unit 10), and a row control line 15 for the unit pixel 3 on the readout address (in the row direction) defined by the vertical decoder 14a. And a vertical drive circuit 14b for driving by supplying a pulse. Note that the vertical decoder 14a selects a row for electronic shutter, in addition to a row from which a signal is read.

  The horizontal scanning circuit 12 sequentially selects the column AD circuit 25 of the column processing unit 26 in synchronization with the low-speed clock CLK2, and guides the signal to a horizontal signal line (horizontal output line) 18. For example, a horizontal decoder 12a that defines a horizontal readout column (selects each column AD circuit 25 in the column processor 26), and each of the column processors 26 according to a read address defined by the horizontal decoder 12a. A horizontal drive circuit 12b for guiding a signal to the horizontal signal line 18. For example, if the number of horizontal signal lines 18 is n (n is a positive integer) handled by the column AD circuit 25, for example, 10 (= n) bits, 10 horizontal signal lines 18 are arranged corresponding to the number of bits. .

  In the solid-state imaging device 1 having such a configuration, the pixel signal output from the unit pixel 3 is supplied to the column AD circuit 25 of the column processing unit 26 via the vertical signal line 19 for each vertical column.

  Each column AD circuit 25 of the column processing unit 26 receives a pixel signal for one column and processes the signal. For example, each column AD circuit 25 has an ADC circuit that converts an analog signal into, for example, 10-bit digital data using, for example, the low-speed clock CLK2.

  As the AD conversion processing in the column processing unit 26, a method is adopted in which analog signals held in parallel in units of rows are subjected to AD conversion in parallel for each row using the column AD circuit 25 provided for each column. At this time, an AD conversion method called a single slope integration type is used. Since this method can realize an AD converter with a simple configuration, it has a feature that the circuit scale does not increase even if it is provided in parallel.

  As for the configuration of the ADC circuit, the analog processing target signal is converted into digital data based on the time from the start of conversion until the reference voltage RAMP and the processing target signal voltage match. As a mechanism for this, in principle, a ramp-shaped reference voltage RAMP is supplied to a comparator (voltage comparator), and at the same time, counting with a clock signal is started and input via the vertical signal line 19. By comparing the analog pixel signal with the reference voltage RAMP and counting until a pulse signal is obtained, AD conversion is performed.

  The pixel data digitized by the column AD circuit 25 is transmitted to the horizontal signal line 18 through a horizontal selection switch (not shown) driven by a horizontal selection signal from the horizontal scanning circuit 12, and further input to the output circuit 28. The Note that 10 bits is an example, and other bit numbers such as less than 10 bits (for example, 8 bits) and more than 10 bits (for example, 14 bits) may be used.

  With such a configuration, pixel signals are sequentially output for each vertical column for each row from the pixel unit 10 in which light receiving elements as charge generation units are arranged in a matrix. Then, one image corresponding to the pixel unit 10 in which the light receiving elements are arranged in a matrix, that is, a frame image, is shown as a set of pixel signals of the entire pixel unit 10.

Next, the reference signal generation unit 27 that generates a reference signal for AD conversion shown in FIG. 4 will be described. The reference signal generation unit 27 is a component including the DAC 110 described with reference to FIGS. 1 and 2.
In this example, as the solid-state imaging device 1, a Bayer-type basic array is used, and as described above, the color filter is repeated every two rows and two columns. The pixel signal is read out in units of rows, and the pixel signal is input to each column AD circuit 25 provided in parallel for each vertical signal line 19. Therefore, one processing target row includes R / G or G / B. There are pixel signals of only two colors. Here, in the example of FIG. 4, as the DAC 110, a DAC 110a corresponding to an odd number column and a DAC 110b corresponding to an even number column are provided.

  Further, the reference signals RAMPa and RAMPb output independently from each DAC are transmitted to the voltage comparison unit 252 through independent common reference signal lines 251a and 251b (collectively referred to as 251). A plurality of voltage comparison units 252a (in odd-numbered columns) and voltage comparison units 252b (in even-numbered columns) are connected to the common reference signal lines 251a and 251b, respectively.

  Each DAC 110a, 110b may be the same as the count clocks CKdaca, CKdacb (count clock CK0) from the communication / timing control unit 20 from the initial value indicated by the control data CN4 (CN4a, CN4b) from the communication / timing control unit 20. ), A stepped sawtooth wave (ramp voltage or slope voltage) is generated, and the generated sawtooth wave is sent to the corresponding column AD circuit 25 of the column processing unit 26 for AD conversion. Reference signals (ADC reference signals) RAMPa and RAMPb are supplied.

  The column AD circuit 25 includes the reference signal RAMP generated by the DAC 110a of the reference signal generation unit 27 and the vertical signal line 19 (H1, H2,...) From the unit pixel 3 for each row control line 15 (V1, V2,...). A voltage comparison unit (comparator) 252 that compares an analog pixel signal obtained via the counter, and a counter unit 254 that counts the time until the voltage comparison unit 252 completes the comparison process and holds the result. And has an n-bit AD conversion function.

  One input terminal RAMP of the voltage comparison unit 252 receives the step-like reference signal RAMP generated by the reference signal generation unit 27 in common with the input terminal RAMP of the other voltage comparison unit 252, and inputs to the other input terminal. Are connected to the vertical signal lines 19 of the corresponding vertical columns, and the pixel signal voltages from the pixel unit 10 are individually inputted. The output signal of the voltage comparison unit 252 is supplied to the counter unit 254.

  The count clock CK0 from the communication / timing control unit 20 is input to the clock terminal CK of the counter unit 254 in common with the clock terminals CK of the other counter units 254.

  The counter unit 254 is omitted from the illustration of the configuration, but can be realized by changing the wiring form of the data storage unit constituted by the latch to the synchronous counter form. Counting is to be performed. Similarly to the stepped voltage waveform, the count clock CK0 is generated based on a high-speed clock (for example, a multiplied clock) from the clock conversion unit 23, so that the count clock CK0 is faster than the master clock CLK0 input through the terminal 5a. be able to.

  A control pulse is input to the counter unit 254 from the horizontal scanning circuit 12 through the control line 12c. The counter unit 254 has a latch function for holding the count result, and holds the counter output value until an instruction by a control pulse through the control line 12c is given.

  The output side of each column AD circuit 25 is connected to the horizontal signal line 18. The horizontal signal line 18 has a signal line of an n-bit width which is the bit width of the column AD circuit 25, and is connected to the output circuit 28 via n sense circuits corresponding to the respective output lines (not shown). The

  In such a configuration, the column AD circuit 25 performs a count operation in the pixel signal readout period corresponding to the horizontal blanking period, and outputs a count result at a predetermined timing. That is, first, the voltage comparison unit 252 compares the ramp waveform voltage from the reference signal generation unit 27 with the pixel signal voltage input via the vertical signal line 19, and if both voltages are the same, the voltage comparison The comparator output of the unit 252 is inverted.

  The counter unit 254 starts the count operation in the down-count mode or the up-count mode in synchronization with the ramp waveform voltage from the reference signal generation unit 27, and when the inverted information of the comparator output is notified to the counter unit 254. Stop counting operation. The AD conversion is completed by latching (holding / storing) the count value at that time as pixel data.

  Thereafter, the counter unit 254 sequentially stores the stored and held pixel data based on the shift operation by the horizontal selection signal CH (i) input from the horizontal scanning circuit 12 via the control line 12c at a predetermined timing. The data is output from the output terminal 5 c to the outside of the column processing unit 26 and the chip having the pixel unit 10.

  The configuration of the solid-state imaging device (element) 1 shown in FIG. 4 is an example, and is not limited to such a configuration. That is, for example, in the example of FIG. 4, the DAC 110 is provided with two sets of the DACs 110 a and 110 b, but is not limited to such a configuration.

FIG. 5 shows an example of the ramp wave RAMP output from the DAC 110a or the DAC 110b in the configuration shown in FIG.
In the example of FIG. 5, the ramp wave that is the reference voltage is configured to sequentially decrease from the initial voltage in synchronization with the clock, and the clock count value at the timing when the reference voltage is lower than the pixel voltage is the pixel signal. It becomes a digital conversion value. The digital conversion of the pixel value by comparing the reference voltage and the pixel voltage in FIG. 5 is repeated each time a signal of one pixel is processed. That is, it is performed in conjunction with a pixel cycle for imaging by an image sensor constituting the solid-state imaging device.

[Example of overall configuration of camera system]
Next, with reference to FIG. 6, an outline of the overall configuration of the camera system including the solid-state imaging device shown in FIG. 4 will be described.
Based on the image light incident on the solid-state imaging device 1 via the lens 305, each pixel signal is generated and read by the solid-state imaging device 1. The pixel signal read from the solid-state imaging device 1 is pixel data that has been digitally converted. The pixel data is supplied to the video processing unit 301, where various video processing is performed and a video signal having a predetermined format is used. The video signal obtained by the video processing unit 301 is supplied to the display unit 302 to be displayed and supplied to the recording unit 303 to be recorded on various recording media. Further, if necessary, the video signal is output to the outside.
Imaging processing in the solid-state imaging device 1 and video processing in the video processing unit 301 are performed in synchronization with a clock supplied from the clock generation unit 304.
Further, processing in each unit in the camera is executed based on the control of the control unit 306.

  As the camera system shown in FIG. 5, the image signal obtained by imaging with the solid-state imaging device having the DAC shown in FIGS. 1 and 2 has noise caused by the distortion of the reference voltage. It is not included, and the occurrence of horizontal streak noise can be effectively prevented.

2. Second Embodiment Next, an example of a second embodiment of the present invention will be described with reference to FIGS. 7 and 8, the same reference numerals are given to the portions corresponding to FIGS. 1 to 6 described above. 7 and 8 show the configurations of the regulator and the DAC for generating the reference voltage. The overall configuration of the imaging device and the configuration of the camera system including the imaging device are, for example, the first one. The configuration described in the embodiment can be applied.

[Configuration of digital / analog converter circuit]
FIG. 7 is a diagram showing the overall configuration of the regulator and the DAC.
The DAC reference regulator 100 includes a driver 105 composed of a P-channel field effect transistor for obtaining a DAC reference voltage. The driver 105 of this example is configured such that the size can be varied in a plurality of stages, like the driver 105 described in the first embodiment. As a configuration for changing the driver size, for example, a plurality of field effect transistors are connected in parallel, and the size is changed by selecting a transistor to be operated. A specific configuration example for changing the size in this embodiment will be described later.

The driver 105 of this P-channel type field effect transistor has a source connected to a terminal from which the power supply voltage Vdd can be obtained, and a drain connected to the DAC output terminal 111 via a resistor 112.
The gate of the driver 105 is controlled by the output of the error amplifier 102. The error amplifier 102 compares the output voltage of the regulator 100 divided by the resistor 112 with the reference voltage from the voltage source 101, detects an error from the target voltage, and detects the error from the driver 105. Supply to the gate. One end of the variable resistor 103 and the capacitor 104 is connected to a connection point between the driver 105 and the resistor 112, and the other end of the variable resistor 103 and the capacitor 104 is grounded. Then, the voltage signal divided by the variable resistor 103 is input to the error amplifier 102. With this configuration, the error amplifier 102 compares the output of the DAC reference regulator 100 with the target voltage, and outputs a constant voltage by controlling the gate voltage of the driver in a direction that reduces the error from the target voltage. To come.

  Then, the connection point between the resistor 112 and the DAC output terminal 111 is connected to the drain of the ramp DAC 110 composed of an N-channel field effect transistor. The field effect transistor constituting the ramp wave DAC 110 has a source connected to the ground potential portion and a gate connected to the gate of the transistor 122. The transistors constituting the ramp-wave DAC 110 are variable, and the voltage output from the DAC output terminal 111 is determined by the variable setting of the transistors. The setting of the transistor 110 and the setting of the size of the driver 105 of the regulator 100 described above are configured in conjunction with each other. As the configuration to be set, for example, a plurality of field effect transistors are connected in parallel, and the size is varied by selecting a transistor to be operated.

  A transistor 122 having a gate connected to a field effect transistor constituting the ramp DAC 110 is an N-channel field effect transistor. The transistor 122 is connected between the power supply potential portion Vdd and the ground potential portion via a P-channel field effect transistor 123. That is, the source of the transistor 123 is connected to the power supply potential portion Vdd, the drain of the transistor 123 is connected to the drain of the transistor 122, and the source of the transistor 122 is connected to the ground potential portion. The transistor 123 constitutes a gain setting DAC and is configured to be variable according to the set gain. This variable configuration will be described later.

The gate of the transistor 123 is connected to a P-channel field effect transistor 124. A current source 125 is connected to the transistor 124 and supplies a constant current using the power source Vdd as a power source.
The gate and the drain of the transistor 124 are connected, and the transistor 123 and the transistor 124 are in a current mirror connection in which current amounts are equal.
With such a configuration, the voltage output from the DAC output terminal 111 is supplied as a reference voltage for digital conversion of the pixel signal.

  In the present embodiment, the driver 105 of the regulator 110 is controlled in conjunction with the control state of the ramp wave DAC 110, and the regulator 110 of the regulator 110 is interlocked with the control state of the transistor 123 constituting the gain setting DAC. The driver 105 is controlled.

  FIG. 8 shows a detailed configuration example of the driver 105 of the regulator 100 shown in FIG. 7, the transistor constituting the ramp wave DAC 110, and the transistor 123 constituting the gain setting DAC. FIG. 8 shows a configuration of a portion B indicated by a broken line in FIG.

  In the example of FIG. 8, the configuration in which the driver 105 is controlled by the transistors that constitute the ramp wave DAC 110 is the same as the configuration shown in FIG. 2 in the first embodiment. That is, the transistors Q21, Q23,... Are individually controlled by the output code of the ramp wave DAC code generator 116, and the transistors Q12, Q14,. Are controlled individually. The gates of the transistors Q22 and Q24 are connected to the gate side of the transistor 122 (FIG. 7) via the terminal 117.

Transistors connected in series with the transistors Q12, Q14,... In the regulator (corresponding to the transistors Q11, Q13,... In FIG. 2) are connected in parallel in a plurality of stages for each set. Prepare.
For example, a set of the transistor Q12 will be described. The power supply potential portion Vdd is connected to the transistor Q12 via P-channel type field effect transistors Q31 and Q32. Then, transistor rows Q33, Q34 and Q35, Q36 having the same configuration as the transistor rows Q31, Q32 are prepared, the transistor rows are connected in parallel, and the drains of the transistors Q32, Q34, Q36 are connected to the source of the transistor Q12. Connect in common.

Transistors Q31, Q33, and Q35 have their gates supplied with the output of error amplifier 102 (FIG. 7) of regulator 100.
The transistors Q32, Q34, and Q36 are controlled by a gain setting DAC code generation unit 130 described later.

  The same connection applies to the set of transistor Q14 in the regulator. That is, the power supply potential portion Vdd is connected to the transistor Q14 via the P-channel field effect transistors Q41 and Q42. Then, transistor rows Q43, Q44 and Q45, Q46 having the same configuration as the transistor rows Q41, Q42 are prepared, the transistor rows are connected in parallel, and the drains of the transistors Q42, Q44, Q46 are connected to the source of the transistor Q14. Connect in common.

Transistors Q41, Q43, and Q45 have their gates supplied with the output of error amplifier 102 (FIG. 7) of regulator 100.
The transistors Q42, Q44, and Q46 are controlled by a gain setting DAC code generation unit 130 described later.

Then, two transistors Q51 and Q52 connected in series are prepared as transistors corresponding to the transistor 123 as the gain setting DAC of FIG. 7, and further, transistors Q53 and Q54 and transistors Q55 and Q56 are prepared. Then, each two transistor sets Q51, Q52 and Q53, Q54 and Q55, Q56 are connected in parallel. Each of the transistors Q51 to Q56 is a P-channel type field effect transistor.
The drains of the transistors Q52, 54, and 56 in each column are connected to the drain of the transistor 122 shown in FIG. The gates of the transistors Q51, Q53, and Q55 are connected to the gate of the transistor 124 shown in FIG. 7 through the terminal 124a.

Output data at different bit positions of the gain setting DAC code generation unit 130 is supplied to the gates of the transistors Q52, Q54, and Q56, and ON / OFF is individually controlled. Further, the transistors Q32, Q34, Q36 and the transistors Q42, Q44, Q46 are controlled by the output data at different bit positions of the gain setting DAC code generator 130.
In FIG. 8, only the configuration of the 3-bit output from the DAC code generation unit 130 is shown, and the same configuration is configured for other bit outputs and connected in parallel.

[Effect of circuit]
The configuration shown in FIGS. 7 and 8 changes the slope of the slope voltage by digitally increasing and decreasing the current value controlled by the ramp DAC 110 in addition to the ramp DAC 110 that generates the slope voltage. Thus, the present invention can be applied to a configuration having a function capable of adjusting the AD conversion gain. According to the configuration of the present embodiment, it can be applied to a higher-accuracy DAC.

3. Third Embodiment Next, an example of a third embodiment of the present invention will be described with reference to FIG. 9 and FIG. 9 and 10, the same reference numerals are given to the portions corresponding to FIGS. 1 to 8 described above. 9 and 10 show the configurations of the regulator and the DAC for generating the reference voltage. The overall configuration of the imaging device and the configuration of the camera system including the imaging device are, for example, the first one. The configuration described in the embodiment can be applied.

[Configuration of digital / analog converter circuit]
FIG. 9 is a diagram illustrating the overall configuration of the regulator and the DAC.
The basic configuration in the present embodiment is the same as the configuration shown in FIG. 7 in the second embodiment. That is, a DAC reference regulator 100, a ramp wave DAC 110, and a gain setting DAC 123 are provided. In the configuration of FIG. 7 described in the second embodiment, the size control of the driver 105 in the regulator 100 is controlled by both the DAC code in the ramp wave DAC 110 and the DAC code in the gain setting DAC 123. The configuration. On the other hand, in this embodiment, as shown in FIG. 9, the size of the driver 105 in the regulator 100 is controlled only by the DAC code of the gain setting DAC 123.

  The basic configuration of FIG. 9 is the same as the configuration shown in FIG. 7 in the second embodiment. However, the size of the driver 105 in the regulator 100 is controlled only by the gain setting DAC code in conjunction with the transistors constituting the gain setting DAC 123.

  FIG. 10 shows a detailed configuration example of the driver 105 of the regulator 100 shown in FIG. 9 and the transistor 123 constituting the gain setting DAC. FIG. 10 shows a configuration of a C portion surrounded by a broken line in FIG. The reference numerals of the transistors shown in FIG. 10 correspond to the reference numerals of the transistors shown in FIG.

  As shown in FIG. 10, the power supply potential portion Vdd is connected to the resistor 112 (see FIG. 8) via P-channel field effect transistors Q31 and Q32. Then, transistor rows Q33, Q34 and Q35, Q36 having the same configuration as the transistor rows Q31, Q32 are prepared, the transistor rows are connected in parallel, and the drains of the transistors Q32, Q34, Q36 are connected to the resistor 112. Connect in common.

Transistors Q31, Q33, and Q35 have their gates supplied with the output of error amplifier 102 (FIG. 7) of regulator 100.
The transistors Q32, Q34, and Q36 are controlled by the gain setting DAC code generator 130.

Then, two transistors Q51 and Q52 connected in series are prepared as transistors corresponding to the transistor 123 as the gain setting DAC of FIG. 9, and further, transistors Q53 and Q54 and transistors Q55 and Q56 are prepared. Then, each two transistor sets Q51, Q52 and Q53, Q54 and Q55, Q56 are connected in parallel. Each of the transistors Q51 to Q56 is a P-channel type field effect transistor.
The drains of the transistors Q52, 54, and 56 in each column are connected to the drain of the transistor 122 shown in FIG. The gates of the transistors Q51, Q53, and Q55 are connected to the gate of the transistor 124 shown in FIG. 9 through the terminal 124a.

Output data at different bit positions of the gain setting DAC code generation unit 130 is supplied to the gates of the transistors Q52, Q54, and Q56, and ON / OFF is individually controlled. Further, the transistors Q32, Q34, Q36 and the transistors Q42, Q44, Q46 are controlled by the output data at different bit positions of the gain setting DAC code generator 130.
In FIG. 10, only the configuration of the 3-bit output from the DAC code generation unit 130 is shown, and the other bit outputs are configured in the same manner and connected in parallel.

  The configuration shown in FIG. 9 and FIG. 10 also constitutes a highly accurate DAC. Characteristically, the control of the size of the driver in the regulator, which is the configuration described in the second embodiment, is controlled by both the DAC code of the ramp wave DAC and the DAC code of the gain setting DAC. Most preferably. However, as shown in FIG. 8, the circuit scale becomes large, and it may not be practical to construct the circuit so far.

  Here, as shown in FIG. 9 and FIG. 10 of the present embodiment, a configuration in which the operation of the error amplifier is suppressed is ensured even by linking the driver size only to the gain setting DAC 123, and good characteristics are obtained. can get.

It is a circuit diagram which shows the structural example by the 1st Embodiment of this invention. It is a circuit diagram which shows the specific example of the A section of FIG. FIG. 3 is a timing diagram illustrating an example of a control state of each transistor in FIG. 2. It is a block diagram which shows the example of whole structure of the solid-state imaging device with which embodiment of this invention is applied. It is a wave form diagram which shows the example of a slope waveform voltage and a pixel voltage. It is a block diagram which shows the structural example of the camera system with which embodiment of this invention is applied. It is a circuit diagram which shows the structural example by the 2nd Embodiment of this invention. It is a circuit diagram which shows the specific example of the B section of FIG. It is a circuit diagram which shows the structural example by the 2nd Embodiment of this invention. It is a circuit diagram which shows the specific example of the C section of FIG. It is explanatory drawing which shows the example when the slope waveform voltage and the waveform are distorted.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 100 ... Regulator for DAC reference, 101 ... Voltage source, 102 ... Error amplifier, 103 ... Variable resistor, 104 ... Capacitor, 105 ... Driver, 106 ... Reference voltage input terminal, 110 ... DAC for ramp wave, 111 ... DAC output terminal DESCRIPTION OF SYMBOLS 112 ... Resistor 113, 114, 115 ... Inverter element 116 ... DAC code generation part 121 ... Current source 122 ... Transistor 130 ... Gain setting DAC code generation part 301 ... Video processing part 302 ... Display , 303 ... Recording unit, 304 ... Clock generation unit, 305 ... Lens, 306 ... Control unit

Claims (7)

A regulator that outputs a reference voltage from a driver;
A reference voltage output from the regulator is supplied, and an analog voltage output unit that outputs an analog voltage according to the input code;
A digital-to-analog converter circuit comprising: a driver size control unit that varies a size of a driver in the regulator according to the code. The driver comprises a plurality of driver units,
The digital-analog converter circuit according to claim 1, wherein the driver size control unit is configured to select a driver unit to be turned on from the plurality of driver units according to the code and to vary the driver size. Each of the plurality of driver units is composed of a plurality of MOS transistors,
The gate of one of the plurality of MOS transistors is controlled by the output of the error amplifier of the regulator, and the gate of the other MOS transistor is controlled by the value of the code. Digital / analog conversion circuit. The digital-to-analog converter circuit according to claim 1, wherein the analog voltage output unit outputs a slope voltage for digitally converting a pixel signal in the image sensor in conjunction with a cycle in which a pixel signal to be imaged by the image sensor is obtained. . A plurality of pixel portions arranged in a matrix;
A regulator that outputs a reference voltage from a driver;
An analog voltage output unit that supplies a reference voltage output from the regulator and outputs a slope voltage in which the voltage sequentially changes according to the input code;
A digital converter that compares the slope voltage with the output voltage of the pixel unit and converts the output voltage of the pixel unit into digital data corresponding to the code;
A solid-state imaging device comprising: a driver size control unit configured to vary a size of a driver in the regulator according to the code. A plurality of pixel portions arranged in a matrix;
A regulator that outputs a reference voltage from a driver;
An analog voltage output unit that supplies a reference voltage output from the regulator and outputs a slope voltage in which the voltage sequentially changes according to the input code;
A digital converter that compares the slope voltage with the output voltage of the pixel unit and converts the output voltage of the pixel unit into digital data corresponding to the code;
A driver size controller that varies the size of the driver in the regulator according to the code;
And a video processing unit that uses the digital data converted by the digital conversion unit as video data. Control the reference voltage output from the driver that constitutes the regulator according to the input code to obtain an analog voltage output,
A digital code analog conversion method in which a size of the driver is variably set according to the code.

Images