WO2020147584A1 - 一种具有多值存储能力的各向异性浮栅存储器 - Google Patents

一种具有多值存储能力的各向异性浮栅存储器 Download PDF

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WO2020147584A1
WO2020147584A1 PCT/CN2020/000019 CN2020000019W WO2020147584A1 WO 2020147584 A1 WO2020147584 A1 WO 2020147584A1 CN 2020000019 W CN2020000019 W CN 2020000019W WO 2020147584 A1 WO2020147584 A1 WO 2020147584A1
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floating gate
gate memory
value storage
anisotropic
dimensional layered
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French (fr)
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韩拯
张志东
王汉文
陈茂林
孙兴丹
李小茜
王志
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中国科学院金属研究所
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND

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  • the invention belongs to the application research fields of nano artificial composites, micro and nano devices, memories and the like, and specifically provides an anisotropic floating gate memory with multi-value storage capabilities.
  • NVM Non-volatile memory
  • Flash flash memory
  • flash memory Flash-based floating gate memory
  • flash memory Flash-based floating gate memory
  • flash memory Flash-based floating gate memory
  • flash memory In 2012, NAND-type Flash has developed to 32nm/64Gbit technology.
  • flash memory Although flash memory has achieved great success and occupies the largest share of the memory market, flash memory itself faces many defects and problems, such as slow erasing speed (0.1ms) and high erasing voltage (5V).
  • flash memory is the limit of downscaling: the continuous reduction in size leads to fewer and fewer electrons stored in a single memory cell, and the probability of electron tunneling due to adjacent memory cells getting closer and closer. The higher the value, the lower the reliability of stored information. Therefore, how to improve the storage density of floating gate memories represented by Flash is a problem to be solved urgently.
  • Some materials with poor crystallographic symmetry often exhibit direction-dependent physical properties, such as mechanical anisotropy, optical anisotropy, and electrical anisotropy.
  • mechanical anisotropy In the two-dimensional limit of materials, due to the disappearance of the z-axis dimension, these anisotropies are often more obvious, and they contain rich physical connotations and huge application prospects.
  • electrical anisotropy of two-dimensional materials For example, in black phosphorus, researchers have observed that it has an in-plane electrical anisotropy of ⁇ a / ⁇ b ⁇ 1.5.
  • the two-dimensional layered material gallium telluride (GaTe) is a p-type semiconductor with a direct band gap ( ⁇ 1.7eV) and has excellent photoelectric properties. Its crystallographic symmetry is very low (C 3 2h space group), showing obvious optical and electrical anisotropy.
  • the purpose of the present invention is to provide a method that can realize floating gate memory with multi-value storage capability, and an anisotropic floating gate memory designed by this method.
  • the method is simple to operate and can obtain excellent performance with multi-value storage capability.
  • Floating gate memory is simple to operate and can obtain excellent performance with multi-value storage capability.
  • a method for realizing the multi-value storage capability of an anisotropic floating gate memory is characterized in that: using the electrical anisotropy and gate adjustability of a two-dimensional layered semiconductor material to realize a floating gate memory with multi-value storage capability.
  • the present invention also provides an anisotropic floating gate memory with multi-value storage capability, which is characterized in that: the anisotropic floating gate memory uses a two-dimensional layered metal material as the buried gate and uses two The layered semiconductor material is used as the channel material, and the insulator is used as the dielectric layer and the encapsulation layer.
  • the two-dimensional layered semiconductor material of the present invention is a material with electrical anisotropy (the resistance of the material is different in different crystallographic orientations), and the magnitude of the electrical anisotropy is regulated by the gate voltage, preferably telluride Gallium (GaTe);
  • the insulator is a two-dimensional layered insulator material, preferably hexagonal boron nitride (h-BN);
  • the two-dimensional layered metal material is preferably a multilayer graphene (FLG).
  • the thickness of the two-dimensional layered semiconductor material of the present invention is 1 nm-30 nm, and it can be prepared by mechanically cleaving single crystal bulk or chemical growth.
  • the two-dimensional layered semiconductor material of the present invention is obtained by the following methods: chemical weather deposition (CVD), mechanical peeling cleavage, ultrasonic peeling in solution or chemical peeling.
  • CVD chemical weather deposition
  • mechanical peeling cleavage mechanical peeling cleavage
  • ultrasonic peeling in solution or chemical peeling.
  • the substrate on which the floating gate memory device of the present invention is placed is a Si substrate, a quartz substrate, a mica sheet or a flexible substrate.
  • the present invention also provides a method for preparing the anisotropic floating gate memory with multi-value storage capability, which is characterized in that:
  • the two-dimensional layered semiconductor material, the two-dimensional layered metal material buried gate, the dielectric layer and the packaging layer are stacked by van der Waals to obtain h-BN/GaTe/h-BN/FLG van der Waals heterojunction; electron beam exposure (EBL), Reactive Ion Etching (RIE), Electron Beam Evaporation (EBE) and other technologies to prepare floating gate memory with electrodes along two-dimensional layered semiconductor materials with different crystal orientations.
  • EBL electron beam exposure
  • RIE Reactive Ion Etching
  • EBE Electron Beam Evaporation
  • the memory of the present invention can realize the regulation of the electrical anisotropy of the channel material by changing the size of the gate voltage, and realize the readout of multi-resistance values through one-time operation voltage writing.
  • the method for preparing an anisotropic floating gate memory with multi-value storage capability of the present invention is characterized in that: the metal electrodes appear in pairs along a certain crystal orientation of the two-dimensional layered semiconductor material, and different pairs of electrodes have a certain angle.
  • the metal used in the metal electrode is one or more of Cr, Ti, Au, Pd, Sc, and Ni.
  • the present invention utilizes the significant electrical anisotropy of the two-dimensional layered material gallium telluride, through van der Waals stacking technology and micro-nano processing technology, using multi-layer graphene (FLG) as the buried gate, and a few layers of GaTe as the channel material. Designing electrodes with different crystal orientations results in a floating gate memory with a large switching ratio (>10 7 ) and a long storage time.
  • FLG multi-layer graphene
  • the GaTe electrical anisotropy can be adjusted (the ratio of maximum current to minimum current (I y /I x ) can reach up to -10 3 orders of magnitude), so that the memory only passes once
  • the ratio of maximum current to minimum current (I y /I x ) can reach up to -10 3 orders of magnitude
  • the gate voltage can significantly control the electrical anisotropy of some two-dimensional layered materials
  • a floating gate memory with excellent performance can be prepared with a large switching ratio (>10 7 ) and a long storage time;
  • Floating gate memory with multi-value storage capability can be prepared, thereby increasing the storage density of the memory.
  • Figure 1 is a schematic diagram of the preparation process of an anisotropic floating gate memory with multi-value storage capabilities: a: Dry transfer of h-BN on FLG; b: vacuum annealing; cd: dry transfer of GaTe; e: dry transfer top layer h-BN; f: vacuum annealing; g: dry etching; h: electron beam evaporation electrode.
  • Figure 2 The performance of anisotropic floating gate memory: a: the transfer characteristic curve of the device (the ordinate takes log); b: the switching response of the device under the time pulse.
  • Figure 3a The "on" state current and the “off” state current of the device change with time; b: the performance of the anisotropic floating gate memory of the present invention and the performance of other floating gate memory constructed based on two-dimensional materials.
  • Figure 4a A schematic diagram of an anisotropic floating gate memory using GaTe as the channel material; b, c: transfer characteristic curves of two pairs of electrodes in the vertical direction under the same compilation voltage; d, e: anisotropic floating gate memory Multi-value storage capacity.
  • EBL electron beam exposure
  • RIE reactive ion etching
  • the buried gate in step (1) is a metallic carbon nanotube (CNT) network.
  • the resulting floating gate memory can realize the capability of multi-value storage.
  • step (2) transfer the GaTe deposited by chemical weathering to PDMS, and then transfer GaTe on PDMS to the h-BN/FLG stacking structure
  • the resulting floating gate memory can realize the capability of multi-value storage.
  • the metal electrode material in step (5) is Ti/Au.
  • the resulting floating gate memory can realize the capability of multi-value storage.

Abstract

本发明的目的是提供一种可以实现浮栅存储器具有多值存储能力的方法，以及采用该方法设计的各向异性浮栅存储器，该方法以多层石墨烯为埋栅，以少数层二维层状半导体材料为沟道，以六方氮化硼为介电层和封装层，通过范德华堆垛技术以及微纳加工技术制备了具有沿GaTe不同晶向的电极的浮栅存储器，通过改变门电压的大小，对沟道材料GaTe的电学各向异性进行调控，实现了开关比大，数据保持时间长，且具有多值存储功能的浮栅存储器的目的。该方法工艺简单，能够获得性能优异，具有多值存储功能的浮栅存储器。

Description

一种具有多值存储能力的各向异性浮栅存储器 技术领域
本发明属于纳米人工复合物、微纳米器件、存储器等应用研究领域，具体提供一种具有多值存储能力的各向异性浮栅存储器。
背景技术
自20世纪40年代第一台计算机诞生以来，现代计算机系统的结构依然基于冯.诺依曼原理，即由存储器、运算器、控制器、输入设备和输出设备等五部分组成。存储器是计算机的记忆单元，用来存储各种程序和数据，是计算机中不可或缺的重要组成。非易失性存储器，简称NVM，是指存储器所存储的信息在电源关掉后依然能长时间保存，不易丢失。随着手机、数码相机等便携式电子设备的快速普及，半导体市场对NVM的需求变得越来越大。目前应用最成熟的NVM是以闪存(Flash)为主的浮栅存储器，它具有功耗小，存取速度快，成本低等优点。2012年，NAND型Flash已经发展到32nm/64Gbit技术。尽管闪存获得了巨大的成功并占据了存储器市场上最大的份额，闪存本身却面临着很多缺陷和难题，如：擦写速度慢(0.1ms)、擦写电压高(5V)等。而闪存更严重的瓶颈在于降尺度的极限：尺寸的不断减小导致单个存储单元内部存储的电子数目越来越少，而相邻存储单元由于相距越来越近发生电子遂穿的概率也越来越高，使得存储信息的可靠性降低。因此如何提高以Flash为代表的浮栅存储器的存储密度是目前亟待解决的问题。
一些晶体学对称性差的材料往往表现出方向依赖性的物理性能，如力学各向异性，光学各向异性，电学各向异性等。而材料在二维极限下，由于z轴维度的消失，这些各向异性往往更加明显，且蕴藏着丰富的物理内涵以及巨大的应用前景。近来，针对二维材料的电学各向异性得到了非常多的关注。如在黑 磷中，研究人员观察到其具有σ a/σ b≈1.5的面内电学各向异性。然而目前报道的电学各向异性相对较小，最大电流与最小电流的比值往往不超过10，这极大地限制了电学各向异性在实际中的应用。二维层状材料碲化镓(GaTe)是一种具有直接带隙(～1.7eV)的p-型半导体，具有优异的光电性能。它的晶体学对称性很低(C 3 2h空间群)，表现出明显的光学及电学各向异性。
发明内容
本发明的目的是提供一种可以实现浮栅存储器具有多值存储能力的方法，以及采用该方法设计的各向异性浮栅存储器，该方法操作简单、能够得到性能优异的具有多值存储能力的浮栅存储器。
本发明技术方案如下：
一种实现各向异性浮栅存储器具有多值存储能力的方法，其特征在于：利用二维层状半导体材料的电学各向异性及门可调性，实现具有多值存储能力的浮栅存储器。
基于上述方法，本发明还提供了一种具有多值存储能力的各向异性浮栅存储器，其特征在于：所述各向异性浮栅存储器是以二维层状金属材料作为埋栅，以二维层状半导体材料作为沟道材料，以绝缘体作为介电层及封装层。
作为优选的技术方案：
本发明所述二维层状半导体材料为具有电学各向异性(材料在不同晶体学取向上的阻值不同)，且电学各向异性的大小受门电压的调控作用的材料，优选为碲化镓(GaTe)；绝缘体为二维层状绝缘体材料，优选为六方氮化硼(h-BN)；二维层状金属材料优选为多层石墨烯(FLG)。
本发明所述二维层状半导体材料的厚度为1nm-30nm，可以通过力学解理单 晶块体或化学生长等方式制备。
本发明所述二维层状半导体材料通过下列方法获得：化学气象沉积(CVD)、力学剥离解理、溶液中超声剥离或化学剥离。
本发明所述浮栅存储器器件放置的基底为Si基底、石英基底、云母片或柔性基底。
本发明还提供了所述具有多值存储能力的各向异性浮栅存储器的制备方法，其特征在于：
将二维层状半导体材料、二维层状金属材料埋栅、介电层及封装层通过范德华堆垛的方式得到h-BN/GaTe/h-BN/FLG范德华异质结；利用电子束曝光(EBL)、反应离子刻蚀(RIE)、电子束蒸发(EBE)等技术，制备具有沿二维层状半导体材料不同晶向的电极的浮栅存储器。
本发明所述存储器可通过改变门电压的大小，实现对沟道材料电学各向异性的调控，通过一次操作电压写入，实现多阻值的读出。
本发明所述具有多值存储能力的各向异性浮栅存储器的制备方法，其特征在于：所述金属电极沿着二维层状半导体材料的某一晶向成对出现，不同对电极呈一定角度。所述金属电极所采用的金属为Cr、Ti、Au、Pd、Sc、Ni之一种或多种。
本发明利用二维层状材料碲化镓显著的电学各向异性，通过范德华堆垛技术以及微纳加工技术，以多层石墨烯(FLG)作为埋栅，少数层GaTe作为沟道材料，沿不同的晶向设计电极，得到了具有大的开关比(＞10 7)以及长的存储时间的浮栅存储器。此外，通过改变门电压的大小，实现了对GaTe电学各向异性的调控(最大电流与最小电流比(I y/I x)最高可达到～10 3量级)，进而使得该存储器仅通过一次操作电压的写入，即可以读出多个阻态，且不同阻态的差异非常 显著，不同阻值间的比值最大可达10 2。对于未来提高浮栅存储器的存储密度提供了一个新的思路，并为电学各向异性的应用提供了一个切实可行的方案。
本发明所述方法的优点在于：
1、利用门电压可以显著地对某些二维层状材料的电学各向异性进行调控；
2、能够制备出性能优异的浮栅存储器，其开关比大(＞10 7)、存储时间长；
3、能够制备出具有多值存储能力的浮栅存储器，从而提高存储器的存储密度。
附图说明
图1为具有多值存储能力的各向异性浮栅存储器的制备过程示意图：a：利用干法转印，将h-BN落在FLG上；b：真空退火；c-d：干法转印GaTe；e：干法转印顶层h-BN；f：真空退火；g：干法刻蚀；h：电子束蒸镀电极。
图2各向异性浮栅存储器的性能：a：器件的转移特性曲线(纵坐标取log)；b：时间脉冲下，器件的开关响应。
图3a：器件“开”态电流及“关”态电流随时间变化；b：本发明各向异性浮栅存储器的性能与其它基于二维材料构建的浮栅存储器的性能的比较。
图4a：以GaTe作为沟道材料的各向异性浮栅存储器的示意图；b、c：相同编译电压下，两对垂直方向的电极的转移特性曲线；d、e：各向异性浮栅存储器的多值存储能力。
具体实施方式
以下实施例将对本发明予以进一步的说明，但并不因此而限制本发明。
实施例1
(1)利用干法转移技术，使用粘性聚合物(PDMS/PPC双层结构)将六方 氮化硼(h-BN)转移至其粘性聚合物上面，然后将h-BN融留在一片多层石墨烯(FLG)上，并将所得堆垛结构的基片(SiO2/Si)置于真空退火炉中，进行真空退火，将堆垛结构上的残留聚合物全部挥发，得到干净的h-BN/FLG结构；
(2)使用scope隐形胶带对GaTe进行机械剥离，然后转移到PDMS上，然后再将PDMS上的GaTe转移到上述h-BN/FLG堆垛结构上，并保证GaTe处于FLG的正上方，以致底部FLG能够充分地调控GaTe，得到GaTe/h-BN/FLG结构；
(3)使用粘性聚合物(PDMS/PPC双层结构)将h-BN转移至其粘性聚合物上面，将PPC上的h-BN融留在上述GaTe/h-BN/FLG结构上，得到h-BN/GaTe/h-BN/FLG二维堆垛的异质结构，以上制备过程在手套箱中进行；
(4)利用电子束曝光(EBL)、反应离子刻蚀(RIE)等技术，对顶层h-BN进行图形化并刻蚀，使得GaTe部分漏出，且漏出部分沿GaTe的某一直边成对出现；
(5)利用电子束蒸发技术，蒸镀电极Cr/Au＝5/30nm，然后剥离得到器件；
(6)通过测量不同对电极的电学性能，可以看出器件沿不同的方向表现出不同的电学性能(如图4b，c)，且通过改变门电压的大小，这种电学各向异性的强度发生变化；
(7)对器件施加一个操作写入电压(0V到-20V再到0V)，此时器件处于“关”态，而当施加一个擦写电压(0V到20V再到0V)，不同对电极间GaTe的阻值明显不同(约有～10 2倍的差异，如图4d，e)。
实施例2
与实施例1的不同之处在于：步骤(1)所述埋栅为金属性碳纳米管(CNT) 网络。
所得浮栅存储器可实现多值存储的能力。
实施例3
与实施例1的不同之处在于：步骤(2)将化学气象沉积的GaTe转移到PDMS上，然后再将PDMS上的GaTe转移到h-BN/FLG堆垛结构上
所得浮栅存储器可实现多值存储的能力。
实施例4
与实施例1的不同之处在于：步骤(5)所述金属电极材料为：Ti/Au。
所得浮栅存储器可实现多值存储的能力。
上述实施例只为说明本发明的技术构思及特点，其目的在于让熟悉此项技术的人士能够了解本发明的内容并据以实施，并不能以此限制本发明的保护范围。凡根据本发明精神实质所作的等效变化或修饰，都应涵盖在本发明的保护范围之内。

Claims (10)

  1. 一种实现各向异性浮栅存储器具有多值存储能力的方法，其特征在于：利用二维层状半导体材料的电学各向异性及门可调性，实现具有多值存储能力的浮栅存储器。
  2. 一种具有多值存储能力的各向异性浮栅存储器，其特征在于：所述各向异性浮栅存储器是以二维层状金属材料作为埋栅，以二维层状半导体材料作为沟道材料，以绝缘体作为介电层及封装层。
  3. 按照权利要求2所述具有多值存储能力的各向异性浮栅存储器，其特征在于：所述二维层状半导体材料为具有电学各向异性，且电学各向异性的大小受门电压的调控作用的材料，绝缘体为二维层状绝缘体材料。
  4. 按照权利要求2或3所述具有多值存储能力的各向异性浮栅存储器，其特征在于：所述二维层状半导体材料的厚度为1nm-30nm。
  5. 按照权利要求2或3所述具有多值存储能力的各向异性浮栅存储器，其特征在于：所述二维层状半导体材料通过下列方法获得：化学气象沉积、力学剥离解理、溶液中超声剥离或化学剥离。
  6. 按照权利要求2或3所述具有多值存储能力的各向异性浮栅存储器，其特征在于：所述二维层状半导体材料为碲化镓，二维层状金属材料为多层石墨烯，绝缘体为六方氮化硼。
  7. 按照权利要求2或3所述具有多值存储能力的各向异性浮栅存储器，其特征在于：所述浮栅存储器器件放置的基底为Si基底、石英基底、云母片或柔性基底。
  8. 一种权利要求2所述具有多值存储能力的各向异性浮栅存储器的制备方法，其特征在于：
    将二维层状半导体材料、二维层状金属材料埋栅以及介电层通过范德华堆 垛的方式得到异质结；利用电子束曝光、反应离子刻蚀以及电子束蒸发技术制备金属电极。
  9. 按照权利要求8所述具有多值存储能力的各向异性浮栅存储器的制备方法，其特征在于：所述金属电极沿着二维层状半导体材料的某一晶向成对出现，不同对电极呈一定角度。
  10. 按照权利要求8或9所述具有多值存储能力的各向异性浮栅存储器的制备方法，其特征在于：所述金属电极所采用的金属为Cr、Ti、Au、Pd、Sc、Ni之一种或多种。
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