WO2020140250A1 - Appareil et procédé de surveillance de batterie de condensateurs - Google Patents

Appareil et procédé de surveillance de batterie de condensateurs Download PDF

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Publication number
WO2020140250A1
WO2020140250A1 PCT/CN2019/070340 CN2019070340W WO2020140250A1 WO 2020140250 A1 WO2020140250 A1 WO 2020140250A1 CN 2019070340 W CN2019070340 W CN 2019070340W WO 2020140250 A1 WO2020140250 A1 WO 2020140250A1
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Prior art keywords
current
capacitor
current signal
signals
signal
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PCT/CN2019/070340
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English (en)
Inventor
Minzhong YANG
Tianyu Liu
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Abb Schweiz Ag
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Priority to CN201980087859.1A priority Critical patent/CN113260869B/zh
Priority to PCT/CN2019/070340 priority patent/WO2020140250A1/fr
Publication of WO2020140250A1 publication Critical patent/WO2020140250A1/fr

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/01—Subjecting similar articles in turn to test, e.g. "go/no-go" tests in mass production; Testing objects at points as they pass through a testing station
    • G01R31/013—Testing passive components
    • G01R31/016—Testing of capacitors

Definitions

  • Embodiments of the present disclosure generally relate to an apparatus and a method for monitoring a capacitor bank.
  • Capacitor banks are widely used in a power system of HV substation for reactive power compensation, transmission line property compensation and harmonic controls.
  • the capacitor bank is normally composed of dozens or hundreds of capacitor modules.
  • the capacitor modules are arranged in parallel and/or serial connection with each other to obtain a required voltage and power rating.
  • Embodiments of the present disclosure are directed to an apparatus and a method for monitoring a capacitor bank, which improve the maintenance and the reliability of the capacitor bank.
  • embodiments of the present disclosure provide an apparatus for monitoring a basic capacitor parallel block, which includes several capacitor modules that are connected in parallel with each other.
  • the apparatus comprises: a plurality of current sensors electrically coupled to a plurality of capacitor modules in the basic capacitor parallel block, the current sensors being configured to sense currents flowing through the respective capacitor modules and to generate a plurality of current signals representing the currents; and a sensor module, comprising: a sensing circuit configured to receive the current signals from the current sensors and to generate a reference current signal representing one of the current signals and current differential signals representing differences between the one of the current signals and other ones of the current signals; and a processor configured to receive the reference current signal and the current differential signals from the sensing circuit.
  • the processor is further configured to calculate ratios of the current differential signals to the reference current signal and to detect a failure in the capacitor modules based on the ratios of the current differential signals to the reference current signal.
  • the apparatus according to embodiments of the present disclosure allows continuous monitoring of the working condition or performance of the capacitor modules, early detection of the degraded capacitor module, and quick identification of the degraded capacitor module from the capacitor bank, without much impact on the existing structure of the capacitor bank.
  • the processor is further configured to, for each of the ratios of the current differential signals to the reference current signal: compare the ratio with a threshold value; and in response to a determination that the ratio exceeds the threshold value, detect a failure occurring in the capacitor modules of the basic capacitor parallel block associated with the ratio.
  • the processor is further configured to, for each of the ratios of the current differential signals to the reference current signal: compare a variant of the ratio against time with a threshold value; and in response to a determination that the variant of the ratio against time exceeds the threshold value, detect a failure occurring in the capacitor modules of the basic capacitor parallel block associated with the variant of the ratio against time.
  • the basic capacitor parallel block comprises a first, a second and a third capacitor modules
  • the sensing circuit is further configured to:receive a first, a second and a third current signals representing the currents flowing through the first, second and third capacitor modules, respectively; generate the reference current signal representing the first current signal; generate a first current differential signal representing the difference between the first current signal and the second current signal; and generate a second current differential signal representing the difference between the first current signal and the third current signal.
  • the current sensors comprise a first plurality of current transformers.
  • Each of the first plurality of current transformers is installed at a bushing base of a corresponding one of the capacitor modules.
  • the sensing circuit comprises a second plurality of current transformers electrically coupled to the current sensors’output circuit and configured to generate the current differential signals and the reference current signal.
  • the sensing circuit comprises: a main circuit loop configured to electrically couple output terminals of the first plurality of current transformers in series; and a plurality of short-cut wires configured to electrically coupled with the main circuit loop to connect the output terminals of the respective current transformers of the first plurality of the current transformers except a reference current transformer of the first plurality of the current transformers, wherein the reference current transformer is configured to generate a first current signal representing the current flowing through a first capacitor module of the capacitor modules, wherein one of the second plurality of the current transformers is electrically coupled with the main circuit loop and is configured to sense the first current signal and to generate the reference current signal representing the first current signal, and wherein other ones of the second plurality of the current transformers are respectively electrically coupled with the plurality of short-cut wires and are configured to generate the current differential signals.
  • the sensor module further comprises an energy harvesting circuit configured to harvest energy from the sensing circuit via at least one further current transformer to power up the sensor module.
  • the sensor module further comprises a wireless communication circuit configured to communicate in a wireless manner.
  • embodiments of the present disclosure provide a system for monitoring a capacitor bank.
  • the system comprises a plurality of the apparatuses as described above, the capacitor bank comprises a plurality of the basic capacitor parallel blocks, and the plurality of the apparatuses are electrically coupled to the plurality of the basic capacitor parallel blocks, respectively.
  • system further comprises a host configured to communicate wirelessly with the plurality of the apparatus.
  • inventions of the present disclosure provide an Internet of Things (IoT) system.
  • the IoT system comprises the system described above.
  • embodiments of the present disclosure provide a method for monitoring a capacitor bank.
  • the method comprises: sensing currents flowing through respective ones of a plurality of capacitor modules, to generate current signals representing the currents, the capacitor modules (104) being connected in parallel with each other in each of a plurality of basic capacitor parallel blocks that are included in the capacitor bank; generating a reference current signal representing one of the current signals and current differential signals representing differences between the one of the current signals and other ones of the current signals; and detecting a failure in the capacitor modules (104) based on ratios of the current differential signals to the reference current signal.
  • detecting the failure comprises, for each of the ratios of the current differential signals to the reference current signal: comparing the ratio with a threshold value; and in response to a determination that the ratio exceeds the threshold value, detecting a failure occurring in the capacitor modules associated with the ratio.
  • detecting the failure comprises, for each of the ratios of the current differential signals to the reference current signal: comparing a variant of the ratio against time with a threshold value; and in response to a determination that the variant of the ratio against time exceeds the threshold value, detecting a failure occurring in the capacitor modules associated with the variant of the ratio against time.
  • the method further comprises: sensing a first, a second and a third current signals representing the currents flowing through a first, a second and a third capacitor modules, respectively, the first, second and third capacitor modules being included in the capacitor modules (104) ; generating the reference current signal representing the first current signal; generating a first current differential signal representing the difference between the first current signal and the second current signal; and generating a second current differential signal representing the difference between the first current signal and the third current signal.
  • the basic capacitor parallel block including one or more degraded capacitor modules may be quickly identified from the capacitor bank at early stage with a higher accuracy without much impact on the original structure of the capacitor bank.
  • Fig. 1 illustrates a diagram of monitoring a capacitor bank based on an unbalance current
  • Fig. 2 illustrates a diagram of a capacitor bank to be monitored according to an embodiment of the present disclosure
  • Fig. 3 illustrates a schematic diagram of an apparatus for monitoring a basic capacitor parallel block according to an embodiment of the present disclosure
  • Fig. 4 illustrates an exemplary diagram of an apparatus for monitoring a basic capacitor parallel block according to an embodiment of the present disclosure
  • Fig. 5 illustrates an equivalent circuit diagram of a basic capacitor parallel block according to an embodiment of the present disclosure
  • Fig. 6 illustrates a diagram of a system for monitoring a capacitor bank according to an embodiment of the present disclosure
  • Fig. 7 illustrates a schematic diagram of a system for monitoring a capacitor bank according to an embodiment of the present disclosure
  • Fig. 8 illustrates a schematic diagram of an Internet of Things system according to an embodiment of the present disclosure.
  • Fig. 9 illustrates a flow chart of a method for monitoring a capacitor bank.
  • the capacitor bank used in the HV substation generally is composed of dozens or hundreds of capacitor modules that are connected in parallel and/or serial connection with each other, the applied voltage and running current of each capacitor module depend on the overall voltage applied on the capacitor bank, the capacitance of each capacitor module and the connection topology of the whole capacitor banks.
  • the capacitance changes, not only the voltage and current applied to that capacitor module changes, but the applied voltage and currents of all other capacitor modules change accordingly, even though there is no performance degradation of other capacitor modules. So it is impossible to decide the failure of one capacitor module by measuring the current of the capacitor module alone.
  • Fig. 1 illustrates a diagram of monitoring a capacitor bank 10’based on an unbalance current.
  • a capacitor bank 10’ includes a plurality of capacitor modules 104’, which are connected in parallel and serial with each other.
  • the capacitor bank 10’ further includes a current transformer CT installed at an internal node of the capacitor bank 10’.
  • a current sensed by the current transformer CT is substantially zero.
  • the current sensed by the current transformer CT exceeds a threshold value.
  • the current is generally referred to as the unbalance current, and the failure is detected in the capacitor bank 10’and the capacitor bank 10’is cut off in response to a determination that the unbalance current exceeds the threshold value.
  • a monitoring solution for the capacitor bank includes sensing the currents flowing through the respective capacitor modules in the capacitor bank to generate current signals representing the currents, generating a reference current signal representing one of the current signals and current differential signals representing differences between the one of the current signals and other ones of the current signals, calculating ratios of the current differential signals to the reference current signal, and detecting the failure in the capacitor modules based on the ratios of current differential signals to the reference current signal.
  • the monitoring solution according to the embodiments of the present disclosure allows the detection of the failure occurring in the specific capacitor modules without much impact on existing structure of the capacitor bank.
  • Fig. 2 illustrates a diagram of a capacitor bank 10 to be monitored according to an embodiment of the present disclosure.
  • a capacitor bank 10 includes a plurality of capacitor modules 104, which are connected in parallel and serial with each other.
  • a basic capacitor parallel block of the capacitor banks several capacitor modules, e.g. two, or three or more are directly connected in parallel with each other, which may be collectively referred to as the basic parallel block 102 herein.
  • the basic parallel block 102a includes three capacitor modules 104 connected in parallel with each other, while the basic parallel block 102b includes two capacitor modules 104 connected in parallel with each other.
  • the basic parallel block includes other number of capacitor modules 104, for example, four capacitor modules connected in parallel with each other.
  • the capacitor bank 10 may include a plurality of the basic parallel blocks arranged in the different manner than that shown in Fig. 2.
  • a performance degrades or a failure occurs in the capacitor module 104
  • the failure occurs in few elements within the capacitor module, which could cause the capacitance change of the capacitor module 104 by several percentages.
  • a degree of such degradation is relatively small in the early stage.
  • the performance of capacitor module 104 will be gradually degraded, which will finally harm the safety and impact the operation of the capacitor module 104 and even the capacitor bank 10.
  • the monitoring solution according to the present disclosure is able to continuously monitor the working condition of the capacitor module 104 in which the performance degradation or failure occurs, thereby achieving early detection and quick identification of the degraded capacitor module 104 or the degraded basic parallel block 102.
  • Fig. 3 illustrates a schematic diagram of an apparatus 100 for monitoring capacitor modules 104 of one basic parallel block 102 according to an embodiment of the present disclosure.
  • the basic parallel block 102 includes a plurality of capacitor modules 104 connected in parallel with each other.
  • the apparatus 100 includes a plurality of current sensors 108 and a sensor module 106.
  • the current sensors 108 are electrically coupled to the plurality of capacitor modules 104, respectively.
  • the current sensors 108 is configured to sense currents flowing through the respective capacitor modules 104 and to generate a plurality of current signals representing the currents.
  • the current sensor 108 comprises a current transformer.
  • the current transformer has a standard output, e.g. 1A/5A.
  • the current transformer is installed at a bushing base of the capacitor modules 104. In this manner, the current sensor 108 may be at the same potential of the capacitor modules, and may measure the current without much impact on the existing structure of the capacitor module.
  • the sensor module 106 includes a sensing circuit 110 and a processor 112.
  • the sensing circuit 110 is electrically coupled to the current sensors 108.
  • the sensing circuit 110 is coupled to the current sensors 108 via any suitable connection ports or open interfaces.
  • the sensing circuit 110 is configured to receive the current signals from the current sensors 108 and to generate a reference current signal representing one of the current signals and current differential signals representing differences between the one of the current signals and other ones of the current signals.
  • the sensing circuit 110 receives a first, a second and a third current signals representing the current flowing through the respective ones of three capacitor modules 104, generates the reference current signal representing the first current signal, and generates a first current differential signal representing the difference between the first current signal and the second current signal, and a second current differential signal representing the difference between the first current signal and the third current signal.
  • the processor 112 is configured to receive the reference current signal and the current differential signals from the sensing circuit 110. In some embodiments, the processor 112 is configured to calculate ratios of the current differential signals to the reference current signal and to detect a failure in the capacitor modules 104 based on the ratios of the current differential signals to the reference current signal. In some embodiments, for each of the ratios of the current differential signals to the reference current signal, the processor 112 is further configured to compare the ratio with a first threshold value, and in response to a determination that the ratio exceeds the first threshold value, detect a failure occurring in the capacitor modules associated with the ratio.
  • the processor 112 is further configured to compare a variant of the ratio against time with a second threshold value, and in response to a determination that the variant of the ratio against time exceeds the second threshold value, detect a failure occurring in the capacitor modules associated with the variant of the ratio against time.
  • the change of the ratio against the time may be the latest calculated ratio against the initial value of the ratio when the system is in a normal condition.
  • the processor 112 receives the reference current signal, the first current differential signal and the second current differential signal, and detects a failure occurring in the respective ones of the three capacitor modules associated with a first ratio of the first current differential signal to the reference current signal and a second ratio of the second current differential signal to the reference current signal.
  • the solution for detecting the failure in the capacitor modules 104 will be described later in detail with reference to Figs. 4 and 5.
  • the sensor module 106 further includes an energy harvesting circuit 114, as shown in Fig. 3.
  • the energy harvesting circuit 114 is configured to harvest energy from the sensing circuit 110 to power up the sensor module 106.
  • the sensor module 106 further comprises a communication circuit 116 that is configured to communicate with external devices in a wireless or wired manner. With the energy harvesting and the wireless communication of the sensor module 106, the sensor module 106 is allowed to be installed at a high potential.
  • Fig. 4 illustrates an exemplary diagram of the apparatus 100 for monitoring the basic parallel block 102 according to an embodiment of the present disclosure.
  • the basic parallel block 102 includes three capacitor modules 104a, 104b, 104c, and the electrical connections among the three capacitor modules 104a, 104b, 104c are omitted.
  • the three capacitor modules 104a, 104b, 104c are connected in parallel with each other.
  • the capacitor modules 104a, 104b, 104c may be collectively referred to as the capacitor modules 104 herein.
  • the apparatus 100 includes the current transformers 402a, 402b, 402c as the current sensor, as shown in Fig. 4.
  • a first current transformer 402a, a second current transformer 402b, and a third current transformer 402c are electrically coupled to a first capacitor module 104a, a second capacitor module 104b, and a third capacitor module 104c, respectively.
  • the first current transformers 402a is configured to sense the current I1 flowing through the first capacitor module 104a, and to generate the first current signal I’ 1 representing the current I1.
  • the second current transformer 402b is configured to sense the current I2 flowing through the second capacitor module 104b, and to generate the second current signal I’ 2 representing the current I2.
  • the third current transformer 402c is configured to sense the current I3 flowing through the third capacitor module 104c, and to generate the third current signal I’ 3 representing the current I3.
  • the first current transformer 402a, the second current transformer 402b, and the third current transformer 402c may be collectively referred to as the current transformer 402 herein. It should be noted that, the apparatus 100 may utilize any suitable kinds of the current sensor to sense the currents flowing through the capacitor modules.
  • the sensing circuit 110 of the sensor module 106 includes a first node A, a second node B, a third node C, and a fourth node D.
  • the first node A is coupled to a second terminal of a secondary side of the first current transformer 402a, a first terminal of a secondary side of the second current transformer 402b, and the second node B.
  • the second node B is coupled to a second terminal of the secondary side of the second current transformer 402b, and the third node C.
  • the third node C is coupled to a first terminal of a secondary side of the third current transformer 402c, and the fourth node D.
  • the fourth node D is coupled to a first terminal of the secondary side of the first current transformer 402a and a second terminal of the secondary side of the third current transformer 402c.
  • the sensing circuit of the sensor module 106 includes a first secondary current transformer 404a, a second secondary current transformer 404b, and a third secondary current transformer 404c.
  • the first secondary current transformer 404a is coupled between the second terminal of the secondary side of the first current transformer 402a and the first node A.
  • the first secondary current transformer 404a is coupled between the second node B and the third node C.
  • the first secondary current transformer 404a is coupled between the first terminal of the secondary side of the first current transformer 402a and the fourth node D.
  • the second secondary current transformer 404b is coupled between the first node A and the second node B.
  • the third secondary current transformer 404c is coupled between the third node C and the fourth node D.
  • the first secondary current transformer 404a, the second secondary current transformer 404b, and the third secondary current transformer 404c may be collectively referred to as the secondary current transformer 404 herein.
  • the sensing circuit of the sensor module 106 may include any other types of the current sensors instead of the secondary current transformers 404.
  • the first, second, and third secondary current transformers 404a, 404b, 404c may be replaced by any other types of the current sensors.
  • all the outputs of the secondary side of the current transformers 402 are connected in series, with additional bypass loop for the current transformers except for the reference current transformer (e.g. the current transformer 402a) , providing the path for current differential between corresponding current transformers and the reference current transformer.
  • the first secondary cunent transformer 404a is coupled to a first terminal of the processor 112 to deliver the reference current signal I 1 representing a first current signal I’ 1 to the processor 112.
  • the second secondary current transformer 404b is coupled to a second terminal of the processor 112 to deliver a first current differential signal I 1 -I 2 representing the difference I’ ⁇ 2 between the first current signal I’ 1 and the second current signal I’ 2 to the processor 112.
  • the third secondary current transformer 404c is coupled to a third terminal of the processor 112 to deliver a second current differential signal I 1 -I 3 representing the difference I’ ⁇ 3 between the first current signal I’ 1 and the third current signal I’ 3 to the processor 112.
  • the processor 112 is configured to detect the failure occurring in the capacitor modules 104 based on the first ratio of the first current differential signal I 1 -I 2 to the reference current signal I 1 and the second ratio of the second current differential signal I 1 -I 3 to the reference current signal I 1 . The main principle of the failure detection will be described later in detail.
  • the sensing circuit 110 includes open interfaces configured to be electrically connected with the current sensors 108.
  • the sensing circuit 110 includes a main circuit loop configured to electrically couple output terminals of the current transformers 402 in series, and a plurality of short-cut wires configured to electrically coupled with the main circuit loop to connect the output terminals of the respective current transformers 402b, 402c except a reference current transformer 402a.
  • a first short-cut wire is configured to connect both output terminals of the second current transformer 402b at the first node A and the second node B
  • a second short-cut wire is configured to connect both output terminals of the third current transformer 402c at the third node C and the fourth node D.
  • the first short-cut wire is a line having two ends connected to the first node A and the second node B, respectively
  • the second short-cut wire is a line having two ends connected to the third node C and the fourth node D, respectively.
  • the first secondary current transformer 404a is electrically coupled with the main circuit loop and is configured to sense the first current signal I’ 1 and to generate the reference current signal I 1 representing the first current signal I’ 1
  • the second secondary current transformer 404b and the third secondary current transformer 404c are respectively electrically coupled with the first short-cut wire and the second short-cut wire, respectively, and are configured to generate the current differential signals I 1 -I 2 , I 1 -I 3 .
  • the secondary current transformers 404 are electrically coupled to the outputs of the secondary side of the current transformers 402, and then the sensor module 112 is electrically coupled to the outputs of the secondary side of the secondary current transformers 404.
  • the current transformers 402 can be installed at the capacitor modules 104 as the standard current transformer that has a generic output rating (5A/1A) and matches with parameters of the capacitor modules 104, without altering the main structure of the sensor module 106.
  • the current transformers 402 provide isolation for the sensor module 106.
  • the output currents of the current transformers 402 are of a limited range, thereby avoiding an overload risk to the secondary current transformers 404, simplifying a design of the sensor module 106 and limiting a total cost.
  • the secondary current transformers 404 are part of the sensor module 106 and may have different ratings to match the reference current signal and the current differential signals, thereby increasing accuracy of the measurements.
  • the secondary current transformers 404 is configured to sense the first current signal, the difference between the second current signal and the first current signal, and the difference between the third current signal and the first current signal, and to generate the reference current signal I 1 , the first differential current signal I 1 -I 2 , and the second current differential signal I 1 -I 3 .
  • the reference current signal I 1 has an order of magnitude much larger than that of the first differential current signal I 1 -I 2 and the second current differential signal I 1 -I 3 .
  • the current differential flowing in the short-cut wire is much smaller than the current signal in the main circuit loop, i.e., the current differential is normally less than 5%.
  • the first secondary current transformer 402a may have a different rating than the second and third secondary current transformers 402b, 402c, for example, the rating for the first secondary current transformer 402a may be 5A, while the rating for the second and third secondary current transformers 402b, 402c may be 0.5A.
  • the second secondary current transformer 402b and the third secondary current transformer 402c may have a lower rating, so that the secondary current transformers are more sensitive for 1-2 percentage variance, thereby improving the accuracy of the measurements for the first and second current differential signals, and improving the accuracy of the failure detection and reliability of the capacitor bank.
  • the configuration of the secondary current transformers 404 in the sensor module 106 facilitates mounting of the sensor module 106 and improves robustness of the sensor module 106.
  • the sensing circuit of the sensor module 106 includes a current transformer 406 that is electrically coupled to the main circuit loop. In some embodiments, the sensing circuit is electrically coupled to the outputs of the secondary side of the current transformers 402.
  • the energy harvesting circuit 114 is configured to harvest the energy from the current transformer 406 to power up the sensor module 106. It should be noted that, the number of the current transformers 406 may be any suitable number, as long as the energy harvesting circuit 114 is able to harvest the energy from the current transformers 402.
  • Fig. 5 illustrates an equivalent circuit diagram of a basic parallel block 102 according to an embodiment of the present disclosure.
  • the first capacitor module 104a, the second capacitor module 104b, and the third capacitor module 104c are connected in parallel with each other, and may be collectively referred to as the capacitor modules 104.
  • the current differential ratio of the capacitor modules i.e. the ratio of the current differential signal with respective to the current of one reference capacitor module, is relevant to only the difference of capacitances, which is independent from applied voltage. In the normal condition, the difference of capacitances between the capacitor modules is very small and within an acceptable range, so is the current differential ratio.
  • the current differential ratios of one basic parallel block shall be stable unless one or more capacitor modules are degraded, and even in this case, the current differential ratio is independent from the applied voltage.
  • the operating parameters can be expressed as:
  • C 1 , C 2 and C 3 denote capacitances of the first, second, third capacitor modules 104a, 104b, 104c, respectively
  • I 1 , I 2 and I 3 denote a first, a second and a third currents flowing through the first, second, third capacitor modules 104a, 104b, 104c, respectively
  • U denotes a voltage across the first, second, third capacitor modules 104a, 104b, 104c.
  • the output current signals I’ 1 , I’ 2 , I’ 3 of the current transformers configured to sense the capacitor modules are proportional to the currents I 1 , I 2 , I 3 , respectively, as below:
  • the difference I ⁇ 2 between the first current I 1 and the second current I 2 and the difference I ⁇ 3 between the first current I 1 and the third current I 3 can be expressed as:
  • the current running through each short-cut wire is the difference between the output current signal of corresponding current transformer and the current signal in the main circuit loop (i.e. represented by the reference current signal) , which can be expressed as:
  • I’ ⁇ 2 denotes the first current differential between the first current signal I’ 1 and the second current signal I’ 2
  • I’ ⁇ 3 denotes the second current differential between the first current signal I’ 1 and the third current signal I’ 3 .
  • the first ratio R 21 of the first current differential I’ ⁇ 2 to the first current signal I’ 1 and the second ratio R 31 of the second current differential I’ ⁇ 3 to the first current signal I’ 1 can be expressed as:
  • the first ratio R 21 and the second ratio R 31 are substantially zero, and thus the ratios of the first and second current differential signals (see Fig. 4) representing the first and second current differentials to the reference current signal representing the first current signal are substantially zero or less than a predefined threshold value, and/or the changes or variants of the ratios against time are substantially zero or less than a predefined threshold value.
  • the operating parameters can be expressed as:
  • ⁇ C 1 denotes a change value of the capacitance of the first capacitor module 104a
  • U′de denotes the voltage across the first, second, and third capacitor modules 104a, 104b, 104c after the failure
  • I 1 ′, I 2 ′and I 3 ′de denote the currents flowing through the first, second, and third capacitor modules 104a, 104b, 104c after the failure.
  • the first ratio R 21 ′and the second ratio R 31 ′after the failure occurs in the first capacitor module 104a can be expressed as:
  • the change values of the first ratio R 21 ′and the second ratio R 31 ′after the failure occurs in the first capacitor module 104a can be expressed as:
  • both the change values ⁇ R 21 and ⁇ R 31 are not zero and exceed a threshold value. Therefore, both the ratios of the first and second current differential signals representing the first and second current differentials to the reference current signal representing the first current signal after the failure occurs in the first capacitor module 104a exceed a predefined threshold value, and/or the changes or variants of the ratios against time exceed a predefined threshold value.
  • the operating parameters can be expressed as:
  • ⁇ C 2 denotes a change value of the capacitance of the second capacitor module 104b
  • the first ratio R 21 ′and the second ratio R 31 ′after the failure occurs in the second capacitor module 104b can be expressed as:
  • the change values of the first ratio R 21 ′and the second ratio R 31 ′after the failure occurs in the second capacitor module 104b can be expressed as:
  • the change value ⁇ R 21 is not substantially zero and exceeds a threshold value, while the change value ⁇ R 31 is substantially zero. Therefore, the first ratio of the first current differential signal representing the first current differential to the reference current signal representing the first current signal after the failure occurs in the second capacitor module 104b exceeds a predefined threshold value, while the second ratio of the second current differential signal representing the second current differential to the reference current signal representing the first current signal after the failure occurs in the second capacitor module 104b is less than the predefined threshold value, and/or the change or variant of the first ratio against time exceeds a predefined threshold value, and the change or variant of the second ratio against time is substantially zero or less than a predefined threshold value.
  • the first ratio of the first current differential signal representing the first current differential to the reference current signal representing the first current signal is less than a predefined threshold value
  • the second ratio of the second current differential signal representing the second current differential to the reference current signal representing the first current signal exceeds the predefined threshold value
  • the change or variant of the first ratio against time is substantially zero or less than a predefined threshold value
  • the change or variant of the second ratio against time exceeds a predefined threshold value.
  • the failure is determined to occur in the associated capacitor modules.
  • the predefined threshold value may be less than 5%.
  • the processor receives the reference current signal I 1 , the first current differential signal I 1 -I 2 , and the second current differential signal I 1 -I 3 from the first, second and third secondary current transformers 404a, 404b, 404c, respectively.
  • the processor 112 is configured to detect the failure occurring in one or more of the first, second and third capacitor modules 104a, 104b, 104c in response to a determination that the first ratio of the first current differential signal I 1 -I 2 to the reference current signal I 1 and/or the second ratio of the second current differential signal I 1 -I 3 to the reference current signal I 1 exceed the threshold value.
  • the processor 112 is configured to detect the failure occurring in one or more of the first, second and third capacitor modules 104a, 104b, 104c in response to a determination that the change of the first ratio against time and/or the change of the second ratio against time exceed the predefined threshold value, e.g. the latest calculated ratio against initial value when the system is in normal condition exceeds the predefined threshold value e.g., 5%, i.e. or ⁇ R>5%.
  • the basic parallel block 102 that includes one or more degraded capacitor modules is detected by the sensor module 106, and the basic parallel block that needs to be replaced by a new parallel block is identified from the capacitor bank.
  • the processor 112 is configured to detect the failure occurring in the capacitor modules 104 associated with the ratios determined to exceed the threshold value. In some embodiments, on the basis of the main principle of the failure detection as described above, the processor 112 may be configured to detect the failure occurring in the first capacitor module 104a in response to a determination that both the changes of the first ratio of the first current differential signal I 1 -I 2 to the reference current signal I 1 and the second ratio of the second current differential signal I 1 -I 3 to the reference current signal I 1 exceed a threshold value, and optionally have the same trend.
  • the processor 112 may be configured to detect the failure occurring in all the first capacitor module 104a, the second capacitor module 104b and the third capacitor module 104c in response to a determination that both the changes of the first ratio and the second ratio exceed a threshold value. In some embodiments, the processor 112 may be further configured to detect the failure occurring in the second capacitor module 104b in response to a determination that the change of the first ratio of the first current differential signal I 1 -I 2 to the reference current signal I 1 exceeds the threshold value while the change of the second ratio of the second current differential signal I 1 -I 3 to the reference current signal I 1 is less than the threshold value.
  • the processor 112 may be further configured to detect the failure occurring in the third capacitor module 104c in response to a determination that the change of the second ratio of the second current differential signal I 1 -I 3 to the reference current signal I 1 exceeds the threshold value while the change of the first ratio of the first current differential signal I 1 -I 2 to the reference current signal I 1 is less that the threshold value.
  • the basic parallel block 102 includes the three capacitor modules 104 is described with reference to Figs. 4 and 5, the present disclosure is not limited to this embodiment.
  • the basic parallel block includes any suitable number of the capacitor modules, e.g. two or four.
  • the current differential signal I 1 -I 2 representing the difference between the first current signal and the second current signal is delivered to the processor 112, and the processor 112 is configured to detect the failure occurring in the first capacitor module or the second capacitor module in response to a determination that the ratio of the current differential signal I 1 -I 2 to the reference current signal I 1 exceeds a threshold value, and/or a determination that the change of the ratio against time exceeds a predefined threshold value.
  • the basic parallel block includes four capacitor modules
  • there is one additional short-cut wire for a fourth current transformer providing the path for current differential between the fourth current transformer and the first current transformer, e.g., there are two additional nodes that are short connected as the first node A and the second node B, or the third node C and the fourth node D.
  • the current differential signals I 1 -I 2 , I 1 -I 3 , I 1 -I 4 represent the differences between the first current signal and other ones of the second current signal, the third current signal and a fourth current signal representing the current flowing through a fourth capacitor module, and are delivered to the processor 112.
  • the processor 112 is configured to detect the failure occurring in one or more of the first through fourth capacitor modules in response to a determination that one or more of the ratios of the current differential signals to the reference current signal exceed a threshold value, and/or a determination that the change of the ratio against time exceeds a predefined threshold value.
  • the failure detection on the individual capacitor module is more complex, and the degraded individual capacitor module may not be identified simply based on the single comparison of the ratio with the threshold value.
  • the basic capacitor parallel block including the degraded capacitor (s) can be identified from the capacitor bank based on the ratios of the current differential signals to the reference current signal. When the ratios are determined to exceed the threshold value, one or more candidates of the capacitor modules in the basic capacitor parallel block associated with the ratios are determined to be degraded.
  • the basic capacitor parallel block including the degraded capacitor module (s) is identified from the capacitor bank, and there is need for replacing only the basic capacitor parallel block, i.e., only several capacitor modules in the basic capacitor parallel block, regardless of normal capacitor module (s) in the determined basic capacitor parallel block.
  • the number of the capacitor modules in the basic capacitor parallel block is relatively small, so identifying the degraded capacitor module (s) is much easier and more effective than the prior art in which it is time and resource consuming effort to identify the degrade module (s) from the dozens or hundreds modules of the whole capacitor bank. Therefore, in some embodiments, the failure detection on the basic capacitor parallel block including the degraded capacitor modules (s) based on the ratios is concerned, and the failure detection on the individual capacitor module is not concerned.
  • the basic capacitor parallel block including one or more degraded capacitor modules can be identified from the capacitor bank.
  • the working condition or performance of the capacitor modules in the basic capacitor parallel block can be continuously monitored, and the degraded capacitor modules can be detected at early stage and identified quickly from the capacitor bank.
  • the degraded capacitor module (s) can be identified and replaced quickly from the impacted basic capacitor parallel block other than from the entire capacitor bank in the power system, which facilitates the maintenance for the capacitor bank and improves the reliability of the capacitor bank.
  • Fig. 6 illustrates a diagram of a system for monitoring the capacitor bank 10 according to an embodiment of the present disclosure.
  • the sensor module 106x1 is provided for the basic parallel block 102x1 in the capacitor bank 10, and receives the current signals from three current sensors 108, each of which is electrically coupled to the corresponding one of three capacitor modules 104 included in the basic parallel block 102x1.
  • the sensor module 106x2 is provided for the basic parallel block 102x2, and receives the current signals from two current sensors 108, each of which is electrically coupled to the corresponding one of two capacitor modules 104 included in the basic parallel block 102x2.
  • the sensor modules 106x1 and 106x2 are configured to detect the failure in the capacitor modules of the basic parallel blocks 102x1 and 102x2 based on the ratios of the current differential signals representing the differences between one of the current signals and other ones of the current signals to the reference current signal representing the one of the current signals. It should be noted that, other sensor modules may be provided for the respective basic parallel blocks to detect the failure in the basic parallel blocks in the similar manner.
  • Fig. 7 illustrates a schematic diagram of a system 700 for monitoring the capacitor bank 10 according to an embodiment of the present disclosure.
  • the capacitor bank 10 includes a plurality of the basic parallel blocks 102x1, 102x2, ..., 102xn, which may be collectively referred to as a plurality of the basic parallel blocks 102 herein.
  • the basic parallel blocks 102 are connected in parallel and/or serial with each other, and each of the basic parallel blocks 102 is similar to the basic parallel block 102 as described with reference to Fig. 3.
  • the system 700 includes the apparatuses 100x1, 100x2, ..., 100xn, which may be collectively referred to as a plurality of the apparatuses 100 herein, and each of which is similar to the apparatus 100 as described with reference to Fig. 3.
  • the apparatuses 100 are electrically coupled to the basic parallel blocks 102, respectively, in order to monitor the capacitor bank 10 by detecting the failure in the capacitor modules of the basic parallel blocks 102 based on the ratios of the current differential signals to the reference current signal as described above.
  • the system 700 further includes a host 702 that is configured to communicate wirelessly with the plurality of the apparatuses 100.
  • the host 702 is configured to collect and store the current differential signals for the capacitor bank 10, and to monitor the working condition of each basic parallel block 102. In this way, the system 700 is allowed to detect the failure occurring in the capacitor modules of the basic parallel blocks, to identify the degraded capacitor module from the basic parallel block, and to identify the degraded basic parallel block from the capacitor bank.
  • the host 702 includes a signal processing unit that processes, analyzes and interprets the signal, tracking the variance of the signal over time, and detects and identifies the degrade basic parallel blocks.
  • Fig. 8 illustrates a schematic diagram of an Internet of Things (IoT) system 800 according to an embodiment of the present disclosure.
  • the IoT system 800 includes the system 700 described in above embodiments.
  • the system 700 is connected to a control system 802 of the IoT system 800 via a wired or wireless communication.
  • more than one system 700 may be included in the IoT system 800 and connected to the control system 802.
  • more than one capacitor bank 10 may be included in the IoT system 800 and connected to the control system 802 via a wired or wireless communication.
  • the capacitor bank 10 may be not connected to the control system 802.
  • control system 802 may be configured to monitor the operating parameters of the capacitor bank 10 sensed by the system 700. In some embodiments, the control system 802 may be further configured to control operations of the system 700, and/or operations of the capacitor bank 10.
  • Fig. 9 illustrates a flow chart 900 of a method for monitoring the capacitor bank 10.
  • the method includes sensing currents flowing through respective ones of a plurality of the capacitor modules 104, to generate current signals representing the currents, the capacitor modules 104 are connected in parallel with each other in each of a plurality of the basic parallel blocks 102 that are included in the capacitor bank 10.
  • the method further includes generating a reference current signal representing one of the current signals and current differential signals representing differences between the one of the current signals and other ones of the current signals.
  • the method further includes detecting a failure in the capacitor modules 104 based on ratios of the current differential signals to the reference current signal.
  • detecting the failure comprises comparing the ratio with a threshold value, and detecting a failure occurring in the capacitor modules associated with the ratio in response to a determination that the ratio exceeds the threshold value.
  • detecting the failure comprises comparing a variant of the ratio against time with a predefined threshold value, and detecting a failure occurring in the capacitor modules associated with the variant of the ratio against time in response to a determination that the variant of the ratio against time exceeds the predefined threshold value.
  • the method further comprises: sensing a first, a second and a third current signals representing the currents flowing through a first, a second and a third capacitor modules, respectively, the first, second and third capacitor modules being included in the capacitor modules 104; generating the reference current signal representing the first current signal; generating a first current differential signal representing the difference between the first current signal and the second current signal; and generating a second current differential signal representing the difference between the first current signal and the third current signal.
  • the method for monitoring the capacitor bank allows continuous monitoring of the working condition or performance of the capacitor modules in the basic capacitor parallel block, early detection of the degraded capacitor modules in the basic capacitor parallel block and quick identification of the degraded basic capacitor parallel blocks from the capacitor bank.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
  • Measurement Of Current Or Voltage (AREA)

Abstract

L'invention concerne un appareil et un procédé de surveillance d'une batterie de condensateurs. Un appareil (100) permettant de surveiller un bloc parallèle de condensateur de base (102) comprenant : une pluralité de capteurs de courant (108) couplés électriquement à une pluralité de modules de condensateur (104), respectivement, les modules de condensateur (104) étant connectés en parallèle les uns avec les autres dans le bloc parallèle de condensateur de base (102), les capteurs de courant (108) étant conçus pour détecter des courants circulant à travers les modules de condensateur respectifs (104) et pour générer une pluralité de signaux de courant représentant les courants ; et un module de capteur (106) comprenant : un circuit de détection (110) conçu pour recevoir les signaux de courant provenant des capteurs de courant (108) et pour générer un signal de courant de référence représentant soit les signaux de courant, soit des signaux différentiels de courant représentant des différences entre l'un des signaux de courant et d'autres signaux de courant ; et un processeur (112) conçu pour recevoir le signal de courant de référence et les signaux différentiels de courant provenant du circuit de détection (110).
PCT/CN2019/070340 2019-01-04 2019-01-04 Appareil et procédé de surveillance de batterie de condensateurs WO2020140250A1 (fr)

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PCT/CN2019/070340 WO2020140250A1 (fr) 2019-01-04 2019-01-04 Appareil et procédé de surveillance de batterie de condensateurs

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