WO2020139077A1 - Method of forming graphene bump structure - Google Patents

Method of forming graphene bump structure Download PDF

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Publication number
WO2020139077A1
WO2020139077A1 PCT/MY2019/050132 MY2019050132W WO2020139077A1 WO 2020139077 A1 WO2020139077 A1 WO 2020139077A1 MY 2019050132 W MY2019050132 W MY 2019050132W WO 2020139077 A1 WO2020139077 A1 WO 2020139077A1
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Prior art keywords
substrate
graphene
layer
metal catalyst
catalyst layer
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French (fr)
Inventor
Hing Wah Lee
Mai Woon LEE
Muhammad Aniq Shazni BIN MOHAMMAD HANIFF
Nurhidaya BINTI SORIADI
Abdul Halim BIN ADOM
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Mimos Bhd
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Mimos Bhd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2924—Structures
    • H10P14/2925—Surface structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/881—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being a two-dimensional material
    • H10D62/882—Graphene
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
    • H10P14/3202—Materials thereof
    • H10P14/3238—Materials thereof being insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
    • H10P14/3202—Materials thereof
    • H10P14/3241—Materials thereof being conductive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
    • H10P14/3242—Structure
    • H10P14/3244—Layer structure
    • H10P14/3248—Layer structure consisting of two layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
    • H10P14/3406—Carbon, e.g. diamond-like carbon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/36—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by treatments done before the formation of the materials

Definitions

  • This invention relates to graphene nanostructures.
  • Graphene is a carbon based material consisting of a single layer of carbon atom arranged in a hexagonal lattice. Graphene draws as an important attention nowadays as a next-generation material for electronic devices due to its high mobility at a room temperature. The graphene also exists as a continuous sheet in nature for applications in electronics, sensor and electronic packaging.
  • Graphene in three dimensional (3D) structure growing rapidly in electronic industries as it can offer high electrical conductivity and improved structural stability.
  • the three dimensional (3D) graphene-based structures such as 3D graphene-based hydrogels, aerogels, foams, and sponges have attracted huge attention owing to the combination of the structural interconnectivities and the outstanding properties of graphene which offer these interesting structures with low density, high porosity, large surface area, stable mechanical properties, fast mass and electron transport.
  • 3D graphene structure for applications in the electronics parts.
  • the graphene itself is unable to be grown directly on patterned polymer substrate due to high temperature growth process. Different structures/ pattern of the graphene also cannot be transferred at exact and precise location on the polymer substrate.
  • the current method of forming the graphene electrode on flexible substrate includes printing and roll to roll technology which is not capable to form 3D monolayer graphene structures.
  • US patent application no. 2012/0248401 A1 relates to a three dimensional graphene structure and method of manufacturing and transferring the same. The method includes forming at least one layer of graphene having a periodically repeated in three-dimensional shape.
  • the three-dimensional graphene structure is formed by forming a pattern having a three dimensional shape on a surface of a substrate.
  • a graphene is grown on the substrate on which the pattern is formed.
  • the 3D structure is then transferred by injecting a gas between the three- dimensional graphene structure and the substrate.
  • the step further separating the three-dimensional graphene structure from the substrate by bonding the three- dimensional graphene structure to an adhesive support, combining the three- dimensional graphene structure with an insulating substrate, and removing the adhesive support.
  • Another US patent no. 8,66,593 B2 disclose a method for fabricating a three dimensional graphene structure using a catalyst template, in which the three dimensional graphene structure in various forms can be obtained through a simple process by using a metal catalyst in various forms as a template and growing graphene thereon. There also provided a method for controlling length of the three dimensional graphene structure from a few nanometers to a few millimeters by controlling length of the metal catalyst template.
  • the present invention provides a method of forming graphene bump structure is characterized by the steps of providing a substrate; etching the substrate to form a cavity structure; growing a silicon dioxide layer on top of the substrate; depositing a thin metal catalyst layer on top of the silicon substrate; synthesizing graphene layer on top of the metal catalyst layer; depositing an epoxy-based photoresist; and removing the thin metal catalyst layer, the silicon dioxide layer and the epoxy-based photoresist layer from the substrate.
  • the method further comprising a step of patterning the epoxy-based photoresist to remove from the cavity structure.
  • the substrate is selected from a group of silicon dioxide.
  • the substrate is etched with a combination of sulphur hexafluoride (SF6) and octaflourocyclobutane (C4F8) plasma.
  • SF6 sulphur hexafluoride
  • C4F8 octaflourocyclobutane
  • the depth of the cavity structure is between 500nm - 1500nm.
  • the silicon dioxide layer is grown by wet or dry oxidation process.
  • the thin metal catalyst layer is deposited by physical vapour deposition method.
  • thickness of the metal catalyst layer is not more than half of the depth of the cavity structure.
  • the graphene layer is synthesized by chemical vapour deposition method.
  • the thin metal catalyst layer and the silicon dioxide layer are removed from the substrate by wet etching process.
  • Figure 1 (a-g) is a cross-sectional view illustrating a method of forming graphene bump structure according to one embodiment of the present invention.
  • Figure 2 is a flow chart showing a method of forming graphene bump structure according to one embodiment of the present invention.
  • the word “may” is used in a permissive sense (i.e. , meaning having the potential to), rather than the mandatory sense (i.e. , meaning must).
  • the words “include,” “including,” and “includes” mean including, but not limited to.
  • the words “a” or “an” mean “at least one” and the word “plurality” means one or more, unless otherwise mentioned. Where the abbreviations of technical terms are used, these indicate the commonly accepted meanings as known in the technical field. For ease of reference, common reference numerals will be used throughout the figures when referring to the same or similar features common to the figures.
  • the present invention relates to a method (200) of forming graphene bump structure (100) in accordance to an embodiment of the present invention.
  • the method of forming the graphene bump structure (100) of the present invention may exempts a need for the graphene or metal etching process through self- assembled of the graphene bump, introducing permanent epoxy based photoresist as a flexible substrate and removing a metal catalyst and dioxide layer.
  • the method (200) of forming the graphene bump structure will now be described with reference to Figure 1 and 2.
  • Figure 1 (a-g) the figures show a cross sectional view of the method (200) of forming the graphene bump structure step by step respectively. Further description on the process of forming the graphene bump structure process will be described further in Figure 2.
  • the method of forming the graphene bump structure comprising a step of providing (210) a substrate (10) layer.
  • the substrate layer preferably selected from a group of silicon dioxide.
  • the substrate is then etched (220) to form a cavity structure (20) on the substrate (10), whereby the etched is performed by combining the substrate with sulphur hexafluoride (SF6) and octaflourocyclobutane (C4F8) plasma.
  • the depth of the cavity structure (20) is between 500nm - 1500nm as illustrated as in figure 1 a.
  • a silicon dioxide layer (30) as illustrated in figure 1 b is grown (230) on top of the substrate (10), whereby the silicon dioxide layer is thermally grown by wet or dry oxidation process.
  • the thickness of the dioxide layer is preferably less than 100nm to form a uniform thickness.
  • the process then further continue by depositing (240) a thin metal catalyst layer (40) on top of the silicon dioxide substrate (30) as illustrated as in figure 1 c, whereby the metal catalyst layer is deposited onto the substrate by physical vapour deposition method such as radio frequency, RF sputtering method.
  • Material of the metal catalyst layer is preferably but not limited to copper, nickel, platinum, ruthenium and iridium.
  • the thickness of metal catalyst layer is preferably within range of 200nm to 1000nm.
  • the oxidation layer formed earlier in step (240) acts as an isolation layer between the metal catalyst layer and the substrate.
  • the substrate then undergoes a chemical vapour deposition process, whereby a graphene (50) is synthesized (250) on top of the metal catalyst layer (40). Illustration of this step shown as in figure 1 d.
  • the synthesized of the graphene (50) will self-assemble to the metal catalyst layer (40), hence forming a graphene bump structure extending outwards of the substrate (10) or inwards to the substrate (10).
  • a thick layer of epoxy-based photoresist (60) will then be deposited (260) onto the graphene layer (50), whereby the epoxy-based photoresist is preferably SU-8 material with thickness range is between 50pm to 100pm.
  • the epoxy-based photoresist is preferably SU-8 material with thickness range is between 50pm to 100pm.
  • An illustration of this step is shown as in figure 1 e
  • the method of forming the graphene bump structure comprises the steps of patterning (280) the epoxy-based photoresist (60) in the cavity structure in order to remove a remaining photoresist from the cavity (20) structure. The aforementioned step illustrated as in figure 1f and 1 g.

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Abstract

The present invention relates to a method (200) of forming graphene bump structure (100) comprising the steps of providing (210) a substrate (10); etching (220) the substrate (10) to form a cavity structure (20); growing (230) a silicon dioxide layer (30) on top of the substrate (10); depositing (240) a thin metal catalyst layer (40) on top of the substrate (30); synthesizing (250) graphene layer (50) on top of the metal catalyst layer (40); depositing (260) an epoxy-based photoresist (60); removing (270) the thin metal catalyst layer (40), the silicon dioxide layer (30) and the epoxy-based photoresist (60) from the substrate (10); and patterning (280) the epoxy-based photoresist (60) to remove from the cavity structure (20) to form the graphene bump structure (100).

Description

METHOD OF FORMING GRAPHENE BUMP STRUCTURE
FIELD OF THE INVENTION
This invention relates to graphene nanostructures. In particular relates to a method of forming graphene bump structure in three dimensional format.
BACKGROUND OF THE INVENTION
Graphene is a carbon based material consisting of a single layer of carbon atom arranged in a hexagonal lattice. Graphene draws as an important attention nowadays as a next-generation material for electronic devices due to its high mobility at a room temperature. The graphene also exists as a continuous sheet in nature for applications in electronics, sensor and electronic packaging.
Graphene in three dimensional (3D) structure growing rapidly in electronic industries as it can offer high electrical conductivity and improved structural stability. The three dimensional (3D) graphene-based structures such as 3D graphene-based hydrogels, aerogels, foams, and sponges have attracted huge attention owing to the combination of the structural interconnectivities and the outstanding properties of graphene which offer these interesting structures with low density, high porosity, large surface area, stable mechanical properties, fast mass and electron transport. However, there are several challenges in forming the 3D graphene structure for applications in the electronics parts.
One of the challenge is the graphene itself is unable to be grown directly on patterned polymer substrate due to high temperature growth process. Different structures/ pattern of the graphene also cannot be transferred at exact and precise location on the polymer substrate. Other than that, the current method of forming the graphene electrode on flexible substrate includes printing and roll to roll technology which is not capable to form 3D monolayer graphene structures. US patent application no. 2012/0248401 A1 relates to a three dimensional graphene structure and method of manufacturing and transferring the same. The method includes forming at least one layer of graphene having a periodically repeated in three-dimensional shape. The three-dimensional graphene structure is formed by forming a pattern having a three dimensional shape on a surface of a substrate. A graphene is grown on the substrate on which the pattern is formed. The 3D structure is then transferred by injecting a gas between the three- dimensional graphene structure and the substrate. The step further separating the three-dimensional graphene structure from the substrate by bonding the three- dimensional graphene structure to an adhesive support, combining the three- dimensional graphene structure with an insulating substrate, and removing the adhesive support.
Another US patent no. 8,66,593 B2 disclose a method for fabricating a three dimensional graphene structure using a catalyst template, in which the three dimensional graphene structure in various forms can be obtained through a simple process by using a metal catalyst in various forms as a template and growing graphene thereon. There also provided a method for controlling length of the three dimensional graphene structure from a few nanometers to a few millimeters by controlling length of the metal catalyst template.
Accordingly, it can be seen in the prior arts that there exists a need to provide a method of forming the graphene bump structure in 3D format for applications in electronics, sensors and electronic packaging.
SUMMARY OF INVENTION
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. Its sole purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later. It is an objective of the present invention to provide a method of forming graphene bump structure in three dimensional monolayer structure.
It is also an objective of the present invention to provide a method of forming the graphene bump structure without a need for graphene or metal etching patterning process for applications in electronics preferably for sensors and electronic packaging.
Accordingly, the present invention provides a method of forming graphene bump structure is characterized by the steps of providing a substrate; etching the substrate to form a cavity structure; growing a silicon dioxide layer on top of the substrate; depositing a thin metal catalyst layer on top of the silicon substrate; synthesizing graphene layer on top of the metal catalyst layer; depositing an epoxy-based photoresist; and removing the thin metal catalyst layer, the silicon dioxide layer and the epoxy-based photoresist layer from the substrate.
In another aspect of the present invention, the method further comprising a step of patterning the epoxy-based photoresist to remove from the cavity structure.
Preferably, the substrate is selected from a group of silicon dioxide.
In another aspect of the present invention, the substrate is etched with a combination of sulphur hexafluoride (SF6) and octaflourocyclobutane (C4F8) plasma.
Preferably, the depth of the cavity structure is between 500nm - 1500nm.
In another aspect of the present invention, the silicon dioxide layer is grown by wet or dry oxidation process.
In another aspect of the present invention, the thin metal catalyst layer is deposited by physical vapour deposition method. Preferably, thickness of the metal catalyst layer is not more than half of the depth of the cavity structure.
In another aspect of the present invention, the graphene layer is synthesized by chemical vapour deposition method.
In another aspect of the present invention, the thin metal catalyst layer and the silicon dioxide layer are removed from the substrate by wet etching process.
The present invention consists of features and a combination of parts hereinafter fully described and illustrated in the accompanying drawings, and it is being understood that various changes in the details may be made without departing from the scope of the invention or scarifying any of the advantages of the present invention.
BRIEF DESCRIPTION OF THE DRAWINGS
The features of the invention will be more readily understood and appreciated from the following detailed description when read in conjunction with the accompanying drawings of the preferred embodiment of the present invention, in which:
Figure 1 (a-g) is a cross-sectional view illustrating a method of forming graphene bump structure according to one embodiment of the present invention.
Figure 2 is a flow chart showing a method of forming graphene bump structure according to one embodiment of the present invention.
DETAILED DESCRIPTION OF THE INVENTION
As required, detailed embodiments of the present invention are disclosed herein; however, it is to be understood that the disclosed embodiments are merely exemplary of the invention, which may be embodied in various forms. Therefore, specific structural and functional details disclosed herein are not to be interpreted as limiting but merely as a basis for claims.
As used throughout this application, the word "may" is used in a permissive sense (i.e. , meaning having the potential to), rather than the mandatory sense (i.e. , meaning must). Similarly, the words "include," "including," and "includes" mean including, but not limited to. Further, the words "a" or "an" mean "at least one” and the word "plurality" means one or more, unless otherwise mentioned. Where the abbreviations of technical terms are used, these indicate the commonly accepted meanings as known in the technical field. For ease of reference, common reference numerals will be used throughout the figures when referring to the same or similar features common to the figures.
The present invention relates to a method (200) of forming graphene bump structure (100) in accordance to an embodiment of the present invention. The method of forming the graphene bump structure (100) of the present invention may exempts a need for the graphene or metal etching process through self- assembled of the graphene bump, introducing permanent epoxy based photoresist as a flexible substrate and removing a metal catalyst and dioxide layer.
In an embodiment of the present invention, the method (200) of forming the graphene bump structure will now be described with reference to Figure 1 and 2. Referring to Figure 1 (a-g), the figures show a cross sectional view of the method (200) of forming the graphene bump structure step by step respectively. Further description on the process of forming the graphene bump structure process will be described further in Figure 2.
In Figure 2, the method of forming the graphene bump structure comprising a step of providing (210) a substrate (10) layer. The substrate layer preferably selected from a group of silicon dioxide. The substrate is then etched (220) to form a cavity structure (20) on the substrate (10), whereby the etched is performed by combining the substrate with sulphur hexafluoride (SF6) and octaflourocyclobutane (C4F8) plasma. The depth of the cavity structure (20) is between 500nm - 1500nm as illustrated as in figure 1 a.
A silicon dioxide layer (30) as illustrated in figure 1 b is grown (230) on top of the substrate (10), whereby the silicon dioxide layer is thermally grown by wet or dry oxidation process. The thickness of the dioxide layer is preferably less than 100nm to form a uniform thickness. The process then further continue by depositing (240) a thin metal catalyst layer (40) on top of the silicon dioxide substrate (30) as illustrated as in figure 1 c, whereby the metal catalyst layer is deposited onto the substrate by physical vapour deposition method such as radio frequency, RF sputtering method. Material of the metal catalyst layer is preferably but not limited to copper, nickel, platinum, ruthenium and iridium. The thickness of metal catalyst layer is preferably within range of 200nm to 1000nm. The oxidation layer formed earlier in step (240) acts as an isolation layer between the metal catalyst layer and the substrate.
Further to above steps, the substrate then undergoes a chemical vapour deposition process, whereby a graphene (50) is synthesized (250) on top of the metal catalyst layer (40). Illustration of this step shown as in figure 1 d. As the metal catalyst layer (40) as somehow been patterned through the silicon structure (30) formation, the synthesized of the graphene (50) will self-assemble to the metal catalyst layer (40), hence forming a graphene bump structure extending outwards of the substrate (10) or inwards to the substrate (10).
In order to form a three dimensional (3D) graphene bump structure on a flexible substrate, a thick layer of epoxy-based photoresist (60) will then be deposited (260) onto the graphene layer (50), whereby the epoxy-based photoresist is preferably SU-8 material with thickness range is between 50pm to 100pm. An illustration of this step is shown as in figure 1 e
Remaining layer of the thin metal catalyst (40), silicon dioxide (30) and epoxy-based photoresist (60) are then be removed (270) from the substrate by wet etching process. In a further embodiment of the present invention, the method of forming the graphene bump structure comprises the steps of patterning (280) the epoxy-based photoresist (60) in the cavity structure in order to remove a remaining photoresist from the cavity (20) structure. The aforementioned step illustrated as in figure 1f and 1 g.
Although the present invention has been described with reference to specific embodiments, also shown in the appended figures, it will be apparent for those skilled in the art that many variations and modifications can be done within the scope of the invention as described in the specification and defined in the following claims.

Claims

1 ) A method (200) of forming graphene bump structure (100) is characterized by the steps of:
providing (210) a substrate (10);
etching (220) the substrate (10) to form a cavity structure (20); growing (230) a silicon dioxide layer (30) on top of the substrate (10); depositing (240) a thin metal catalyst layer (40) on top of the silicon substrate (30);
synthesizing (250) graphene layer (50) on top of the metal catalyst layer (40);
depositing (260) an epoxy-based photoresist (60); and removing (270) the thin metal catalyst layer (40), the silicon dioxide layer (30) and photoresist layer from the substrate (10).
2) The method according to Claim 1 , wherein the method further comprising a step of patterning (280) the epoxy-based photoresist (60) to remove from the cavity (20) structure.
3) The method according to Claim 1 , wherein the substrate is etched with a combination of sulphur hexafluoride, SF6 and octaflourocyclobutane, C4F8 plasma.
4) The method according to Claim 1 , wherein depth of the cavity structure is between 500nm - 1500nm.
5) The method according to Claim 1 , wherein the silicon dioxide layer is grown by wet or dry oxidation process.
6) The method according to Claim 1 , wherein the thin metal catalyst layer is deposited by physical vapour deposition method. 7) The method according to Claim 1 , wherein thickness of the metal catalyst layer is not more than half of the depth of the cavity structure.
8) The method according to Claim 1 , wherein the graphene layer is synthesized by chemical vapour deposition method.
9) The method according to Claim 1 , the thin metal catalyst layer (40), the silicon dioxide layer (30) and photoresist layer are removed from the substrate by wet etching process.
PCT/MY2019/050132 2018-12-26 2019-12-26 Method of forming graphene bump structure Ceased WO2020139077A1 (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20110018851A (en) * 2009-08-18 2011-02-24 세종대학교산학협력단 Carbon nanostructure pattern and manufacturing method thereof, and Carbon nanostructure thin film transistor and manufacturing method thereof
KR20150094284A (en) * 2014-02-11 2015-08-19 광주과학기술원 Method for direct growth of patterned graphene and graphene using the same
KR20150132816A (en) * 2015-11-06 2015-11-26 한국과학기술원 Method and board for growing high quality graphene layer using high pressure annealing
US20160230304A1 (en) * 2013-09-16 2016-08-11 Griffith University Process for forming graphene layers on silicon carbide
US20180204976A1 (en) * 2015-07-13 2018-07-19 Crayonano As Nanowires or nanopyramids grown on graphitic substrate

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20110018851A (en) * 2009-08-18 2011-02-24 세종대학교산학협력단 Carbon nanostructure pattern and manufacturing method thereof, and Carbon nanostructure thin film transistor and manufacturing method thereof
US20160230304A1 (en) * 2013-09-16 2016-08-11 Griffith University Process for forming graphene layers on silicon carbide
KR20150094284A (en) * 2014-02-11 2015-08-19 광주과학기술원 Method for direct growth of patterned graphene and graphene using the same
US20180204976A1 (en) * 2015-07-13 2018-07-19 Crayonano As Nanowires or nanopyramids grown on graphitic substrate
KR20150132816A (en) * 2015-11-06 2015-11-26 한국과학기술원 Method and board for growing high quality graphene layer using high pressure annealing

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