WO2020133579A1 - 限流电路及显示装置 - Google Patents

限流电路及显示装置 Download PDF

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Publication number
WO2020133579A1
WO2020133579A1 PCT/CN2019/071074 CN2019071074W WO2020133579A1 WO 2020133579 A1 WO2020133579 A1 WO 2020133579A1 CN 2019071074 W CN2019071074 W CN 2019071074W WO 2020133579 A1 WO2020133579 A1 WO 2020133579A1
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Prior art keywords
circuit
voltage
output current
switch
current
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PCT/CN2019/071074
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English (en)
French (fr)
Inventor
张良
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HKC Co Ltd
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HKC Co Ltd
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Priority to US17/257,978 priority Critical patent/US11295691B2/en
Publication of WO2020133579A1 publication Critical patent/WO2020133579A1/zh
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    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611Control of matrices with row and column drivers
    • G09G3/3674Details of drivers for scan electrodes
    • G09G3/3677Details of drivers for scan electrodes suitable for active matrices only
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G3/2096Details of the interface to the display terminal specific for a flat panel
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02HEMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/02Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess current
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02Details of power systems and of start or stop of display operation
    • G09G2330/025Reduction of instantaneous peaks of current
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/04Display protection

Definitions

  • This application relates to the field of display technology, in particular to a current limiting circuit and a display device.
  • GDL Gate driverless, no gate drive liquid crystal display panels
  • the GDL circuit is composed of two parts: level shifter IC (boost integrated circuit) and shift register (shift register), level shifter IC is set on the driver board, shift register is set on the LCD panel, level shifter IC transmits CLK (Clock) The signal is given to shift to complete the driving of the liquid crystal display panel.
  • the level shifter IC is installed on the driver board so that the frame length of the LCD panel can be reduced.
  • a current limiting circuit and a display device are provided.
  • a current limiting circuit includes:
  • a switch circuit respectively connected to the voltage input terminal and the voltage output terminal, and configured to transmit the input voltage from the voltage input terminal to the voltage output terminal;
  • the voltage stabilizing circuit is respectively connected to the switch circuit, the voltage input terminal and the voltage output terminal, and is arranged to communicate with the switch when the output current of the voltage output terminal increases and the output current is less than the preset output current
  • the circuit controls the output current to decrease; it is also set to control the output current to zero with the switch circuit when the output current at the voltage output terminal is greater than or equal to the preset output current.
  • the switch circuit includes a first switch circuit, the first switch circuit is respectively connected to the voltage stabilizing circuit, the voltage input terminal and the voltage output terminal, and is set to When the output current of the output end increases and the output current is less than the preset output current, the output current is controlled by the voltage stabilizing circuit to decrease; it is also set that when the output current of the voltage output end is greater than or equal to the preset output current, The voltage regulator circuit controls the output current to zero.
  • the switch circuit further includes a second switch circuit, the second switch circuit and the first switch circuit, the voltage stabilizing circuit, the voltage input terminal and the voltage output terminal respectively Connection; the voltage stabilizing circuit and the first switching circuit are further configured to control the second switching circuit to turn on when the output current of the voltage output terminal increases and the output current is less than a preset output current; The voltage circuit and the first switch circuit are further configured to control the second switch circuit to turn off when the output current of the voltage output terminal is greater than or equal to a preset output current.
  • the voltage stabilizing circuit includes a voltage stabilizing tube and a first resistor, the first end of the voltage stabilizing tube is connected to the voltage output terminal, and the second end of the voltage stabilizing tube is The first terminal of the first resistor, the first switching circuit, and the second switching circuit are connected, and the second terminal of the first resistor is connected to the voltage input terminal.
  • the voltage stabilizing tube is a voltage stabilizing diode, and the first end and the second end of the voltage stabilizing tube respectively correspond to the anode and the cathode of the voltage stabilizing diode.
  • the first switch circuit includes a first electronic switch, a second resistor, and a third resistor.
  • the first end of the first electronic switch is connected to the second end of the regulator tube, so The second terminal of the first electronic switch is connected to the voltage output terminal through the second resistor, and the third terminal of the first electronic switch is connected to the voltage input terminal through the third resistor.
  • the third terminal of an electronic switch is also connected to the second switch circuit.
  • the second switch circuit includes a second electronic switch and a fourth resistor, the first end of the second electronic switch is connected to the third end of the first electronic switch, and the second The second terminal of the electronic switch is connected to the voltage input terminal, the third terminal of the second electronic switch is connected to the voltage output terminal through the fourth resistor, and the third terminal of the second electronic switch is also It is connected to the second end of the regulator tube.
  • the first electronic switch is an N-channel field effect transistor, and the first end, the second end, and the third end of the first electronic switch correspond to the gate and source of the N-channel field effect transistor, respectively Pole and drain.
  • the first electronic switch is an NPN transistor, and the first end, the second end, and the third end of the first electronic switch correspond to the base, emitter, and collector of the NPN transistor, respectively. .
  • the second electronic switch is a P-channel field effect transistor, and the first end, the second end, and the third end of the second electronic switch correspond to the gate and source of the P-channel field effect transistor, respectively Pole and drain.
  • the second electronic switch is a PNP transistor, and the first end, the second end, and the third end of the second electronic switch correspond to the base, emitter, and collector of the PNP transistor, respectively. .
  • a current limiting circuit includes:
  • a switch circuit respectively connected to the voltage input terminal and the voltage output terminal, and configured to transmit the input voltage from the voltage input terminal to the voltage output terminal;
  • the voltage stabilizing circuit is respectively connected to the switch circuit, the voltage input terminal and the voltage output terminal, and is arranged to communicate with the switch when the output current of the voltage output terminal increases and the output current is less than the preset output current
  • the circuit controls the output current to be reduced; it is also set to control the output current to zero with the switch circuit when the output current at the voltage output terminal is greater than or equal to the preset output current;
  • the switch circuit includes:
  • the first switch circuit is respectively connected to the voltage stabilizing circuit, the voltage input terminal and the voltage output terminal, and is set to be connected to the voltage when the output current of the voltage output terminal increases and the output current is less than the preset output current
  • the voltage stabilizing circuit controls the output current to be reduced; it is also set to control the output current to zero with the voltage stabilizing circuit when the output current of the voltage output terminal is greater than or equal to the preset output current
  • the second switch circuit is respectively connected to the first switch circuit, the voltage stabilizing circuit, the voltage input terminal and the voltage output terminal;
  • the voltage stabilizing circuit and the first switching circuit are further configured to control the second switching circuit to turn on when the current output by the voltage output terminal increases and the output current is less than a preset output current;
  • the circuit and the first switch circuit are further configured to control the second switch circuit to turn off when the output current of the voltage output terminal is greater than or equal to a preset output current.
  • a display device includes a power supply integrated circuit, a booster integrated circuit, a drive circuit board, a display panel, a shift register, and the above current limiting circuit; the current limiting circuit is connected to the power supply integrated circuit and the Between the booster integrated circuits; the power integrated circuit, the booster integrated circuit, and the current limiting circuit are all disposed on the driving circuit board, and the shift register is disposed on both sides of the display panel .
  • the signal transmitted by the current limiting circuit to the boost integrated circuit is a low potential signal
  • the boost integrated circuit is configured to convert the low potential signal into a high potential signal
  • the absolute value of the potential of the low potential signal is smaller than the absolute value of the potential of the high potential signal.
  • the low potential signal is a digital signal
  • the high potential signal is an analog signal
  • the display panel is a liquid crystal display panel.
  • the display panel includes an active array substrate, a color filter layer substrate, and a liquid crystal layer formed between the two substrates.
  • the shift register is disposed on the active array substrate.
  • the display panel is a curved display panel.
  • FIG. 1 is a circuit diagram of a current limiting circuit provided by an embodiment
  • FIG. 2 is a schematic block diagram of a display device provided by an embodiment
  • FIG. 3 is a schematic block diagram of a display device provided by another embodiment.
  • FIG. 1 is a circuit diagram of a current limiting circuit 100 provided by this application.
  • the current limiting circuit 100 includes a switching circuit 10 and a voltage stabilizing circuit 20.
  • the switch circuit 10 is respectively connected to a voltage input terminal VIN and a voltage output terminal VOUT, and is used for transmitting an input voltage from the voltage input terminal VIN to the voltage output terminal VOUT.
  • the voltage stabilizing circuit 20 is respectively connected to the switching circuit 10, the voltage input terminal VIN and the voltage output terminal VOUT, and is used when the output current of the voltage output terminal VOUT increases and the output current is less than the preset output At the time of current, it is controlled by the switch circuit 10 to reduce the output current; it is also used to control the output current to zero by the switch circuit 10 when the output current of the voltage output terminal VOUT is greater than or equal to the preset output current.
  • the current limiting circuit 100 is connected between the power integrated circuit 200 and the boost integrated circuit 300. Specifically, the voltage input terminal VIN of the current limiting circuit 100 is connected to the power integrated circuit 200. The voltage output terminal VOUT of the current limiting circuit 100 is connected to the boosting integrated circuit 300.
  • the current limiting circuit 100, the power integrated circuit 200 and the boost integrated circuit 300 are used in a display device. The power of the system motherboard is processed by the power integrated circuit 200, the current limiting circuit 100, and the boost integrated circuit 300, and then transmitted to the shift register, and the display of the display panel is driven by the shift register.
  • the current limiting circuit 100 limits the current driving the liquid crystal display panel to prevent the liquid crystal display panel from being damaged due to excessive driving current.
  • the switch circuit 10 when the output current of the voltage output terminal VOUT increases and the output current is less than the preset output current, the switch circuit 10 is in a conducting state, and the power integrated circuit 200 can pass the current limiting circuit 100 transmits power to the boost integrated circuit 300.
  • the switching circuit 10 When the output current of the voltage output terminal VOUT is zero, the switching circuit 10 is turned off, and the path between the power integrated circuit 200 and the boost integrated circuit 300 is disconnected.
  • the switch circuit 10 includes a first switch circuit 11.
  • the first switch circuit 11 is connected to the voltage stabilizing circuit 20, the voltage input terminal VIN and the voltage output terminal VOUT, respectively.
  • the first switch circuit 11 is used to control the output current of the voltage regulator circuit 20 to decrease when the output current of the voltage output terminal VOUT increases and the output current is less than the preset output current.
  • the voltage The output terminal VOUT still has a current output and can suppress the increase of the output current, avoiding that the protection current provided in the booster integrated circuit 300 to protect the liquid crystal display panel is too small, which may easily trigger the shutdown of the liquid crystal display panel.
  • the first switch circuit 11 is also used to control the output current to zero with the voltage stabilizing circuit 20 when the output current of the voltage output terminal VOUT is greater than or equal to a preset output current. At this time, the switch circuit 10 The cut-off prevents the output current of the voltage output terminal VOUT from being too large and damaging the liquid crystal display panel.
  • the switch circuit 10 further includes a second switch circuit 12.
  • the second switch circuit 12 is connected to the first switch circuit 11, the voltage stabilizing circuit 20, the voltage input terminal VIN and the voltage output terminal VOUT, respectively.
  • the voltage stabilizing circuit 20 and the first switching circuit 11 are also used to control the second switching circuit 12 to turn on when the output current of the voltage output terminal VOUT increases and the output current is less than the preset output current.
  • the voltage stabilizing circuit 20 and the first switching circuit 11 are also used to control the second switching circuit 12 to turn off when the output current of the voltage output terminal VOUT is greater than or equal to the preset output current.
  • the second switch circuit 12 and the first switch circuit 11 realize the conduction between the voltage input terminal VIN and the voltage output terminal VOUT when the output current of the voltage output terminal VOUT is less than the preset output current , And limit the increase in output current.
  • the voltage stabilizing circuit 20 includes a voltage stabilizing tube D1 and a first resistor R1.
  • the first end of the regulator tube D1 is connected to the voltage output terminal VOUT, the second end of the regulator tube D1 and the first terminal of the first resistor R1, the first switch circuit 11 and The second switch circuit 12 is connected, and the second terminal of the first resistor R1 is connected to the voltage input terminal VIN.
  • the voltage stabilizing tube D1 is used to maintain the voltage of the second end thereof as a regulated voltage when the voltage of the second end thereof is greater than its regulated voltage.
  • the voltage regulator tube D1 is a voltage regulator diode.
  • the first switch circuit 11 includes a first electronic switch Q1, a second resistor R2, and a third resistor R3.
  • the first end of the first electronic switch Q1 is connected to the second end of the regulator D1.
  • the second terminal of the first electronic switch Q1 is connected to the voltage output terminal VOUT through the second resistor R2, and the third terminal of the first electronic switch Q1 is connected to the voltage input through the third resistor R3
  • the terminal VIN is connected, and the third terminal of the first electronic switch Q1 is also connected to the second switch circuit 12.
  • the second switch circuit 12 includes a second electronic switch Q2 and a fourth resistor R4.
  • the first end of the second electronic switch Q2 is connected to the third end of the first electronic switch Q1, the second end of the second electronic switch Q2 is connected to the voltage input terminal VIN, and the second electron
  • the third terminal of the switch Q2 is connected to the voltage output terminal VOUT through the fourth resistor R4, and the third terminal of the second electronic switch Q2 is also connected to the second terminal of the regulator D1.
  • the first electronic switch Q1 is an NMOS transistor or an NPN transistor, and the first end, the second end, and the third end of the first electronic switch Q1 correspond to the gate and source of the NMOS transistor, respectively And the base, emitter and collector of the drain or NPN transistor.
  • the first electronic switch Q1 may also be other switches having the same or similar functions, such as insulated gate bipolar transistors.
  • the first electronic switch Q1 uses an NMOS transistor or an NPN transistor, which has low loss, fast response, and is stable and reliable.
  • the second electronic switch Q2 is a PMOS transistor or a PNP transistor, and the first end, the second end, and the third end of the second electronic switch Q2 correspond to the gate and source of the PMOS transistor, respectively And the base, emitter and collector of the drain or PNP transistor.
  • the first electronic switch Q1 may also be other switches having the same or similar functions, such as insulated gate bipolar transistors.
  • the second electronic switch Q2 uses a PMOS transistor or a PNP transistor, which has low loss, fast response, and is stable and reliable.
  • the working principle of the current limiting circuit 100 will be described below by taking the first electronic switch Q1 as an NMOS tube and the second electronic switch Q2 as a PMOS tube as an example.
  • the input voltage of the voltage input terminal VIN is Vin
  • the regulated voltage of the voltage regulator tube D1 is V1
  • the output voltage of the voltage output terminal VOUT is Vout
  • the voltage between the gate and the source of the NMOS tube The voltage is VGS1
  • the voltage VGS2 between the gate and the source of the PMOS tube and the voltage across the second resistor R2 is VR2.
  • the power integrated circuit 200 is powered on again, and the regulated voltage of the regulator D1 is maintained at V1, and the NMOS When the tube is turned on, and then the PMOS tube is turned on, the current limiting circuit 100 works normally.
  • the present application further provides a display device including a current limiting circuit 100, a power integrated circuit 200, a boost integrated circuit 300, a driving circuit board 400, a display panel 500 and a shift register 600.
  • the current limiting circuit 100 and the power integrated circuit 200 are both disposed on the driving circuit board 400.
  • the signal transmitted by the current limiting circuit 100 to the booster integrated circuit 300 is a low-potential signal, and the booster integrated circuit 300 is used to convert the low-potential signal into a high-potential signal.
  • the absolute value of the potential of the low potential signal is smaller than the absolute value of the potential of the high potential signal.
  • the low potential signal is a digital signal
  • the high potential signal is an analog signal
  • the GDL circuit includes a boost integrated circuit 300 and a shift register 600.
  • the boost integrated circuit 300 is disposed on the driving circuit board 400, and the shift register 600 is disposed on both sides of the display panel 500.
  • the area occupied by the shift register 600 is very small. Therefore, the display panel of the GDL architecture can achieve a narrow border.
  • the display panel 500 includes an active film (TFT) substrate 501, a color filter (CF) substrate 502, and a liquid crystal layer (not shown) formed between the two substrates.
  • TFT active film
  • CF color filter
  • the shift register 600 is disposed on the active array substrate 501.
  • the display panel 500 is a curved display panel.
  • the display panel 500 may be any one of the following: liquid crystal display panel, OLED display panel, QLED display panel, twisted nematic (TN) or super twisted nematic (Super Twisted Nematic, STN) ) Type, In-Plane Switching (IPS) type, Vertical Alignment (VA) type, or other display panels.
  • TN twisted nematic
  • STN super twisted nematic
  • IPS In-Plane Switching
  • VA Vertical Alignment
  • the active array and the color filter layer may be formed on the same substrate.
  • the voltage stabilizing circuit and the switching circuit when the output current of the voltage output terminal is greater than or equal to the preset output current, the voltage stabilizing circuit and the switching circuit can control the output current to be zero, which can avoid excessive output current damage Liquid crystal display panel; when the current output by the voltage output terminal increases and the output current is less than the preset output current, the voltage stabilizing circuit and the switching circuit can control the output current to decrease so that the output current is at the preset output current It can be limited when the range is increased; therefore, the preset output current can be set to be larger and the display panel is not likely to cause false shutdown.

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Abstract

一种限流电路(100),包括开关电路(10)及稳压电路(20),开关电路(10)分别与电压输入端VIN及电压输出端VOUT连接,用于将输入电压从电压输入端VIN传输至电压输出端VOUT;稳压电路(20)分别与开关电路(10)、电压输入端VIN及电压输出端VOUT连接,用于当该电压输出端VOUT的输出电流增大且输出电流小于预设输出电流时,与该开关电路(10)控制输出电流减小;还用于当该电压输出端VOUT的输出电流大于或等于预设输出电流时,与该开关电路(10)控制输出电流为零。

Description

限流电路及显示装置
本申请要求于2018年12月27日提交中国专利局、申请号为2018116107670、申请名称为“限流电路及显示装置”的中国专利申请的优先权,其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域,特别涉及一种限流电路及显示装置。
背景技术
这里的陈述仅提供与本申请有关的背景信息,而不必然地构成现有技术。
随着人们对窄边框电视的需求越来越强烈,GDL(Gate driver less,无栅极驱动)的液晶显示面板越来越受到欢迎。GDL电路由level shifter IC(升压集成电路)和shift register(移位寄存器)两部分组成,level shifter IC设置于驱动板上,shift register设置于液晶显示面板上,level shifter IC传输CLK(Clock)信号给shift register完成对液晶显示面板的驱动。level shifter IC设置于驱动板使得液晶显示面板的边框长度可以减小。
现有的GDL电路通常通过在level shifter IC中设置一个预设输出电流对显示面板进行保护,但此保护方式,若预设输出电流设置得过小,则容易引起显示面板的误关机;若预设输出电流设置得过大,过大的输出电流则会导致液晶显示面板玻璃的损坏。
发明内容
根据本申请的各种实施例提供一种限流电路及显示装置。
一种限流电路,所述限流电路包括:
开关电路,分别与电压输入端及电压输出端连接,设置为将输入电压从所述电压输入端传输至所述电压输出端;及
稳压电路,分别与所述开关电路、所述电压输入端及所述电压输出端连接,设置为当所述电压输出端的输出电流增大且输出电流小于预设输出电流时,与所述开关电路控制输出电流减小;还设置为当所述电压输出端的输出电流大于或等于预设输出电流时,与所述开关电路控制输出电流为零。
在其中一个实施例中,所述开关电路包括第一开关电路,所述第一开关电路分别与所述稳压电路、所述电压输入端及所述电压输出端连接,设置为当所述电压输出端的输出电流增大且输出电流小于预设输出电流时,与所述稳压电路控制输出电流减小;还设置为当所述电压输出端的输出电流大于或等于预设输出电流时,与所述稳压电路控制输出电流为零。
在其中一个实施例中,所述开关电路还包括第二开关电路,所述第二开关电路分别与所述第一开关电路、所述稳压电路、所述电压输入端及所述电压输出端连接;所述稳压电路及所述第一开关电路还设置为当所述电压输出端的输出电流增大且输出电流小于预设输出电流时,控制所述第二开关电路导通;所述稳压电路及所述第一开关电路还设置为当所述电压输出端的输出电流大于或等于预设输出电流时,控制所述第二开关电路截止。
在其中一个实施例中,所述稳压电路包括稳压管及第一电阻,所述稳压管的第一端与所述电压输出端连接,所述稳压管的第二端分别与所述第一电阻的第一端、所述第一开关电路及所述第二开关电路连接,所述第一电阻的第二端与所述电压输入端连接。
在其中一个实施例中,所述稳压管为稳压二极管,所述稳压管的第一端及第二端分别对应稳压二极管的阳极及阴极。
在其中一个实施例中,所述第一开关电路包括第一电子开关、第二电阻及第三电阻,所述第一电子开关的第一端与所述稳压管的第二端连接,所述第一电子开关的第二端通过所述第二电阻与所述电压输出端连接,所述第一电子开关的第三端通过所述第三电阻与所述电压输入端连接,所述第一电子开关的第三端还与所述第二开关电路连接。
在其中一个实施例中,所述第二开关电路包括第二电子开关及第四电阻,所述第二电子开关的第一端与所述第一电子开关的第三端连接,所述第二电子开关的第二端与所述电压输入端连接,所述第二电子开关的第三端与通过所述第四电阻与所述电压输出端连接,所述第二电子开关的第三端还与所述稳压管的第二端连接。
在其中一个实施例中,所述第一电子开关为N沟道场效应管,所述第一电子开关的第一端、第二端及第三端分别对应N沟道场效应管的栅极、源极及漏极。
在其中一个实施例中,所述第一电子开关为NPN型三极管,所述第一电子开关的第一端、第二端及第三端分别对应NPN型三极管的基极、发射极及集电极。
在其中一个实施例中,所述第二电子开关为P沟道场效应管,所述第二电子开关的第一端、第二端及第三端分别对应P沟道场效应管的栅极、源极及漏极。
在其中一个实施例中,所述第二电子开关为PNP型三极管,所述第二电子开关的第一端、第二端及第三端分别对应PNP型三极管的基极、发射极及 集电极。
一种限流电路,所述限流电路包括:
开关电路,分别与电压输入端及电压输出端连接,设置为将输入电压从所述电压输入端传输至所述电压输出端;及
稳压电路,分别与所述开关电路、所述电压输入端及所述电压输出端连接,设置为当所述电压输出端的输出电流增大且输出电流小于预设输出电流时,与所述开关电路控制输出电流减小;还设置为当所述电压输出端的输出电流大于或等于预设输出电流时,与所述开关电路控制输出电流为零;
所述开关电路包括:
第一开关电路,分别与所述稳压电路、所述电压输入端及所述电压输出端连接,设置为当所述电压输出端的输出电流增大且输出电流小于预设输出电流时,与所述稳压电路控制输出电流减小;还设置为当所述电压输出端的输出电流大于或等于预设输出电流时,与所述稳压电路控制输出电流为零;以及
第二开关电路,分别与所述第一开关电路、所述稳压电路、所述电压输入端及所述电压输出端连接;
所述稳压电路及所述第一开关电路还设置为当所述电压输出端输出的电流增大且输出电流小于预设输出电流时,控制所述第二开关电路导通;所述稳压电路及所述第一开关电路还设置为当所述电压输出端的输出电流大于或等于预设输出电流时,控制所述第二开关电路截止。
一种显示装置,所述显示装置包括电源集成电路、升压集成电路、驱动电路板、显示面板、移位寄存器及上述的限流电路;所述限流电路连接于所述电源集成电路与所述升压集成电路之间;所述电源集成电路、所述升压集 成电路及所述限流电路均设置于所述驱动电路板上,所述移位寄存器设置于所述显示面板的两侧。
在其中一个实施例中,所述限流电路传输至所述升压集成电路的信号为低电位信号,所述升压集成电路设置为将所述低电位信号转换成高电位信号。
在其中一个实施例中,所述低电位信号的电位绝对值小于所述高电位信号的电位绝对值。
在其中一个实施例中,所述低电位信号为数字信号,所述高电位信号为模拟信号。
在其中一个实施例中,所述显示面板为液晶显示面板。
在其中一个实施例中,所述显示面板包括主动阵列基板、彩色滤光层基板与形成于两基板之间的液晶层。
在其中一个实施例中,所述移位寄存器设置于所述主动阵列基板上。
在其中一个实施例中,所述显示面板为曲面型显示面板。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其它特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本申请的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他实施例的附图。
图1为一个实施例提供的限流电路的电路图;
图2为一个实施例提供的显示装置的原理框图;
图3为另一个实施例提供的显示装置的原理框图。
具体实施方式
为了便于理解本申请,下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的首选实施例。但是,本申请可以以许多不同的形式来实现,并不限于本文所描述的实施例。相反地,提供这些实施例的目的是使对本申请的公开内容更加透彻全面。
除非另有定义,本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的,不是旨在于限制本申请。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
需要说明的是,当一个元件被认为是“连接”另一个元件,它可以是直接连接到另一个元件或者可能同时存在居中元件。
下面结合附图,对本申请的具体实施方式进行详细描述。
请参阅图1,图1为本申请提供的限流电路100的电路图。所述限流电路100包括开关电路10及稳压电路20。所述开关电路10分别与电压输入端VIN及电压输出端VOUT连接,用于将输入电压从所述电压输入端VIN传输至所述电压输出端VOUT。所述稳压电路20分别与所述开关电路10、所述电压输入端VIN及所述电压输出端VOUT连接,用于当所述电压输出端VOUT的输出电流增大且输出电流小于预设输出电流时,与所述开关电路10控制输出电流减小;还用于当所述电压输出端VOUT的输出电流大于或等于预设输出电流时,与所述开关电路10控制输出电流为零。
请参阅图2,所述限流电路100连接于电源集成电路200与升压集成电路300之间,具体的,所述限流电路100的电压输入端VIN与所述电源集成电路200连接,所述限流电路100的电压输出端VOUT与所述升压集成电路300连接。所述限流电路100、所述电源集成电路200及所述升压集成电路300应用于显示装置中。系统主板电源通过所述电源集成电路200、所述限流电路100及所述升压集成电路300的处理后,再传输至移位寄存器,通过移位寄存器驱动显示面板的显示。所述限流电路100对驱动液晶显示面板的电流进行限制,以防止液晶显示面板因驱动电流过大而发生损坏。
需要说明的是,当所述电压输出端VOUT的输出电流增大且输出电流小于预设输出电流时,所述开关电路10处于导通状态,所述电源集成电路200能够通过所述限流电路100传输电源至所述升压集成电路300。所述电压输出端VOUT的输出电流为零即所述开关电路10截止,所述电源集成电路200与所述升压集成电路300之间通路断开。
所述开关电路10包括第一开关电路11。所述第一开关电路11分别与所述稳压电路20、所述电压输入端VIN及所述电压输出端VOUT连接。所述第一开关电路11用于当所述电压输出端VOUT的输出电流增大且输出电流小于预设输出电流时,与所述稳压电路20控制输出电流减小,此时,所述电压输出端VOUT仍有电流输出且可以抑制输出电流的增大,避免了所述升压集成电路300中设置的对液晶显示面板进行保护的保护电流过小,而容易触发液晶显示面板关机的现象。所述第一开关电路11还用于当所述电压输出端VOUT的输出电流大于或等于预设输出电流时,与所述稳压电路20控制输出电流为零,此时,所述开关电路10截止,避免了所述电压输出端VOUT的输出电流过大而损坏液晶显示面板。
所述开关电路10还包括第二开关电路12。所述第二开关电路12分别与所述第一开关电路11、所述稳压电路20、所述电压输入端VIN及所述电压输出端VOUT连接。所述稳压电路20及所述第一开关电路11还用于当所述电压输出端VOUT的输出电流增大且输出电流小于预设输出电流时,控制所述第二开关电路12导通。所述稳压电路20及所述第一开关电路11还用于当所述电压输出端VOUT的输出电流大于或等于预设输出电流时,控制所述第二开关电路12截止。所述第二开关电路12及所述第一开关电路11实现了所述电压输出端VOUT的输出电流小于预设输出电流时,对所述电压输入端VIN与所述电压输出端VOUT的导通,且对输出电流增大的限制。
所述稳压电路20包括稳压管D1及第一电阻R1。所述稳压管D1的第一端分别与所述电压输出端VOUT连接,所述稳压管D1的第二端与所述第一电阻R1的第一端、所述第一开关电路11及所述第二开关电路12连接,所述第一电阻R1的第二端与所述电压输入端VIN连接。所述稳压管D1用于当其第二端的电压大于其稳压电压时,维持其第二端的电压为稳压电压。
在一实施例中,所述稳压管D1为稳压二极管。
所述第一开关电路11包括第一电子开关Q1、第二电阻R2及第三电阻R3。所述第一电子开关Q1的第一端与所述稳压管D1的第二端连接。所述第一电子开关Q1的第二端通过所述第二电阻R2与所述电压输出端VOUT连接,所述第一电子开关Q1的第三端通过所述第三电阻R3与所述电压输入端VIN连接,所述第一电子开关Q1的第三端还与所述第二开关电路12连接。
所述第二开关电路12包括第二电子开关Q2及第四电阻R4。所述第二电子开关Q2的第一端与所述第一电子开关Q1的第三端连接,所述第二电子开关Q2的第二端与所述电压输入端VIN连接,所述第二电子开关Q2的第三 端与通过所述第四电阻R4与所述电压输出端VOUT连接,所述第二电子开关Q2的第三端还与所述稳压管D1的第二端连接。
在一实施例中,所述第一电子开关Q1为NMOS管或NPN型三极管,所述第一电子开关Q1的第一端、第二端及第三端分别对应NMOS管的栅极、源极及漏极或NPN型三极管的基极、发射极及集电极。在其它实施例中,所述第一电子开关Q1还可以是其它具有相同或相似功能的开关,如绝缘栅双极型晶体管。所述第一电子开关Q1采用NMOS管或NPN型三极管,损耗小,响应快,稳定可靠。
在一实施例中,所述第二电子开关Q2为PMOS管或PNP型三极管,所述第二电子开关Q2的第一端、第二端及第三端分别对应PMOS管的栅极、源极及漏极或PNP型三极管的基极、发射极及集电极。在其它实施例中,所述第一电子开关Q1还可以是其它具有相同或相似功能的开关,如绝缘栅双极型晶体管。所述第二电子开关Q2采用PMOS管或PNP型三极管,损耗小,响应快,稳定可靠。
下面以所述第一电子开关Q1为NMOS管及所述第二电子开关Q2为PMOS管为例对上述的限流电路100的工作原理进行说明。
所述电压输入端VIN的输入电压为Vin,所述稳压管D1的稳压电压为V1,所述电压输出端VOUT的输出电压为Vout,所述NMOS管的栅极与源极之间的电压为VGS1,所述PMOS管的栅极与源极之间的电压VGS2,所述第二电阻R2两端的电压为VR2。当所述电压输出端VOUT的输出电流增大且输出电流小于预设输出电流时,所述第二电阻R2两端的电压VR2增大,由于V1=VGS1+VR2,则VGS1=V1-VR2减小,根据MOS管的特性,I=g*VGS1(g为MOS管固定参数),I为通过所述NMOS管的电流,进而, 通过所述NMOS管的电流I减小,从而,所述电压输出端VOUT的输出电流减小,但此时,所述NMOS管及所述PMOS管均导通,保证了对增大的输出电流的抑制,同时不影响液晶显示面板的驱动。当所述电压输出端VOUT的输出电流大于或等于预设输出电流时,VGS1≦V1-VR2,所述NMOS管截止,所述PMOS管的栅极电压为Vin,所述PMOS管的栅极与源极之间的电压VGS2=Vin-Vin=0,因此,所述PMOS管截止,进而,所述NMOS管的栅极与源极之间的电压VGS1=Vout-Vout=0,所述NMOS管维持截止状态,所述电压输出端VOUT的输出电流为0,从而防止所述电压输出端VOUT的输出电流过大而损坏液晶显示面板。
当引起所述电压输出端VOUT的输出电流大于或等于预设输出电流的故障解决后,所述电源集成电路200重新上电,所述稳压管D1的稳压电压维持为V1,所述NMOS管导通,进而所述PMOS管导通,所述限流电路100正常工作。
请参阅图3,本申请还提供一种显示装置,所述显示装置包括限流电路100、电源集成电路200、升压集成电路300、驱动电路板400、显示面板500及移位寄存器600。
所述限流电路100及所述电源集成电路200均设置于所述驱动电路板400上。
所述限流电路100传输至所述升压集成电路300的信号为低电位信号,所述升压集成电路300用于将所述低电位信号转换成高电位信号。
所述低电位信号的电位绝对值小于所述高电位信号的电位绝对值。
所述低电位信号为数字信号,所述高电位信号为模拟信号。
GDL电路包括升压集成电路300及移位寄存器600,所述升压集成电路 300设置于所述驱动电路板400,所述移位寄存器600设置于所述显示面板500的两侧,由于所述移位寄存器600占的面积很小,因此,GDL架构的显示面板可以做到较窄的边框。
所述显示面板500包括主动阵列(thin film transistor,TFT)基板501、彩色滤光层(color filter,CF)基板502与形成于两基板之间的液晶层(图未示)。所述移位寄存器600设置于所述主动阵列基板501上。
在一实施例中,所述显示面板500为曲面型显示面板。在其他实施例中,所述显示面板500可以为以下任一种:液晶显示面板、OLED显示面板、QLED显示面板、扭曲向列(Twisted Nematic,TN)或超扭曲向列(Super Twisted Nematic,STN)型,平面转换(In-Plane Switching,IPS)型、垂直配向(Vertical Alignment,VA)型、或其他显示面板。
在一实施例中,所述主动阵列及所述彩色滤光层可形成于同一基板上。
上述的限流电路及显示装置,当所述电压输出端的输出电流大于或等于预设输出电流时,所述稳压电路与所述开关电路能够控制输出电流为零,能够避免输出电流过大损坏液晶显示面板;当所述电压输出端输出的电流增大且输出电流小于预设输出电流时,所述稳压电路与所述开关电路能够控制输出电流减小,使得输出电流在预设输出电流范围内增大时可以得到限制;因此,所述预设输出电流可以设置得更大且显示面板不易引起误关闭。
以上所述实施例的各技术特征可以进行任意的组合,为使描述简洁,未对上述实施例中的各个技术特征所有可能的组合都进行描述,然而,只要这些技术特征的组合不存在矛盾,都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式,其描述较为具体和详细,但并不能因此而理解为对发明专利范围的限制。应当指出的是,对于本 领域的普通技术人员来说,在不脱离本申请构思的前提下,还可以做出若干变形和改进,这些都属于本申请的保护范围。因此,本申请专利的保护范围应以所附权利要求为准。

Claims (20)

  1. 一种限流电路,所述限流电路包括:
    开关电路,分别与电压输入端及电压输出端连接,设置为将输入电压从所述电压输入端传输至所述电压输出端;及
    稳压电路,分别与所述开关电路、所述电压输入端及所述电压输出端连接,设置为当所述电压输出端的输出电流增大且输出电流小于预设输出电流时,与所述开关电路控制输出电流减小;还设置为当所述电压输出端的输出电流大于或等于预设输出电流时,与所述开关电路控制输出电流为零。
  2. 根据权利要求1所述的限流电路,其中,所述开关电路包括第一开关电路,所述第一开关电路分别与所述稳压电路、所述电压输入端及所述电压输出端连接,设置为当所述电压输出端的输出电流增大且输出电流小于预设输出电流时,与所述稳压电路控制输出电流减小;还设置为当所述电压输出端的输出电流大于或等于预设输出电流时,与所述稳压电路控制输出电流为零。
  3. 根据权利要求2所述的限流电路,其中,所述开关电路还包括第二开关电路,所述第二开关电路分别与所述第一开关电路、所述稳压电路、所述电压输入端及所述电压输出端连接;所述稳压电路及所述第一开关电路还设置为当所述电压输出端的输出电流增大且输出电流小于预设输出电流时,控制所述第二开关电路导通;所述稳压电路及所述第一开关电路还设置为当所述电压输出端的输出电流大于或等于预设输出电流时,控制所述第二开关电路截止。
  4. 根据权利要求3所述的限流电路,其中,所述稳压电路包括稳压管及第一电阻,所述稳压管的第一端与所述电压输出端连接,所述稳压管的第二 端分别与所述第一电阻的第一端、所述第一开关电路及所述第二开关电路连接,所述第一电阻的第二端与所述电压输入端连接。
  5. 根据权利要求4所述的限流电路,其中,所述稳压管为稳压二极管,所述稳压管的第一端及第二端分别对应稳压二极管的阳极及阴极。
  6. 根据权利要求4所述的限流电路,其中,所述第一开关电路包括第一电子开关、第二电阻及第三电阻,所述第一电子开关的第一端与所述稳压管的第二端连接,所述第一电子开关的第二端通过所述第二电阻与所述电压输出端连接,所述第一电子开关的第三端通过所述第三电阻与所述电压输入端连接,所述第一电子开关的第三端还与所述第二开关电路连接。
  7. 根据权利要求6所述的限流电路,其中,所述第二开关电路包括第二电子开关及第四电阻,所述第二电子开关的第一端与所述第一电子开关的第三端连接,所述第二电子开关的第二端与所述电压输入端连接,所述第二电子开关的第三端与通过所述第四电阻与所述电压输出端连接,所述第二电子开关的第三端还与所述稳压管的第二端连接。
  8. 根据权利要求6所述的限流电路,其中,所述第一电子开关为N沟道场效应管,所述第一电子开关的第一端、第二端及第三端分别对应N沟道场效应管的栅极、源极及漏极。
  9. 根据权利要求6所述的限流电路,其中,所述第一电子开关为NPN型三极管,所述第一电子开关的第一端、第二端及第三端分别对应NPN型三极管的基极、发射极及集电极。
  10. 根据权利要求7所述的限流电路,其中,所述第二电子开关为P沟道场效应管,所述第二电子开关的第一端、第二端及第三端分别对应P沟道场效应管的栅极、源极及漏极。
  11. 根据权利要求7所述的限流电路,其中,所述第二电子开关为PNP型三极管,所述第二电子开关的第一端、第二端及第三端分别对应PNP型三极管的基极、发射极及集电极。
  12. 一种限流电路,所述限流电路包括:
    开关电路,分别与电压输入端及电压输出端连接,设置为将输入电压从所述电压输入端传输至所述电压输出端;及
    稳压电路,分别与所述开关电路、所述电压输入端及所述电压输出端连接,设置为当所述电压输出端的输出电流增大且输出电流小于预设输出电流时,与所述开关电路控制输出电流减小;还设置为当所述电压输出端的输出电流大于或等于预设输出电流时,与所述开关电路控制输出电流为零;
    所述开关电路包括:
    第一开关电路,分别与所述稳压电路、所述电压输入端及所述电压输出端连接,设置为当所述电压输出端的输出电流增大且输出电流小于预设输出电流时,与所述稳压电路控制输出电流减小;还设置为当所述电压输出端的输出电流大于或等于预设输出电流时,与所述稳压电路控制输出电流为零;以及
    第二开关电路,分别与所述第一开关电路、所述稳压电路、所述电压输入端及所述电压输出端连接;
    所述稳压电路及所述第一开关电路还设置为当所述电压输出端输出的电流增大且输出电流小于预设输出电流时,控制所述第二开关电路导通;所述稳压电路及所述第一开关电路还设置为当所述电压输出端的输出电流大于或等于预设输出电流时,控制所述第二开关电路截止。
  13. 一种显示装置,所述显示装置包括电源集成电路、升压集成电路、 驱动电路板、显示面板、移位寄存器及权利要求1所述的限流电路;所述限流电路连接于所述电源集成电路与所述升压集成电路之间;所述电源集成电路、所述升压集成电路及所述限流电路均设置于所述驱动电路板上,所述移位寄存器设置于所述显示面板的两侧。
  14. 根据权利要求13所述的显示装置,其中,所述限流电路传输至所述升压集成电路的信号为低电位信号,所述升压集成电路设置为将所述低电位信号转换成高电位信号。
  15. 根据权利要求14所述的显示装置,其中,所述低电位信号的电位绝对值小于所述高电位信号的电位绝对值。
  16. 根据权利要求14所述的显示装置,其中,所述低电位信号为数字信号,所述高电位信号为模拟信号。
  17. 根据权利要求13所述的显示装置,其中,所述显示面板为液晶显示面板。
  18. 根据权利要求17所述的显示装置,其中,所述显示面板包括主动阵列基板、彩色滤光层基板与形成于两基板之间的液晶层。
  19. 根据权利要求18所述的显示装置,其中,所述移位寄存器设置于所述主动阵列基板上。
  20. 根据权利要求13所述的显示装置,其中,所述显示面板为曲面型显示面板。
PCT/CN2019/071074 2018-12-27 2019-01-10 限流电路及显示装置 Ceased WO2020133579A1 (zh)

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