WO2020132880A1 - 阵列基板及其制造方法及显示装置 - Google Patents

阵列基板及其制造方法及显示装置 Download PDF

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Publication number
WO2020132880A1
WO2020132880A1 PCT/CN2018/123564 CN2018123564W WO2020132880A1 WO 2020132880 A1 WO2020132880 A1 WO 2020132880A1 CN 2018123564 W CN2018123564 W CN 2018123564W WO 2020132880 A1 WO2020132880 A1 WO 2020132880A1
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active layer
layer
electrode
insulating layer
gate
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French (fr)
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高伟程
蔡武卫
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Shenzhen Royole Technologies Co Ltd
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Shenzhen Royole Technologies Co Ltd
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Priority to PCT/CN2018/123564 priority patent/WO2020132880A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates

Definitions

  • Embodiments of the present application relate to the field of display technology, and in particular, to an array substrate, a method for manufacturing the same, and a display device using the array substrate.
  • the resolution of the display screen is getting higher and higher. Due to the increase in resolution, the current supplied to the organic light-emitting diode is reduced due to the reduction in area.
  • the device size width-to-length ratio (W/L) of the thin film transistor usually needs to be reduced to meet the demand current of the organic light emitting diode, but when the length of the thin film transistor increases, the relative design space will be affected, which is not conducive to follow up to a higher resolution.
  • low-temperature polycrystalline oxide technology uses low-temperature polycrystalline silicon technology and indium gallium zinc oxide technology to define the components as P-type and N-type semiconductors, but the low-temperature polycrystalline oxide technology equipment is expensive Moreover, the production efficiency of the low-temperature polysilicon technology is low.
  • the embodiments of the present application aim to provide an array substrate, a manufacturing method thereof, and a display device using the array substrate, to solve the technical problem of low production efficiency of the array substrate in the prior art.
  • a method for manufacturing an array substrate comprising: forming a first active layer on a substrate;
  • first gate electrode and second gate electrode Forming a spaced apart first gate electrode and second gate electrode on the gate insulating layer, the first gate electrode being located directly above the first active layer;
  • a second source electrode and a second drain electrode are formed on opposite sides of the second active layer.
  • the forming the first active layer on the substrate includes:
  • a first metal oxide semiconductor layer is formed on the substrate, and the first metal oxide semiconductor layer is patterned to form the first active layer.
  • the forming a second active layer on the interlayer insulating layer includes:
  • the second metal oxide semiconductor layer Forming a second metal oxide semiconductor layer on the interlayer insulating layer, and patterning the second metal oxide semiconductor layer to form the second active layer, the second metal oxide
  • the carrier mobility is lower than the carrier mobility of the first metal oxide.
  • the step of forming a gate insulating layer on the first active layer includes: forming a first source electrode and a first drain electrode on two opposite sides of the first active layer respectively, in the A gate insulating layer is formed on the first active layer, the first source electrode, and the first drain electrode.
  • the method further includes:
  • Via holes corresponding to both sides of the first active layer are formed on the interlayer insulating layer and the gate insulating layer, and a first source electrode and a first drain are simultaneously formed on the interlayer insulating layer Electrode, the second source electrode and the second drain electrode, the first source electrode and the first drain electrode are in contact with the first active layer through the via hole, respectively.
  • the step of forming the first active layer on the substrate includes:
  • a flexible substrate is formed on the base, and the first active layer is formed on the flexible substrate.
  • the method before the step of forming the first active layer on the substrate, the method further includes:
  • a buffer layer is formed on the flexible substrate, and the first active layer is formed on the buffer layer.
  • a method for manufacturing an array substrate comprising: forming a first gate electrode on a substrate;
  • a first source electrode, a first drain electrode, and a second gate electrode are simultaneously formed on the gate insulating layer and the first active layer, the first source electrode and the first drain electrode are Opposite sides of an active layer are in contact, and the second gate electrode is formed at a predetermined distance from the first gate electrode;
  • a second source electrode and a second drain electrode are formed on opposite sides of the second active layer.
  • the forming a first active layer corresponding to the first gate electrode on the gate insulating layer includes: forming a first metal oxide semiconductor layer on the gate insulating layer, and The first metal oxide semiconductor layer is patterned to form the first active layer.
  • the forming a second active layer on the interlayer insulating layer includes: forming a second metal oxide semiconductor layer on the interlayer insulating layer, and forming a second metal oxide semiconductor layer The layer is patterned to form the second active layer, and the carrier mobility of the second metal oxide is lower than that of the first metal oxide.
  • the step of forming the first gate electrode on the substrate includes:
  • a flexible substrate is formed on the base, and the first gate electrode is formed on the flexible substrate.
  • the method before the step of forming the first gate electrode on the substrate, the method further includes:
  • a buffer layer is formed on the flexible substrate, and the first gate electrode is formed on the buffer layer.
  • An array substrate includes: a base and a first active layer formed on the base, a first gate electrode, a first source electrode, a first drain electrode, a second active layer, a second gate electrode, a second A source electrode, a second drain electrode, a gate insulating layer and an interlayer insulating layer; the first active layer and the first gate electrode are arranged directly opposite, the gate insulating layer is located between the first active layer and the Between the first gate electrode to insulate them; the first source electrode and the first drain electrode are in contact with opposite sides of the first active layer; the second active layer is The second gate electrode is disposed directly opposite, and the interlayer insulating layer is located between the second active layer and the second gate electrode to insulate the two from each other; the second gate electrode is located at the Between the gate insulating layer and the interlayer insulating layer; the second source electrode and the second drain electrode are respectively in contact with opposite sides of the second active layer; the first active layer and the The second active layer is made of different materials, so that the electrical properties of the
  • the first active layer is formed by sputtering a high mobility amorphous indium gallium zinc oxide target,
  • the second active layer is sputtered from a common amorphous indium gallium zinc oxide target, and the carrier mobility of the first active layer is higher than that of the second active layer rate.
  • the first active layer is located on a side of the gate insulating layer close to the substrate.
  • the first source electrode and the first drain electrode are located on a side of the gate insulating layer close to the first active layer.
  • the first source electrode and the first drain electrode are located on a side of the interlayer insulating layer away from the substrate, and the first source electrode and the first drain electrode pass through the Vias of the interlayer insulating layer and the gate insulating layer are in contact with the first active layer, respectively.
  • the array substrate further includes a flexible substrate formed on the base, the first active layer, the first gate electrode, the first source electrode, the first drain electrode, The second active layer, the second gate electrode, the second source electrode, the second drain electrode, the gate insulating layer and the interlayer insulating layer are all formed on the flexible substrate.
  • the array substrate further includes a buffer layer formed on the flexible substrate, the first active layer, the first gate electrode, the first source electrode, the first drain electrode, The second active layer, the second gate electrode, the second source electrode, the second drain electrode, the gate insulating layer, and the interlayer insulating layer are all formed on the buffer layer.
  • a display device includes the above array substrate.
  • the array substrate provided in the embodiments of the present application uses the same preparation process and different materials to prepare the first active layer and the second active layer, and then the array substrate Thin film transistor devices with different device characteristics are obtained on the substrate, which improves production efficiency and facilitates the use of layout space.
  • FIG. 1 is a schematic structural diagram of an array substrate provided by one embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of an array substrate provided by another embodiment of the present application.
  • 3a is a flow chart of a method for manufacturing an array substrate provided by one embodiment of this application.
  • 3b is a flowchart of a method for manufacturing an array substrate provided by another embodiment of the present application.
  • 4a to 4g are schematic diagrams of the manufacturing method of the array substrate shown in FIG. 3b at different stages;
  • FIG. 5a is a flowchart of a method for manufacturing an array substrate provided by yet another embodiment of the present application.
  • 5b is a flowchart of a method for manufacturing an array substrate according to another embodiment of the present application.
  • 6a to 6g are schematic diagrams of the manufacturing method of the array substrate shown in FIG. 5b at different stages.
  • an array substrate 100 provided in one embodiment of the present application includes: a first thin film transistor 10 and a second thin film transistor 20, and the first thin film transistor 10 and the second thin film transistor 20 are spaced apart.
  • the first thin film transistor 10 includes a first active layer 18;
  • the second thin film transistor 20 includes a second active layer 26, and the first active layer 18 and the second active layer 26 are each composed of Made of different materials, thereby making the electrical properties of the first active layer 18 and the second active layer 26 different, so the first thin film transistor 10 and the second thin film transistor 20 have different devices characteristic.
  • the electrical properties of the first active layer 18 and the second active layer 26 include carrier concentration, Hall carrier migration, and defect state density.
  • the first thin film transistor 10 and the second thin film transistor 20 are a switching thin film transistor and a driving thin film transistor, respectively.
  • the first thin-film transistor 10 and the second thin-film transistor 20 are simultaneously prepared from different targets in the same process.
  • the first thin film transistor 10 and the second thin film transistor 20 share a common base 2, flexible substrate 3, buffer layer 4, interlayer insulating layer 5 and gate insulating layer 6.
  • the base 2 serves as a substrate carrying the first thin film transistor 10 and the second thin film transistor 20, and the base 2 is formed with the flexible substrate 3, the buffer layer 4, the gate insulating layer 6 and the layer in this order Between the insulating layer 5.
  • the above design of the array substrate 100 does not need to adjust the width-to-length ratio (W/L) of the first thin-film transistor 10 or the second thin-film transistor 20, which improves the utilization rate of the layout space and is conducive to a higher resolution display screen Direction development.
  • the first thin film transistor 10 further includes a first source electrode 12, a first drain electrode 14, and a first gate electrode 16, the first active layer 18, the first source electrode 12, and the first drain electrode 14 are provided on the Between the buffer layer 4 and the gate insulating layer 6, the first source electrode 12 and the first drain electrode 14 are respectively disposed on opposite sides of the first active layer 18, and the first gate The electrode 16 is provided between the gate insulating layer 6 and the interlayer insulating layer 5.
  • the second thin film transistor 20 further includes a second source electrode 22, a second drain electrode 24, and a second gate electrode 28.
  • the second gate electrode 28 is disposed between the gate insulating layer 6 and the interlayer insulating layer 5, the second active layer 26 is disposed on the interlayer insulating layer 5, the second source The electrode 22 and the second drain electrode 24 are respectively disposed on opposite sides of the second active layer 26.
  • the first thin film transistor 10 adopts a top gate structure
  • the second thin film transistor 20 adopts a bottom gate structure
  • the first source electrode 12 and the first drain electrode 14 of the first thin film transistor 10 may be provided on the interlayer insulating layer 5 and penetrate the interlayer by being provided The via holes of the insulating layer 5 and the gate insulating layer 6 make the first source electrode 12 and the first drain electrode 14 contact the first active layer 18 respectively.
  • the first source electrode 12 and the first drain electrode 14 may be patterned from the same metal layer as the second source electrode 22 and the second drain electrode 24.
  • the array substrate 100 a provided in some embodiments of the present application is basically the same as the array substrate 100 shown in FIG. 1, except that the first gate electrode 16 of the first thin film transistor 10 a in the array substrate 100 a is provided at Between the buffer layer 4 and the gate insulating layer 6, the first active layer 18, the first source electrode 12, and the first drain electrode 14 are provided on the interlayer insulating layer 5 and the gate insulating layer 6 In between, the first source electrode 12 and the first drain electrode 14 are respectively disposed on opposite sides of the first active layer 18.
  • the substrate 2 is made of transparent materials such as glass and is pre-cleaned.
  • the substrate 2 may also be made of alkali-free glass.
  • the flexible substrate 3 is a substrate for supporting and protecting various elements that can be formed thereon.
  • the flexible substrate 3 may be formed of various materials.
  • the flexible substrate 3 may be formed of a flexible insulating material.
  • flexible insulating materials may include polyimide (PI), polyetherimide (PEI), polyethylene terephthalate (PES), polycarbonate (PC), polystyrene (PS) , Styrene-acrylonitrile copolymer, and silicone acrylic resin.
  • PI polyimide
  • PEI polyetherimide
  • PES polyethylene terephthalate
  • PC polycarbonate
  • PS polystyrene
  • Styrene-acrylonitrile copolymer and silicone acrylic resin.
  • the flexible substrate 3 may be formed of a flexible transparent insulating material.
  • the buffer layer 4 is used to block impurities contained in the flexible substrate 2 from diffusing into the active layer of the thin film transistor and prevent the threshold voltage, source leakage current, and other characteristics of the thin film transistor device from being affected.
  • the buffer layer 4 can enhance the adhesion between the active layer or gate insulating layer 6 and the flexible substrate 3, increase the firmness of the contact between the active layer or gate insulating layer 6 and the flexible substrate 3, and thus avoid the active layer Or the shedding of the gate insulating layer 6 improves the stability of the thin film transistor.
  • the buffer layer 4 can also be disposed on one or both sides of the gate electrode, source electrode or drain electrode, which can improve the adhesion between the gate electrode, source electrode or drain electrode and the thin film layer connected thereto At the same time, it can also effectively prevent atoms in the gate electrode, source electrode or drain electrode from diffusing into the film layer connected thereto, thereby improving the reliability of the thin film transistor.
  • the material of the buffer layer 4 is a copper alloy material.
  • the buffer layer 4 as a barrier film having high adhesion can be produced.
  • the copper alloy material contains nitrogen or oxygen, copper, and aluminum.
  • the content of nitrogen or oxygen, copper, and aluminum can be set according to different requirements, and is not specifically limited here.
  • the atomic percentage of aluminum atoms in the total number of atoms in the copper alloy material may be 0.05-30%
  • the atomic percentage of nitrogen or oxygen in the total number of atoms in the copper alloy material may also be 0.05-30%
  • the rest is copper.
  • the atomic percentage of aluminum atoms in the total number of atoms in the copper alloy material may be 0.05-30%.
  • the buffer layer 4 made with the aluminum element content within this range has better adhesion and barrier properties.
  • the copper alloy material may further contain non-copper and non-aluminum metal elements.
  • the non-copper and non-aluminum metal element may include at least one element of Ca, Mg, Na, K, Be, Li, Ge, Sr, and Ba elements.
  • the atomic percentage of non-copper and non-aluminum metal atoms in the total number of atoms in the copper alloy material is 0.05-30%, so that the buffer layer 4 can have a high adhesion and a high barrier .
  • the gate insulating layer 6 uses ammonia gas (NH 3 ) and monosilane (SiH 4 ) as reaction source gases, and a series of hydrogenation is deposited on the buffer layer 4 by radio frequency plasma enhanced chemical vapor deposition (RF-PECVD) method
  • RF-PECVD radio frequency plasma enhanced chemical vapor deposition
  • An amorphous silicon nitride (a-SiNx:H) thin film, the silicon nitride thin film has excellent insulation withstand voltage performance and better interface characteristics.
  • the thickness of the gate insulating layer 6 is 100-400 nm. Because of its good interface characteristics, the prepared semiconductor device has a small leakage current, which improves the electrical performance of the device.
  • the gate insulating layer 6 may also adopt a single-layer silicon dioxide (SiO 2 ) or double-layer silicon dioxide/silicon nitride (SiO 2 /SiNx) structure.
  • the interlayer insulating layer 5 can passivate the back channel of the active layer, which helps to improve the electrical characteristics of the thin film transistor.
  • the interlayer insulating layer 5 uses a silicon nitride insulating layer.
  • the silicon nitride insulating layer has the advantages of excellent photoelectric performance, mechanical performance, and strong resistance to impurity particle diffusion and water vapor penetration.
  • the thinner silicon nitride gate insulating layer 6 is not easy to block the diffusion phenomenon, and as the thickness of the interlayer insulating layer 5 increases, the concentration of pollutants at the interface of the active layer decreases, but when the thickness exceeds a critical value, pollution The concentration of the substance will no longer be greatly reduced to a minimum value, so the thickness of the interlayer insulating layer 5 is set to 100-400 nm.
  • the interlayer insulating layer 5 may also adopt a single-layer silicon dioxide (SiO 2 ) or double-layer silicon dioxide/silicon nitride (SiO 2 /SiNx) structure.
  • the first active layer 18 and the second active layer 26 are respectively sputtered from a high mobility amorphous indium gallium zinc oxide (a-IGZO) target and an ordinary amorphous indium gallium zinc oxide target .
  • a-IGZO amorphous indium gallium zinc oxide
  • the first active layer 18 and the second active layer 26 have different electrical properties.
  • the first active layer 18 has a high carrier mobility
  • the second active layer 26 has a relatively low carrier mobility.
  • thin film transistor devices with different electrical characteristics are prepared at the same time.
  • the amorphous indium gallium zinc oxide (a-IGZO) semiconductor has many excellent properties, and the a-IGZO semiconductor is superior in performance to other amorphous semiconductors.
  • the amorphous indium gallium zinc oxide thin film transistor (a-IGZO-SFS) has been able to achieve a switching current ratio of ⁇ 10 10 , and the electron mobility of a-IGZO is between 2-50cm 2 /Vs, which is a-Si panel 20-50 times, and the wiring is thinner when it is prepared, which can achieve 4 times the resolution at the same transmittance.
  • IGZO thin film transistors have excellent turn-off performance, and have the advantages of low leakage current and low power consumption.
  • the first active layer 18 and the second active layer 26 may be various metal oxide semiconductors.
  • Quaternary metal oxides such as indium tin gallium zinc oxide (InSnGaZnO) based materials, materials such as indium gallium zinc oxide (InGaZnO) based materials, indium tin zinc oxide (InSnZnO) based materials, indium aluminum zinc oxide based Materials (InAlZnO), materials based on indium hafnium zinc oxide (InHfZnO), materials based on tin gallium zinc oxide (SnGaZnO), materials based on aluminum gallium zinc oxide (AlGaZnO), or based on tin aluminum zinc oxide (SnAlZnO) ternary metal oxide, and materials such as indium zinc oxide (InZnO), tin zinc oxide (SnZnO), aluminum zinc oxide (AlZnO), zinc magnesium Oxide (ZnMgO) material, tin-magnesium oxide (SnMg
  • the first active layer 18 and the second active layer 26 may also be amorphous silicon, polycrystalline silicon or organic materials, which can mainly enable the first thin film transistor 10/10a and the second thin film transistor 20 Just have different electrical characteristics.
  • the material of the first source electrode 12, the first drain electrode 14, the second source electrode 22 and the second drain electrode 24 may be selected from metals such as Cu, Ni, ISO, Au, or metal oxides with high work functions.
  • the first source electrode 12, the second source electrode 22, the first drain electrode 14, and the second drain electrode 24 may have a multi-layer structure.
  • the multilayer electrode includes a metal layer having Ag, Mg, Al, PS, Pd, Au, Ni, Nd, Ir, Cr, or a mixture thereof, and a transparent conductive oxide layer including a transparent conductive oxide material.
  • the transparent conductive oxide material may include indium tin oxide (ISO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ISZO), and the like.
  • the multilayer electrode may have a three-layer structure configured to include a first transparent conductive oxide layer, a metal layer, and a second transparent conductive oxide layer.
  • the multilayer electrode may also have a two-layer structure configured to include a transparent conductive oxide layer and a metal layer.
  • the first source electrode 12, the second source electrode 22, the first drain electrode 14 and the second drain electrode 24 each include a flexible substrate, a conductive metal wire layer and a conductive film, the conductive metal wire The layer is disposed between the flexible substrate and the conductive film.
  • the material of the flexible substrate is a material with a visible light transmittance greater than 80%, which may be polyethylene terephthalate, ethylene glycol ester (PES), polyethersulfone (PES), polyethylene naphthalate ( PEN), cycloolefin copolymer (COC) or transparent polyimide (PI).
  • the thickness of the flexible substrate may be 0.1 mm-0.5 mm.
  • the material of the conductive film may be poly(3,4-dioxyethylthiophene)/poly(p-styrenesulfonic acid) (PEDOS:PSS), and the mass ratio of PSS to PEDOS may be 1:20.
  • the thickness of the conductive film may be 15 ⁇ m-1100 ⁇ m.
  • the conductive metal wire layer includes a plurality of conductive metal wires, and the plurality of conductive metal wires are arranged on the flexible substrate.
  • the plurality of conductive metal wires are arranged in a mesh on the flexible substrate material.
  • multiple conductive metal wires may also be arranged in a grid.
  • the diameter of the conductive metal wire is 10 ⁇ m-1000 ⁇ m, the distance between the adjacent two conductive metal wires is 0.2 mm-10 mm, and the material of the conductive metal wire may be gold, silver, aluminum, copper or nickel .
  • the electrode is provided with the conductive metal wire layer between the flexible substrate and the conductive film, and a plurality of conductive metal wires of the conductive metal wire layer are covered with a conductive film to form an internal conductive network, reducing The surface resistance improves the conductivity of the electrode. Please refer to FIG. 3a and FIG. 3b together.
  • An example of the present application provides a method for manufacturing an array substrate. It should be noted that the above explanation of the implementation of the array substrate is also applicable to the array substrate of this embodiment.
  • the manufacturing method of the array substrate includes:
  • Step S31 forming a flexible substrate 3 on the base 2.
  • Step S32 forming a buffer layer 4 on the flexible substrate 3.
  • a plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor DeposiSion: cylinder called PECVD) method, a low pressure chemical vapor deposition (Low Pressure Chemical Vapor DeposiSion: cylinder called LPCVD), atmospheric pressure chemical
  • the buffer layer 4 is formed by vapor deposition (ASmospheric Pressure Chemical Vapor DeposiSion: cylinder called APCVD) method or electron cyclotron resonance chemical vapor deposition (ElecSron CycloSron Resonance Chemical Vapor DeposiSion: cylinder called ECR-CVD) method or sputtering method.
  • the thickness range of the buffer layer 4 is The deposition temperature is less than or equal to 600°C.
  • the specific manufacturing method of the buffer layer 4 is: placing copper and aluminum targets into the deposition chamber, depositing the buffer layer 4 on the flexible substrate 3 by sputtering or evaporation, and passing nitrogen or oxygen during the deposition.
  • the atomic percentage of aluminum atoms in the total number of atoms in the copper alloy material is 0.05-30%
  • the atomic percentage of nitrogen or oxygen in the total number of atoms in the copper alloy material is 0.05- 30% of the copper alloy material is copper.
  • non-copper and non-aluminum metal elements you can put non-copper and non-aluminum metals together with copper and aluminum into the deposition chamber, and then deposit the buffer layer 4 on the flexible substrate 3 by sputtering or evaporation. And during the deposition, nitrogen or oxygen is introduced.
  • the specific manufacturing method of the buffer layer 4 may also be that: nitrogen or oxygen, copper, and aluminum are formed into a target material according to a set atomic ratio, and then deposited on the flexible substrate 3 to form Buffer layer 4. Exceptionally, if it is necessary to add non-copper and non-aluminum metal elements, nitrogen or oxygen, copper, aluminum, and non-copper and non-aluminum metals can also be made into targets according to the set atomic ratio, and then deposited to form the buffer layer 4.
  • the buffer layer 4 may be a single-layer or multi-layer structure, and when it is a multi-layer structure, the materials of each layer may be the same or different.
  • step S32 may be omitted, that is, the buffer layer 4 is omitted.
  • Step S33 forming a first active layer 18 on the buffer layer 4 through a patterning process.
  • a first metal oxide semiconductor layer is formed on the buffer layer 4 after step S2, and the first metal oxide semiconductor layer is patterned to form the first Source layer 18.
  • the first metal oxide semiconductor layer is formed on the buffer layer 4 by a sputtering method.
  • the target used for sputtering is a high mobility amorphous indium gallium zinc oxide (a-IGZO) target.
  • the first active layer 18 formed through the patterning process is sputtered from a high mobility amorphous indium gallium zinc oxide (a-IGZO) target, so that it has a high carrier mobility.
  • the patterning process may include only a photolithography process, or a photolithography process and an etching step, and may also include other processes for forming a predetermined pattern such as printing, inkjet, etc.
  • the photolithography process refers to including film formation, Exposure, development and other processes use photoresist, mask, exposure machine, etc. to form patterns.
  • the corresponding patterning process can be selected according to the structure formed in the embodiment of the present application.
  • a layer of photoresist is formed on the first metal oxide semiconductor layer, the photoresist is exposed and developed, and then the first metal oxide semiconductor layer is dry etched, To form the first active layer 18.
  • step S31 may also be omitted, that is, the first active layer 18 is formed directly on the buffer layer 4.
  • step S31, step S32, and step S33 may be replaced with step S311, which is to form the first active layer 18 on the substrate 2.
  • Step S34 forming a first source electrode 12 and a first drain electrode 14 on opposite sides of the first active layer 18 by a patterning process.
  • a layer is deposited on the first active layer 18 and the buffer layer 4 through step S3 by magnetron sputtering, thermal evaporation or other film forming methods.
  • the source-drain metal layer is coated with a layer of photoresist on the source-drain metal layer, and the photoresist is exposed and developed using a mask plate to form the photoresist into a photoresist non-reserved area and a photoresist reserved area , Where the photoresist reserved areas are located on opposite sides of the first active layer 18, and the photoresist unreserved areas are other areas; the source and drain metals in the photoresist unreserved areas are completely etched away by the etching process The thin film is stripped of the remaining photoresist to form the first source electrode 12 and the first drain electrode 14.
  • Step S35 forming a gate insulating layer 6 simultaneously on the buffer layer 4, the first active layer 18, the first source electrode 12, and the first drain electrode 14.
  • a plasma enhanced chemical vapor deposition (PECVD) method may be used to pass the buffer layer 4, the first active layer 18, the first source electrode 12, and the The deposition thickness on the first drain electrode 14 is about Of the gate insulating layer 6, wherein the material of the gate insulating layer 6 may be oxide, nitride or oxynitride, and the gate insulating layer 6 may have a single-layer, double-layer or multi-layer structure. Specifically, the gate insulating layer 6 may be SiNx, SiOx, or Si(ON)x.
  • steps S34 and S35 can be replaced with step S312, which is to form the gate insulating layer 6 on the first active layer 18.
  • Step S36 forming a first gate electrode 16 and a second gate electrode 28 simultaneously on the gate insulating layer 6 by a patterning process, the first gate electrode 16 is located directly above the first active layer 18, The first gate electrode 16 and the second gate electrode 28 are separated by a preset distance.
  • a layer with a thickness of about 1 can be deposited on the gate insulating layer 6 after step S5 by magnetron sputtering, thermal evaporation or other film forming methods
  • Gate metal layer coat a layer of photoresist on the gate metal layer, use a mask to expose and develop the photoresist, so that the photoresist forms a photoresist unreserved area and a photoresist reserved area;
  • the etching process etches away the gate metal layer in the area where the photoresist does not remain, strips the remaining photoresist, and forms the first gate electrode and the second gate electrode, the first gate electrode is located at the first Directly above the active layer, the second gate electrode and the first gate electrode are separated by a preset distance.
  • Step S37 forming the interlayer insulating layer 5 simultaneously on the first gate electrode 16, the second gate electrode 28, and the gate insulating layer 6.
  • the thickness range of the interlayer insulating layer 5 is The same way as the gate insulating layer 6 is deposited, the interlayer insulating layer 5 can be formed by plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, or electron cyclotron resonance chemical vapor deposition , The deposition temperature is less than or equal to 600 °C.
  • the interlayer insulating layer 5 may use a single layer of silicon oxide material, silicon oxide material, or silicon nitride material to form a stack of multiple sub-layers.
  • Step S38 forming a second active layer 26 on the interlayer insulating layer 5 through a patterning process, the second active layer 26 is provided directly above the second gate electrode 28, wherein the first An active layer and the second active layer are made of different materials, respectively, so that the electrical properties of the first active layer and the second active layer are different.
  • a second metal oxide semiconductor layer is formed on the interlayer insulating layer 5 after step S7 by a sputtering method.
  • the target used for sputtering is an ordinary amorphous indium gallium zinc oxide (a-IGZO) target.
  • the second active layer 26 formed by the patterning process is formed by sputtering an ordinary indium gallium zinc oxide (a-IGZO) target, so that the carrier mobility of the second metal oxide is low Carrier mobility of the first metal oxide.
  • the patterning process may include only a photolithography process, or a photolithography process and an etching step, and may also include other processes for forming a predetermined pattern such as printing, inkjet, etc.
  • the photolithography process refers to including film formation, Exposure, development and other processes use photoresist, mask, exposure machine, etc. to form patterns.
  • the corresponding patterning process can be selected according to the structure formed in the embodiment of the present application.
  • a layer of photoresist is formed on the second metal oxide semiconductor layer, the photoresist is exposed and developed, and then the second metal oxide semiconductor layer is dry etched, To form the second active layer 26.
  • Step S39 forming a second source electrode 22 and a second drain electrode 24 on opposite sides of the second active layer 26 by a patterning process.
  • a layer having a thickness of about 1 can be deposited on the second active layer 26 and the interlayer insulating layer 5 after step S38 by magnetron sputtering, thermal evaporation or other film forming methods
  • the source-drain metal layer is coated with a layer of photoresist on the source-drain metal layer, and the photoresist is exposed and developed using a mask plate to form the photoresist into a photoresist non-reserved area and a photoresist reserved area , Where the photoresist reserved area is on both sides and above the second active layer 26, and the photoresist unreserved area is other areas; the source and drain of the photoresist unreserved area are completely etched through the etching process The metal thin film is stripped of the remaining photoresist to form the second source electrode 22 and the second drain electrode 24.
  • the step S34 may be adjusted between step S37 and step S38, that is, after the interlayer insulating layer 5 is formed, the first source is formed directly on the interlayer insulating layer 5
  • the first source electrode 12 and the first drain electrode 14 are respectively connected to the first through the vias penetrating the interlayer insulating layer 5 and the gate insulating layer 6.
  • the source layer 18 is in contact.
  • the step S34 may also be after the step S38, that is, the first source electrode 12, the first drain electrode 14 and the second source electrode 22, the second drain electrode 24 are in It is formed by patterning the same conductive layer at the same time.
  • the first source electrode 12 and the first drain electrode 14 are respectively connected to the first active layer through vias penetrating the interlayer insulating layer 5 and the gate insulating layer 6 18 contacts.
  • FIG. 5a and FIG. 5b Another embodiment of the present application provides a method for manufacturing an array substrate. It should be noted that the above explanation of the array substrate embodiment is also applicable to the array substrate of this embodiment. In order to avoid redundancy, the preparation method will not be detailed here. It should be noted that, in the following embodiments, there is not necessarily a certain order between the following steps. Those of ordinary skill in the art can understand from the description of the embodiments of the present application that in different embodiments, the following Each step may have a different execution order, that is, it may be executed in parallel, or may be executed interchangeably; in different embodiments, some of the steps described below may also be omitted or replaced.
  • the manufacturing method of the array substrate includes:
  • Step S51 a flexible substrate 3 is formed on the base 2.
  • Step S52 forming a buffer layer 4 on the flexible substrate 3.
  • Step S53 forming a first gate electrode 16 on the buffer layer 4 through a patterning process.
  • a layer with a thickness of about 1 can be deposited on the buffer layer 4 after step S2 by magnetron sputtering, thermal evaporation or other film forming methods
  • Gate metal layer coat a layer of photoresist on the gate metal layer, use a mask to expose and develop the photoresist, so that the photoresist forms a photoresist unreserved area and a photoresist reserved area, where ,
  • the photoresist retention area is close to one end of the buffer layer 4, the photoresist non-retention area is other areas; the gate metal layer of the photoresist non-retention area is completely etched through the etching process, and the remaining photoresist is stripped ,
  • the first gate electrode 16 is formed.
  • step S51 may also be omitted, that is, the first gate electrode 16 is formed directly on the buffer layer 4.
  • step S51, step 52, and step 53 may be replaced with step S511, which is to form a first gate electrode on the substrate.
  • Step S54 Referring to FIG. 6b, a gate insulating layer 6 is simultaneously formed on the first gate electrode 16 and the buffer layer 4.
  • Step S55 forming a first active layer 18 on the gate insulating layer 6 by a patterning process, the first active layer 18 directly corresponds to the first gate electrode 16.
  • a first metal oxide semiconductor layer is formed on the gate insulating layer 6 by a sputtering method.
  • the target used for sputtering is a high mobility amorphous indium gallium zinc oxide (a-IGZO) target.
  • the first active layer 18 formed through the patterning process is sputtered from a pure amorphous indium gallium zinc oxide (a-IGZO) target, so that it has a high carrier mobility.
  • Step S56 Referring to FIG. 6d, the first source electrode 12, the first drain electrode 14, and the second gate electrode 28 are simultaneously formed through a patterning process.
  • the first source electrode 12 and the first drain electrode 14 are respectively in contact with opposite sides of the first active layer 18, and the second gate electrode 28 is preset at a distance from the first gate electrode 16 Formed at a distance.
  • Step S57 Referring to FIG. 6e, an interlayer insulating layer 5 is simultaneously formed on the first source electrode 12, the first drain electrode 14, the second gate electrode 28, and the gate insulating layer 6.
  • Step S58 forming a second active layer 26 on the interlayer insulating layer 5 by a patterning process, the second active layer 26 is located directly above the second gate electrode 28, wherein the first An active layer 18 and the second active layer 26 are made of different materials, respectively, so that the electrical properties of the first active layer 18 and the second active layer 26 are different;
  • the second metal oxide semiconductor layer is formed on the interlayer insulating layer 5 after step S7 by a sputtering method.
  • the target used for sputtering is an ordinary amorphous indium gallium zinc oxide (a-IGZO) target.
  • the second active layer 26 formed by the patterning process is formed by sputtering an ordinary indium gallium zinc oxide (a-IGZO) target, so that the carrier mobility of the second metal oxide is low The carrier mobility of the first metal oxide.
  • Step S59 forming a second source electrode 22 and a second drain electrode 24 on opposite sides of the second active layer 26 by a patterning process.
  • the above array substrate can be applied to a display device including a light emitting layer and a protective layer, the light emitting layer is formed above the array substrate, the protective layer is formed above the light emitting layer, and the array substrate is used for The light-emitting layer is driven to emit light to enable the display device to realize a display function.
  • the array substrate may further include other necessary electronic components to realize the display driving. These components are similar to the prior art, and will not be repeated here. It should be noted that when the above array substrates are applied to a flexible display device, the base and the flexible substrate may be peeled off, and the light-emitting layer and the protective layer may be formed on the flexible substrate in order. After the sides of the first and second thin film transistors are formed, the base and the flexible substrate are peeled off.
  • the display device can implement the execution of various application functions by setting bending parameters such as a bending sensor and using bending parameters detected by the bending sensor, thereby greatly improving the user's experience.
  • the array substrate 100 or 100a of the display device of the present application uses the same preparation process, using targets with different doping concentrations or different electrical properties, and at the same time obtains different values on one array substrate 100 or 100a.
  • the thin-film transistor device with device characteristics improves production efficiency and facilitates the use of layout space.

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  • Thin Film Transistor (AREA)

Abstract

一种阵列基板及其制造方法及显示装置，其中阵列基板的制造方法包括：在基底(2)上形成第一有源层(18)；在所述第一有源层(18)上形成栅绝缘层(6)；在所述栅绝缘层(6)上同时形成第一栅电极(16)和第二栅电极(28)；在所述第一栅电极(16)和所述第二栅电极(28)上同时形成所述层间绝缘层(5)；在所述层间绝缘层(5)上形成第二有源层(26)，通过利用同一种制备工艺，不同的材料制备而成所述第一有源层(18)和所述第二有源层(26)，进而在一种阵列基板上得到具有不同器件特性的薄膜晶体管器件，提高了生产效率，同时利于布局空间的使用。

Description

阵列基板及其制造方法及显示装置 技术领域
本申请实施例涉及显示技术领域，尤其涉及一种阵列基板及其制造方法及使用该阵列基板的显示装置。
背景技术
随著现有有源矩阵有机发光二极体工艺技术提升,显示屏解析度越做越高,由于解析度提高,供给有机发光二极管的电流因面积减小而减小,为了能降低开关电流,达到器件的工作范围,薄膜晶体管的器件尺寸宽长比(W/L)通常也需要降低，才能满足有机发光二极管的需求电流，但当薄膜晶体管的长度增加,相对设计空间会受到影响,不利于后续往更高解析度发展。
目前以低温多晶氧化物技术为开发方向，现有低温多晶氧化物工艺利用低温多晶硅技术与铟镓锌氧化物技术定义元件为P型与N型半导体，然而低温多晶氧化物技术设备昂贵且低温多晶硅技术工艺生产效率较低。
发明内容
本申请实施例旨在提供一种阵列基板及其制造方法及使用该阵列基板的显示装置，以解决现有技术中阵列基板生产效率不高的技术问题。
本申请实施例解决其技术问题提供以下技术方案：
一种阵列基板的制造方法，包括：在基底上形成第一有源层；
在所述第一有源层上形成栅绝缘层；
在所述栅绝缘层上同时形成间隔设置的第一栅电极和第二栅电极，所述第一栅电极位于所述第一有源层的正上方；
在所述第一栅电极、所述第二栅电极和所述栅绝缘层上形成所述层间绝缘层；
在所述层间绝缘层上形成第二有源层，所述第二有源层设于所述第二栅电极的正上方，其中所述第一有源层和所述第二有源层分别由不同的材料制得，进而使得所述第一有源层和所述第二有源层的电学性能不同；
在所述第二有源层的相对两侧形成第二源电极和第二漏电极。
可选地，所述在所述基底上形成第一有源层，包括：
在所述基底上形成第一金属氧化物半导体层，并对所述第一金属氧化物半导体层进行图案化，以形成所述第一有源层。
可选地，所述在所述层间绝缘层上形成第二有源层，包括：
在所述层间绝缘层上形成第二金属氧化物半导体层，并对所述第二金属氧化物半导体层进行图案化，以形成所述第二有源层，所述第二金属氧化物的载流子迁移率低于所述第一金属氧化物的载流子迁移率。
可选地，所述在所述第一有源层上形成栅绝缘层的步骤包括：在所述第一有源层的两相对侧分别形成第一源电极和第一漏电极，在所述第一有源层、所述第一源电极和第一漏电极上形成栅绝缘层。
可选地，所述在所述第一栅电极、所述第二栅电极和所述栅绝缘层上形成所述层间绝缘层之后，还包括：
在所述层间绝缘层、所述栅绝缘层上形成与所述第一有源层的两侧对应的过孔，并且在所述层间绝缘层上同时形成第一源电极、第一漏极、所述第二源电极和所述第二漏电极，所述第一源电极和所述第一漏极分别通过所述过孔与所述第一有源层接触。
可选地，所述在基底上形成第一有源层的步骤之前包括：
在所述基底上形成柔性基板，所述第一有源层形成在所述柔性基板上。
可选地，所述在基底上形成第一有源层的步骤之前还包括：
在所述柔性基板上形成缓冲层，所述第一有源层形成在所述缓冲层上。
本申请实施例解决其技术问题还提供以下技术方案：
一种阵列基板的制造方法，包括：在基底上形成第一栅电极；
在所述第一栅电极上形成栅绝缘层；
在所述栅绝缘层上形成正对应所述第一栅电极的第一有源层；
在所述栅绝缘层、所述第一有源层上同时形成第一源电极、第一漏电极和第二栅电极，所述第一源电极和所述第一漏电极分别与所述第一有源层的相对两侧接触，所述第二栅电极在与所述第一栅电极间隔预设距离处形成；
在所述第一源电极、所述第一漏电极、所述第二栅电极和所述栅绝缘层上形成层间绝缘层；
在所述层间绝缘层上形成第二有源层，所述第二有源层位于所述第二栅电极的正上方，其中所述第一有源层和所述第二有源层分别由不同的材料制得，进而使得所述第一有源层和所述第二有源层的电学性能不同；
在所述第二有源层的相对两侧形成第二源电极和第二漏电极。
可选地，所述在所述栅绝缘层上形成正对应所述第一栅电极的第一有源层，包括：在所述栅绝缘层上形成第一金属氧化物半导体层，并对所述第一金属氧化物半导体层进行图案化，以形成所述第一有源层。
可选地，所述在所述层间绝缘层上形成第二有源层，包括：在所述层间绝缘层上形成第二金属氧化物半导体层，并对所述第二金属氧化物半导体层进行图案化，以形成所述第二有源层，所述第二金属氧化物的载流子迁移率低于所述第一金属氧化物的载流子迁移率。
可选地，所述在基底上形成第一栅电极的步骤之前包括：
在所述基底上形成柔性基板，所述第一栅电极形成在所述柔性基板上。
可选地，所述在基底上形成第一栅电极的步骤之前还包括：
在所述柔性基板上形成缓冲层，所述第一栅电极形成在所述缓冲层上。
本申请实施例解决其技术问题还提供以下技术方案：
一种阵列基板，包括：基底及形成于所述基底上的第一有源层、第一栅电极、第一源电极、第一漏电极、第二有源层、第二栅电极、第二 源电极、第二漏电极、栅绝缘层和层间绝缘层；所述第一有源层与所述第一栅电极正对设置，所述栅绝缘层位于所述第一有源层与所述第一栅电极之间以使二者相互绝缘；所述第一源电极与所述第一漏电极分别与所述第一有源层的相对两侧接触；所述第二有源层与所述第二栅电极正对设置，所述层间绝缘层位于所述第二有源层与所述第二栅电极之间以使二者相互绝缘设置；所述第二栅电极位于所述栅绝缘层与所述层间绝缘层之间；所述第二源电极与所述第二漏电极分别与所述第二有源层的相对两侧接触；所述第一有源层和所述第二有源层分别由不同的材料制得，进而使得所述第一有源层和所述第二有源层的电学性能不同。
可选地，所述第一有源层由高迁移率非晶铟镓锌氧化物靶材溅射而成，
所述第二有源层由普通非晶铟镓锌氧化物靶材溅射而成，所述第一有源层的载流子迁移率高于所述第二有源层的载流子迁移率。
可选地，所述第一有源层位于所述栅绝缘层靠近所述基底的一侧。可选地，所述第一源电极和所述第一漏电极位于所述栅绝缘层靠近所述第一有源层的一侧。
可选地，所述第一源电极和所述第一漏电极位于所述层间绝缘层远离所述基底的一侧，所述第一源电极、所述第一漏电极分别通过贯穿所述层间绝缘层和所述栅绝缘层的过孔，分别与所述第一有源层接触。
可选地，所述阵列基板还包括形成于所述基底上的柔性基板，所述第一有源层、所述第一栅电极、所述第一源电极、所述第一漏电极、所述第二有源层、所述第二栅电极、所述第二源电极、所述第二漏电极、所述栅绝缘层和所述层间绝缘层均形成于所述柔性基板上。
可选地，所述阵列基板还包括形成于所述柔性基板上的缓冲层，所述第一有源层、所述第一栅电极、所述第一源电极、所述第一漏电极、所述第二有源层、所述第二栅电极、所述第二源电极、所述第二漏电极、所述栅绝缘层和所述层间绝缘层均形成于所述缓冲层上。
本申请实施例解决其技术问题还提供以下技术方案：
一种显示装置，包括以上所述的阵列基板。
与现有技术相比较，在本申请实施例提供的阵列基板通过利用同一种制备工艺，不同的材料制备而成所述第一有源层和所述第二有源层，进而在一种阵列基板上得到具有不同器件特性的薄膜晶体管器件，提高了生产效率，同时利于布局空间的使用。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图示出的结构获得其他的附图。
图1是本申请其中一个实施例提供的一种阵列基板的结构示意图；
图2是本申请另一个实施例提供的一种阵列基板的结构示意图；
图3a是本申请其中一个实施例提供的一种阵列基板的制造方法的流程图；
图3b是本申请另一实施例提供的一种阵列基板的制造方法的流程图；
图4a至图4g是图3b示出的阵列基板的制造方法在不同阶段的制备示意图；
图5a是本申请再一实施例提供的一种阵列基板的制造方法的流程图；
图5b是本申请又一实施例提供的一种阵列基板的制造方法的流程图；
图6a至图6g是图5b示出的阵列基板的制造方法在不同阶段的制备示意图。
具体实施方式
为了便于理解本申请，下面结合附图和具体实施例，对本申请进行更详细的说明。需要说明的是，当元件被表述“固定于”另一个元件， 它可以直接在另一个元件上、或者其间可以存在一个或多个居中的元件。当一个元件被表述“连接”另一个元件，它可以是直接连接到另一个元件、或者其间可以存在一个或多个居中的元件。本说明书所使用的术语“垂直的”、“水平的”、“左”、“右”、“内”、“外”以及类似的表述只是为了说明的目的，并且仅表达实质上的位置关系，例如对于“垂直的”，如果某位置关系因为了实现某目的的缘故并非严格垂直，但实质上是垂直的，或者利用了垂直的特性，则属于本说明书所述“垂直的”范畴。
除非另有定义，本说明书所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。在本申请的说明书中所使用的术语只是为了描述具体地实施例的目的，不是用于限制本申请。本说明书所使用的术语“和/或”包括一个或多个相关的所列项目的任意的和所有的组合。
此外，下面所描述的本申请不同实施例中所涉及的技术特征只要彼此之间未构成冲突就可以相互结合。
请参阅图1，本申请其中一个实施例提供的阵列基板100包括：第一薄膜晶体管10和第二薄膜晶体管20，所述第一薄膜晶体管10和所述第二薄膜晶体管20间隔设置。所述第一薄膜晶体管10包括第一有源层18；所述第二薄膜晶体管20,包括第二有源层26，所述第一有源层18和所述第二有源层26分别由不同的材料制得，进而使得所述第一有源层18和所述第二有源层26的电学性能不同，因此所述第一薄膜晶体管10和所述第二薄膜晶体管20具有不同的器件特性。
所述第一有源层18和第二有源层26的电学性能包括载流子浓度、霍尔载流子迁移和缺陷态密度等。
在本实施例中，所述第一薄膜晶体管10和第二薄膜晶体管20分别为开关薄膜晶体管和驱动薄膜晶体管。所述第一薄膜晶体管10和所述第二薄膜晶体管20由同一工艺不同靶材同时制备而成。
所述第一薄膜晶体管10和所述第二薄膜晶体管20共用共同的基底2、柔性基板3、缓冲层4、层间绝缘层5和栅绝缘层6。所述基底2作 为承载所述第一薄膜晶体管10和所述第二薄膜晶体管20的衬底，所述基底2依次形成有所述柔性基板3、所述缓冲层4、栅绝缘层6以及层间绝缘层5。
上述阵列基板100的设计不需调整第一薄膜晶体管10或所述第二薄膜晶体管20的宽长比(W/L),提高了布局空间的使用率，有利于显示屏往更高解析度的方向发展。
所述第一薄膜晶体管10还包括第一源电极12、第一漏电极14和第一栅电极16，所述第一有源层18，第一源电极12、第一漏电极14设于所述缓冲层4和所述栅绝缘层6之间，所述第一源电极12和所述第一漏电极14分别设于所述第一有源层18的相对两侧，所述第一栅电极16设于所述栅绝缘层6和所述层间绝缘层5之间。
所述第二薄膜晶体管20还包括第二源电极22、第二漏电极24和第二栅电极28。所述第二栅电极28设于所述栅绝缘层6和所述层间绝缘层5之间，所述第二有源层26设置于所述层间绝缘层5上，所述第二源电极22和所述第二漏电极24分别设置于所述第二有源层26的相对两侧。
本实施方式中，所述第一薄膜晶体管10采用顶栅极结构，所述第二薄膜晶体管20采用底栅极结构。
在变更实施方式中(未图示)，所述第一薄膜晶体管10的第一源电极12和第一漏电极14可设置在所述层间绝缘层5上，通过设置穿透所述层间绝缘层5和所述栅绝缘层6的过孔使所述第一源电极12和所述第一漏电极14分别与所述第一有源层18接触。所述第一源电极12、所述第一漏电极14可与所述第二源电极22、所述第二漏电极24由同一金属层图案化而成。
请参阅图2，本申请一些实施例提供的阵列基板100a与图1所示的阵列基板100基本相同，区别在于所述阵列基板100a中的第一薄膜晶体管10a的第一栅电极16设于所述缓冲层4和所述栅绝缘层6之间，所述第一有源层18，第一源电极12、第一漏电极14设于所述层间绝缘层5和所述栅绝缘层6之间，所述第一源电极12和所述第一漏电极14分别 设置于所述第一有源层18的相对两侧。
所述基底2采用玻璃等透明材料制成，且经过预先清洗。在一些实施例中，因传统碱玻璃中铝、钡和钠等金属杂质含量较高，容易在高温处理工艺中发生金属杂质的扩散，因此基底2也可以采用无碱玻璃制成。
所述柔性基板3是用于支撑和保护可以在其上形成的多种元件的基板。所述柔性基板3可以由多种材料形成。例如，当薄膜晶体管在诸如柔性显示设备的柔性应用中使用时，柔性基板3可以由柔性绝缘材料形成。柔性绝缘材料的示例可以包括聚酰亚胺(PI)、聚醚酰亚胺(PEI)、聚对苯二甲酸乙二醇酯(PES)、聚碳酸酯(PC)、聚苯乙烯(PS)、苯乙烯-丙烯腈共聚物、以及硅丙烯酸树脂。而且，当薄膜晶体管在具有高透射率的应用(诸如，透明显示设备)中使用时，柔性基板3可以由柔性透明绝缘材料形成。
所述缓沖层4用于阻挡柔性基底2中所含的杂质扩散进入薄膜晶体管的有源层中，防止对薄膜晶体管器件的阈值电压和源漏电流等特性产生影响。同时所述缓冲层4能够增强有源层或栅绝缘层6与柔性基板3之间的密接性，增大有源层或栅绝缘层6与柔性基板3的接触牢固度，进而避免有源层或栅绝缘层6的脱落，提高了薄膜晶体管的稳定性。
在一些实施例中，所述缓冲层4也可设置于栅电极、源电极或漏电极的一侧或两侧，可以提高栅电极、源电极或漏电极和与其相连的薄膜层之间的密接性，同时，还能够有效地阻止栅电极、源电极或漏电极中的原子扩散到与其相连的膜层中，从而提高薄膜晶体管的可靠性。
所述缓冲层4的材料为铜合金材料。当合金材料中含有金属铜元素和非金属氮元素或氧元素时，能够制作出具有较高密接性的作为阻挡膜的缓冲层4。
在所述铜合金材料中，含有氮或氧、铜、铝。其中氮或氧、铜、铝的含量可以根据不同需求进行设定，在此不做具体限定。比如：铝原子占铜合金材料中总原子个数的原子百分比可以为0.05-30％，氮或氧占铜合金材料中总原子个数的原子百分比也可以为0.05-30％，其余为铜。铝原子占铜合金材料中总原子个数的原子百分比可以为0.05-30％。铝 元素的含量在该范围内所制作出来的缓冲层4具有更好的密接性和阻挡性。
在一些实施例中，所述铜合金材料中还可以含有非铜非铝的金属元素。例如，非铜非铝的金属元素可以包括Ca、Mg、Na、K、Be、Li、Ge、Sr和Ba元素中的至少一种元素。可选地，非铜非铝的金属原子占铜合金材料中总原子个数的原子百分比为0.05-30％，这样能够使制作出来的缓冲层4具有较高的密接性和较高的阻挡性。
所述栅绝缘层6是以氨气(NH 3)和甲硅烷(SiH 4)为反应源气体，采用射频等离子体增强化学气相沉积(RF-PECVD)法在缓冲层4上沉积了一系列氢化非晶氮化硅(a-SiNx∶H)薄膜，所述氮化硅薄膜具有优良的绝缘耐压性能以及较好的界面特性。同时通过调整所述栅绝缘层6的厚度可改善有源层背面界面的质量，防止在所述有源层界面形成漏电的途径。所述栅绝缘层6的厚度为100-400nm，因为其良好的界面特性，所制备的半导体器件具有较小的泄露电流，提高了器件的电学性能。
在一些实施例中，所述栅绝缘层6也可采用单层二氧化硅(SiO 2)或双层二氧化硅/氮化硅(SiO 2/SiNx)结构。
所述层间绝缘层5能够对有源层的背沟道进行钝化，有助于薄膜晶体管电学特性的提高。所述层间绝缘层5采用的是氮化硅绝缘层，所述氮化硅绝缘层具有优良的光电性能、机械性能以及强的阻挡杂质粒子扩散和水汽渗透等优点。较薄的所述氮化硅栅绝缘层6不易阻隔扩散现象，并随着层间绝缘层5厚度的增加，有源层界面的污染物浓度随之降低，但当厚度超过一临界值，污染物浓度将不再大幅度降低而达到一极小值，因而设置所述层间绝缘层5的厚度为100-400nm。
在一些实施例中，所述层间绝缘层5也可采用单层二氧化硅(SiO 2)或双层二氧化硅/氮化硅(SiO 2/SiNx)结构。
所述第一有源层18和第二有源层26的分别由高迁移率非晶铟镓锌氧化物(a-IGZO)靶材和普通非晶铟镓锌氧化物靶材溅射而成。通过在溅射过程中改变所述第一有源层18和第二有源层26的厚度、溅射过程中的氧分压及不同的非晶铟镓锌氧化物靶材，所制备出的所述第一有源 层18和所述第二有源层26具有不同的电学性能。例如，所述第一有源层18具有高的载流子迁移率，所述第二有源层26具有相对较低的载流子迁移率。进一步的，同时制备出具有不同电学特性的薄膜晶体管器件。
所述非晶铟镓锌氧化物(a-IGZO)半导体有着很多优异的性能，a-IGZO半导体在性能上优于其他非晶半导体。目前非晶铟镓锌氧化物薄膜晶体管(a-IGZO-SFS)已经能够实现≥10 10的开关电流比，a-IGZO的电子迁移率在2-50cm 2/V-s之间，是a-Si面板的20-50倍，且其制备的时配线变细，可实现同等透过率下4倍的分辨率。另外，IGZO薄膜晶体管的关断性能优越，具有漏电流低，功耗低的优点。
在一些实施例中，所述第一有源层18和第二有源层26可以为多种金属氧化物半导体。诸如基于铟锡镓锌氧化物(InSnGaZnO)的材料的四元金属氧化物、诸如基于铟镓锌氧化物(InGaZnO)的材料、基于铟锡锌氧化物(InSnZnO)的材料、基于铟铝锌氧化物(InAlZnO)的材料、基于铟铪锌氧化物(InHfZnO)的材料、基于锡镓锌氧化物(SnGaZnO)的材料、基于铝镓锌氧化物(AlGaZnO)的材料、或者基于锡铝锌氧化物(SnAlZnO)的材料的三元金属氧化物、以及诸如基于铟锌氧化物(InZnO)的材料、基于锡锌氧化物(SnZnO)的材料、基于铝锌氧化物(AlZnO)的材料、基于锌镁氧化物(ZnMgO)的材料、基于锡镁氧化物(SnMgO)的材料、基于铟镁氧化物(InMgO)的材料、基于铟镓氧化物(InGaO)的材料的二元金属氧化物、基于铟氧化物(InO)的材料、基于锡氧化物(SnO)的材料、或者基于锌氧化物(ZnO)的材料的一元金属氧化物。
在其他实施方式中，所述第一有源层18和所述第二有源层26还可以非晶硅、多晶硅或有机材料，主要能使第一薄膜晶体管10/10a和第二薄膜晶体管20具有不同电学特性即可。
所述第一源电极12、第一漏电极14、第二源电极22和第二漏电极24的材料可选择Cu、Ni、ISO、Au等功函数较高的金属或金属氧化物。
在一些实施例中，所述第一源电极12、第二源电极22、第一漏电极14和第二漏电极24可以多层结构。所述多层电极包括具有Ag、Mg、Al、PS、Pd、Au、Ni、Nd、Ir、Cr或其混合物的金属层和包括透明导电 氧化物材料的透明导电氧化物层。所述透明导电氧化物材料可以包括氧化铟锡(ISO)、氧化铟锌(IZO)、氧化锌(ZnO)、氧化铟锡锌(ISZO)等。所述多层电极可以具有被配置为包括第一透明导电氧化物层、金属层和第二透明导电氧化物层的三层结构。所述多层电极也可以具有被配置为包括透明导电氧化物层和金属层的两层结构。
在一些实施例中，所述第一源电极12、第二源电极22、第一漏电极14和第二漏电极24均包括柔性基材、导电金属线层以及导电薄膜，所述导电金属线层设置于所述柔性基材和所述导电薄膜之间。
所述柔性基材的材质选择可见光透过率大于80％的材料，可以为聚对苯二甲酸、乙二醇酯(PES)、聚醚砜(PES)、聚萘二甲酸乙二醇酯(PEN)、环烯烃共聚物(COC)或透明聚酰亚胺(PI)。所述柔性基材的厚度可以为0.1mm-0.5mm。
所述导电薄膜的材质可为聚(3,4-二氧乙基噻吩)/聚(对苯乙烯磺酸)(PEDOS:PSS)，PSS与PEDOS的质量比可以为1：20。所述导电薄膜的厚度可以为15μm-1100μm。
所述导电金属线层包括多根导电金属线,多根所述导电金属线排布于所述柔性基材，本实施例中，多根所述导电金属线网状排布于所述柔性基材。在一些实施例中，多根所述导电金属线也可以采用栅状排布。
所述导电金属线直径为10μm-1000μm，相邻的所述两根导电金属线之间的距离为0.2mm-10mm，所述导电金属线的材质可以为是金、银、铝、铜或镍。所述电极在所述柔性基材和所述导电薄膜之间设置所述导电金属线层，所述导电金属线层的多个导电金属线被导电薄膜覆盖包裹，形成一个内部的导电网络，降低了表面电阻，使得电极的导电能力得到提高。请一并参阅图3a和图3b，本申请其中一个实施例提供一种阵列基板的制造方法，需要说明的是，上述对阵列基板的实施方式的解释说明也适用于本实施方式的阵列基板的制备方法，为避免冗余，在此不再详细展开。需要说明的是，在下述各个实施例中，下述各步骤之间并不必然存在一定的先后顺序，本领域普通技术人员，根据本申请实施例的描述可以理解，不同实施例中，下述各步骤可以有不同的执行顺序， 亦即，可以并行执行，亦可以交换执行等等；不同实施例中，下述有些步骤亦可以省略或被代替。
所述阵列基板的制造方法包括：
步骤S31:在基底2上形成柔性基板3。
步骤S32:在所述柔性基板3上形成缓冲层4。
具体地，在所述柔性基板3上，采用等离子体增强化学气相沉积(Plasma Enhanced Chemical Vapor DeposiSion:筒称PECVD)方式、低压化学气相沉积方式(Low Pressure Chemical Vapor DeposiSion:筒称LPCVD)、大气压化学气相沉积(ASmospheric Pressure Chemical Vapor DeposiSion:筒称APCVD)方式或电子回旋谐振化学气相沉积(ElecSron CycloSron Resonance Chemical Vapor DeposiSion:筒称ECR-CVD)方式或溅射方式形成所述缓沖层4。所述缓冲层4的厚度范围为
Figure PCTCN2018123564-appb-000001
沉积温度小于或等于600℃。
所述缓冲层4的具体地制作方法为：将铜、铝靶材放入沉积腔室，通过溅射或者蒸镀在柔性基板3上沉积缓冲层4，并且在沉积时通入氮气或者氧气。该方法可以根据加入的原料的量，制作出铝原子占铜合金材料中总原子个数的原子百分比为0.05-30％、氮或氧占铜合金材料中总原子个数的原子百分比为0.05-30％、其余为铜的铜合金材料。此外，如果需要增加非铜非铝的金属元素，则可以将非铜非铝的金属与铜、铝一起放入沉积腔室，再通过溅射或者蒸镀在柔性基板3上沉积缓冲层4，并且在沉积时通入氮气或者氧气。
在一些实施例中，所述缓冲层4的具体地制作方法为也可以是：将氮或氧、铜、铝按照设定的原子比例制作成靶材，然后在柔性基板3上进行沉积以形成缓冲层4。例外，如果需要增加非铜非铝的金属元素，也可以将氮或氧、铜、铝和非铜非铝的金属按照设定的原子比例制作成靶材，然后进行沉积以形成缓冲层4。其中，所述缓冲层4可以为单层或多层结构，当为多层结构时，各层的材料可以相同或不相同。在一些实施方式中步骤S32可以省略，也即省略所述缓冲层4。
步骤S33:通过一次图案化工艺在所述缓冲层4上形成第一有源层 18。
请参阅图4a,具体地，在经过步骤S2的所述缓冲层4上形成第一金属氧化物半导体层，并对所述第一金属氧化物半导体层进行图案化，以形成所述第一有源层18。
具体地，通过溅射法在所述缓沖层4上形成所述第一金属氧化物半导体层。溅射所使用的靶材为高迁移率非晶铟镓锌氧化物(a-IGZO)靶材。经过图案化工艺形成的第一有源层18因为是由高迁移率非晶铟镓锌氧化物(a-IGZO)靶材溅射而成，从而其具有高的载流子迁移率。
所述图案化工艺可只包括光刻工艺，或包括光刻工艺以及刻蚀步骤，同时还可以包括打印、喷墨等其他用于形成预定图形的工艺；光刻工艺，是指包括成膜、曝光、显影等工艺过程的利用光刻胶、掩模板、曝光机等形成图形的工艺。可根据本申请实施例中所形成的结构选择相应的构图工艺。
在本实施例中，在所述第一金属氧化物半导体层上形成一层光刻胶，对光刻胶进行曝光和显影，然后对所述第一金属氧化物半导体层进行干法刻蚀，以形成所述第一有源层18。
在一些实施例中，步骤S31也可以省略，即直接在所述缓冲层4上形成所述第一有源层18。在另一些实施例中，步骤S31、步骤S32和步骤S33可用步骤S311代替，所述步骤S311为在所述基底2上形成所述第一有源层18。
步骤S34：通过一次图案化工艺在所述第一有源层18的相对两侧分别形成第一源电极12和第一漏电极14。
请参阅图4b,具体地，在经过步骤S3的所述第一有源层18和缓冲层4上采用磁控溅射、热蒸发或其它成膜方法沉积一层厚度约为
Figure PCTCN2018123564-appb-000002
的源漏金属层，在源漏金属层上涂覆一层光刻胶，采用掩膜板对光刻胶进行曝光，显影，使光刻胶形成光刻胶不保留区域和光刻胶保留区域，其中，光刻胶保留区域位于所述第一有源层18的相对两侧，光刻胶不保留区域为其他区域；通过刻蚀工艺完全刻蚀掉光刻胶不保留区域的源漏金属薄膜，剥离剩余的光刻胶，形成所述第一源电极12 和第一漏电极14。
步骤S35:在所述缓冲层4、所述第一有源层18、所述第一源电极12以及所述第一漏电极14上同时形成栅绝缘层6。
请参阅图4c,具体地，可以采用等离子体增强化学气相沉积(PECVD)方法，在经过步骤S4的所述缓冲层4、所述第一有源层18、所述第一源电极12以及所述第一漏电极14上沉积厚度约为
Figure PCTCN2018123564-appb-000003
的栅绝缘层6，其中，栅绝缘层6材料可以选用氧化物、氮化物或者氮氧化物，栅绝缘层6可以为单层、双层或多层结构。具体地，栅绝缘层6可以是SiNx，SiOx或Si(ON)x。
在一些实施例中，步骤S34和S35可用步骤S312代替，所述步骤S312为在所述第一有源层18上形成栅绝缘层6。
步骤S36:通过一次图案化工艺在所述栅绝缘层6上同时形成第一栅电极16和第二栅电极28，所述第一栅电极16位于所述第一有源层18的正上方，所述第一栅电极16和第二栅电极28间隔预设距离。
请参阅图4d,具体地，可以在经过步骤S5的所述栅绝缘层6上采用磁控溅射、热蒸发或其它成膜方法沉积一层厚度约为
Figure PCTCN2018123564-appb-000004
的栅金属层，在栅金属层上涂覆一层光刻胶，采用掩膜板对光刻胶进行曝光，显影，使光刻胶形成光刻胶不保留区域和光刻胶保留区域；通过刻蚀工艺刻蚀掉光刻胶不保留区域的栅金属层，剥离剩余的光刻胶，形成所述第一栅电极和所述第二栅电极，所述第一栅电极位于所述第一有源层的正上方，所述第二栅电极与所述第一栅电极间隔预设距离。
步骤S37:在所述第一栅电极16、所述第二栅电极28和所述栅绝缘层6上同时形成所述层间绝缘层5。
请参阅图4e,具体地，所述层间绝缘层5的厚度范围为
Figure PCTCN2018123564-appb-000005
与沉积所述栅绝缘层6的方式相同，可采用等离子体增强化学气相沉积方式、低压化学气相沉积方式、大气压化学气相沉积方式或电子回旋谐振化学气相沉积方式沉积形成所述层间绝缘层5,沉积温度小于或等于600℃。所述层间绝缘层5可采用单层的氧化硅材料或者氧化硅材料、氮化硅材料形成多个子层的叠层。
步骤S38:通过一次图案化工艺在所述层间绝缘层5上形成第二有源层26，所述第二有源层26设于所述第二栅电极28的正上方,其中所述第一有源层和所述第二有源层分别由不同的材料制得，进而使得所述第一有源层和所述第二有源层的电学性能不同。
请参阅图4f,具体地，通过溅射法在经过步骤S7的所述层间绝缘层5上形成第二金属氧化物半导体层。溅射所使用的靶材为普通非晶铟镓锌氧化物(a-IGZO)靶材。经过图案化工艺形成的第二有源层26因为是由普通非晶铟镓锌氧化物(a-IGZO)靶材溅射而成，从而所述第二金属氧化物的载流子迁移率低于所述第一金属氧化物的载流子迁移率。
所述图案化工艺可只包括光刻工艺，或包括光刻工艺以及刻蚀步骤，同时还可以包括打印、喷墨等其他用于形成预定图形的工艺；光刻工艺，是指包括成膜、曝光、显影等工艺过程的利用光刻胶、掩模板、曝光机等形成图形的工艺。可根据本申请实施例中所形成的结构选择相应的构图工艺。
在本实施例中，在所述第二金属氧化物半导体层上形成一层光刻胶，对光刻胶进行曝光和显影，然后对所述第二金属氧化物半导体层进行干法刻蚀，以形成所述第二有源层26。
步骤S39:通过一次图案化工艺在所述第二有源层26的相对两侧形成第二源电极22和第二漏电极24。
请参阅图4g,具体地，可以在经过步骤S38的所述第二有源层26和层间绝缘层5上采用磁控溅射、热蒸发或其它成膜方法沉积一层厚度约为
Figure PCTCN2018123564-appb-000006
的源漏金属层，在源漏金属层上涂覆一层光刻胶，采用掩膜板对光刻胶进行曝光，显影，使光刻胶形成光刻胶不保留区域和光刻胶保留区域，其中，光刻胶保留区域为所述第二有源层26的两侧和上方，光刻胶不保留区域为其他区域；通过刻蚀工艺完全刻蚀掉光刻胶不保留区域的源漏金属薄膜，剥离剩余的光刻胶，形成所述第二源电极22和第二漏电极24。
在一些实施例中，所述步骤S34可以调至步骤S37与步骤S38之间，即，在形成所述层间绝缘层5后，直接在所述层间绝缘层5上形成所述 第一源电极12和所述第一漏电极14，所述第一源电极12和所述第一漏电极14通过贯穿所述层间绝缘层5和栅绝缘层6的过孔分别与所述第一有源层18接触。在另一些实施例中，所述步骤S34也可以在步骤S38之后，即，第一源电极12、所述第一漏电极14和所述第二源电极22、所述第二漏电极24在由同一导电层同时图案化形成，所述第一源电极12和所述第一漏电极14通过贯穿所述层间绝缘层5和栅绝缘层6的过孔分别与所述第一有源层18接触。
请一并参阅图5a和图5b，本申请另一实施例提供一种阵列基板的制造方法，需要说明的是，上述对阵列基板的实施例的解释说明也适用于本实施例的阵列基板的制备方法，为避免冗余，在此不再详细展开。需要说明的是，在下述各个实施例中，下述各步骤之间并不必然存在一定的先后顺序，本领域普通技术人员，根据本申请实施例的描述可以理解，不同实施例中，下述各步骤可以有不同的执行顺序，亦即，可以并行执行，亦可以交换执行等等；不同实施例中，下述有些步骤亦可以省略或被代替。
所述阵列基板的制造方法包括：
步骤S51：在基底2上形成柔性基板3。
步骤S52：在所述柔性基板3上形成缓冲层4。
步骤S53：通过一次图案化工艺在所述缓冲层4上形成第一栅电极16。
请参阅图6a,具体地，可以在经过步骤S2的所述缓冲层4上采用磁控溅射、热蒸发或其它成膜方法沉积一层厚度约为
Figure PCTCN2018123564-appb-000007
的栅金属层，在栅金属层上涂覆一层光刻胶，采用掩膜板对光刻胶进行曝光，显影，使光刻胶形成光刻胶不保留区域和光刻胶保留区域，其中，光刻胶保留区域靠近所述缓冲层4的一端，光刻胶不保留区域为其他区域；通过刻蚀工艺完全刻蚀掉光刻胶不保留区域的栅金属层，剥离剩余的光刻胶，形成所述第一栅电极16。
在一些实施例中，步骤S51也可以省略，即直接在所述缓冲层4上形成所述第一栅电极16。在另一些实施例中，步骤S51、步骤52和步 骤53可用步骤S511代替，所述步骤S511为在基底上形成第一栅电极。
步骤S54：请参阅图6b,在所述第一栅电极16和所述缓冲层4上同时形成栅绝缘层6。
步骤S55：通过一次图案化工艺在所述栅绝缘层6上形成第一有源层18，所述第一有源层18正对应所述第一栅电极16。
请参阅图6c,具体地，通过溅射法在所述栅绝缘层6上形成第一金属氧化物半导体层。溅射所使用的靶材为高迁移率非晶铟镓锌氧化物(a-IGZO)靶材。经过图案化工艺形成的第一有源层18因为是由纯非晶铟镓锌氧化物(a-IGZO)靶材溅射而成，从而其具有高的载流子迁移率。
步骤S56：请参阅图6d，通过一次图案化工艺同时形成所述第一源电极12、第一漏电极14和第二栅电极28。所述第一源电极12和所述第一漏电极14分别与所述第一有源层18的相对两侧接触，所述第二栅电极28在与所述第一栅电极16间隔预设距离处形成。
步骤S57：请参阅图6e,在第一源电极12、第一漏电极14、第二栅电极28上和栅绝缘层6上同时形成层间绝缘层5。
步骤S58：通过一次图案化工艺在在所述层间绝缘层5上形成第二有源层26，所述第二有源层26位于所述第二栅电极28的正上方，其中所述第一有源层18和所述第二有源层26分别由不同的材料制得，进而使得所述第一有源层18和所述第二有源层26的电学性能不同；
请参阅图6f,具体地，通过溅射法在经过步骤S7的所述层间绝缘层5上形成所述第二金属氧化物半导体层。溅射所使用的靶材为普通非晶铟镓锌氧化物(a-IGZO)靶材。经过图案化工艺形成的第二有源层26因为是由普通非晶铟镓锌氧化物(a-IGZO)靶材溅射而成，从而所述第二金属氧化物的载流子迁移率低于所述第一金属氧化物的载流子迁移率。
步骤S59：通过一次图案化工艺在所述第二有源层26的相对两侧形成第二源电极22和第二漏电极24。
上述阵列基板可应用于一显示装置，该显示装置包括发光层及保护 层，所述发光层形成于所述阵列基板上方，所述保护层形成于所述发光层上方，所述阵列基板用于驱动所述发光层发光而使所述显示装置的实现显示功能。当然，所述阵列基板还可包括其他必要的电子元件以实现显示驱动，这些元件与现有技术相似，此处不再赘述。需要说明的是，当上述各阵列基板应用于柔性显示装置时，所述基底与所述柔性基板可进行剥离,可以是先将所述发光层及所述保护层依次形成于所述柔性基板上形成有上述第一、二薄膜晶体管的一侧后，再将所述基底与所述柔性基板进行剥离。
所述显示装置可通过设置诸如弯曲传感器之类，利用弯曲传感器检测的弯曲参数，以实现各类应用功能的执行，从而极大提升用户的体验感。
与现有技术相比较，本申请显示装置的阵列基板100或100a，通过同一种制备工艺，利用不同掺杂浓度或不同电学性能的靶材，同时在一种阵列基板100或100a上得到具有不同器件特性的薄膜晶体管器件，提高了生产效率，同时利于布局空间的使用。
最后应说明的是：以上实施例仅用以说明本申请的技术方案，而非对其限制；在本申请的思路下，以上实施例或者不同实施例中的技术特征之间也可以进行组合，步骤可以以任意顺序实现，并存在如上所述的本申请的不同方面的许多其它变化，为了简明，它们没有在细节中提供；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (20)

  1. 一种阵列基板的制造方法，其特征在于，
    在基底上形成第一有源层；
    在所述第一有源层上形成栅绝缘层；
    在所述栅绝缘层上同时形成间隔设置的第一栅电极和第二栅电极，所述第一栅电极位于所述第一有源层的正上方；
    在所述第一栅电极、所述第二栅电极和所述栅绝缘层上形成所述层间绝缘层；
    在所述层间绝缘层上形成第二有源层，所述第二有源层设于所述第二栅电极的正上方，其中所述第一有源层和所述第二有源层分别由不同的材料制得，进而使得所述第一有源层和所述第二有源层的电学性能不同；
    在所述第二有源层的相对两侧形成第二源电极和第二漏电极。
  2. 根据权利要求1所述的方法，其特征在于：
    所述在所述基底上形成第一有源层，包括：
    在所述基底上形成第一金属氧化物半导体层，并对所述第一金属氧化物半导体层进行图案化，以形成所述第一有源层。
  3. 根据权利要求2所述的方法，其特征在于：所述在所述层间绝缘层上形成第二有源层，包括：
    在所述层间绝缘层上形成第二金属氧化物半导体层，并对所述第二金属氧化物半导体层进行图案化，以形成所述第二有源层，所述第二金属氧化物的载流子迁移率低于所述第一金属氧化物的载流子迁移率。
  4. 根据权利要求1所述的方法，其特征在于：
    所述在所述第一有源层上形成栅绝缘层的步骤包括：在所述第一有源层的两相对侧分别形成第一源电极和第一漏电极，在所述第一有源 层、所述第一源电极和第一漏电极上形成栅绝缘层。
  5. 根据权利要求1所述的方法，其特征在于：
    所述在所述第一栅电极、所述第二栅电极和所述栅绝缘层上形成所述层间绝缘层之后，还包括：
    在所述层间绝缘层、所述栅绝缘层上形成与所述第一有源层的两侧对应的过孔，并且在所述层间绝缘层上同时形成第一源电极、第一漏极、所述第二源电极和所述第二漏电极，所述第一源电极和所述第一漏极分别通过所述过孔与所述第一有源层接触。
  6. 根据权利要求1所述的方法，其特征在于：
    所述在基底上形成第一有源层的步骤之前包括：
    在所述基底上形成柔性基板，所述第一有源层形成在所述柔性基板上。
  7. 根据权利要求6所述的方法，其特征在于：
    所述在基底上形成第一有源层的步骤之前还包括：
    在所述柔性基板上形成缓冲层，所述第一有源层形成在所述缓冲层上。
  8. 一种阵列基板的制造方法，其特征在于，
    在基底上形成第一栅电极；
    在所述第一栅电极上形成栅绝缘层；
    在所述栅绝缘层上形成正对应所述第一栅电极的第一有源层；
    在所述栅绝缘层、所述第一有源层上同时形成第一源电极、第一漏电极和第二栅电极，所述第一源电极和所述第一漏电极分别与所述第一有源层的相对两侧接触，所述第二栅电极在与所述第一栅电极间隔预设距离处形成；
    在所述第一源电极、所述第一漏电极、所述第二栅电极和所述栅绝 缘层上形成层间绝缘层；
    在所述层间绝缘层上形成第二有源层，所述第二有源层位于所述第二栅电极的正上方，其中所述第一有源层和所述第二有源层分别由不同的材料制得，进而使得所述第一有源层和所述第二有源层的电学性能不同；
    在所述第二有源层的相对两侧形成第二源电极和第二漏电极。
  9. 根据权利要求8所述的方法，其特征在于：
    所述在所述栅绝缘层上形成正对应所述第一栅电极的第一有源层，包括：在所述栅绝缘层上形成第一金属氧化物半导体层，并对所述第一金属氧化物半导体层进行图案化，以形成所述第一有源层。
  10. 根据权利要求9所述的方法，其特征在于：
    所述在所述层间绝缘层上形成第二有源层，包括：在所述层间绝缘层上形成第二金属氧化物半导体层，并对所述第二金属氧化物半导体层进行图案化，以形成所述第二有源层，所述第二金属氧化物的载流子迁移率低于所述第一金属氧化物的载流子迁移率。
  11. 根据权利要求8所述的方法，其特征在于：
    所述在基底上形成第一栅电极的步骤之前包括：
    在所述基底上形成柔性基板，所述第一栅电极形成在所述柔性基板上。
  12. 根据权利要求11所述的方法，其特征在于：
    所述在基底上形成第一栅电极的步骤之前还包括：
    在所述柔性基板上形成缓冲层，所述第一栅电极形成在所述缓冲层上。
  13. 一种阵列基板，其特征在于，包括：基底及形成于所述基底上 的第一有源层、第一栅电极、第一源电极、第一漏电极、第二有源层、第二栅电极、第二源电极、第二漏电极、栅绝缘层和层间绝缘层；所述第一有源层与所述第一栅电极正对设置，所述栅绝缘层位于所述第一有源层与所述第一栅电极之间以使二者相互绝缘；所述第一源电极与所述第一漏电极分别与所述第一有源层的相对两侧接触；所述第二有源层与所述第二栅电极正对设置，所述层间绝缘层位于所述第二有源层与所述第二栅电极之间以使二者相互绝缘设置；所述第二栅电极位于所述栅绝缘层与所述层间绝缘层之间；所述第二源电极与所述第二漏电极分别与所述第二有源层的相对两侧接触；所述第一有源层和所述第二有源层分别由不同的材料制得，进而使得所述第一有源层和所述第二有源层的电学性能不同。
  14. 根据权利要求13所述的阵列基板，其特征在于，
    所述第一有源层由高迁移率非晶铟镓锌氧化物靶材溅射而成，
    所述第二有源层由普通非晶铟镓锌氧化物靶材溅射而成，所述第一有源层的载流子迁移率高于所述第二有源层的载流子迁移率。
  15. 根据权利要求13所述的阵列基板，其特征在于，所述第一有源层位于所述栅绝缘层靠近所述基底的一侧。
  16. 根据权利要求15所述的阵列基板，其特征在于，
    所述第一源电极和所述第一漏电极位于所述栅绝缘层靠近所述第一有源层的一侧。
  17. 根据权利要求15所述的阵列基板，其特征在于，所述第一源电极和所述第一漏电极位于所述层间绝缘层远离所述基底的一侧，所述第一源电极、所述第一漏电极分别通过贯穿所述层间绝缘层和所述栅绝缘层的过孔，分别与所述第一有源层接触。
  18. 根据权利要求13所述的阵列基板，其特征在于，所述阵列基板还包括形成于所述基底上的柔性基板，所述第一有源层、所述第一栅电极、所述第一源电极、所述第一漏电极、所述第二有源层、所述第二栅电极、所述第二源电极、所述第二漏电极、所述栅绝缘层和所述层间绝缘层均形成于所述柔性基板上。
  19. 根据权利要求18所述的阵列基板，其特征在于，所述阵列基板还包括形成于所述柔性基板上的缓冲层，所述第一有源层、所述第一栅电极、所述第一源电极、所述第一漏电极、所述第二有源层、所述第二栅电极、所述第二源电极、所述第二漏电极、所述栅绝缘层和所述层间绝缘层均形成于所述缓冲层上。
  20. 一种显示装置，其特征在于，包括如权利要求13至19任一项所述的阵列基板。
PCT/CN2018/123564 2018-12-25 2018-12-25 阵列基板及其制造方法及显示装置 Ceased WO2020132880A1 (zh)

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