WO2020119641A1 - 阵列基板、显示面板及显示装置 - Google Patents

阵列基板、显示面板及显示装置 Download PDF

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Publication number
WO2020119641A1
WO2020119641A1 PCT/CN2019/124047 CN2019124047W WO2020119641A1 WO 2020119641 A1 WO2020119641 A1 WO 2020119641A1 CN 2019124047 W CN2019124047 W CN 2019124047W WO 2020119641 A1 WO2020119641 A1 WO 2020119641A1
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Prior art keywords
array substrate
floating
pins
pin
driving chip
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English (en)
French (fr)
Inventor
陈伟
纪飞林
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HKC Co Ltd
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HKC Co Ltd
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells

Definitions

  • the present application relates to the technical field of liquid crystal display, in particular to an array substrate, a display panel and a display device.
  • Thin film transistor liquid crystal display utilizes the change of electric field strength sandwiched on the liquid crystal layer to change the direction of liquid crystal molecules, thereby controlling the intensity of light transmission to display images.
  • the TFT-LCD array substrate has two architectures, one is a normal (Normal) architecture, and the other is a dual gate (Dual gate) architecture.
  • the dual gate line architecture increases the gate The number of lines reduces the number of data lines, thereby reducing the number of source driver chips used to transfer pixel data to the data lines, and increasing the number of gate driver chips, because the price of source driver chips on the market is higher than The gate drive chip, so compared with the conventional architecture, the cost of using a dual gate line architecture is lower.
  • the main purpose of this application is to propose an array substrate.
  • the array substrate proposed in this application is based on a dual-gate line architecture and includes:
  • the substrate is laid with data lines, and the number of said data lines is defined as N, then N ⁇ 6;
  • a source driving module is connected between the timing controller and the substrate.
  • the source driving module includes a first driving chip and a second driving chip.
  • the first driving chip includes a first output pin and a first A floating pin
  • the second driving chip includes a second output pin and a second floating pin
  • the number of the first output pins is x1
  • the number of the first floating pins is y1
  • the number of the second output pins is x2
  • the number of the second floating pins is y2
  • a first floating pin is provided on the first driving chip and a second floating pin is provided on the second driving chip, and the first output pin is added with the first floating pin
  • the number of pins is equal to the number of second output pins and second floating pins, so that when transmitting image data, only the timing controller needs to insert a certain amount of virtual into the image data transmitted to the source driver module Data is sent to the first floating pin and/or the second floating pin, so that the first driver chip and the second driver chip output the same amount of data, so that the sub-pixel data loss when the array substrate is displaying the screen can be avoided.
  • FIG. 1 is a schematic structural diagram of an array substrate with a display area pixel of 1366*768 and based on a double gate line architecture
  • FIG. 2 is a schematic diagram of data transmission between a timing controller and a source driving module in an embodiment of this application;
  • FIG. 3 is a schematic structural diagram of an array substrate in the embodiment shown in FIG. 2;
  • FIG. 4 is a schematic diagram of data transmission between a timing controller and a source driving module in another embodiment of the present application.
  • the directional indication is only set to be interpreted in a specific posture (as shown in the drawings) If the specific posture changes, the directional indication will change accordingly.
  • first”, “second”, etc. are only set for the purpose of description, and cannot be understood as instructions or hints Its relative importance or implicitly indicates the number of technical features indicated.
  • the features defined with “first” and “second” may include at least one of the features either explicitly or implicitly.
  • the meaning of “and/or” appearing throughout the text includes three parallel plans. Taking “A and/or B” as an example, it includes plan A, or plan B, or plans that both A and B satisfy.
  • FIG. 1 is a schematic diagram of an array substrate with a display area pixel of 1366*768 and based on a double-gate line architecture.
  • the array substrate has data lines 1 laid on it.
  • the display panel displays a picture of one pixel requires the array substrate to output information of 3 sub-pixels 7 (ie R/G/B) at the same time.
  • the conventional architecture since one data line 1 controls only one sub-pixel 7, the horizontal row
  • each source driver chip has a maximum of 1026 output channels, and the source driver chip and the data line 1 are connected through output pins, that is, a source driver chip can transmit data to a maximum of 1026 data lines 1, Therefore, in the double-gate line architecture of the 1366 pixel substrate, at least two source driver chips are required to transmit data information to 2049 data lines 1.
  • Mini-LVDS Mini Low Voltage Differential Signaling
  • Mini-LVDS has two buses, each of which carries the image data of the left half panel and the right half panel (that is, the two buses respectively transmit half the image data of the display area of the array substrate).
  • the timing controller 3 divides the data of one row of pixels into two parts and transmits them to the source driver chips responsible for the left half panel and the right half panel of the array substrate respectively. In this embodiment, the timing controller 3 The data will be transmitted to the two source driver chips separately.
  • both the output channel and the data line 1 are in units of positive integers. Therefore, in actual design, the two source driver chips will be connected to 1025 and 1024 data lines 1, respectively. Taking this case as an example, the R subpixel 7 of the 684th pixel is connected to the 1025th data line 1, and the G subpixel 7 and the B subpixel 7 of the 684th pixel are controlled by the 1026th data line 1.
  • the 1025th data line 1 can only send data to the B sub-pixel of the 683th pixel. 7 Transmit the voltage signal, so that when the array substrate is displaying the screen, the R sub-pixel 7 of the 684th pixel cannot be lit, resulting in the lack of image data; at the same time, the driver chip connected with 1024 data lines 1 cannot The data information carried by the 1024.5 data line 1 is completely output, so a pixel on the other half of the panel will also lack the image data of one sub-pixel 7, which results in the lack of screen information when the array substrate displays the image. Therefore, the double-gate line architecture cannot be adopted for the array substrate with a horizontal pixel of 1366, resulting in the high cost of the array substrate with a horizontal pixel of 1366.
  • the horizontal pixels referred to in this application do not limit the pixels in the horizontal direction on the array substrate, but refer to the pixels on the array substrate that are responsible for the transmission of the voltage signal by the data line 1. At the same time, through reasonable calculations, it can be known that any array substrate whose horizontal pixels cannot be divisible by 4 cannot use the double-gate line architecture for the above reasons.
  • the present application proposes an array substrate to solve the technical problem that a panel with horizontal pixels that cannot be divisible by 4 cannot use a double-gate line architecture.
  • the array substrate includes a timing controller 3, a substrate 9, and a source driving module 4, wherein the substrate 9 is laid with data lines 1, defining the data line 1 The quantity is N, then N ⁇ 6; the source driving module 4 is connected between the timing controller 3 and the substrate 9.
  • the source driving module includes a first driving chip 41 and a second driving chip 42, wherein the first driving chip 41 The first output pin 411 and the first floating pin 412 are included, and the second driving chip 42 includes the second output pin 422 and the second floating pin 421;
  • the number of the second output pins 422 is x2, and the number of the second floating pins 421 is y2;
  • the first output pin 411 described in this application refers to a pin that connects the first driving chip 41 to the data line 1 and can transmit the voltage signal of the sub-pixel 7, and the first floating pin 412 It means that the first driving chip 41 is connected to the data line 1, but the transmitted data cannot be displayed in the display area of the array substrate, or is neither connected to the data line 1, nor can the transmitted data be displayed in the display area of the array substrate
  • the first floating chip 412 is provided on the first driving chip 41 and the second floating pin 421 is provided on the second driving chip 42.
  • the number of output pins 411 plus the first floating pin 412 is equal to the number of the second output pin 422 and the second floating pin 421, so that when transmitting image data, only the timing controller 3 needs to drive to the source Insert virtual dummy data into the first floating pin 412 and/or the second floating pin 421 in the image data transmitted by the module 4, so that the first driving chip 41 and the second driving chip 42 output equal amounts of data, In this way, it is possible to avoid the phenomenon that the sub-pixel 7 data is missing when the array substrate is displaying the screen, thereby avoiding the loss of screen information, and thereby solving the problem that the double-gate line structure cannot be used in the TFT-LCD whose horizontal pixels cannot be divided by 4. The manufacturing cost of such TFT-LCD is reduced.
  • the virtual data referred to in this application refers to the data information inserted into the image data by the timing controller 3, which can be any form of data, but can only be directed to the first floating pin 412 and/or Or, the second floating pin 421 cannot be displayed in the display area of the array substrate.
  • an array substrate of 1366*768 pixels is used as an example to explain how to use the technical solution of the present application to make the array substrate whose horizontal pixels cannot be divided by 4 use a double-gate line architecture.
  • the timing controller 3 transmits the image data to the source driving module 4, it inserts 3 pieces of non-picture data virtual data into the received 2049 pieces of data to obtain temporary storage data occupying 2052 output channels, and Both of the temporary storage data are transmitted to the first driving chip 41 and the second driving chip 42 respectively.
  • the second driving chip 42 Since the number of the first output pins 411 of the first driving chip 41 is 1026, the second driving chip 42 The number of the two output pins 422 is 1023. Therefore, the three pieces of dummy data inserted by the timing controller 3 will be transmitted to the three second floating pins 421 of the second driving chip 42. Because the second floating pins 421 transmit The data will not be displayed in the display area of the array substrate. Therefore, the actual display screen of the array substrate is the same as the screen received by the timing controller 3, thereby avoiding the lack of screen information, and thus realizing the double grid line Structure, thereby reducing the manufacturing cost of the array substrate.
  • the technical solution of the present application can be used to implement a dual-gate line architecture.
  • the dangling pins provided in the source driver chip of this application are not limited to three, but different numbers of dangling pins can be inserted according to the specific horizontal pixels, regardless of the first dangling pin
  • the number of 412 or the second floating pin 421 can be adjusted adaptively according to the actual production application.
  • the technical solution disclosed in the present application is not limited to the array substrate with 1366 horizontal pixels.
  • the floating pin 421 is not provided, but the first floating pin 412 is not provided.
  • the advantage of this setting is that, first of all, please refer to FIG. 1 and FIG. 2, at this time, the three sub-pixels 7 of the 684th pixel are controlled by the 1025th data line 1 and the 1026th data line 1, respectively.
  • the first driving chip 41 is responsible for transmitting the image data of the left half of the display area of the array substrate.
  • the timing controller 3 Three copies of dummy data are inserted into the video transmitted by the second driving chip 42, so that three second floating pins 421 are correspondingly set on the second driving chip 42.
  • the timing controller 3 will increase the output frequency to increase the display of the array substrate
  • the refresh rate of the screen will increase the power consumption of the timing controller 3 and cause the temperature of the timing controller 3 to rise, which is not conducive to the performance of the timing controller 3. Therefore, all sub-pixels 7 of one pixel are transmitted by the same bus of Mini-LVDS, which can not only improve the stability of the screen display of the array substrate, but also reduce the power consumption and ensure the stability of the performance of the timing controller 3.
  • the first driving chip 41 and the second driving chip 42 may also be set by the following data to implement a dual-gate line architecture:
  • a plurality of second floating pins 421 are arranged adjacent to each other.
  • the timing controller 3 transmits the video data to the source driving module 4, it needs to insert the same amount of dummy data as the second dangling pin 421 through its own settings, and transfer the dummy data to the second dangling pin 421 Therefore, setting the plurality of second floating pins 421 adjacent to each other can reduce the calculation amount of the timing controller 3 to reduce the heat generation and energy consumption of the timing controller 3. And from the perspective of the manufacturing process, it is also simpler to arrange the plurality of second dangling pins 421 in an adjacent form, as compared to the discrete arrangement of the plurality of second dangling pins 421.
  • first floating pins 412 may also be arranged adjacent to each other.
  • plurality of second floating pins 421 may also be arranged discretely.
  • multiple second floating pins 421 are disposed on the same side of the second driving chip 42. Since the TFT-LCD display is opened line by line, when image data is transmitted on the source driver chip, it is transmitted from one side of the source driver chip to the other.
  • the second floating pin 421 is set on one side of the second floating pin 421, and when transmitting virtual data to the second driving chip 42, it is only necessary to insert the virtual at the beginning or end of the image data Only the data is required, the amount of calculation required is lower, and the energy consumption is relatively lower.
  • the physical positions of the plurality of second floating pins 421 are set on the same side of the second driving chip 42 as compared to the second driving pins 421 set on the second driving
  • the central position of the chip 42 is simpler, and it takes less time to manufacture the second driving chip 42.
  • the first floating pin 412 can also be set in the same manner as the second floating pin 421.
  • the second floating pin 421 may also be disposed in the middle of the second driving chip 42.
  • the data transmitted by the timing controller 3 is transmitted from the first driving chip 41 to the second driving chip 42, that is, the timing control is directed to the source driving module 4
  • the data transmitted is set to one-way transmission.
  • a plurality of second floating pins 421 are provided at the end of the second driving chip 42 close to the first driving chip 41. It can be understood that since the image data is unidirectionally transmitted, this can reduce the calculation amount of the timing controller 3 itself, so as to reduce the energy consumption of the timing controller 3.
  • the plurality of second floating pins 421 are arranged on the side of the second driving chip 42 close to the first driving chip 41, which is equivalent to the second floating pins 421 are arranged on the second driving chip 42 at the beginning of data transmission.
  • the second floating pin 421 may also be disposed at the end of the second driving chip 42 in the data transmission direction.
  • the image data may also be from the side where the first drive chip 41 and the second drive chip 42 are close to each other to the side where the first drive chip 41 and the second drive chip 42 are away from each other transmission.
  • the array substrate includes a display area and a non-display area.
  • the black matrix is used to block the light source.
  • the edge of the black matrix set in the non-display area is generally aligned with the display area.
  • the auxiliary pixel unit 6 (Dummy Pixel).
  • the design of the auxiliary pixel unit 6 is basically consistent with the structure of the pixel unit in the display area, but usually the TFT device in the auxiliary pixel unit 6 will be removed.
  • the second floating pin 421 is connected to the auxiliary pixel unit 6 through the connection line 5, so that the timing controller 3
  • the inserted virtual signal can be the same as or similar to the image data, simplify the operation difficulty of the timing controller 3 to realize the output of the virtual data, and at the same time reduce the design difficulty of the array substrate, so as to facilitate the manufacture of the array substrate and improve the quality of the product rate.
  • connection line 5 the material and the forming method of the connection line 5 are the same as those of the data line 1, which can further reduce the difficulty of manufacturing the array substrate and is suitable for mass production.
  • the connecting wire 5 can also be formed in other ways.
  • the second floating pin 421 may also be directly connected to the load, or may be indirectly connected to the load through the connection line 5, as long as the load does not cause the display of the array substrate screen The interference and influence are sufficient.
  • the load may be a resistance or the like.
  • the first floating pin 412 may also be connected to the auxiliary pixel unit 6 through the connection line 5.
  • the source driving module 4 when 2052 ⁇ N ⁇ 3078, the source driving module 4 further includes a third driving chip 43, which Located between the first driving chip 41 and the second driving chip 42, the third driving chip 43 includes a third output pin and a third floating pin 431, defining the number of the third output pin as x3, defining the third The number of three floating pins 431 is y3, then
  • " indicates the division, that is, "(x3+y3)
  • the array substrate needs to use three source driver chips to transfer data to the data line 1.
  • the data transmitted by the third driver chip 43 will be equally divided into In the display area of the left and right halves of the array substrate, in order to avoid the loss of screen information during transmission, a certain number of third floating pins 431 can be set in the third driver chip 43.
  • the timing controller 3 is in the source When the polar driver module 4 transmits image data, the same amount of dummy data as the third floating pin 431 is inserted and transmitted to the third floating pin 431 to balance the data output from the left and right sides of the third driving chip 43, so that Both the left and right sides of the three driving chips 43 can deliver complete image data, thereby avoiding the loss of image data during transmission.
  • the horizontal pixel conversion of the array substrate it is known that at least three source driver chips are required to control the data line 1 at this time.
  • the number of the third floating pins 431 is not limited to three, and can be adjusted adaptively according to actual production applications.
  • the third floating pin 431 may also be connected to The auxiliary pixel unit 6 is connected or directly connected to the load.
  • the third floating pin 431 can also be set in the same form as the first floating pin 412 or the second floating pin 421, such as multiple third The floating pins 431 are arranged in an adjacent form.
  • the present application also proposes a display panel including an array substrate.
  • the specific structure of the array substrate refers to the above embodiments. Since the display panel proposed by the present application adopts all the technical solutions of all the above embodiments, it has at least the above All the effects brought by the technical solutions of the embodiments will not be repeated here one by one.
  • the present application also proposes a display device including an array substrate.
  • the specific structure of the array substrate refers to the above embodiments. Since the display device proposed by the present application adopts all the technical solutions of all the above embodiments, it has at least the above All the effects brought by the technical solutions of the embodiments will not be repeated here one by one.

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Abstract

一种阵列基板、显示面板及显示装置，其中，阵列基板包括基板(9)以及源极驱动模块(4)，基板(9)上铺设有数据线(1)，定义数据线(1)的数量为N，则N不能被6整除；源极驱动模块(4)包括第一驱动芯片(41)及第二驱动芯片(42)，第一驱动芯片(41)包括第一输出引脚(411)及第一悬空引脚(412)，第二驱动芯片(42)包括第二输出引脚(422)及第二悬空引脚(421)，定义第一输出引脚(411)的数量为x1，第一悬空引脚(412)的数量为y1，第二输出引脚(422)的数量为x2，第二悬空引脚(421)的数量为y2，则x1+x2＝N；x1+y1＝x2+y2。

Description

阵列基板、显示面板及显示装置
相关申请的交叉引用
本申请要求2018年12月12日申请的，申请号为201811521945.2，名称为“阵列基板、显示面板及显示装置”的中国专利申请的优先权，在此将其全文引入作为参考。
技术领域
本申请涉及液晶显示技术领域，特别涉及一种阵列基板、显示面板及显示装置。
 背景技术
这里陈述的仅提供与本申请有关的背景信息，而不必然的构成限定性技术。
薄膜晶体管液晶显示器（Thin Film Transistor Liquid Crystal Display，TFT-LCD）是利用夹在液晶层上电场强度的变化，改变液晶分子的转向，从而控制透光的强弱来显示图像。
通常，TFT-LCD的阵列基板中具有两种架构，一种为常规（Normal）架构，另一种为双栅线（Dual gate）架构，与常规架构相比，双栅线架构增加了栅极线的数量，减少了数据线的数量，进而减少了用以向数据线传输像素数据的源极驱动芯片的数量，增加了栅极驱动芯片的数量，由于市面上源极驱动芯片的价格高于栅极驱动芯片，因此与常规架构相比，采用双栅线架构的成本更低。
但是当TFT-LCD的横排像素无法被4整除时，由于时序控制器（Timing Controller，TCON）与驱动芯片间通过微型低压差分信号（Mini Low Voltage Differential Signaling，Mini-LVDS）传输，当Mini-LVDS的输出信号为3对（pair）时，由于Mini-LVDS是双总线的拓扑结构，会导致该类TFT-LCD在显示画面时出现画面信息缺失的现象，导致该类TFT-LCD无法使用双栅线架构。
 技术解决方案
本申请的主要目的是提出一种阵列基板。
本申请提出的阵列基板，基于双栅线架构，包括：
时序控制器；
基板，铺设有数据线,定义所述数据线的数量为N，则N∤6；以及
源极驱动模块，连接于所述时序控制器与所述基板之间，所述源极驱动模块包括第一驱动芯片及第二驱动芯片，所述第一驱动芯片包括第一输出引脚及第一悬空引脚，所述第二驱动芯片包括第二输出引脚及第二悬空引脚，
定义所述第一输出引脚的数量为x1，所述第一悬空引脚的数量为y1，所述第二输出引脚的数量为x2，所述第二悬空引脚的数量为y2，则
x1+x2=N；
x1+y1=x2+y2。
本申请技术方案所提供的阵列基板，通过在第一驱动芯片上设置第一悬空引脚，在第二驱动芯片上设置第二悬空引脚的方式，通过使第一输出引脚加第一悬空引脚的数量与第二输出引脚与第二悬空引脚的数量相等，这样，在传输图像数据时，只需时序控制器在向源极驱动模块传输的图像数据中插入虚拟一定份的虚拟数据至第一悬空引脚和/或第二悬空引脚中，以使第一驱动芯片与第二驱动芯片输出等量数据，这样，就能避免阵列基板在显示画面时，出现子像素数据缺失的现象，从而避免画面信息的丢失，进而解决横排像素无法被4整除的TFT-LCD无法使用双栅线架构的问题，降低了此类TFT-LCD的制造成本。
 附图说明
为了更清楚地说明本申请实施例的技术方案，下面将对本申请实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图示出的结构获得其他的附图。
图1为显示区域像素为1366*768且基于双栅线架构的阵列基板的结构示意图
图2为本申请一实施例中时序控制器与源极驱动模块间的数据传输示意图；
图3为图2所示实施例中阵列基板的结构示意图；
图4为本申请另一实施例中时序控制器与源极驱动模块间的数据传输示意图。
本申请目的的实现、功能特点及优点将结合实施例，参照附图做进一步说明。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
需要说明，若本申请实施例中有涉及方向性指示（诸如上、下、左、右、前、后……），则该方向性指示仅设置为解释在某一特定姿态（如附图所示）下各部件之间的相对位置关系、运动情况等，如果该特定姿态发生改变时，则该方向性指示也相应地随之改变。
另外，若本申请实施例中有涉及“第一”、“第二”等的描述，则该“第一”、“第二”等的描述仅设置为描述目的，而不能理解为指示或暗示其相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。另外，全文中出现的“和/或”的含义为，包括三个并列的方案，以“A和/或B”为例，包括A方案，或B方案，或A和B同时满足的方案。另外，各个实施例之间的技术方案可以相互结合，但是必须是以本领域普通技术人员能够实现为基础，当技术方案的结合出现相互矛盾或无法实现时应当认为这种技术方案的结合不存在，也不在本申请要求的保护范围之内。
请参照图1所示，图1为显示区域像素为1366*768且基于双栅线架构的阵列基板的结构示意图，该阵列基板的基板上铺设有数据线1。通常，显示面板显示一个像素的画面需要阵列基板同时输出3个子像素7（即R/G/B）的信息，在常规架构中，由于一根数据线1只控制一个子像素7，因此横排像素为1366的阵列基板需要1366*3=4098根数据线1，而在双栅线架构中，由于一根数据线1能够控制两个子像素7，因此双栅线架构的阵列基板上只需要铺设1366*3/2=2049根数据信号。
一般而言，阵列基板要显示画面，需要时序控制器3将接收到的图像数据按一定的时间顺序排序，然后通过源极驱动芯片传递到每根数据线1上，为每个子像素7传递不同的电压信号，使每个子像素7以不同的亮度显示。这其中，每块源极驱动芯片最大拥有1026个输出通道，源极驱动芯片与数据线1之间通过输出引脚相连通，即一块源极驱动芯片最多可向1026根数据线1传输数据，因此在1366像素基板的双栅线架构中，需要至少两块源极驱动芯片，以向2049根数据线1传输数据信息。
再进一步，时序控制器3与驱动芯片之间的数据传输是通过微型低压差分信号（Mini Low Voltage Differential Signaling，Mini-LVDS）实现的。从拓扑结构上看，Mini-LVDS具有两根总线，每根总线分别携带左半面板与右半面板的图像数据（即两根总线分别传输阵列基板显示区域一半的图像数据）。在传输时，时序控制器3会将一行像素的数据均分为两份，分别传递给负责阵列基板左半面板及右半面板的源极驱动芯片，在本实施例中，时序控制器3的数据会分别传输给两块源极驱动芯片，那么，理论上每块源极驱动芯片接收到2049/2=1024.5份数据，即每块源极驱动芯片有1024.5个输出通道与数据线1相连接，但是实际上无论是输出通道还是数据线1都是以正整数为单位的。因此，在实际设计时，两块源极驱动芯片将分别连接1025根及1024根数据线1。以这种情况为例，第684个像素的R子像素7，与第1025根数据线1相连接，第684个像素的G子像素7、B子像素7由第1026根数据线1控制，而由于每块源极驱动芯片从时序控制器3处接收到的数据仅为1024.5根数据线1控制的像素数据，因此实际上第1025根数据线1仅能向第683个像素的B子像素7传输电压信号，这样就导致了阵列基板在显示画面时，第684个像素的R子像素7无法被点亮，从而导致了图像数据的缺失；同时连接有1024根数据线1的驱动芯片无法完整输出1024.5数据线1所承载的数据信息，因此另一半面板上的某个像素也会缺失一个子像素7的图像数据，这样就导致了阵列基板在显示图像时画面信息的缺失。因此，对于横排像素为1366的阵列基板无法采用双栅线架构，造成了这种横排像素为1366的阵列基板成本居高不下。
需要说明的是，本申请所指的横排像素并非限定阵列基板上水平方向上的像素，而是指阵列基板上由数据线1负责传输的电压信号的像素。同时，通过合理的计算可知，凡是横排像素无法被4整除的阵列基板，基于上述原因，均无法使用双栅线架构。
本申请提出一种阵列基板，旨在解决横排像素无法被4整除的面板无法使用双栅线架构的技术问题。
在本申请实施例中，请结合图2与图3所示，该阵列基板包括时序控制器3、基板9、以及源极驱动模块4，其中基板9铺设有数据线1，定义数据线1的数量为N，则N∤6；源极驱动模块4连接于时序控制器3与基板9之间，该源极驱动模包括第一驱动芯片41及第二驱动芯片42，其中第一驱动芯片41包括第一输出引脚411及第一悬空引脚412，第二驱动芯片42包括第二输出引脚422及第二悬空引脚421；
定义第一输出引脚411的数量为x1，第一悬空引脚412的数量为y1；
第二输出引脚422的数量为x2，第二悬空引脚421的数量为y2；
则，
x1+x2=N；
x1+y1=x2+y2。
需要说明的是，符号“∤”在数学中表示的意思为“不整除”，即“N∤6”表示的意思为N不能被6整除，由于数据线1的数量N=阵列基板的横排像素*3/2，因此N∤6即表示阵列基板的横排像素不能被4整除。
还需要说明的是，本申请中所述的第一输出引脚411指的是第一驱动芯片41与数据线1相连接并可传输子像素7电压信号的引脚，第一悬空引脚412是指第一驱动芯片41与数据线1相连接，但所传输的数据无法在阵列基板的显示区域中显示，或既不与数据线1连接，所传输的数据也无法在阵列基板的显示区域中显示的引脚。这其中，在本申请所公开的技术方案中，第一悬空引脚412或第二悬空引脚421的数量可设置为0。同时，由于第二输出引脚422与第一输出引脚411的功能相同，第二悬空引脚421与第一悬空引脚412的功能相同，此处不再赘述。
可以理解，本申请技术方案所提供的阵列基板，通过在第一驱动芯片41上设置第一悬空引脚412，在第二驱动芯片42上设置第二悬空引脚421的方式，通过使第一输出引脚411加第一悬空引脚412的数量与第二输出引脚422与第二悬空引脚421的数量相等，这样，在传输图像数据时，只需时序控制器3在向源极驱动模块4传输的图像数据中插入虚拟一定份的虚拟数据至第一悬空引脚412和/或第二悬空引脚421中，以使第一驱动芯片41与第二驱动芯片42输出等量数据，这样，就能避免阵列基板在显示画面时，出现子像素7数据缺失的现象，从而避免画面信息的丢失，进而解决横排像素无法被4整除的TFT-LCD无法使用双栅线架构的问题，降低了此类TFT-LCD的制造成本。
需要说明的是，本申请所指的虚拟数据，是指由时序控制器3插入至图像数据中数据信息，其可以为任何形式的数据，但是只能定向传输给第一悬空引脚412和/或第二悬空引脚421，因此无法在阵列基板的显示区域显示出来。
具体地，在本实施例中，以1366*768像素的阵列基板为例，解释通过本申请的技术方案如何使横排像素不能被4整除的阵列基板使用双栅线架构。此时，N=1366*3/2=2049，设置第一输出引脚411的数量x1=1026，第二输出引脚422的数量x2=1023，则第一悬空引脚412的数量y1=0，第二悬空引脚421的数量y2=3。
在进行视频输出时，时序控制器3实际收到的2049根数据线1图像数据，但是在本实施例中，第一驱动芯片41与第二驱动芯片42共有x1+y1+x2+y2=1026+0+1023+3=2052个输出引脚，即2052个输出通道的数据。此时，时序控制器3向源极驱动模块4传输图像数据时，会在收到的2049份数据中插入3份非画面数据的虚拟数据，得到占用为2052个输出通道的暂存数据，并将该暂存数据均为两份，分别传输给第一驱动芯片41及第二驱动芯片42，由于第一驱动芯片41的第一输出引脚411的数量为1026，第二驱动芯片42的第二输出引脚422的数量为1023，因此，时序控制器3所插入的3份虚拟数据会传输给第二驱动芯片42的3个第二悬空引脚421，由于第二悬空引脚421所传输的数据不会在阵列基板的显示区域显示，因此阵列基板的显示区域，实际所显示的画面与时序控制器3所接收到的画面一致，从而避免了画面信息的缺失，进而实现了双栅线架构，从而降低了阵列基板的制造成本。
从上述内容可知，无论阵列基板采用偶数块源极驱动芯片还是奇数块源极芯片与数据线1相连接，都可用本申请的技术方案实现双栅线架构，本申请奇数方案的核心在通过在源极驱动芯片中设置悬空引脚，并使时序控制器3在向源极驱动模块4传输数据时，插入一定量的虚拟数据，以使源极驱动模块4的左右两侧均能传输完整的图像数据。
需要说明的是，本申请在源极驱动芯片中所设置的悬空引脚并非限定为3个，而是可以根据具体横排像素的不同，插入不同数量的悬空引脚，无论第一悬空引脚412还是第二悬空引脚421的数量均可根据实际生产应用作出适应性的调整。
在本实施例中，数据线1的数量N=2049，即阵列基板的横排像素为1366，而在实际生产应用中，1366*768像素的阵列基板在便携计算机中的应用十分广泛，因此针对1366*768像素的阵列基板使用双栅线架构，具有广泛的应用场景，以及巨大的经济效益。当然，本申请所公开的技术方案，也并非仅针对于横排像素为1366的阵列基板。
请继续结合图2与图3所示，从前述内容可知，在本实施例中，x1=1026，y1=0，x2=1023，y2=3，即仅在第二驱动芯片42上设置第二悬空引脚421，而不设置第一悬空引脚412。这样设置的好处在于，首先，请结合图1与图2所示，此时，第684个像素的三个子像素7分别由第1025根数据线1及第1026根数据线1控制，由于在Mini-LVDS传输协议下，第一驱动芯片41负责传输阵列基板显示区域左半部分的图像数据，通过将第一输出芯片的第一输出引脚411设置为1026个，能够使第684个像素，即一个像素的所有子像素7由同一根总线传输，进而避免一个像素的子像素7通过不同的总线传输，相应的，为平衡Mini-LVDS两根总线中所传输的数据量，时序控制器3在向第二驱动芯片42传输的视频中插入3份虚拟数据，这样，第二驱动芯片42上就相应设置3个第二悬空引脚421。
需要说明的是，当一个像素的三个子像素7分别有Mini-LVDS的两根总线传输时，为使显示画面不出现撕裂感，时序控制器3会提高输出频率，以增加阵列基板所显示画面的刷新频率，这样会导致时序控制器3的功耗增加，同时导致时序控制器3的温度上升，不利于时序控制器3性能的发挥。因此使一个像素的所有子像素7由Mini-LVDS的同一根总线传输，不仅能够提高阵列基板画面显示的稳定性，同时能够降低功耗，保证时序控制器3性能发挥的稳定性。
还需要说明的是，在本申请的其他实施例中，针对横排像素为1366的阵列基板，还可通过如下数据设置第一驱动芯片41及第二驱动芯片42以实现双栅线架构：
（1）x1=1025,y1=0;x2=1024,y2=1;
（2）x1=1025,y1=1;x2=1024,y2=2。
再者，由于仅第二驱动芯片42上需设置有第二悬空引脚421，而无需在第一驱动芯片41上设置第一悬空引脚412，因此能够节约工程量，减少阵列基板的制造时间并降低成本。
可选地，请继续参照图2所示，在本实施例中，多个第二悬空引脚421相邻设置。由于时序控制器3在向源极驱动模块4传输视频数据时，需要通过自身的设置插入与第二悬空引脚421数量相同的虚拟数据，并将该虚拟数据定向传输给第二悬空引脚421，因此将多个第二悬空引脚421设置为相邻，能够减少时序控制器3的运算量，以降低时序控制器3的发热与能耗。且从制作工艺的角度而言，将多个第二悬空引脚421设置为相邻的形式，相较于多个第二悬空引脚421离散设置而言也更为简单。可以理解，在某些设置有第一悬空引脚412的实施例中，多个第一悬空引脚412也可相邻设置。需要说明的是，在本申请的其他实施例中，多个第二悬空引脚421也可离散分布设置。
可选地，多个第二悬空引脚421设置于第二驱动芯片42的同一侧。由于TFT-LCD显示屏是逐行打开的，图像数据在源极驱动芯片上进行传输时，是从源极驱动芯片的一侧传输向另一侧的。对于时序控制器3而言，将第二悬空引脚421设置于第二悬空引脚421的一侧，在向第二驱动芯片42传输虚拟数据时，只需在图像数据的始端或末端插入虚拟数据即可，所需要的运算量更低，能耗相对也更低。从第二驱动芯片42的制造工艺上来说，将多个第二悬空引脚421的物理位置设置于第二驱动芯片42的同一侧，相较于将第二悬空引脚421设置于第二驱动芯片42的中部位置而言更为简单，制造第二驱动芯片42所需要时间也更少。当然，对于第一悬空引脚412也可以用与第二悬空引脚421相同的方式设置。需要说明的是，在本申请的其他实施例中，第二悬空引脚421也可设置于第二驱动芯片42的中间。
可选地，请继续参照图2所示，在本实施例中，时序控制器3所传输的数据自第一驱动芯片41向第二驱动芯片42的方向传输，即时序控制向源极驱动模块4传输的数据设置为单向传输，相应的，多个第二悬空引脚421同设于第二驱动芯片42靠近第一驱动芯片41的一端。可以理解，由于图像数据单向传输的，这样可减少时序控制器3自身的计算量，以降低时序控制器3的能耗。而多个第二悬空引脚421同设于第二驱动芯片42靠近第一驱动芯片41的一侧，相当于第二悬空引脚421设置于第二驱动芯片42于数据传输的始端，这样，对于时序控制器3而言，插入并传输虚拟数据所需的运算量更低，有利于降低时序控制器3的功耗。需要说明的是，在其他实施例中，第二悬空引脚421也可设置于第二驱动芯片42上数据传输方向的末端。还需要说明的是，在其他实施例中，图像数据也可自第一驱动芯片41及第二驱动芯片42相互靠近的一侧向第一驱动芯片41及第二驱动芯片42相互远离的一侧传输。
可选地，阵列基板上铺设有连接线5，第二悬空引脚421通过连接线5与辅助像素单元6相连接。需要说明的是，一般而言，阵列基板包括显示区域与非显示区域，在阵列基板的显示区域中，彩膜基板的R、G、B三个子像素7之间、及非显示区域均设置有黑矩阵，以实现对光源的遮挡，非显示区域设置的黑矩阵的边缘一般与显示区域对齐。在阵列基板的设计中，各种设备在其动作起始端和动作结束端的均一性较差，而在其工作中间段的均一性较好，为了保证显示区域内各个像素单元的工艺的均一线，通常会在黑矩阵中设置辅助像素单元6（Dummy Pixel）。辅助像素单元6的设计基本与显示区域内的像素单元结构一致，但是通常辅助像素单元6内的TFT器件会被去除。
可以理解，由于辅助像素单元6本就存在于阵列基板内，且辅助像素单元6无法在显示区域显示，通过连接线5将第二悬空引脚421与辅助像素单元6相连接，使得时序控制器3插入的虚拟信号可以与图像数据相同或相近，简化时序控制器3的运算难度，以实现对虚拟数据的输出，同时能够降低阵列基板的设计难度，以便于阵列基板的制造，提高产品的良品率。
具体地，在本实施例中，连接线5的材质及形成方式与数据线1相同，这样可进一步降低阵列基板的制造难度，适合大批量生产。在其他实施例中，连接线5也可以其他方式形成。
需要说明的是，在本申请的其他实施例中，第二悬空引脚421也可直接与负载相连接，也可通过连接线5间接与负载相连接，只要该负载不对阵列基板画面的显示造成干扰与影响即可，示例性的，该负载可以为电阻等。
还需要说明的是，在本申请某些设置有第一悬空引脚412的实施例中，第一悬空引脚412也可通过连接线5与辅助像素单元6相连接。
请参照图4所示，可选地，在本申请的某一示例性实施例中，当2052<N<3078时，源极驱动模块4还包括第三驱动芯片43，该第三驱动芯片43位于第一驱动芯片41及第二驱动芯片42之间，该第三驱动芯片43包括第三输出引脚及第三悬空引脚431，定义该第三输出引脚的数量为x3，定义该第三悬空引脚431的数量为y3，则
x1=x2=1026，
x3=N-x1-x2，
（x3+y3）|2。
需要说明的是，在数学公式中，符号“|”标示的意思是整除，即“（x3+y3）|2”表明第三输出引脚与第三悬空引脚431的数量之和能够被2整除。同时，由于第三输出引脚的功能与第一输出引脚411相同，第三悬空引脚431的功能与第一悬空引脚412相同，此处不再赘述。
可以理解，当2052<N<3078时，阵列基板需要使用三块源极驱动芯片以向数据线1传输数据，根据Mini-LVDS传输方式，第三驱动芯片43所传输的数据会被均分至阵列基板的左右两半显示区域内，为避免传输过程中导致画面信息的丢失，可在第三驱动芯片43中设置一定数量的第三悬空引脚431，相同的，时序控制器3在向源极驱动模块4传输图像数据时，会插入与第三悬空引脚431数量相同的虚拟数据，并传输给第三悬空引脚431，以平衡第三驱动芯片43左右两侧输出的数据，使第三驱动芯片43的左右两侧均能输送完整的图像数据，进而避免图像数据在传输过程中缺失。
具体地，请继续参照图4所示，根据阵列基板的横排像素换算可知，此时需要至少3块源极驱动芯片控制数据线1。此时阵列基板上铺设的数据线1的数量N=1766*3/2=2649，此时x1=x2=1026，则第三输出引脚x3=N-x1-x2=2649-1026-1025=597，设置第三悬空引脚431的数量y3=3。于是，在实际传输数据的过程中第二驱动芯片42接收到的图像数据为597/2=298.5份，为避免传输过程中画面数据的丢失，我们在第三驱动芯片43中插入了3个第三悬空引脚431，同时设置时序控制器3在向第三驱动芯片43传输图像数据时，会插入3份虚拟数据，并将这3份虚拟数据传输至第三驱动芯片43的3个第三悬空引脚431中，进而平衡了第三驱动芯片43左右两侧传输的图像数据，进而避免了画面数据的丢失，从而实现双栅线架构。
需要说明的是，在本申请所公开的技术方案中，第三悬空引脚431的数量也并非限位为3个，也可根据实际生产应用作出适应性的调整。
还需要说明的是，与第一悬空引脚412或第二悬空引脚421相同，在本申请设置第三悬空引脚431的实施例中，第三悬空引脚431也可通过连接线5与辅助像素单元6相连接，或直接与负载相连接，显然，第三悬空引脚431也可与第一悬空引脚412或第二悬空引脚421以相同的形式设置，如将多个第三悬空引脚431设置为相邻的形式。
本申请还提出一种显示面板，该显示面板包括阵列基板，该阵列基板的具体结构参照上述实施例，由于本申请所提出的显示面板采用了上述所有实施例的全部技术方案，因此至少具有上述实施例的技术方案所带来的所有效果，在此不再一一赘述。
本申请还提出一种显示装置，该显示装置包括阵列基板，该阵列基板的具体结构参照上述实施例，由于本申请所提出的显示装置采用了上述所有实施例的全部技术方案，因此至少具有上述实施例的技术方案所带来的所有效果，在此不再一一赘述。
以上所述仅为本申请的可选实施例，并非因此限制本申请的专利范围，凡是在本申请的发明构思下，利用本申请说明书及附图内容所作的等效结构变换，或直接/间接运用在其他相关的技术领域均包括在本申请的专利保护范围内。

Claims (17)

  1. 一种阵列基板，基于双栅线架构，其中，包括：
    时序控制器；
    基板，铺设有数据线，定义所述数据线的数量为N，则N∤6；以及
    源极驱动模块，连接于所述时序控制器与所述基板之间，所述源极驱动模块包括第一驱动芯片及第二驱动芯片，所述第一驱动芯片包括第一输出引脚及第一悬空引脚，所述第二驱动芯片包括第二输出引脚及第二悬空引脚，
    定义所述第一输出引脚的数量为x1，所述第一悬空引脚的数量为y1，所述第二输出引脚的数量为x2，所述第二悬空引脚的数量为y2，则
    x1+x2=N；
    x1+y1=x2+y2。
  2. 如权利要求1所述的阵列基板，其中，所述N=2049，所述x1=1026，所述x2=1023。
  3. 如权利要求1所述的阵列基板，其中，所述N=2049，所述x1=1025，所述y1=0，所述x2=1024，所述y2=1。
  4. 如权利要求1所述的阵列基板，其中，所述N=2049，所述x1=1025，所述y1=1，所述x2=1024，所述y2=2。
  5. 如权利要求2所述的阵列基板，其中，多个所述第二悬空引脚相邻设置。
  6. 如权利要求2所述的整列基板，其中，多个所述第二悬空引脚离散分布设置。
  7. 如权利要求2所述的阵列基板，其中，多个所述第二悬空引脚同设于所述第二驱动芯片的一侧。
  8. 如权利要求7所述的阵列基板，其中，所述时序控制器的传输数据自所述第一驱动芯片向所述第二驱动芯片的方向传输，所述第二悬空引脚设置于所述第二驱动芯片靠近所述第一驱动芯片的一端。
  9. 如权利要求2所述的阵列基板，其中，多个所述第二悬空引脚设于所述第二驱动芯片的中间。
  10. 如权利要求1所述的阵列基板，其中，所述阵列基板上铺设有连接线，所述第二悬空引脚通过连接线与辅助像素单元相连接。
  11. 如权利要求10所述的阵列基板，其中，所述连接线与所述数据线材质相同。
  12. 如权利要求1所述的阵列基板，其中，所述第二悬空引脚与负载相连接。
  13. 如权利要求12所述的阵列基板，其中，所述负载为电阻。
  14. 如权利要求1所述的阵列基板，其中，所述阵列基板上铺设有连接线，所述第一悬空引脚通过所述连接线与辅助像素单元相连接。
  15. 如权利要求1所述的阵列基板，其中，当2052<N<3078时，所述源极驱动模块还包括第三驱动芯片，所述第三驱动芯片位于所述第一驱动芯片及所述第二驱动芯片之间，所述第三驱动芯片包括第三输出引脚及第三悬空引脚，定义所述第三输出引脚的数量为x3，所述第三悬空引脚的数量为y3，则
    x1=x2=1026；
    x3=N-x1-x2；
    （x3+y3）|2。
  16. 一种显示面板，其中，包括阵列基板，所述阵列基板基于双栅线架构，包括：时序控制器；
    基板，铺设有数据线,定义所述数据线的数量为N，则N∤6；以及
    源极驱动模块，连接于所述时序控制器与所述基板之间，所述源极驱动模块包括第一驱动芯片及第二驱动芯片，所述第一驱动芯片包括第一输出引脚及第一悬空引脚，所述第二驱动芯片包括第二输出引脚及第二悬空引脚，
    定义所述第一输出引脚的数量为x1，所述第一悬空引脚的数量为y1，所述第二输出引脚的数量为x2，所述第二悬空引脚的数量为y2，则
    x1+x2=N；
    x1+y1=x2+y2。
  17. 一种显示装置，其中，包括阵列基板，所述阵列基板基于双栅线架构，包括：时序控制器；
    基板，铺设有数据线,定义所述数据线的数量为N，则N∤6；以及
    源极驱动模块，连接于所述时序控制器与所述基板之间，所述源极驱动模块包括第一驱动芯片及第二驱动芯片，所述第一驱动芯片包括第一输出引脚及第一悬空引脚，所述第二驱动芯片包括第二输出引脚及第二悬空引脚，
    定义所述第一输出引脚的数量为x1，所述第一悬空引脚的数量为y1，所述第二输出引脚的数量为x2，所述第二悬空引脚的数量为y2，则
    x1+x2=N；
    x1+y1=x2+y2。
PCT/CN2019/124047 2018-12-12 2019-12-09 阵列基板、显示面板及显示装置 Ceased WO2020119641A1 (zh)

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