WO2020119559A1 - 显示面板的驱动架构及方法 - Google Patents

显示面板的驱动架构及方法 Download PDF

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Publication number
WO2020119559A1
WO2020119559A1 PCT/CN2019/123092 CN2019123092W WO2020119559A1 WO 2020119559 A1 WO2020119559 A1 WO 2020119559A1 CN 2019123092 W CN2019123092 W CN 2019123092W WO 2020119559 A1 WO2020119559 A1 WO 2020119559A1
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Prior art keywords
display panel
control chip
address
flash memory
circuit board
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PCT/CN2019/123092
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English (en)
French (fr)
Inventor
胡云川
赵文勤
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HKC Co Ltd
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HKC Co Ltd
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Publication of WO2020119559A1 publication Critical patent/WO2020119559A1/zh
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems

Definitions

  • the present application relates to the field of liquid crystal display, in particular to a driving structure and method of a display panel.
  • LCD( LCD) has the advantages of light, thin and low power consumption, and is generally recognized by the market and consumers.
  • the Mura erasing technology (De-mura technology) is applied to the LCD screen to improve the uniformity of the screen display brightness.
  • control circuit board of the LCD screen and the horizontal direction circuit panel are separately manufactured and sold.
  • the control circuit board (CB, Control The flash memory 1 (Flash1) on the board) stores the control chip, such as the initialization parameters and digital gamma of the timing controller (TCON, Timing Controller) Gamma) and over-driving technology (over driving) display lookup table (LUT, Look up Table). Since the actual situation of each display panel does not pass, the optical compensation data generated by the De-mura technology is stored on the horizontal direction circuit board (XB, referred to as X- Flash memory 2 (Flash2) of the board). After the TCON is powered on, the data stored in the flash memory (Flash1 and Flash2) is obtained through the interfaces (SPI1 and SPI2).
  • Flash manufacturers provide Flash products with capacity specifications of 2 Mbit and 8Mbit, if you want to buy other specifications of Flash, you need to order, the price is higher.
  • the total size of the data stored in the above Flash1 is less than 2 Mbit
  • the optical compensation data generated by De-mura technology is about 4 Mbit
  • the capacity of Flash1 is 2 Mbit Flash
  • the capacity of Flash2 is 8 Mbit Flash.
  • 8 Mbit Flash2 to store about 4 Mbit of data results in a waste of flash memory capacity.
  • the main purpose of the present application is to provide a driver-side architecture and method for a display panel, which aims to avoid a waste of flash memory capacity in the driver-side architecture of the display panel.
  • the present application provides a driving architecture for a display panel.
  • the driving architecture of the display panel has a control circuit board and a horizontal direction circuit board.
  • the control circuit board has a control chip in the horizontal direction circuit board.
  • a flash memory that stores the operation data of the control chip and the optical compensation data of the display panel.
  • control chip is connected to the flash memory through an interface.
  • the interface is a serial external interface.
  • the flash memory includes a first address and a second address.
  • the operation data of the control chip is stored in the first address; the optical compensation data of the display panel is stored in the first address and the first address In the second address.
  • the read priority of the first address is higher than that of the second address.
  • the first address is a low address
  • the second address is a high address
  • the operation data of the control chip includes at least one of initialization parameters of the control chip and a display lookup table of the function module.
  • the functional module includes at least one of digital gamma and overvoltage driving technology.
  • the driving structure of the display panel has a control circuit board and a horizontal direction circuit board;
  • the control circuit board has a timing control chip
  • the horizontal circuit board has a flash memory that stores operation data of the timing control chip and optical compensation data of the display panel;
  • the timing control chip is connected to the flash memory through an interface.
  • the flash memory includes a first address and a second address
  • the operation data of the timing control chip is stored in the first address
  • optical compensation data of the display panel is stored in the first address and the second address.
  • the operation data of the control chip includes at least one of the initialization parameters of the timing control chip and the display look-up table of the function module.
  • the present application also provides a driving method of a display panel, wherein the driving method of the display panel is based on a driving structure of the display panel, wherein the driving structure of the display panel has a control circuit board and a level A direction circuit board, the control circuit board has a control chip, and the horizontal direction circuit board has a flash memory that stores the operation data of the control chip and the optical compensation data of the display panel, and the driving method of the display panel includes The following steps:
  • the display panel is controlled to display images.
  • the operation data of the control chip and the optical compensation data stored in the flash memory are sequentially acquired through a serial external interface, wherein the operation data of the control chip and the optical compensation data are stored in Among the first address and the second address of the flash memory, the read priority of the first address is higher than that of the second address.
  • the operation data of the control chip includes at least one of initialization parameters of the control chip and a display lookup table of the function module.
  • the functional module includes at least one of digital gamma and overvoltage driving technology.
  • a driving structure and method for a display panel proposed in the embodiments of the present application, when the control chip is powered on, first obtain the operation data of the control chip stored in the flash memory, restore the working capacity of the control chip, and then obtain the storage in the flash memory
  • the optical compensation data of the display panel to overcome the defect of uneven display brightness in the display panel.
  • the display panel is controlled to display the received screen based on the acquired operation data and optical compensation data.
  • Store the operation data of the control chip and the optical compensation data of the display panel in the same flash memory and store the data stored in the two flash memories in the exemplary technology in the flash memory in the horizontal circuit board, which can reasonably use the capacity of the flash memory, To avoid the waste of flash memory capacity, while reducing one flash memory, saving the production cost of the display panel.
  • FIG. 1 is a schematic diagram of a driving structure of a display panel in an exemplary technology
  • FIG. 2 is a schematic diagram of a driving architecture in an embodiment of a driving architecture of a display panel of the present application
  • FIG. 3 is a schematic flowchart of an embodiment of a method for driving a display panel of the present application.
  • the display panel is controlled to display images.
  • the exemplary technology adopts a large-capacity flash memory to store data with a small occupied capacity, it leads to a waste of flash memory capacity.
  • This application provides a solution, when the control chip is powered on, first obtain the operation data of the control chip stored in the flash memory, restore the working capacity of the control chip, and then obtain the optical compensation data of the display panel stored in the flash memory To overcome the defect of uneven display brightness in the display panel. Furthermore, the display panel is controlled to display the received screen based on the acquired operation data and optical compensation data. Store the operation data of the control chip and the optical compensation data of the display panel in the same flash memory, and store the data stored in the two flash memories in the exemplary technology in the flash memory in the horizontal circuit board, which can reasonably use the capacity of the flash memory, To avoid the waste of flash memory capacity, while reducing one flash memory, saving the production cost of the display panel.
  • the driving structure of the display panel includes a control circuit board (CB, Control board) and horizontal circuit board (XB, X-board).
  • control chips in the control circuit board, such as timing control chips (TOCN, Timing Controller), etc., with flash memory (Flash2) in the horizontal circuit board.
  • TOCN timing control chips
  • Flash2 flash memory
  • the integrated circuit (IC, Integrated) of the control chip circuit) does not have a storage function, so the configuration parameters and other data required to control the chip work are stored in a specific storage integrated circuit, such as flash memory.
  • a specific storage integrated circuit such as flash memory.
  • the brightness display uniformity of each display panel and the display area are different, so the display panel is equipped with its applicable optical compensation data.
  • the control chip reads the optical compensation data can effectively overcome the display panel brightness. The defects are uniform and improve the picture quality.
  • the operation data of the control chip mainly includes the initialization parameters of the control chip and the display look-up table (LUT, Look up) of the function modules of the control chip Table).
  • the functional modules shown at least include digital gamma and over-voltage driving technology (over Driving).
  • the human visual system generally has a logarithmic relationship to the brightness or perception of the display, but a non-linear relationship.
  • gamma correction needs to be introduced into the display.
  • Gamma correction is implemented using a brightness look-up table. The brightness address is stored in the look-up table.
  • the gray scale of the picture is adjusted according to the look-up table to eliminate uneven brightness of the image and improve the image quality.
  • the look-up table is displayed through voltage drive technology
  • the driven gray scale can be obtained according to the input gray scale corresponding to the current frame image and the previous frame image, and the gray scale is output to the display panel to display the image.
  • the optical compensation data of the display panel is the Ram erasure compensation data generated by the algorithm of the Ram erasure technology (De-mura technology).
  • the storage size of the operating data of the control chip is about 4Mbit
  • the optical compensation data of the display panel is less than 2Mbit
  • the capacity of the flash memory (Flash2) in the horizontal direction circuit board is 8 Mbit. Therefore, in this application, the operation data of the control chip and the optical compensation data of the display panel configuration are stored in the flash memory (Flash 2) located on the horizontal circuit board, which can reasonably use the capacity of the flash memory and directly eliminate the need for exemplary technologies
  • the flash memory (Flash1) on the control circuit board in the drive frame of the display panel (as shown in FIG. 1) in the system saves the production cost of the display panel.
  • the control chip in the control circuit board is connected to the flash memory (Flash 2) in the horizontal circuit board through the interface.
  • the operating data of the control chip and the optical compensation data of the display panel are obtained from the flash memory through the interface to realize the display The image display function of the panel.
  • the operation data of the control chip is stored in the first address of the flash memory (Flash2)
  • the optical compensation data of the display panel is stored in the second address of the flash memory (Flash2)
  • the control chip reads the data
  • the first After the operation data in the address is restored the optical compensation data of the display panel in the second address is acquired after the operation capability of the control chip is restored, so as to eliminate the uneven brightness of the display panel. Therefore, the read priority of the first address is higher than that of the second address.
  • serial external interface SPI, Serial Peripheral interface
  • the interface used is preferably a serial external interface.
  • the display panel driving architecture provided by the present application reduces the flash memory (Flash1) located in the control circuit board, and stores the operation data of the control chip in the flash memory (Flash2) of the horizontal circuit board, thereby There is no need to connect the interface between the control chip and Flash1 (SPI1), so that the interface in the drive architecture is reduced from two to one (only SPI2 connected to Flash2 is required).
  • SPI1 Flash1
  • TOCN integrated circuit
  • the driving architecture of the display panel has a control circuit board and a horizontal direction circuit board, the control circuit board has a control chip, and the horizontal direction circuit board has a flash memory, and the operating data of the control chip and all The optical compensation data of the display panel is described.
  • the display panel driving architecture includes a control circuit board (CB, Control board) and horizontal circuit board (XB, X-board).
  • CB Control board
  • XB horizontal circuit board
  • TOCN Timing control chips
  • Flash2 flash memory
  • the operation data for the operation of the timing control chip and the optical compensation data matched with the display panel are stored. Due to the integrated circuit (IC, Integrated) of the timing control chip circuit) does not have a storage function, therefore, the timing control chip is connected to the Flash 2 through the interface, so that the flash memory stores configuration parameters and other data required by the timing control chip.
  • the timing control chip reads the optical compensation data can effectively overcome the display panel brightness Uneven defects improve picture quality.
  • the operation data of the timing control chip mainly includes the initialization parameters of the control chip and the display lookup table (LUT, Look) of the function module of the timing control chip up Table).
  • the functional modules shown at least include digital gamma and over-voltage driving technology (over Driving).
  • the human visual system generally has a logarithmic relationship to the brightness or perception of the display, but a non-linear relationship.
  • gamma correction needs to be introduced into the display.
  • Gamma correction is implemented using a brightness look-up table. The brightness address is stored in the look-up table.
  • the gray scale of the picture is adjusted according to the look-up table to eliminate uneven brightness of the image and improve the image quality.
  • the look-up table is displayed through voltage drive technology
  • the driven gray scale can be obtained according to the input gray scale corresponding to the current frame image and the previous frame image, and the gray scale is output to the display panel to display the image.
  • the optical compensation data of the display panel is the Ram erasure compensation data generated by the algorithm of the Ram erasure technology (De-mura technology).
  • the timing control chip in the control circuit board is connected to the flash memory (Flash2) in the horizontal direction circuit board through the interface.
  • the operation data of the timing control chip and the optical compensation data of the display panel are obtained from the flash memory through the interface To realize the image display function of the display panel.
  • the operation data of the timing control chip is stored in the first address of the flash memory (Flash2)
  • the optical compensation data of the display panel is stored in the second address of the flash memory (Flash2).
  • the control chip reads the data, the first After recovering the operation data of the timing control chip from the operating data in one address, the optical compensation data of the display panel in the second address is acquired to eliminate the uneven brightness of the display panel. Therefore, the read priority of the first address is higher than that of the second address.
  • serial external interface SPI, Serial Peripheral interface
  • the interface used is preferably a serial external interface.
  • a display panel driving architecture provided by the present application reduces the flash memory (Flash1) in the control circuit board, and stores the operation data of the timing control chip in the flash memory (Flash2) of the horizontal circuit board, There is no need to connect the interface between the timing control chip and Flash1 (SPI1), so that the interface in the drive architecture is reduced from two to one (only SPI2 that needs to be connected to Flash2).
  • SPI1 Flash1
  • TOCN integrated circuit
  • the driving structure of the display panel has a control circuit board and a horizontal direction circuit board, a timing control chip is provided in the control circuit board, a flash memory is provided in the horizontal direction circuit board, and the operating data of the control chip is stored in the flash memory and Optical compensation data of the display panel.
  • the timing control chip is connected with Flash2 through the interface, so that the configuration parameters and other data required by the timing control chip are stored in the flash memory.
  • an embodiment of a driving method of a display panel of the present application the driving method of the display panel includes:
  • Step S10 When the power-on signal is detected, sequentially obtain the operation data of the control chip in the flash memory and the optical compensation data of the display panel.
  • the driving structure includes a control circuit board (CB) and a horizontal direction circuit board (XB), and a control chip is stored in flash memory 1 (Flash1) on the control circuit board (TCON) initialization parameters, digital gamma (Digital gamma) and over-voltage drive technology (over Driving) display lookup table (LUT).
  • the optical compensation data generated by the De-mura technology is stored in the flash memory 2 (Flash 2) of the horizontal circuit board.
  • the driving architecture of the display panel provided by the present application includes a control circuit board and a horizontal direction circuit board. There is a control chip (TOCN) in the control circuit board, and a flash memory (Flash2) in the horizontal direction circuit board. In Flash2, the operation data for the operation of the control chip and the optical compensation data matched with the display panel are stored.
  • the integrated circuit of the control chip does not have a storage function, so the configuration parameters and other data required to control the chip work are stored in a specific storage integrated circuit, such as flash memory.
  • a specific storage integrated circuit such as flash memory.
  • the brightness display uniformity and display area of each display panel are different, so the display panel is equipped with its applicable optical compensation data.
  • the control chip reads the optical compensation data can effectively overcome the display panel brightness. The defects are uniform and improve the picture quality.
  • control chip When the control chip detects the power-on signal, it sequentially obtains the operation data from the flash memory (Flash2) to realize the basic operation function of the control chip and the optical compensation data of the display panel to overcome the uneven brightness of the display panel defect.
  • flash2 flash memory
  • the operation data of the control chip is stored in the first address of the flash memory (Flash2)
  • the optical compensation data of the horizontal direction circuit board is stored in the second address of the flash memory (Flash2), so that the control chip reads the Operating data and the optical compensation data.
  • Set the read priority of the first address to be higher than the second address, so that after the control chip is powered on, it first reads the operating data in the first address, and then obtains the optical compensation data of the display panel in the second address to eliminate The brightness of the display panel is uneven.
  • the control chip (TOCN) in the control circuit board is connected to the flash memory (Flash2) in the horizontal direction circuit board through the interface.
  • flash2 flash memory
  • Due to the serial external interface (SPI, Serial Peripheral interface) has the advantages of supporting duplex operation, simple operation and high data transmission rate.
  • the interface used is preferably a serial external interface.
  • step S20 the display panel is controlled to display images according to the operation data and the optical compensation data.
  • the operation data of the control chip mainly includes the initialization parameters of the control chip and the display look-up table of the function modules of the control chip.
  • the functional modules shown include at least, digital gamma (Digital gamma) and over-voltage drive technology (over Driving).
  • the human visual system has a logarithmic relationship to the brightness or perception of the display, but a non-linear relationship.
  • gamma correction needs to be introduced into the display.
  • the gray scale curve of the display is debugged to achieve the best visual effect.
  • Gamma correction is implemented using a brightness look-up table.
  • the brightness address is stored in the look-up table, and the gray scale of the picture is adjusted according to the look-up table to eliminate uneven brightness of the image and improve the image quality.
  • the look-up table is displayed through voltage drive technology
  • the driven gray scale can be obtained according to the input gray scale corresponding to the current frame image and the previous frame image, and the gray scale is output to the display panel to display the image.
  • the optical compensation data of the display panel is the Ram erasure compensation data generated by the algorithm of the Ram erasure technology (De-mura technology).
  • the basic working capacity of the control chip is started according to the initialization parameters of the control chip in the operation data, and then the screen display is realized according to the display lookup table of the function module in the operation data and the optical compensation data of the display panel.
  • the storage size of the operating data of the control chip is about 4Mbit
  • the optical compensation data of the display panel is less than 2Mbit
  • the capacity of the flash memory (Flash2) in the horizontal direction circuit board is 8 Mbit. Therefore, in this application, the operation data of the control chip and the optical compensation data of the display panel configuration are stored in the flash memory (Flash 2) located on the horizontal circuit board, which can reasonably use the capacity of the flash memory and directly eliminate the need for exemplary technologies
  • the flash memory (Flash1) on the control circuit board in the drive frame of the display panel (as shown in FIG. 1) in the system saves the production cost of the display panel.
  • the display panel driving architecture provided by the present application reduces the flash memory (Flash1) located in the control circuit board, and stores the operation data of the control chip in the flash memory (Flash2) of the horizontal circuit board, thereby There is no need to connect the interface between the control chip and Flash1 (SPI1), so that the interface in the drive architecture is reduced from two to one (only SPI2 connected to Flash2 is required).
  • SPI1 Flash1
  • TOCN integrated circuit
  • control chip when the control chip is powered on, it first obtains the operation data of the control chip stored in the flash memory, restores the working capability of the control chip, and then obtains the optical compensation data of the display panel stored in the flash memory to Overcome the defect of uneven display brightness in the display panel. Furthermore, the display panel is controlled to display the received screen based on the acquired operation data and optical compensation data. Store the operation data of the control chip and the optical compensation data of the display panel in the same flash memory, and store the data stored in the two flash memories in the exemplary technology in the flash memory in the horizontal circuit board, which can reasonably use the capacity of the flash memory, To avoid the waste of flash memory capacity, while reducing one flash memory, saving the production cost of the display panel.
  • the methods in the above embodiments can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware, but in many cases the former is better Implementation.
  • the technical solution of the present application can be embodied in the form of a software product in essence or part that contributes to the exemplary technology, and the computer software product is stored in a storage medium (such as ROM/RAM) as described above , Disk, CD), including several instructions to make a terminal device (which can be a mobile phone, computer, server, air conditioner, or network equipment, etc.) to perform the method described in each embodiment of the present application.

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Abstract

一种显示面板的驱动架构，其中所述显示面板的驱动架构具有控制电路板（CB）和水平方向电路板（XB），控制电路板（CB）中具有时序控制芯片（TOCN），水平方向电路板（XB）中具有存储时序控制器控制芯片（TOCN）的运行数据以及显示面板的光学补偿数据的闪存（Flash2）。

Description

显示面板的驱动架构及方法
相关申请
本申请要求2018年12月12日申请的，申请号为201811522481.7，名称为“显示面板的驱动架构及方法”的中国专利申请的优先权，在此将其全文引入作为参考。
技术领域
本申请涉及液晶显示领域，尤其涉及显示面板的驱动架构及方法。
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然地构成现有技术。
液晶显示屏（ LCD）具有轻薄低功耗等优点，普遍得到市场和消费者的认可。为满足人们对液晶显示屏显示图像的高画质要求，在液晶显示屏中应用姆拉擦除技术（De-mura技术）来提升画面显示亮度的均匀性。
通常，液晶显示屏的控制电路板和水平方向电路面板分开制造与销售，现有的适用于液晶显示屏的应用架构（如图1）中，在控制电路板（CB，Control board）上的闪存1（Flash1）中存储有控制芯片，如时序控制器（TCON，Timing Controller）的初始化参数、数字伽马（Digital gamma）以及过电压驱动技术（over Driving）的显示查找表（LUT，Look up Table）。由于每个显示面板的实际情况不通过，故将De-mura技术产生的光学补偿数据存储在水平方向电路板（XB，简称X- board）的闪存2（Flash2）中。在TCON上电后通过接口（SPI1和SPI2）获取闪存（Flash1和Flash2）中存储的数据。
根据市场需求，Flash生产厂家提供的Flash成品的容量规格有2 Mbit和8Mbit，若要购买其他规格的Flash则需要订购，价格较高。上述Flash1中存储的数据总大小小于2 Mbit，De-mura技术产生的光学补偿数据约4 Mbit，则Flash1采用的容量为2 Mbit的Flash，Flash2采用的容量为8 Mbit的Flash。采用8 Mbit的Flash2存储约4 Mbit的数据，导致闪存容量的浪费。
发明内容
本申请的主要目的在于提供一种显示面板的驱动方架构及方法，旨在避免显示面板的驱动方架构中闪存容量浪费。
为实现上述目的，本申请提供一种显示面板的驱动架构，所述显示面板的驱动架构具有控制电路板和水平方向电路板，所述控制电路板中具有控制芯片，所述水平方向电路板中具有存储所述控制芯片的运行数据以及所述显示面板的光学补偿数据的闪存。
可选的，所述控制芯片通过接口与所述闪存连接。
可选的，所述接口为串行外接接口。
可选的，所述闪存包括第一地址和第二地址所述控制芯片的运行数据存储在所述第一地址中；所述显示面板的光学补偿数据存储在所述第一地址和所述第二地址中。
可选的，所述第一地址的读取优先级高于所述第二地址。
可选的，所述第一地址为低地址，所述第二地址为高地址。
可选的，所述控制芯片的运行数据至少包括所述控制芯片的初始化参数以及功能模块的显示查找表中的一个。
可选的，所述功能模块至少包括数字伽马以及过电压驱动技术中的一个。
可选的，所述显示面板的驱动架构具有控制电路板和水平方向电路板；
所述控制电路板中具有时序控制芯片；
所述水平方向电路板中具有存储所述时序控制芯片的运行数据以及存储所述显示面板的光学补偿数据的闪存；
所述时序控制芯片通过接口与所述闪存连接。
可选的，所述闪存包括第一地址和第二地址；
所述时序控制芯片的运行数据存储在所述第一地址中；
以及，所述显示面板的光学补偿数据存储在所述第一地址和所述第二地址中。
可选的，所述控制芯片的运行数据至少包括所述时序控制芯片的初始化参数以及功能模块的显示查找表中的一个。
此外，为实现上述目的，本申请还提供一种显示面板的驱动方法，其中，所述显示面板的驱动方法基于显示面板的驱动架构，其中，所述显示面板的驱动架构具有控制电路板和水平方向电路板，所述控制电路板中具有控制芯片，所述水平方向电路板中具有存储所述控制芯片的运行数据以及所述显示面板的光学补偿数据的闪存，所述显示面板的驱动方法包括以下步骤：
检测到上电信号时，依次获取所述闪存中的所述控制芯片的运行数据以及所述显示面板的光学补偿数据；
根据所述运行数据和所述光学补偿数据控制所述显示面板进行画面显示。
可选的，通过串行外接接口依次获取所述闪存中存储的所述控制芯片的运行数据以及所述光学补偿数据，其中，所述控制芯片的运行数据与所述光学补偿数据存储分别存储在所述闪存的第一地址和第二地址中，所述第一地址的读取优先级高于所述第二地址。
可选的，所述控制芯片的运行数据至少包括所述控制芯片的初始化参数以及功能模块的显示查找表中的一个。
可选的，所述功能模块至少包括数字伽马以及过电压驱动技术中的一个。
本申请实施例提出的一种显示面板的驱动架构及方法在控制芯片上电时，首先获取闪存中存储的所述控制芯片的运行数据，恢复所述控制芯片的工作能力，再获取闪存中存储的显示面板的光学补偿数据，以克服显示面板中显示亮度不均的缺陷。进而根据获取到的运行数据和光学补偿数据控制显示面板对接收到的画面进行画面显示。在同一个闪存中存储控制芯片的运行数据和显示面板的光学补偿数据，将示例性技术中存储在两个闪存中的数据存储在水平方向电路板中的闪存中，能够合理利用闪存的容量，避免闪存容量的浪费，同时减少一个闪存，节省了显示面板的生产成本。
附图说明
图1为示例性技术中显示面板的驱动架构的示意图；
图2为本申请显示面板的驱动架构的一实施例中的驱动架构的示意图；
图3为本申请显示面板的驱动方法的一实施例的流程示意图。
本申请目的的实现、功能特点及优点将结合实施例，参照附图做进一步说明。
具体实施方式
应当理解，此处所描述的具体实施例仅仅用以解释本申请，并不用于限定本申请。
本申请实施例的主要解决方案是：
检测到上电信号时，依次获取所述闪存中的所述控制芯片的运行数据以及所述显示面板的光学补偿数据；
根据所述运行数据和所述光学补偿数据控制所述显示面板进行画面显示。
由于示例性技术中采用大容量的闪存存储占用容量小的数据，导致闪存容量的浪费。
本申请提供一种解决方案，在控制芯片上电时，首先获取闪存中存储的所述控制芯片的运行数据，恢复所述控制芯片的工作能力，再获取闪存中存储的显示面板的光学补偿数据，以克服显示面板中显示亮度不均的缺陷。进而根据获取到的运行数据和光学补偿数据控制显示面板对接收到的画面进行画面显示。在同一个闪存中存储控制芯片的运行数据和显示面板的光学补偿数据，将示例性技术中存储到两个闪存中的数据存储在水平方向电路板中的闪存中，能够合理利用闪存的容量，避免闪存容量的浪费，同时减少一个闪存，节省了显示面板的生产成本。
参照图2，本申请显示面板的驱动框架实施例中驱动框架的结构示意图。如图2所示，显示面板的驱动架构包括控制电路板（CB，Control board）和水平方向电路板（XB，X- board）。在控制电路板中有控制芯片，例如时序控制芯片（TOCN，Timing Controller）等，在水平方向电路板中具有闪存（Flash2）。在Flash2中存储着供控制芯片运行的运行数据以及与显示面板匹配的光学补偿数据。
由于控制芯片的集成电路（IC，Integrated circuit）不具有存储功能，故控制芯片工作所需要的配置参数等数据均存储在特定的存储集成电路中，如闪存。同时，每个显示面板的亮度显示均匀程度以及显示区域存在差异，故针对显示面板配置有其适用的光学补偿数据，在图像显示时，控制芯片读取该光学补偿数据能够有效克服显示面板亮度不均的缺陷，提高画面质量。
控制芯片的运行数据主要包括控制芯片的初始化参数和控制芯片的功能模块的显示查找表（LUT，Look up Table）。所示功能模块至少包括，数字伽马（Digital gamma）以及过电压驱动技术（over Driving）。人类的视觉系统对于显示器的亮度或感觉大致呈对数关系，而非线性关系，为保证显示器呈现的图像与原图像相同，在显示器中需要引入伽马校正。通过数字伽马的伽马校正对显示器的灰阶曲线进行调试，以达到最佳视觉效果。伽马校正是采用亮度查找表实现，在查找表中存储亮度的地址，根据查找表对图片灰阶进行调整，消除图像的亮度不均，提高图像的画质；通过电压驱动技术的显示查找表根据输入的本帧画面和上一帧画面所对应的灰阶即可得到驱动的灰阶，将此灰阶输出给显示面板，以显示画面。
显示面板的光学补偿数据为经过拉姆擦除技术（De-mura技术）的算法产生的拉姆擦除补偿数据。
通常，该控制芯片的运行数据的存储大小约4Mbit，显示面板的光学补偿数据小于2Mbit，而水平方向电路板中的闪存（Flash2）的容量为8 Mbit。因此，在本申请中，将控制芯片的运行数据和显示面板配置的光学补偿数据均存储在位于水平方向电路板的闪存（Flash2）中，能够合理利用闪存的容量，直接不再需要示例性技术中的显示面板的驱动框架（如图1所示）中控制电路板上的闪存（Flash1），节省了显示面板的生产成本。
控制电路板中的控制芯片通过接口与水平方向电路板中的闪存（Flash2）连接，在控制芯片上电时，通过接口从闪存中获取控制芯片的运行数据以及显示面板的光学补偿数据，实现显示面板的图像显示功能。其中，控制芯片的运行数据存储在闪存（Flash2）的第一地址中，显示面板的光学补偿数据存储在闪存（Flash2）的第二地址中，在控制芯片读取数据时，先读取第一地址中的运行数据，恢复控制芯片的工作能力之后，再获取第二地址中显示面板的光学补偿数据，以消除显示面板的亮度不均。故，第一地址的读取优先级高于第二地址。
此外，由于串行外接接口（SPI，Serial Peripheral interface）具有支持双工操作、操作简单、数据传输速率高等有点。在控制芯片通过接口读取闪存中存储的数据时，采用的接口以串行外接接口为佳。
与示例性技术相比，本申请提供的一种显示面板的驱动架构减少位于控制电路板中的闪存（Flash1），将控制芯片的运行数据存储在水平方向电路板的闪存（Flash2）中，从而无需连接控制芯片与Flash1的接口（SPI1），使得驱动架构中的接口由两条减为一条（仅需要与Flash2连接的SPI2）。选择只有一组的SPI块函数的程序中，使得控制芯片的集成电路（TOCN IC）封装面积减小，众所周知，芯片的体积越小价格越低，从而减少接口数量降低了控制芯片的集成电路的成本，提高显示面板的经济效益。
在本实施例中，显示面板的驱动架构具有控制电路板和水平方向电路板，控制电路板中具有控制芯片，水平方向电路板中具有闪存，在闪存中存储所述控制芯片的运行数据以及所述显示面板的光学补偿数据。将示例性技术中存储在两个闪存中的数据存储在水平方向电路板中的闪存中，能够合理利用闪存的容量，避免闪存容量的浪费，同时减少一个闪存，节省了显示面板的生产成本。
参照图2，在本申请显示面板的驱动架构另一实施例中，显示面板的驱动架构包括控制电路板（CB，Control board）和水平方向电路板（XB，X- board）。在控制电路板中有时序控制芯片（TOCN，Timing Controller），在水平方向电路板中具有闪存（Flash2）。在Flash2中存储着供时序控制芯片运行的运行数据以及与显示面板匹配的光学补偿数据。由于时序控制芯片的集成电路（IC，Integrated circuit）不具有存储功能，故，时序控制芯片通过接口与Flash2连接，以使闪存中存储时序控制芯片所需要的配置参数等数据。
同时，每个显示面板的亮度显示均匀程度以及显示区域存在差异，故针对显示面板配置有其适用的光学补偿数据，在图像显示时，时序控制芯片读取该光学补偿数据能够有效克服显示面板亮度不均的缺陷，提高画面质量。
时序控制芯片的运行数据主要包括控制芯片的初始化参数和时序控制芯片的功能模块的显示查找表（LUT，Look up Table）。所示功能模块至少包括，数字伽马（Digital gamma）以及过电压驱动技术（over Driving）。人类的视觉系统对于显示器的亮度或感觉大致呈对数关系，而非线性关系，为保证显示器呈现的图像与原图像相同，在显示器中需要引入伽马校正。通过数字伽马的伽马校正对显示器的灰阶曲线进行调试，以达到最佳视觉效果。伽马校正是采用亮度查找表实现，在查找表中存储亮度的地址，根据查找表对图片灰阶进行调整，消除图像的亮度不均，提高图像的画质；通过电压驱动技术的显示查找表根据输入的本帧画面和上一帧画面所对应的灰阶即可得到驱动的灰阶，将此灰阶输出给显示面板，以显示画面。
显示面板的光学补偿数据为经过拉姆擦除技术（De-mura技术）的算法产生的拉姆擦除补偿数据。
控制电路板中的时序控制芯片通过接口与水平方向电路板中的闪存（Flash2）连接，在时序控制芯片上电时，通过接口从闪存中获取时序控制芯片的运行数据以及显示面板的光学补偿数据，实现显示面板的图像显示功能。其中，时序控制芯片的运行数据存储在闪存（Flash2）的第一地址中，显示面板的光学补偿数据存储在闪存（Flash2）的第二地址中，在控制芯片读取数据时，先读取第一地址中的运行数据，恢复时序控制芯片的工作能力之后，再获取第二地址中显示面板的光学补偿数据，以消除显示面板的亮度不均。故，第一地址的读取优先级高于第二地址。
此外，由于串行外接接口（SPI，Serial Peripheral interface）具有支持双工操作、操作简单、数据传输速率高等有点。在时序时序控制芯片通过接口读取闪存中存储的数据时，采用的接口以串行外接接口为佳。
与示例性技术相比，本申请提供的一种显示面板的驱动架构减少位于控制电路板中的闪存（Flash1），将时序控制芯片的运行数据存储在水平方向电路板的闪存（Flash2）中，从而无需连接时序控制芯片与Flash1的接口（SPI1），使得驱动架构中的接口由两条减为一条（仅需要与Flash2连接的SPI2）。选择只有一组的SPI块函数的程序中，使得时序控制芯片的集成电路（TOCN IC）封装面积减小，众所周知，芯片的体积越小价格越低，从而减少接口数量降低了时序控制芯片的集成电路的成本，提高显示面板的经济效益。
在本实施例中，显示面板的驱动架构具有控制电路板和水平方向电路板，控制电路板中具有时序控制芯片，水平方向电路板中具有闪存，在闪存中存储所述控制芯片的运行数据以及所述显示面板的光学补偿数据。时序控制芯片通过接口与Flash2连接，以使闪存中存储时序控制芯片所需要的配置参数等数据。将示例性技术中存储在两个闪存中的数据存储在水平方向电路板中的闪存中，能够合理利用闪存的容量，避免闪存容量的浪费，同时减少一个闪存，节省了显示面板的生产成本。
参照图3，本申请显示面板的驱动方法一实施例，所述显示面板的驱动方法包括：
步骤S10，检测到上电信号时，依次获取所述闪存中的所述控制芯片的运行数据以及所述显示面板的光学补偿数据。
示例性技术中的显示面板的驱动架构（如图1）中，驱动架构包含控制电路板（CB）和水平方向电路板（XB），控制电路板上的闪存1（Flash1）中存储有控制芯片（TCON）的初始化参数、数字伽马（Digital gamma）以及过电压驱动技术（over Driving）的显示查找表（LUT）。在水平方向电路板的闪存2（Flash2）中存储De-mura技术产生的光学补偿数据。如图2所示，本申请提供的显示面板的驱动架构中包括控制电路板和水平方向电路板。在控制电路板中有控制芯片（TOCN），在水平方向电路板中具有闪存（Flash2）。在Flash2中存储着供控制芯片运行的运行数据以及与显示面板匹配的光学补偿数据。
由于控制芯片的集成电路（TOCN IC）不具有存储功能，故控制芯片工作所需要的配置参数等数据均存储在特定的存储集成电路中，如闪存。同时，每个显示面板的亮度显示均匀程度以及显示区域存在差异，故针对显示面板配置有其适用的光学补偿数据，在图像显示时，控制芯片读取该光学补偿数据能够有效克服显示面板亮度不均的缺陷，提高画面质量。
在控制芯片检查到上电信号时，依次从闪存（Flash2）中获取时序控制去的运行数据以实现控制芯片的基本运行功能，和显示面板的光学补偿数据，以克服显示面板的亮度不均的缺陷。
进一步的，将控制芯片的运行数据存储在闪存（Flash2）的第一地址中，水平方向电路板的光学补偿数据存储在闪存（Flash2）的第二地址中，以实现控制芯片分别读取所述运行数据和所述光学补偿数据。设置第一地址的读取优先级高于第二地址，以实现控制芯片在上电后，先读取第一地址中的运行数据，再获取第二地址中显示面板的光学补偿数据，以消除显示面板的亮度不均。
控制电路板中的控制芯片（TOCN）通过接口与水平方向电路板中的闪存（Flash2）连接。由于串行外接接口（SPI，Serial Peripheral interface）具有支持双工操作、操作简单、数据传输速率高等有点。在控制芯片通过接口读取闪存中存储的数据时，采用的接口以串行外接接口为佳。
步骤S20，根据所述运行数据和所述光学补偿数据控制所述显示面板进行画面显示。
控制芯片的运行数据主要包括控制芯片的初始化参数和控制芯片的功能模块的显示查找表。所示功能模块至少包括，数字伽马（Digital gamma）以及过电压驱动技术（over Driving）。人类的视觉系统对于显示器的亮度或感觉大致呈对数关系，而非线性关系，为保证显示器呈现的图像与原图像相同，在显示器中需要引入伽马校正。通过数字伽马的伽马校正对显示器的灰阶曲线进行调试，以达到最佳视觉效果。伽马校正是采用亮度查找表实现，在查找表中存储亮度的地址，根据查找表对图片灰阶进行调整，消除图像的亮度不均，提高图像的画质；通过电压驱动技术的显示查找表根据输入的本帧画面和上一帧画面所对应的灰阶即可得到驱动的灰阶，将此灰阶输出给显示面板，以显示画面。显示面板的光学补偿数据为经过拉姆擦除技术（De-mura技术）的算法产生的拉姆擦除补偿数据。
在控制芯片获取到运行数据后，根据运行数据中控制芯片的初始化参数启动控制芯片的基础工作能力，进而根据运行数据中的功能模块的显示查找表以及显示面板的光学补偿数据实现画面显示。
通常，该控制芯片的运行数据的存储大小约4Mbit，显示面板的光学补偿数据小于2Mbit，而水平方向电路板中的闪存（Flash2）的容量为8 Mbit。因此，在本申请中，将控制芯片的运行数据和显示面板配置的光学补偿数据均存储在位于水平方向电路板的闪存（Flash2）中，能够合理利用闪存的容量，直接不再需要示例性技术中的显示面板的驱动框架（如图1所示）中控制电路板上的闪存（Flash1），节省了显示面板的生产成本。
与示例性技术相比，本申请提供的一种显示面板的驱动架构减少位于控制电路板中的闪存（Flash1），将控制芯片的运行数据存储在水平方向电路板的闪存（Flash2）中，从而无需连接控制芯片与Flash1的接口（SPI1），使得驱动架构中的接口由两条减为一条（仅需要与Flash2连接的SPI2）。选择只有一组的SPI块函数的程序中，使得控制芯片的集成电路（TOCN IC）封装面积减小，众所周知，芯片的体积越小价格越低，从而减少接口数量降低了控制芯片的集成电路的成本，提高显示面板的经济效益。
在本实施例中，在控制芯片上电时，首先获取闪存中存储的所述控制芯片的运行数据，恢复所述控制芯片的工作能力，再获取闪存中存储的显示面板的光学补偿数据，以克服显示面板中显示亮度不均的缺陷。进而根据获取到的运行数据和光学补偿数据控制显示面板对接收到的画面进行画面显示。在同一个闪存中存储控制芯片的运行数据和显示面板的光学补偿数据，将示例性技术中存储在两个闪存中的数据存储在水平方向电路板中的闪存中，能够合理利用闪存的容量，避免闪存容量的浪费，同时减少一个闪存，节省了显示面板的生产成本。
需要说明的是，在本文中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者系统不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者系统所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者系统中还存在另外的相同要素。
上述本申请实施例序号仅仅为了描述，不代表实施例的优劣。
通过以上的实施方式的描述，本领域的技术人员可以清楚地了解到上述实施例方法可借助软件加必需的通用硬件平台的方式来实现，当然也可以通过硬件，但很多情况下前者是更佳的实施方式。基于这样的理解，本申请的技术方案本质上或者说对示例性技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品存储在如上所述的一个存储介质(如ROM/RAM、磁碟、光盘)中，包括若干指令用以使得一台终端设备(可以是手机，计算机，服务器，空调器，或者网络设备等)执行本申请各个实施例所述的方法。
以上仅为本申请的可选实施例，并非因此限制本申请的专利范围，凡是利用本申请说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本申请的专利保护范围内。

Claims (17)

  1. 一种显示面板的驱动架构，其中，所述显示面板的驱动架构具有控制电路板和水平方向电路板；
    所述控制电路板中具有控制芯片；
    所述水平方向电路板中具有存储所述控制芯片的运行数据以及存储所述显示面板的光学补偿数据的闪存。
  2. 如权利要求1所述的显示面板的驱动架构，其中，所述控制芯片通过接口与所述闪存连接。
  3. 如权利要求2所述的显示面板的驱动架构，其中，所述接口为串行外接接口。
  4. 如权利要求1所述的显示面板的驱动架构，其中，所述闪存包括第一地址和第二地址；
    所述控制芯片的运行数据存储在所述第一地址中；
    以及，所述显示面板的光学补偿数据存储在所述第一地址和所述第二地址中。
  5. 如权利要求4所述的显示面板的驱动架构，其中，所述第一地址的读取优先级高于所述第二地址。
  6. 如权利要求5所述的显示面板的驱动架构，其中，所述第一地址为低地址，所述第二地址为高地址。
  7. 如权利要求1所述的显示面板的驱动架构，其中，所述控制芯片的运行数据至少包括所述控制芯片的初始化参数以及功能模块的显示查找表中的一个。
  8. 如权利要求7所述的显示面板的驱动架构，其中，所述功能模块至少包括数字伽马以及过电压驱动技术中的一个。
  9. 如权利要求2所述的显示面板的驱动架构，其中，所述控制芯片的运行数据至少包括所述控制芯片的初始化参数以及功能模块的显示查找表中的一个。
  10. 如权利要求4所述的显示面板的驱动架构，其中，所述控制芯片的运行数据至少包括所述控制芯片的初始化参数以及功能模块的显示查找表中的一个。
  11. 一种显示面板的驱动架构，其中，所述显示面板的驱动架构具有控制电路板和水平方向电路板；
    所述控制电路板中具有时序控制芯片；
    所述水平方向电路板中具有存储所述时序控制芯片的运行数据以及存储所述显示面板的光学补偿数据的闪存；
    以及，所述时序控制芯片通过接口与所述闪存连接。
  12. 如权利要求11所述的显示面板的驱动架构，其中，所述闪存包括第一地址和第二地址；
    所述时序控制芯片的运行数据存储在所述第一地址中；
    以及，所述显示面板的光学补偿数据存储在所述第一地址和所述第二地址中。
  13. 如权利要求11所述的显示面板的驱动架构，其中，所述控制芯片的运行数据至少包括所述时序控制芯片的初始化参数以及功能模块的显示查找表中的一个。
  14. 一种显示面板的驱动方法，其中，所述显示面板的驱动方法基于显示面板的驱动架构，其中，所述显示面板的驱动架构具有控制电路板和水平方向电路板，所述控制电路板中具有控制芯片，所述水平方向电路板中具有存储所述控制芯片的运行数据以及所述显示面板的光学补偿数据的闪存，所述显示面板的驱动方法包括以下步骤：
    检测到上电信号时，依次获取所述闪存中的所述控制芯片的运行数据以及所述显示面板的光学补偿数据；
    根据所述运行数据和所述光学补偿数据控制所述显示面板进行画面显示。
  15. 如权利要求14中所述的显示面板的驱动方法，其中，通过串行外接接口依次获取所述闪存中存储的所述控制芯片的运行数据以及所述光学补偿数据，其中，所述控制芯片的运行数据与所述光学补偿数据存储分别存储在所述闪存的第一地址和第二地址中，所述第一地址的读取优先级高于所述第二地址。
  16. 如权利要求15中所述的显示面板的驱动方法，其中，所述控制芯片的运行数据至少包括所述控制芯片的初始化参数以及功能模块的显示查找表中的一个。
  17. 如权利要求16中所述的显示面板的驱动方法，其中，所述功能模块至少包括数字伽马以及过电压驱动技术中的一个。
PCT/CN2019/123092 2018-12-12 2019-12-04 显示面板的驱动架构及方法 Ceased WO2020119559A1 (zh)

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CN112908241A (zh) * 2021-03-01 2021-06-04 惠科股份有限公司 一种显示控制方法、装置、设备及标识码识别系统
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CN113506548B (zh) * 2021-06-29 2022-05-10 惠科股份有限公司 驱动装置、消除面板单端信号反射的方法及显示装置
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