WO2020119186A1 - 显示面板、像素电路及其驱动方法 - Google Patents

显示面板、像素电路及其驱动方法 Download PDF

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Publication number
WO2020119186A1
WO2020119186A1 PCT/CN2019/103380 CN2019103380W WO2020119186A1 WO 2020119186 A1 WO2020119186 A1 WO 2020119186A1 CN 2019103380 W CN2019103380 W CN 2019103380W WO 2020119186 A1 WO2020119186 A1 WO 2020119186A1
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Prior art keywords
pixel circuit
switch tube
circuit unit
tube
electroluminescent element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
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PCT/CN2019/103380
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English (en)
French (fr)
Inventor
范龙飞
王龙彦
朱晖
韩珍珍
胡思明
吴剑龙
张露
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Kunshan Govisionox Optoelectronics Co Ltd
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Kunshan Govisionox Optoelectronics Co Ltd
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Publication of WO2020119186A1 publication Critical patent/WO2020119186A1/zh
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix

Definitions

  • the present application relates to the field of display technology, in particular to a display panel, a pixel circuit and a driving method thereof.
  • AMOLED Active-matrix organic light-emitting diode
  • active matrix organic light-emitting diode or active matrix organic light-emitting diode (OLED) display screens are widely used in mobile phones and TVs due to their advantages of wide viewing angle and low power consumption.
  • OLED organic light-emitting diode
  • a technical solution adopted by the present application is to provide a pixel circuit including a driving chip, and a plurality of pixel circuit units and a plurality of detection circuit units connected to the driving chip, wherein each A detection circuit unit independently corresponds to a group of pixel circuit units arranged along the first direction, and is selectively coupled to each pixel circuit unit in the group of pixel circuit units.
  • the first direction is pixels arranged in an array The row direction or column direction of the circuit unit; wherein each pixel circuit unit includes at least a first switch tube and an electroluminescent element, a passage end of the first switch tube is electrically connected to the anode of the electroluminescent element, and the first switch tube
  • the control terminal is connected to the scanning signal terminal; each detection circuit unit includes at least a selection circuit, and the selection circuit includes at least a second switch tube, and the first path end of the second switch tube is connected to the electroluminescent element of the corresponding pixel circuit unit through the corresponding The anode, the control end of the second switch tube is connected to the first timing signal terminal, and the second path end of the second switch tube is connected to the driver chip; wherein, when the second switch tube in the detection circuit unit is in a conducting state and coupled to it When the first switch tube in the pixel circuit unit is also in the conductive state, the driving chip detects the potential of the anode of the electroluminescent element in the pixel circuit unit corresponding to the
  • the driving method includes: detecting the potential of the anode of the electroluminescent element in each pixel circuit unit The potential of the anode of the electroluminescent element is collected in the driving chip to form an anode voltage compensation signal; wherein each pixel circuit unit includes at least a first switch tube and an electroluminescent element; each detection circuit unit includes at least a selection circuit and a selection circuit At least a second switching tube; the step of detecting the potential of the anode of the electroluminescent element in each pixel circuit unit includes: inputting a first timing signal to control the second switching tube in the detecting circuit unit to turn on, and inputting a scanning signal to control the corresponding The first switch tube in the pixel circuit unit is turned on, so that the driving chip and the anode of the electroluminescent element in the corresponding pixel circuit unit are turned on, thereby obtaining the potential of the anode of the electrolum
  • the pixel circuit is the above pixel circuit, including: a driving chip, and A plurality of pixel circuit units and a plurality of detection circuit units connected to the driving chip, wherein each detection circuit unit independently corresponds to a group of pixel circuit units arranged along the first direction, and a group of pixel circuit units
  • Each pixel circuit unit is selectively coupled and connected, the first direction is the row direction or column direction of the pixel circuit units arranged in an array; wherein, each pixel circuit unit includes at least a first switch tube and an electroluminescent element, so A passage end of the first switch tube is electrically connected to the anode of the electroluminescent element, the control end of the first switch tube is connected to the scan signal terminal;
  • each detection circuit unit includes at least a selection circuit, and the selection circuit includes at least a second Switch, the first path end of the second switch is connected to the anode of the electro
  • the pixel circuit includes a driving chip, a plurality of pixel circuit units connected to the driving chip, and a plurality of detection circuit units.
  • the detection circuit unit is used to turn on the anode of the electroluminescent element in the driving chip and the corresponding pixel circuit unit . Therefore, it is convenient for the driving chip to obtain the anode potential of the electroluminescent element, which is convenient for the compensation of the anode potential in the subsequent display stage.
  • the circuit can be better integrated with the pixel circuit unit, the circuit structure is simple, and the circuit structure is convenient for the detection stage and The display stage is designed independently of each other so that the detection stage does not affect the display stage.
  • FIG. 1 is a schematic diagram of a circuit structure of a pixel circuit according to a first embodiment of this application;
  • FIG. 2 is a schematic diagram of a circuit structure of a pixel circuit according to a second embodiment of this application;
  • FIG. 3 is a schematic diagram of the principle of the structure of the double gate switch tube according to an embodiment of the present application.
  • FIG. 4 is a schematic flowchart of a driving method of a pixel circuit according to an embodiment of the present application
  • FIG. 5 is a specific flowchart of a display stage of a driving method of a pixel circuit according to an embodiment of the present application
  • FIG. 6 is a schematic structural diagram of a display panel according to an embodiment of the present application.
  • FIG. 1 is a schematic diagram of a circuit structure of a pixel circuit according to a first embodiment of the present application.
  • the pixel circuit includes a driving chip 10 and a plurality of pixel circuit units 20 and a plurality of detection circuit units 30 connected to the driving chip 10.
  • Each detection circuit unit 30 independently corresponds to a group of pixel circuit units 20 arranged along the first direction, and is selectively coupled to each pixel circuit unit 20 in the group of pixel circuit units 20.
  • the first direction is The row direction or column direction of the pixel circuit units 20 arranged in an array.
  • the first direction may be the column direction of the pixel circuit units arranged in an array.
  • 1 is only a schematic diagram, which only illustrates the connection relationship between one pixel circuit unit 20 and the detection circuit unit 30 of a plurality of pixel circuit units 20 in a row. It is not difficult to understand that the other pixel circuit units 20 in the row are connected to the The connection relationship of the detection circuit unit 30 is the same, which is not shown one by one in the figure.
  • Each pixel circuit unit 20 includes at least a first switch tube T1 and an electroluminescent element D.
  • a via terminal of the first switch tube T1 is electrically connected to the anode of the electroluminescent element D, and the control terminal of the first switch tube T1 is connected to the scan Signal (scan) end.
  • Each detection circuit unit 30 includes at least a selection circuit 31, and the selection circuit 31 includes at least a second switch T2, and the first path end of the second switch T2 is connected to it through a corresponding pixel circuit unit 20 (referring to the corresponding pixel circuit unit )
  • the control terminal of the second switch tube T2 is connected to the first timing signal (S1) terminal, and the second path terminal (as a connection terminal) of the second switch tube T2 is connected to the driver chip 10.
  • the corresponding pixel circuit unit refers to a pixel circuit unit in a conducting state with the detection circuit unit 30.
  • the driving chip 10 detects the first The potential of the anode of the electroluminescent element D in the pixel circuit unit 20 corresponding to a switch tube T1.
  • the first switch tubes T1 in each pixel circuit unit 20 arranged in the second direction are connected to the same scan signal terminal, that is, share the same scan signal scan, the second direction is different from the first direction, which is an array
  • the pixel circuit units 20 are arranged in a column direction or a row direction.
  • the second direction is the row direction of the pixel circuit units 20 arranged in an array.
  • each detection circuit unit 30 further includes a reset circuit 32, and the reset circuit 32 includes at least a third switch tube T3, and the first path end of the third switch tube T3 is connected to it through the corresponding pixel circuit unit 20 (referring to the Corresponding to the anode of the electroluminescent element D in the pixel circuit unit, the control terminal of the third switch tube T3 is connected to the second timing signal S2, and the second path terminal of the third switch tube T3 is connected to the reset signal (reset) terminal.
  • FIG. 2 is a schematic diagram of a circuit structure of a pixel circuit according to a second embodiment of the present application.
  • each pixel circuit unit 20 further includes a storage capacitor C and a current control drive tube (T5) coupled to the anode of the electroluminescent element D, the storage capacitor C is selectively coupled to the drive chip 10, and It is selectively coupled to the control end of the current control drive tube (T5), and is used to receive and store the anode voltage compensation signal from the drive chip 10, and control the current control drive tube (T5) according to the anode voltage compensation signal.
  • the first path end of the third switch tube T3 in each detection circuit unit 30 is selectively coupled to the storage capacitor C for selectively resetting the storage capacitor C.
  • By resetting the storage capacitor C it is beneficial to improve the storage accuracy of the storage capacitor C to the anode voltage compensation signal.
  • the pixel circuit unit 20 further includes a fourth switching tube T4, a fifth driving tube T5, a sixth switching tube T6, a seventh switching tube T7, an eighth switching tube T8, and a ninth switching tube T9, where the fifth The driving tube T5 is a current control driving tube.
  • the first path end of the fourth switch T4 is connected to the first working voltage VDD and the first end of the storage capacitor C, and the first end of the storage capacitor C is also connected to the first working voltage (VDD) end.
  • the second path end is connected to the first path end of the fifth drive tube T5 and the second path end of the ninth switch tube T9, and the first path end of the fifth drive tube T5 is also connected to the second path end of the ninth switch tube T9
  • the control terminal of the fourth switch T4 is connected to the enable signal (EM) terminal.
  • the second path end of the fifth driving tube T5 is connected to the first path end of the sixth switching tube T6 and the second path end of the seventh switching tube T7, and the first path end of the sixth switching tube T6 is also connected to the seventh switching tube
  • the second path end of T7; the control end of the fifth driving tube T5 is connected to the second end of the storage capacitor C.
  • the second path terminal of the sixth switch tube T6 is connected to the second path terminal of the first switch tube T1 and the anode of the electroluminescent element D, and the control terminal of the sixth switch tube T6 is connected to the enable signal (EM) terminal.
  • the first path terminal of the seventh switch tube T7 is connected to the control terminal of the fifth driving tube T5 and the second terminal of the storage capacitor, and the control terminal of the seventh switch tube T7 is connected to the third timing signal (S3) terminal.
  • the first path end of the eighth switch tube T8 is connected to the second end of the storage capacitor C, and the second path end of the eighth switch tube T8 is connected to the first path end of the first switch tube T1 and the first path of the second switch tube T2 And the first path end of the third switch T3, and the control end of the eighth switch T8 are connected to the fourth timing signal (S4) end.
  • the first path end of the ninth switch T9 is connected to the first path end of the fifth switch T5, the second path end of the ninth switch T9 is connected to the driver chip, and the first path end of the ninth switch T9 is also connected to the second The first path end of the switch T2 and the control end of the ninth switch T9 are connected to the third timing signal (S3) end.
  • the first terminal of the storage capacitor C is connected to the first operating voltage (VDD) terminal
  • the cathode of the electroluminescent element D is connected to the second operating voltage (VSS) terminal
  • the first path terminal of the second switching tube T2 is connected to the first switching tube T1
  • the second path end of the eighth switch tube T8 and the first path end of the third switch tube T3 connects the first path end of the first switch tube T1 and the second path end of the eighth switch tube T8.
  • the first switch tubes T1 in each pixel circuit unit 20 arranged in the second direction share the same scan signal (scan) terminal; the first switch tubes in each pixel circuit unit 20 arranged in the first direction T1 is independently connected to corresponding scanning signals; during the detection phase and the display phase, each pixel circuit unit 20 in the pixel circuit is scanned progressively along the first direction.
  • the third switch tube T3 in the detection circuit unit 30 shares the same second timing signal S2 and the same reset signal reset.
  • the control end of the second switch tube T2 in the detection circuit unit 30 is accessed according to the light emission color of the electroluminescent element D in the corresponding pixel circuit unit 20 Different first timing signals S1(R), S1(G) or S1(B).
  • the second path end of the second switch tube T2 in the detection circuit unit 30 is independently connected to different input and output pins Out(( 1), Out(2) or Out(3).
  • the first direction is the column direction and the second direction is the row direction.
  • the first switching transistors T1 in each pixel circuit unit 20 in the same row share the same scan signal scan; each pixel circuit unit in the same column
  • the first switch tubes T1 in 20 are independently connected to the corresponding scan signals, that is, they can not simultaneously receive the scan signals; during the detection phase and the display phase, each pixel circuit unit 20 in the pixel circuit is scanned row by row along the column direction.
  • the third switch tube T3 in the detection circuit unit 30 shares the same second timing signal S2 and the same reset signal reset.
  • the control terminal of the second switch tube T2 in the detection circuit unit 30 accesses different first timing signals S1(R according to the light emission color of the electroluminescent element D in the corresponding pixel circuit unit 20 ), S1(G) or S1(B); for each pixel circuit unit 20 in the same row, the second path end of the second switch tube T2 in the detection circuit unit 30 is independently connected to different input and output leads of the driving chip 10 Foot Out(1), Out(2) or Out(3).
  • each pixel circuit unit 20 corresponds to a sub-pixel unit of the display panel.
  • the three sub-pixel units from left to right in FIG. 2 are a red sub-pixel unit (R) and a green sub-pixel unit (G) ), blue sub-pixel unit (B).
  • the adjacent red, green, and blue sub-pixel units (RGB) form a pixel unit.
  • the red, green, and blue sub-pixel units (RGB) are mixed. Realize different display colors of the pixel unit.
  • the sub-pixel units of different colors located in the same row share one scan signal scan (that is, share the same scan line), share the same reset signal reset, and share the same second timing signal S2.
  • the connection terminals of the sub-pixel units of different colors are connected to the different input and output pins Out(1), Out(2) or Out(3) of the driving chip 10 in a one-to-one correspondence.
  • the control terminals of the second switch tubes T2 of the sub-pixel units of different colors are connected in a one-to-one correspondence with different first timing signals S1(R), S1(G) or S1(B).
  • FIG. 3 is a schematic diagram of the principle of the double-gate switch tube structure according to an embodiment of the present application.
  • the seventh switch tube T7 and the eighth switch tube T8 are both double-gate switch tubes.
  • the double-gate switch tube structure includes a first sub-switch tube T01 and a second sub-switch tube T02, and the first sub-switch tube T01 and The gate of the second sub-switch tube T02 is connected together as the control end of the double-gate switch tube structure, the first path end of the first sub-switch tube T01 is used as the first path end of the double-gate switch tube structure, and the second sub-switch tube
  • the second path end of T02 serves as the second path end of the double gate switch tube structure, and the second path end of the first sub switch tube T01 is connected to the first path end of the second sub switch tube T02.
  • the leakage current of the seventh switch tube T7 and the eighth switch tube T8 can be reduced, power consumption can be reduced, and the display effect of the electroluminescent element D can be improved.
  • the seventh switch tube T7 and the eighth switch tube T8 may also use single-gate MOS tubes, which is not limited in the embodiments of the present application.
  • Both T8 and the ninth switching tube T9 can be MOS tubes, which can be thin film transistors, and the first path terminal and the second path terminal are connected when the control terminal is connected to a low potential, and the first channel terminal is connected when the control terminal is connected to a high potential. One channel end and the second channel end are cut off.
  • the opposite configuration may be performed, for example, when the control terminal is connected to a low potential, the first path terminal and the second path terminal are cut off, and when the control terminal is connected to a high potential, the first path terminal and the second path terminal Turn on.
  • a P-type MOS tube is turned on when a low-potential signal is connected to the control terminal, and is turned off when a high-potential signal is connected;
  • an N-type MOS tube is turned on when a high-potential signal is connected to the control terminal, and is turned off when it is connected to a low potential.
  • One of the first and second path ends of T8 and the ninth switch T9 is the source, the other is the drain, and the respective control ends are all gates.
  • the electroluminescent element may be an OLED light-emitting element, specifically an AMOLED (Active-matrix organic light-emitting diode, active matrix organic light-emitting diode or active matrix organic light-emitting diode).
  • AMOLED Active-matrix organic light-emitting diode, active matrix organic light-emitting diode or active matrix organic light-emitting diode.
  • other electroluminescent elements may also be used, which is not limited in the embodiments of the present application.
  • FIG. 4 is a schematic flowchart of an embodiment of a driving method of a pixel circuit according to an embodiment of the present application.
  • the driving method of the pixel circuit may include:
  • Step S11 Detection stage: detect the potential of the anode of the electroluminescent element in each pixel circuit unit, and record the potential of the anode of the electroluminescent element in the driving chip to form an anode voltage compensation signal.
  • Each pixel circuit unit 20 includes at least a first switching tube T1 and an electroluminescent element D; each detection circuit unit 30 includes at least a selection circuit 31, and the selection circuit includes at least a second switching tube T2; each pixel is detected
  • the step of the potential of the anode of the electroluminescent element D in the circuit unit 20 may specifically include: inputting the first timing signal S1 to control the conduction of the first and second path ends of the second switching tube T2 in the detection circuit unit 30, The input scan signal scan controls the conduction of the first and second path ends of the first switch tube T1, so that the driving chip 10 and the anode of the electroluminescent element D in the corresponding pixel circuit unit 20 are connected, and then electroluminescence is acquired The potential of the anode of element D.
  • the potential of the first timing signal S1 and the potential of the second timing signal S2 may not be required, which can cause the electroluminescent element D to emit light, but in order to reduce the detection stage for electroluminescence For the influence of the element D, it is recommended that the potential of the first timing signal S1 and the potential of the second timing signal S2 be as small as possible.
  • first timing signal S1 there is no limit to the first timing signal S1 in this application, as long as the first timing signal S1 used in each detection stage is kept the same, and the second timing signal S2 used in each detection stage is kept the same, by Each time the potential difference of the anode of the electroluminescent element D is detected, an anode voltage compensation signal is formed.
  • Step S12 Display stage: the driving chip calls the anode voltage compensation signal and outputs the anode voltage compensation signal to the corresponding pixel circuit unit.
  • Each detection circuit unit 30 in the present application further includes a reset circuit 32, and the reset circuit 32 includes at least a third switch tube T3; optionally, detects the potential of the anode of the electroluminescent element D in each pixel circuit unit 20
  • the step further includes: before acquiring the potential of the anode of the electroluminescent element D in the corresponding pixel circuit unit 20, initializing the potential of the anode of the electroluminescent element D in advance.
  • the step of initializing the potential of the anode of the electroluminescent element D includes: inputting a second timing signal S2 to control the conduction of the first and second path ends of the third switching tube T3, and inputting a scan signal scan to control the first
  • the first path end and the second path end of the switch tube T1 are turned on, so that the reset signal (reset) end is connected to the anode of the electroluminescent element D in the corresponding pixel circuit unit 20, and then the anode of the electroluminescent element D To be initialized.
  • a second timing signal is input S2 controls the first path end and the second path end of the third switch tube T3 to continue conducting, so that the electroluminescent element D continues to emit light, thereby reducing the influence of the detection stage on the electroluminescent element D.
  • FIG. 5 is a specific flowchart of a display stage of an embodiment of a driving method of a pixel circuit according to an embodiment of the present application.
  • Each pixel circuit unit 20 further includes a storage capacitor C and a current control drive tube (T5) coupled to the anode of the electroluminescent element D.
  • the display stage may specifically include:
  • Step S121 Perform a signal writing process on the storage capacitor C in each pixel circuit unit 20.
  • the step of performing the signal writing process on the storage capacitor C in each pixel circuit unit 20 includes: controlling the second switch tube T2 in the detection circuit unit 30 to be in a conducting state, and controlling the second switch tube T2 and the corresponding pixel circuit
  • the circuit between the storage capacitors C in the unit 20 is in a conducting state, so that the driving chip 10 is electrically connected to the storage capacitor C in the corresponding pixel circuit unit 20, and then the anode voltage compensation signal in the driving chip 10 is output to the corresponding pixel circuit In the storage capacitor C in the unit 20.
  • the step of performing the signal writing process on the storage capacitor C in each pixel circuit unit 20 further includes (before signal writing) the step of initializing the storage capacitor C in the corresponding pixel circuit unit 20 in advance ;
  • the steps of initializing the storage capacitor C in the corresponding pixel circuit unit 20 include: controlling the third switch tube T3 in the detection circuit unit 30 to be in a conducting state, and controlling the third switch tube T3 and the corresponding pixel circuit unit 20 The circuit between the storage capacitors C is in a conducting state, so that the reset signal (reset) terminal is connected to the storage capacitor C in the corresponding pixel circuit unit 20, and then the storage capacitor C is initialized.
  • Step S122 driving the electroluminescent element D in each pixel circuit unit 20 to emit light.
  • the step of driving the electroluminescent element D in each pixel circuit unit 20 to emit light includes: releasing the current in the storage capacitor C to control the current control driving tube (T5) in the conductive state with the storage capacitor C in the open state , So that the corresponding electroluminescent element D is in a light-emitting state.
  • the step of driving the electroluminescent element D in each pixel circuit unit 20 to emit light further includes (before causing the electroluminescent element D to emit light) the pre-processing of the corresponding electroluminescent element D in the corresponding pixel circuit unit 20
  • the step of resetting the anode; the step of resetting the anode of the electroluminescent element D in the corresponding pixel circuit unit 20 includes: controlling the third switch tube T3 in the detection circuit unit 30 to be in a conducting state, and controlling the corresponding The first switch tube T1 in the pixel circuit unit 20 is in a conducting state, so that the reset signal (reset) terminal is connected to the anode of the electroluminescent element D in the corresponding pixel circuit unit 20, so that the corresponding electroluminescent element D The anode potential is reset.
  • the current control drive tube uses a reset signal used in the detection phase different from the reset signal used in the display phase.
  • the reset signal reset has a higher potential than the second operating voltage VSS, and the reset signal The voltage difference between reset and the second operating voltage VSS is greater than the turn-on voltage of the electroluminescent element D.
  • the potential of the reset signal reset is less than or equal to the potential of the second operating voltage VSS.
  • each pixel circuit unit 20 further includes a fourth switching tube T4, a fifth driving tube T5, a sixth switching tube T6, a seventh switching tube T7, an eighth switching tube T8, and a ninth switching tube T9.
  • the steps of initializing the storage capacitor in the corresponding pixel circuit unit include: controlling the enable signal EM to control the first and second path ends of the fourth switching transistor T4 to be turned off, and controlling the sixth path of the sixth switching transistor T6
  • the first channel end and the second channel end are cut off;
  • the scan signal scan is controlled to control the first path end and the second path end of the first switching tube T1 to be cut off;
  • the third timing signal S3 is controlled to control the seventh switching tube T7
  • the first path end and the second path end are cut off, and the first path end and the second path end of the ninth switching tube T9 are controlled to be cut off;
  • the second timing signal S2 is input to control the first path end and the third path of the third switching tube T3
  • the step of outputting the anode voltage compensation signal in the driving chip 10 to the storage capacitor in the corresponding pixel circuit unit includes: controlling the enable signal EM to control the first and second path ends of the fourth switch T4 to be cut off, and control The first and second path ends of the sixth switching tube T6 are cut off; the scan signal scan is controlled to control the first and second path ends of the first switching tube T1 to be cut off; the fourth timing signal S4 is controlled to control The first path end and the second path end of the eighth switch tube T8 are cut off; the third timing signal S3 is input to control the conduction of the first path end and the second path end of the seventh switch tube T7, and the ninth switch tube is controlled The first path end and the second path end of T9 are turned on so that the driving chip 10 writes the anode voltage compensation signal into the storage capacitor C.
  • the fifth driving tube T5 is also in a conducting state, because the storage capacitor C will retain a certain current after the initialization process is completed, and this part of the current will be input to the control terminal of the fifth driving tube to Control the conduction of the first and second path ends of the fifth driving tube T5.
  • the ninth switching tube T9, the fifth driving tube T5, and the seventh switching tube T7 are all in the conducting state, and the driving chip 10 can turn the anode The voltage compensation signal is written into the storage capacitor C.
  • the step of resetting the anode of the electroluminescent element D in the corresponding pixel circuit unit 20 includes: controlling the enable signal EM to control the first and second path ends of the fourth switch T4 to be cut off, and controlling the first The first and second path ends of the six switching tubes T6 are turned off; the third timing signal S3 is controlled to control the first and second path ends of the seventh switching tube T7 to be turned off, and the ninth switching tube T9 is controlled The first path end and the second path end are turned off; the fourth timing signal S4 is controlled to control the first path end and the second path end of the eighth switching tube T8 to be turned off, and the scan signal scan is input to control the first switching tube T1 The first path end and the second path end are turned on; a second timing signal is input to control the first path end and the second path end of the third switch tube T3 so that the reset signal resets the anode potential of the electroluminescent element D Reset.
  • the step of making the corresponding electroluminescent element D in a light-emitting state includes: controlling the scan signal scan to control the first and second path ends of the first switching tube T1 to be cut off; controlling the third timing signal S3 to control the seventh switching tube The first path end and the second path end of T7 are cut off, and the first path end and the second path end of the ninth switch tube T9 are controlled to be cut off; the fourth timing signal S4 is controlled to control the first path of the eighth switch tube T8 End and the second path end are cut off; input enable signal EM to control the first path end and the second path end of the fourth switching transistor T4 to conduct, and control the first path end and the second path of the sixth switching transistor T6 The terminal is turned on, so that the electroluminescent element D emits light.
  • the driving method provided by the present application is a continuous process. Specifically, the scan signal scan is controlled to scan each pixel circuit unit 20 arranged along the first direction line by line (second direction), and to the same line (second Direction) each pixel circuit unit 20 performs storage capacitor C initialization, storage capacitor C signal writing, anode potential reset of the electroluminescent element D, and electroluminescent element D light emission at the same time; ) The pixel circuit unit 20 in order to initialize the storage capacitor C, write the storage capacitor C signal, reset the anode potential of the electroluminescent element D, and emit light from the electroluminescent element D; that is, the pixel circuit unit in the fourth column When the storage capacitor C in 20 is initialized, the storage capacitor C in the third column of the pixel circuit unit 20 where the storage capacitor C is initialized is signal-written, and the second column of the pixel circuit unit 20 in which the storage capacitor C signal is written is signal-written The anode potential of the electroluminescent element D in is reset, and the electroluminescent element D in
  • FIG. 6 is a schematic structural diagram of a display panel according to an embodiment of the present application.
  • the display panel includes a substrate 41 and a pixel circuit 42 provided on the substrate 41.
  • the pixel circuit 42 may be the pixel circuit in any of the above embodiments.
  • the substrate 41 may be a hard substrate or a flexible substrate, which is not limited in the embodiments of the present application.
  • the pixel circuit includes a driving chip, a plurality of pixel circuit units connected to the driving chip, and a plurality of detection circuit units.
  • the detection circuit unit is used to turn on the anode of the electroluminescent element in the driving chip and the corresponding pixel circuit unit . Therefore, it is convenient for the driving chip to obtain the anode potential of the electroluminescent element, which is convenient for the compensation of the anode potential in the subsequent display stage.
  • the circuit can be better integrated with the pixel circuit unit, the circuit structure is simple, and the circuit structure is convenient for the detection stage and The display stage is designed independently of each other so that the detection stage does not affect the display stage.

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Abstract

一种显示面板、像素电路(42)及其驱动方法，其中像素电路(42)包括驱动芯片(10)以及若干个像素电路单元(20)和若干个侦测电路单元(30)，每一侦测电路单元(30)分别独立的对应沿第一方向排布的一组像素电路单元(20)，每一像素电路单元(20)至少包括第一开关管(T1)和电致发光元件(D)，第一开关管(T1)的一通路端与电致发光元件(D)的阳极电连接，第一开关管(T1)的控制端连接扫描信号(scan)端；每一侦测电路单元(30)至少包括选择电路(31)，选择电路(31)至少包括第二开关管(T2)，第二开关管(T2)的第一通路端通过对应像素电路单元(20)连接其中的电致发光元件(D)的阳极，第二开关管(T2)的控制端连接第一时序信号(S1(R)、S1(G)、S1(B))端，第二开关管(T2)的第二通路端连接驱动芯片(10)。像素电路(42)能够提高显示面板的显示效果，提高显示面板的使用寿命。

Description

显示面板、像素电路及其驱动方法 【技术领域】
本申请涉及显示技术领域，具体涉及一种显示面板、像素电路及其驱动方法。
【背景技术】
AMOLED(Active-matrix organic light-emitting diode，有源矩阵有机发光二极体或主动矩阵有机发光二极体)显示屏由于广视角、低功耗等优势被大量应用于手机、电视中。
然而，随着时间的流逝，OLED(organic light-emitting diode，有机发光二极体)的效率也会快速衰退，这将导致屏体亮度逐渐降低，从而影响显示面板的显示效果以及使用寿命。
【发明内容】
为解决上述技术问题，本申请采用的一技术方案是：提供一种像素电路，该像素电路包括驱动芯片、以及与驱动芯片连接的若干个像素电路单元和若干个侦测电路单元，其中，每一侦测电路单元分别独立的对应沿第一方向排布的一组像素电路单元，并与一组像素电路单元中每一像素电路单元选择性耦合连接，第一方向为呈阵列排布的像素电路单元的行方向或列方向；其中，每一像素电路单元至少包括第一开关管和电致发光元件，第一开关管的一通路端与电致发光元件的阳极电连接，第一开关管的控制端连接扫描信号端；每一侦测电路单元至少包括选择电路，选择电路至少包括第二开关管，第二开关管的第一通路端通过对应像素电路单元连接其中的电致发光元件的阳极，第二开关管的控制端连接第一时序信号端，第二开关管的第二通路端连接驱动芯片；其中，当侦测电路单元中的第二开关管处于导通状态且与其耦合连接的像素电路单元中的第一开关管也处于导通状态时，驱动芯片侦测导通状态的第 一开关管对应的像素电路单元中电致发光元件的阳极的电位。
为解决上述技术问题，本申请采用的另一技术方案是：提供一种上述像素电路的驱动方法，驱动方法包括：侦测每一像素电路单元中电致发光元件的阳极的电位，并将电致发光元件的阳极的电位收录在驱动芯片中形成阳极电压补偿信号；其中，每一像素电路单元至少包括第一开关管和电致发光元件；每一侦测电路单元至少包括选择电路，选择电路至少包括第二开关管；侦测每一像素电路单元中电致发光元件的阳极的电位的步骤包括：输入第一时序信号控制侦测电路单元中第二开关管导通，输入扫描信号控制对应像素电路单元中第一开关管导通，以使得驱动芯片与对应像素电路单元中电致发光元件的阳极导通，进而获取电致发光元件的阳极的电位；驱动芯片调用阳极电压补偿信号并将阳极电压补偿信号输出至对应的像素电路单元。
为解决上述技术问题，本申请采用的又一技术方案是：提供一种显示面板，该显示面板包括基板和设置于基板上的像素电路，像素电路为上述的像素电路，包括：驱动芯片、以及与驱动芯片连接的若干个像素电路单元和若干个侦测电路单元，其中，每一侦测电路单元分别独立的对应沿第一方向排布的一组像素电路单元，并与一组像素电路单元中每一像素电路单元选择性耦合连接，第一方向为呈阵列排布的像素电路单元的行方向或列方向；其中，每一像素电路单元至少包括第一开关管和电致发光元件，所述第一开关管的一通路端与电致发光元件的阳极电连接，第一开关管的控制端连接扫描信号端；每一侦测电路单元至少包括选择电路，所述选择电路至少包括第二开关管，第二开关管的第一通路端通过对应像素电路单元连接其中的电致发光元件的阳极，第二开关管的控制端连接第一时序信号端，第二开关管的第二通路端连接驱动芯片；其中，当侦测电路单元中的第二开关管处于导通状态且与其耦合连接的像素电路单元中的第一开关管也处于导通状态时，驱动芯片侦测导通状态的第一开关管对应的像素电路单元中电致发光元件的阳极的电位。
本申请通过设置像素电路包括驱动芯片、以及与驱动芯片连接的若 干个像素电路单元和若干个侦测电路单元，利用侦测电路单元导通驱动芯片与对应像素电路单元中电致发光元件的阳极。从而能够便于驱动芯片获取到电致发光元件的阳极电位，便于后续显示阶段对阳极电位的补偿，该电路能够较好的与像素电路单元融合，电路结构简单，且该电路结构便于侦测阶段与显示阶段相互独立设计，使得侦测阶段不会对显示阶段产生影响。
【附图说明】
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。其中：
图1是本申请第一实施例的像素电路的电路结构示意图；
图2是本申请第二实施例的像素电路的电路结构示意图；
图3是本申请实施例双栅开关管结构的原理示意图；
图4是本申请实施例的像素电路的驱动方法的流程示意图；
图5是本申请实施例的像素电路的驱动方法的一种显示阶段的具体流程示意图；
图6是本申请实施例显示面板的结构示意图。
【具体实施方式】
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性的劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
请参阅图1，图1是本申请第一实施例的像素电路的电路结构示意图。
在本实施例中，像素电路包括驱动芯片10以及与驱动芯片10连接 的若干个像素电路单元20和若干个侦测电路单元30。
每一侦测电路单元30分别独立的对应沿第一方向排布的一组像素电路单元20，并与一组像素电路单元20中每一像素电路单元20选择性耦合连接，第一方向为呈阵列排布的像素电路单元20的行方向或列方向。
例如，第一方向可以为呈阵列排布的像素电路单元的列方向。图1中仅为示意，其仅示意出一列的若干个像素电路单元20中的一个像素电路单元20与侦测电路单元30的连接关系，不难理解，该列的其他像素电路单元20与该侦测电路单元30的连接关系与之相同，图中不逐一体现。
每一像素电路单元20至少包括第一开关管T1和电致发光元件D，第一开关管T1的一通路端与电致发光元件D的阳极电连接，第一开关管T1的控制端连接扫描信号(scan)端。
每一侦测电路单元30至少包括选择电路31，选择电路31至少包括第二开关管T2，第二开关管T2的第一通路端通过对应像素电路单元20连接其(指代该对应像素电路单元)中的电致发光元件D的阳极，第二开关管T2的控制端连接第一时序信号(S1)端，第二开关管T2的第二通路端(作为连接端子)连接驱动芯片10。其中，对应像素电路单元是指与侦测电路单元30处于导通状态的像素电路单元。
当侦测电路单元30中的第二开关管T2处于导通状态且与其耦合连接的像素电路单元20中的第一开关管T1也处于导通状态时，驱动芯片10侦测导通状态的第一开关管T1对应的像素电路单元20中电致发光元件D的阳极的电位。
可选地，沿第二方向排布的各像素电路单元20中的第一开关管T1连接至同一扫描信号端，即共用同一扫描信号scan，第二方向与第一方向不同，其为呈阵列排布的像素电路单元20的列方向或行方向。例如，如图1所示，第二方向为呈阵列排布的像素电路单元20的行方向。
可选地，每一侦测电路单元30进一步包括复位电路32，复位电路32至少包括第三开关管T3，第三开关管T3的第一通路端通过对应像素 电路单元20连接其(指代该对应像素电路单元)中电致发光元件D的阳极，第三开关管T3的控制端连接第二时序信号S2，第三开关管T3的第二通路端连接复位信号(reset)端。
请参阅图2，图2是本申请第二实施例的像素电路的电路结构示意图。
在本实施例中，每一像素电路单元20进一步包括存储电容C和与电致发光元件D的阳极耦合连接的电流控制驱动管(T5)，存储电容C选择性与驱动芯片10耦合连接，并且选择性与电流控制驱动管(T5)的控制端耦合连接，用于接收并存储来自驱动芯片10的阳极电压补偿信号，并根据阳极电压补偿信号控制电流控制驱动管(T5)。
每一侦测电路单元30中第三开关管T3的第一通路端选择性与存储电容C耦合连接，用于对储存电容C进行选择性复位处理。通过对储存电容C进行复位处理，有利于提高存储电容C对阳极电压补偿信号的存储精度。
可选地，像素电路单元20进一步包括第四开关管T4、第五驱动管T5、第六开关管T6、第七开关管T7、第八开关管T8以及第九开关管T9，其中，第五驱动管T5为电流控制驱动管。
第四开关管T4的第一通路端连接第一工作电压VDD和储存电容C的第一端，同时储存电容C的第一端也连接第一工作电压(VDD)端，第四开关管T4的第二通路端连接第五驱动管T5的第一通路端和第九开关管T9的第二通路端，同时第五驱动管T5的第一通路端也连接第九开关管T9的第二通路端，第四开关管T4的控制端连接使能信号(EM)端。
第五驱动管T5的第二通路端连接第六开关管T6的第一通路端和第七开关管T7的第二通路端，同时第六开关管T6的第一通路端也连接第七开关管T7的第二通路端；第五驱动管T5的控制端连接存储电容C的第二端。
第六开关管T6的第二通路端连接第一开关管T1的第二通路端和电致发光元件D的阳极，第六开关管T6的控制端连接使能信号(EM)端。
第七开关管T7的第一通路端连接第五驱动管T5的控制端和储存电容的第二端，第七开关管T7的控制端连接第三时序信号(S3)端。
第八开关管T8的第一通路端连接存储电容C的第二端，第八开关管T8的第二通路端连接第一开关管T1的第一通路端、第二开关管T2的第一通路端和第三开关管T3的第一通路端，第八开关管T8的控制端连接第四时序信号(S4)端。
第九开关管T9的第一通路端连接第五开关管T5的第一通路端，第九开关管T9的第二通路端连接驱动芯片，第九开关管T9的第一通路端还连接第二开关管T2的第一通路端，第九开关管T9的控制端连接第三时序信号(S3)端。
存储电容C的第一端连接第一工作电压(VDD)端，电致发光元件D的阴极连接第二工作电压(VSS)端，第二开关管T2的第一通路端连接第一开关管T1的第一通路端和第八开关管T8的第二通路端，第三开关管T3的第一通路端连接第一开关管T1的第一通路端和第八开关管T8的第二通路端。
可选地，沿第二方向排布的各像素电路单元20中的第一开关管T1共用同一扫描信号(scan)端；沿第一方向排布的各像素电路单元20中的第一开关管T1各自独立连接相应扫描信号；在侦测阶段和显示阶段，沿第一方向对像素电路中各像素电路单元20进行逐行扫描。
可选地，对应于沿第二方向排布的各像素电路单元20，侦测电路单元30中第三开关管T3共用同一第二时序信号S2和同一复位信号reset。
可选地，对应于沿第二方向排布的各像素电路单元20，侦测电路单元30中第二开关管T2的控制端根据相应像素电路单元20中电致发光元件D的发光颜色接入不同的第一时序信号S1(R)、S1(G)或者S1(B)。
可选地，对应于沿第二方向排布的各像素电路单元20，侦测电路单元30中第二开关管T2的第二通路端各自独立的连接驱动芯片10的不同输入输出引脚Out(1)、Out(2)或者Out(3)。
例如，如图1所示，第一方向为列方向，第二方向为行方向，同一 行的各像素电路单元20中的第一开关管T1共用同一扫描信号scan；同一列的各像素电路单元20中的第一开关管T1各自独立连接相应扫描信号，即可以不同时接收扫描信号；在侦测阶段和显示阶段，沿列方向对像素电路中各像素电路单元20进行逐行扫描。对于同一行的各像素电路单元20，侦测电路单元30中第三开关管T3共用同一第二时序信号S2和同一复位信号reset。对于同一行的各像素电路单元20，侦测电路单元30中第二开关管T2的控制端根据相应像素电路单元20中电致发光元件D的发光颜色接入不同的第一时序信号S1(R)、S1(G)或者S1(B)；对于同一行的各像素电路单元20，侦测电路单元30中第二开关管T2的第二通路端各自独立的连接驱动芯片10的不同输入输出引脚Out(1)、Out(2)或者Out(3)。
具体而言，每一像素电路单元20对应于显示面板的一个亚像素单元，例如图2中从左到右的三个亚像素单元分别为红色亚像素单元(R)、绿色亚像素单元(G)、蓝色亚像素单元(B)。相邻的红、绿、蓝三种颜色的亚像素单元(RGB)组成一个像素单元，通过控制亚像素单元的不同灰阶，使得红、绿、蓝三种颜色的亚像素单元(RGB)混色实现像素单元的不同显示颜色。
位于同一行的不同颜色的亚像素单元共用一个扫描信号scan(即共用同一扫描线)、共用同一个复位信号reset、共用同一个第二时序信号S2。不同颜色的亚像素单元的连接端子一一对应地连接驱动芯片10的不同输入输出引脚Out(1)、Out(2)或者Out(3)。不同颜色的亚像素单元的第二开关管T2的控制端一一对应地连接的连接不同的第一时序信号S1(R)、S1(G)或者S1(B)。
请参阅图3，图3是本申请实施例双栅开关管结构的原理示意图。可选地，第七开关管T7和第八开关管T8均为双栅开关管结构，双栅开关管结构包括第一子开关管T01和第二子开关管T02，第一子开关管T01和第二子开关管T02的栅极连接在一起作为双栅开关管结构的控制端，第一子开关管T01的第一通路端作为双栅开关管结构的第一通路端，第二子开关管T02的第二通路端作为双栅开关管结构的第二通路端，第一 子开关管T01的第二通路端和第二子开关管T02的第一通路端连接。
通过上述方式，可以降低第七开关管T7和第八开关管T8的漏电流，降低功率损耗，提升电致发光元件D的显示效果。当然，在其他实施例中，第七开关管T7和第八开关管T8也可以采用单个栅极的MOS管，本申请实施例对此不做限定。
可选地，第一开关管T1、第二开关管T2、第三开关管T3、第四开关管T4、第五驱动管T5、第六开关管T6、第七开关管T7、第八开关管T8以及第九开关管T9均为可以为MOS管，具体可以是薄膜晶体管，且在控制端接入低电位时第一通路端与第二通路端导通，在控制端接入高电位时第一通路端与第二通路端截止。在其他实施例中，可以进行相反的配置，例如，在控制端接入低电位时第一通路端与第二通路端截止，在控制端接入高电位时第一通路端与第二通路端导通。例如，P型MOS管是在控制端接入低电位信号时导通，接入高电位信号时截止；N型MOS管是在控制端接入高电位导通，接入低电位时截止。
可选地，第一开关管T1、第二开关管T2、第三开关管T3、第四开关管T4、第五驱动管T5、第六开关管T6、第七开关管T7、第八开关管T8以及第九开关管T9各自的第一通路端和第二通路端中的其中一者为源极，另一者为漏极，各自的控制端均为栅极。
可选地，电致发光元件可以是OLED发光元件，具体可以是AMOLED(Active-matrix organic light-emitting diode，有源矩阵有机发光二极体或主动矩阵有机发光二极体)。在其他实施例中，也可以采用其他的电致发光元件，本申请实施例对此不做限定。
请参阅图4，图4是本申请实施例的像素电路的驱动方法的实施例的流程示意图。
在本实施例中，像素电路的驱动方法可包括：
步骤S11：侦测阶段：侦测每一像素电路单元中电致发光元件的阳极的电位，并将电致发光元件的阳极的电位收录在驱动芯片中形成阳极电压补偿信号。
其中，每一像素电路单元20至少包括第一开关管T1和电致发光元 件D；每一侦测电路单元30至少包括选择电路31，选择电路至少包括第二开关管T2；侦测每一像素电路单元20中电致发光元件D的阳极的电位的步骤具体可以包括：输入第一时序信号S1控制侦测电路单元30中第二开关管T2的第一通路端和第二通路端导通，输入扫描信号scan控制第一开关管T1的第一通路端和第二通路端导通，以使得驱动芯片10与对应像素电路单元20中电致发光元件D的阳极导通，进而获取电致发光元件D的阳极的电位。
可选地，在侦测阶段，第一时序信号S1的电位和第二时序信号S2的电位可以没有要求，其能够使得电致发光元件D发光即可，但为了减少侦测阶段对于电致发光元件D的影响，建议第一时序信号S1的电位和第二时序信号S2的电位的尽可能的小。
本申请中对于第一时序信号S1可以没有限制，只要保持每个侦测阶段中所采用的第一时序信号S1相同，且保持每个侦测阶段中所采用的第二时序信号S2相同，通过每次侦测电致发光元件D的阳极的电位差异形成阳极电压补偿信号。
步骤S12：显示阶段：驱动芯片调用阳极电压补偿信号并将阳极电压补偿信号输出至对应的像素电路单元。
本申请中每一侦测电路单元30进一步包括复位电路32，复位电路32至少包括第三开关管T3；可选地，侦测每一像素电路单元20中电致发光元件D的阳极的电位的步骤还包括：在获取对应像素电路单元20中电致发光元件D的阳极的电位之前，预先对该电致发光元件D的阳极的电位进行初始化处理。
其中对电致发光元件D的阳极的电位进行初始化处理的步骤包括：输入第二时序信号S2控制第三开关管T3的第一通路端和第二通路端导通，输入扫描信号scan控制第一开关管T1的第一通路端和第二通路端导通，以使复位信号(reset)端与对应像素电路单元20中电致发光元件D的阳极导通，进而对电致发光元件D的阳极的电位进行初始化。
可选地，在侦测与一个侦测电路单元30对应的一组像素电路单元20中电致发光元件D的阳极的电位(包括对阳极进行初始化的过程) 的过程中，输入第二时序信号S2控制第三开关管T3的第一通路端和第二通路端持续导通，从而使得电致发光元件D持续发光，从而能够减少侦测阶段对于电致发光元件D的影响。
请参阅图5，图5是本申请实施例的像素电路的驱动方法的实施例一种显示阶段的具体流程示意图。每一像素电路单元20还包括存储电容C和与电致发光元件D的阳极耦合连接的电流控制驱动管(T5)。
可选地，显示阶段具体可以包括：
步骤S121：对每一像素电路单元20中存储电容C进行信号写入处理。
其中，对每一像素电路单元20中存储电容C进行信号写入处理的步骤包括：控制侦测电路单元30中第二开关管T2处于导通状态，并控制第二开关管T2与对应像素电路单元20中的存储电容C之间的电路处于导通状态，以使驱动芯片10与对应像素电路单元20中的存储电容C电连通，进而将驱动芯片10中阳极电压补偿信号输出至对应像素电路单元20中的储存电容C中。
可选地，对每一像素电路单元20中存储电容C进行信号写入处理的步骤中，还包括(在信号写入前)预先对对应像素电路单元20中的存储电容C进行初始化处理的步骤；对对应像素电路单元20中的存储电容C进行初始化处理的步骤包括：控制侦测电路单元30中第三开关管T3处于导通状态，并控制第三开关管T3与对应像素电路单元20中的存储电容C之间的电路处于导通状态，以使复位信号(reset)端与对应像素电路单元20中的存储电容C导通，进而对该存储电容C进行初始化。
步骤S122：驱动每一像素电路单元20中电致发光元件D进行发光。
其中驱动每一像素电路单元20中电致发光元件D进行发光的步骤包括：释放存储电容C中的电流，以控制与该存储电容C处于导通状态的电流控制驱动管(T5)处于开通状态，进而使得对应的电致发光元件D处于发光状态。
可选地，驱动每一像素电路单元20中电致发光元件D进行发光的 步骤，还包括(在促使电致发光元件D发光前)预先对对应像素电路单元20中的电致发光元件D的阳极进行复位处理的步骤；对对应像素电路单元20中的电致发光元件D的阳极进行复位处理的步骤包括：控制侦测电路单元30中第三开关管T3处于导通状态，并控制对应的像素电路单元20中第一开关管T1处于导通状态，以使复位信号(reset)端与对应像素电路单元20中的电致发光元件D的阳极导通，以对相应电致发光元件D的阳极电位进行复位处理。
电流控制驱动管可选地，侦测阶段采用的复位信号与显示阶段所采用的复位信号不同，具体而言，在侦测阶段，复位信号reset的电位高于第二工作电压VSS，且复位信号reset与第二工作电压VSS的压差大于电致发光元件D的开启电压。在显示阶段，复位信号reset的电位小于等于第二工作电压VSS的电位。通过上述方式，能够使得在侦测阶段电致发光元件D发光，以减少侦测过程对于电致发光元件D的影响。
如图2所示，每一像素电路单元20进一步包括第四开关管T4、第五驱动管T5、第六开关管T6、第七开关管T7、第八开关管T8以及第九开关管T9。
具体而言，对每一像素电路单元20中存储电容C进行信号写入处理的步骤中，
对对应像素电路单元中的存储电容进行初始化处理的步骤包括：控制使能信号EM，以控制第四开关管T4的第一通路端和第二通路端截止，且控制第六开关管T6的第一通路端和第二通路端截止；控制扫描信号scan，以控制第一开关管T1的第一通路端和第二通路端截止；控制第三时序信号S3，以控制第七开关管T7的第一通路端和第二通路端截止，且控制第九开关管T9的第一通路端和第二通路端截止；输入第二时序信号S2，以控制第三开关管T3的第一通路端和第二通路端导通，输入第四时序信号S4，以控制第八开关管T8的第一通路端和第二通路端导通，以使复位信号reset对存储电容C进行复位。
将驱动芯片10中阳极电压补偿信号输出至对应像素电路单元中的储存电容的步骤包括：控制使能信号EM，以控制第四开关管T4的第一 通路端和第二通路端截止，且控制第六开关管T6的第一通路端和第二通路端截止；控制扫描信号scan，以控制第一开关管T1的第一通路端和第二通路端截止；控制第四时序信号S4，以控制第八开关管T8的第一通路端和第二通路端截止；输入第三时序信号S3，以控制第七开关管T7的第一通路端和第二通路端导通，且控制第九开关管T9的第一通路端和第二通路端导通以使驱动芯片10将阳极电压补偿信号写入存储电容C。
在前面描述的步骤中，第五驱动管T5也是处于导通状态的，这是因为存储电容C在完成初始化处理后，会留存一定电流，这部分电流会输入第五驱动管的控制端，以控制第五驱动管T5的第一通路端和第二通路端导通，此时第九开关管T9、第五驱动管T5和第七开关管T7均处于导通状态，驱动芯片10能够将阳极电压补偿信号写入存储电容C，与此同时，第七开关管T7第一通路端输出的电流会有一部分流入第五驱动管T5的控制端，以控制第五驱动管T5的第一通路端和第二通路端处于持续导通状态。
具体地，驱动每一像素电路单元20中电致发光元件D进行发光的步骤中，
对对应像素电路单元20中的电致发光元件D的阳极进行复位处理的步骤包括：控制使能信号EM，以控制第四开关管T4的第一通路端和第二通路端截止，且控制第六开关管T6的第一通路端和第二通路端截止；控制第三时序信号S3，以控制第七开关管T7的第一通路端和第二通路端截止，且控制第九开关管T9的第一通路端和第二通路端截止；控制第四时序信号S4，以控制第八开关管T8的第一通路端和第二通路端截止，输入扫描信号scan，以控制第一开关管T1的第一通路端和第二通路端导通；输入第二时序信号，以控制第三开关管T3的第一通路端和第二通路端以使复位信号reset对电致发光元件D的阳极电位进行复位。
使得对应的电致发光元件D处于发光状态的步骤包括：控制扫描信号scan控制第一开关管T1的第一通路端和第二通路端截止；控制第三 时序信号S3，以控制第七开关管T7的第一通路端和第二通路端截止，且控制第九开关管T9的第一通路端和第二通路端截止；控制第四时序信号S4，以控制第八开关管T8的第一通路端和第二通路端截止；输入使能信号EM，以控制第四开关管T4的第一通路端和第二通路端导通，且控制第六开关管T6的第一通路端和第二通路端导通，以使得电致发光元件D发光。
本申请所提供的驱动方法是一个连续的过程，具体地，控制扫描信号scan对沿第一方向排布的各像素电路单元20进行逐行(第二方向)扫描，对位于同一行(第二方向)中的各像素电路单元20同步进行存储电容C初始化、存储电容C信号写入、电致发光元件D的阳极电位复位、电致发光元件D发光；同时，对位于同一列(第一方向)中的像素电路单元20依次进行存储电容C初始化、存储电容C信号写入、电致发光元件D的阳极电位复位、电致发光元件D发光处理；即，在对第四列中像素电路单元20中存储电容C初始化时，对完成存储电容C初始化的第三列的像素电路单元20中的存储电容C进行信号写入，对完成存储电容C信号写入的第二列的像素电路单元20中的电致发光元件D的阳极电位进行复位，对完成电致发光元件D的阳极电位复位的第一列的像素电路单元20中的电致发光元件D进行发光。
请参阅图6，图6是本申请实施例显示面板的结构示意图。在本实施例中，显示面板包括基板41和设置于基板41上的像素电路42。该像素电路42可以是上述任意一实施例中的像素电路。
基板41可以为硬质基板也可以为柔性基板，本申请实施例对此不做限定。
本申请通过设置像素电路包括驱动芯片、以及与驱动芯片连接的若干个像素电路单元和若干个侦测电路单元，利用侦测电路单元导通驱动芯片与对应像素电路单元中电致发光元件的阳极。从而能够便于驱动芯片获取到电致发光元件的阳极电位，便于后续显示阶段对阳极电位的补偿，该电路能够较好的与像素电路单元融合，电路结构简单，且该电路结构便于侦测阶段与显示阶段相互独立设计，使得侦测阶段不会对显示 阶段产生影响。
以上仅为本申请的实施例，并非因此限制本申请的专利范围，凡是利用本申请说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本申请的专利保护范围内。

Claims (20)

  1. 一种像素电路，包括驱动芯片、以及与所述驱动芯片连接的若干个像素电路单元和若干个侦测电路单元，其中，每一所述侦测电路单元分别独立的对应沿第一方向排布的一组所述像素电路单元，并与一组所述像素电路单元中每一所述像素电路单元选择性耦合连接，所述第一方向为呈阵列排布的像素电路单元的行方向或列方向；其中，
    每一所述像素电路单元至少包括第一开关管和电致发光元件，所述第一开关管的一通路端与所述电致发光元件的阳极电连接，所述第一开关管的控制端连接扫描信号端；
    每一所述侦测电路单元至少包括选择电路，所述选择电路至少包括第二开关管，所述第二开关管的第一通路端通过对应像素电路单元连接其中的电致发光元件的阳极，所述第二开关管的控制端连接第一时序信号端，所述第二开关管的第二通路端连接所述驱动芯片；
    其中，当所述侦测电路单元中的第二开关管处于导通状态且与其耦合连接的所述像素电路单元中的第一开关管也处于导通状态时，所述驱动芯片侦测导通状态的第一开关管对应的像素电路单元中所述电致发光元件的阳极的电位。
  2. 根据权利要求1所述的像素电路，其中，沿第二方向排布的各所述像素电路单元中的第一开关管连接至同一扫描信号端，所述第二方向与第一方向不同，其为呈阵列排布的像素电路单元的列方向或行方向。
  3. 根据权利要求1所述的像素电路，其中，
    每一所述侦测电路单元进一步包括复位电路，所述复位电路至少包括第三开关管，所述第三开关管的第一通路端通过对应所述像素电路单元连接其中所述电致发光元件的阳极，所述第三开关管的控制端连接第二时序信号端，所述第三开关管的第二通路端连接复位信号端。
  4. 根据权利要求3所述的像素电路，其中，
    每一所述像素电路单元进一步包括存储电容和与所述电致发光元件的阳极耦合连接的电流控制驱动管，所述存储电容选择性与所述驱动 芯片耦合连接，并且选择性与所述电流控制驱动管的控制端耦合连接，用于接收并存储来自驱动芯片的阳极电压补偿信号，并根据所述阳极电压补偿信号控制所述电流控制驱动管。
  5. 根据权利要求4所述的像素电路，其中，每一所述侦测电路单元中第三开关管的第一通路端与对应所述像素电路单元中的所述存储电容耦合连接，用于对所述储存电容进行选择性复位处理。
  6. 根据权利要求4所述的像素电路，其中，每一所述像素电路单元进一步包括第四开关管、第五驱动管、第六开关管、第七开关管、第八开关管以及第九开关管，其中，所述第五驱动管为所述电流控制驱动管；
    所述第四开关管的第一通路端连接第一工作电压端，所述第四开关管的第二通路端连接第五驱动管的第一通路端和所述第九开关管的第二通路端，所述第四开关管的控制端连接使能信号端；
    所述第五驱动管的第二通路端连接所述第六开关管的第一通路端和所述第七开关管的第二通路端，所述第五驱动管的控制端连接所述存储电容的第二端；
    所述第六开关管的第二通路端连接所述第一开关管的第二通路端和所述电致发光元件的阳极，所述第六开关管的控制端连接所述使能信号端；
    所述第七开关管的第一通路端连接所述第五驱动管的控制端，所述第七开关管的控制端连接第三时序信号端；
    所述第八开关管的第一通路端连接所述存储电容的第二端，所述第八开关管的第二通路端连接所述第二开关管的第一通路端和第三开关管的第一通路端，所述第八开关管的控制端连接第四时序信号端；
    所述第九开关管的第一通路端连接所述第五开关管的第一通路端，所述第九开关管的第二通路端连接驱动芯片，所述第九开关管的控制端连接所述第三时序信号端；
    所述存储电容的第一端连接所述第一工作电压，所述电致发光元件的阴极连接第二工作电压，所述第二开关管的第一通路端连接所述第一 开关管的第一通路端，所述第三开关管的第一通路端连接第一开关管的第一通路端。
  7. 根据权利要求6所述的像素电路，其中，所述第七开关管和所述第八开关管均为双栅开关管结构，所述双栅开关管结构包括第一子开关管和第二子开关管，所述第一子开关管和所述第二子开关管的栅极连接在一起作为所述双栅开关管结构的控制端，所述第一子开关管的第一通路端作为所述双栅开关管结构的第一通路端，所述第二子开关管的第二通路端作为所述双栅开关管结构的第二通路端，所述第一子开关管的第二通路端和所述第二子开关管的第一通路端连接。
  8. 一种像素电路的驱动方法，包括：
    侦测每一像素电路单元中电致发光元件的阳极的电位，并将电致发光元件的阳极的电位收录在驱动芯片中形成阳极电压补偿信号；其中，每一所述像素电路单元至少包括第一开关管和电致发光元件；每一所述侦测电路单元至少包括选择电路，所述选择电路至少包括第二开关管；侦测每一所述像素电路单元中电致发光元件的阳极的电位的步骤包括：输入第一时序信号控制侦测电路单元中第二开关管导通，输入扫描信号控制对应像素电路单元中第一开关管导通，以使得驱动芯片与对应像素电路单元中电致发光元件的阳极导通，进而获取所述电致发光元件的阳极的电位；
    所述驱动芯片调用所述阳极电压补偿信号并将所述阳极电压补偿信号输出至对应的像素电路单元。
  9. 根据权利要求8所述的驱动方法，其中，每一所述侦测电路单元进一步包括复位电路，所述复位电路至少包括第三开关管；
    侦测每一所述像素电路单元中电致发光元件的阳极的电位的步骤还包括：在获取对应像素电路单元中所述电致发光元件的阳极的电位之前，对该电致发光元件的阳极的电位进行初始化处理；
    其中，对所述电致发光元件的阳极的电位进行初始化处理的步骤包括：输入第二时序信号控制所述第三开关管导通，输入扫描信号控制所述第一开关管导通，以使复位信号端与对应像素电路单元中所述电致发 光元件的阳极导通，进而对所述电致发光元件的阳极的电位进行初始化。
  10. 根据权利要求9所述的驱动方法，其中，
    在侦测与一个所述侦测电路单元对应的一组像素电路单元中电致发光元件的阳极的电位的过程中，输入第二时序信号控制所述第三开关管的第一通路端和第二通路端持续导通。
  11. 根据权利要求8所述的驱动方法，其中，每一像素电路单元还包括存储电容和与所述电致发光元件的阳极耦合连接的电流控制驱动管，
    所述驱动方法包括：
    对每一像素电路单元中存储电容进行信号写入处理；其中对每一像素电路单元中存储电容进行信号写入处理的步骤包括：控制所述侦测电路单元中第二开关管处于导通状态，并控制所述第二开关管与对应像素电路单元中的存储电容之间的电路处于导通状态，以使所述驱动芯片与对应像素电路单元中的存储电容电连通，进而将所述驱动芯片中阳极电压补偿信号输出至对应像素电路单元中的储存电容中；以及
    驱动每一像素电路单元中电致发光元件进行发光；其中驱动每一像素电路单元中电致发光元件进行发光的步骤包括：释放存储电容中的电流，以控制与该存储电容处于导通状态的电流控制驱动管处于开通状态，进而使得对应的电致发光元件处于发光状态。
  12. 根据权利要求11所述的驱动方法，其中，对每一像素电路单元中存储电容进行信号写入处理的步骤中，还包括预先对对应的像素电路单元中的存储电容进行初始化处理的步骤；对对应像素电路单元中的存储电容进行初始化处理的步骤包括：控制所述侦测电路单元中第三开关管处于导通状态，并控制所述第三开关管与对应像素电路单元中的存储电容之间的电路处于导通状态，以使复位信号端与对应像素电路单元中的存储电容导通，进而对该存储电容进行初始化；
    驱动每一像素电路单元中电致发光元件进行发光的步骤，还包括预先对对应像素电路单元中的电致发光元件的阳极进行复位处理的步骤； 对对应像素电路单元中的电致发光元件的阳极进行复位处理的步骤包括：控制所述侦测电路单元中第三开关管处于导通状态，并控制对应的像素电路单元中第一开关管处于导通状态，以使所述复位信号端与对应像素电路单元中的电致发光元件的阳极导通，以对相应电致发光元件的阳极电位进行复位处理电流控制驱动管。
  13. 根据权利要求8所述的驱动方法，其中，每一像素电路单元还包括存储电容、与所述电致发光元件的阳极耦合连接的第五驱动管、第四开关管、第六开关管、第七开关管、第八开关管以及第九开关管；
    所述驱动方法包括：
    对每一像素电路单元中存储电容进行信号写入处理；其中对每一像素电路单元中存储电容进行信号写入处理的步骤包括：控制所述第四开关管、所述第六开关管、所述第一开关管和所述第八开关管截止；并控制所述第五驱动管、所述第七开关管、所述第九开关管导通，以使所述驱动芯片将所述阳极电压补偿信号写入所述存储电容；以及
    驱动每一像素电路单元中电致发光元件进行发光，其中驱动每一像素电路单元中电致发光元件进行发光的步骤包括：控制所述第一开关管、所述第七开关管、所述第八开关管和所述第九开关管截止，并控制所述第四开关管、所述第五驱动管、所述第六开关管导通，以使得所述电致发光元件发光。
  14. 根据权利要求13所述的驱动方法，其中，对每一像素电路单元中存储电容进行信号写入处理的步骤中，还包括：
    预先对对应像素电路单元中的存储电容进行初始化处理的步骤：控制所述第四开关管、所述第六开关管、所述第一开关管、所述第七开关管和所述第九开关管截止；并控制所述侦测电路单元的第三开关管和所述第八开关管导通，以使复位信号对所述存储电容进行复位；
    驱动每一像素电路单元中电致发光元件进行发光的步骤，还包括：
    预先对对应像素电路单元中的电致发光元件的阳极进行复位处理的步骤包括：控制所述第四开关管、所述第六开关管、所述第七开关管、所述第八开关管、所述第九开关管截止，并控制所述第一开关管和所述 侦测电路单元的第三开关管导通，以使所述复位信号对所述电致发光元件的阳极电位进行复位。
  15. 根据权利要求8所述的驱动方法，其中，沿第二方向排布的各所述像素电路单元中的第一开关管共用同一扫描信号；沿第一方向排布的各所述像素电路单元中的第一开关管各自独立连接相应扫描信号；在侦测阶段和显示阶段，沿第一方向对所述像素电路中各像素电路单元进行逐行扫描。
  16. 根据权利要求8所述的驱动方法，其中，对应于沿第二方向排布的各所述像素电路单元，所述侦测电路单元中第三开关管共用同一第二时序信号和同一复位信号。
  17. 根据权利要求8所述的驱动方法，其中，对应于沿第二方向排布的各像素电路单元，所述侦测电路单元中第二开关管的控制端根据相应像素电路单元中电致发光元件的发光颜色接入不同的第一时序信号。
  18. 一种显示面板，包括基板和设置于基板上的像素电路，所述像素电路包括驱动芯片、以及与所述驱动芯片连接的若干个像素电路单元和若干个侦测电路单元，其中，每一所述侦测电路单元分别独立的对应沿第一方向排布的一组所述像素电路单元，并与一组所述像素电路单元中每一所述像素电路单元选择性耦合连接，所述第一方向为呈阵列排布的像素电路单元的行方向或列方向；其中，
    每一所述像素电路单元至少包括第一开关管和电致发光元件，所述第一开关管的一通路端与所述电致发光元件的阳极电连接，所述第一开关管的控制端连接扫描信号端；
    每一所述侦测电路单元至少包括选择电路，所述选择电路至少包括第二开关管，所述第二开关管的第一通路端通过对应像素电路单元连接其中的电致发光元件的阳极，所述第二开关管的控制端连接第一时序信号端，所述第二开关管的第二通路端连接所述驱动芯片；
    其中，当所述侦测电路单元中的第二开关管处于导通状态且与其耦合连接的所述像素电路单元中的第一开关管也处于导通状态时，所述驱动芯片侦测导通状态的第一开关管对应的像素电路单元中所述电致发 光元件的阳极的电位。
  19. 根据权利要求18所述的像素电路，其中，沿第二方向排布的各所述像素电路单元中的第一开关管连接至同一扫描信号端，所述第二方向与第一方向不同，其为呈阵列排布的像素电路单元的列方向或行方向。
  20. 根据权利要求18所述的像素电路，其中，
    每一所述侦测电路单元进一步包括复位电路，所述复位电路至少包括第三开关管，所述第三开关管的第一通路端通过对应所述像素电路单元连接其中所述电致发光元件的阳极，所述第三开关管的控制端连接第二时序信号端，所述第三开关管的第二通路端连接复位信号端。
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