WO2020118947A1 - Flash memory data scrambler design capable of automatically modulating excitation mode - Google Patents

Flash memory data scrambler design capable of automatically modulating excitation mode Download PDF

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WO2020118947A1
WO2020118947A1 PCT/CN2019/078466 CN2019078466W WO2020118947A1 WO 2020118947 A1 WO2020118947 A1 WO 2020118947A1 CN 2019078466 W CN2019078466 W CN 2019078466W WO 2020118947 A1 WO2020118947 A1 WO 2020118947A1
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initial value
excitation
selection module
random number
module
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PCT/CN2019/078466
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吴恒毅
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江苏华存电子科技有限公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1009—Address translation using page tables, e.g. page table structures
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/54—Arrangements for designing test circuits, e.g. design for test [DFT] tools

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  • the invention relates to the technical field of flash memory data scramblers, in particular to a design of a flash memory data scrambler that can automatically adjust the excitation mode.
  • the goal of scrambling input data is to reduce local energy concentration in the memory chip and the resulting adverse effects.
  • the pseudo-random number sequence usually generated by the random number generator performs an exclusive OR operation with the input data, and the result of the operation is the saved data.
  • Figure 2 describes the circuit diagram of a common data scrambler in flash memory chips.
  • 14 XOR gates 100 to 113 and a 32-bit register from r 0 to r 31 for providing random numbers are called It is a random number generator.
  • the random number generator and XOR gates 114 to 121 are called scramblers.
  • the 32-bit registers from r 0 to r 31 perform a left shift in synchronization with the clock signal for scrambling, which is not shown in Figure 2.
  • the random number generation period of the random number generator is 4KB (kilobytes), and matches the frame data of 4KB in size, and a certain number of frames form a page.
  • XOR gates 114 to 121 XOR the 8 output bits 0 to 7 of the random number generator and 1 byte of input data D0 to D7, and the obtained result is used as the scrambling result.
  • the random number initial value selection module shown in FIG. 3 Since the random number is generated for a frame during the modulation process, in order to make the random number sequence used by the adjacent frame data different, the random number initial value selection module shown in FIG. 3 is introduced, which passes the input page address and frame address. And other signals are calculated to obtain a value of 0 to 66. Look up the table of register initialization values. When the scrambling of each frame data begins, initialize the registers in the random number generator to generate scrambling that is different from other frame data. The random number sequence used.
  • An object of the present invention is to provide a flash data scrambler design that can automatically modulate an excitation method to solve the problems raised in the background art.
  • a flash data scrambler design with an automatic modulation excitation method including an initial value form module, a register set, an excitation value form module, and a register initial value selection module
  • the register group is provided with a page address unit, a frame address unit, a hard disk function signal generator, a W/E signal counting unit, the initial value form module, a page address unit, a frame address unit, a hard disk function signal generator, W/E
  • the signal counting unit is respectively connected to a register initial value selection module
  • the register initial value selection module is connected to an excitation selection module
  • the excitation value form module is connected to an excitation selection module.
  • a design method of a flash memory data scrambler with an automatic modulation excitation method includes the following steps:
  • the register initial value selection module calculates the page address of the stored data. However, the frame address unit and other signals are calculated and used to find the initial value table to obtain a 32-bit initial value output;
  • the incentive selection module calculates the page address of the stored data and uses this to look up the incentive value form to obtain a 32-bit incentive value output;
  • the beneficial effect of the present invention is that the scrambler has an excitation generator, which generates a 32-bit output, and performs an exclusive OR operation with the 32-bit output of the random number generator initial value selection module, and the result is used as a register
  • the initialization value of the invention is to add an excitation generator and extend the random number sequence period of the random number generator of the scrambler to 8 times before. Such a scrambler can be applied to a larger capacity storage system .
  • Figure 1 is a schematic diagram of the system of the present invention
  • Figure 2 is a circuit diagram of a common data scrambler in a flash memory chip
  • Figure 3 is a block diagram of the random number initial value selection module.
  • a flash data scrambler design with automatic modulation excitation mode including initial value form module 1, register group 2, excitation value form module 3, and register initial value selection Module 4,
  • the register group 2 is provided with a page address unit 5, a frame address unit 6, a hard disk function signal generator 7, a W/E signal counting unit 8, the initial value form module 1, a page address unit 5, a frame
  • the address unit 6, the hard disk function signal generator 7, and the W/E signal counting unit 8 are respectively connected to the register initial value selection module 4, the register initial value selection module 4 is connected to the excitation selection module 3, and the excitation value form module 3 is connected to the excitation Select module 9.
  • the register initial value selection module calculates the page address of the stored data. However, the frame address unit and other signals are calculated and used to find the initial value table to obtain a 32-bit initial value output;
  • the incentive selection module calculates the page address of the stored data and uses this to look up the incentive value table in the following table to obtain a 32-bit incentive value output;
  • the 32-bit result obtained after the XOR of the above two 32-bit output signals passes the registers r 0 to r 31 of the random number generator module.
  • the random number generator has a larger random number period and can be applied In storage systems with higher storage capacity.
  • the scrambler has an excitation generator, which generates a 32-bit output, and performs an exclusive OR operation with the 32-bit output of the random number generator initial value selection module, and the result is used as the initial value of the register.
  • Excitation generator and can extend the random number sequence period of the random number generator of the scrambler to 8 times before, such a scrambler can be applied to a larger capacity storage system.

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Abstract

Disclosed is a flash memory data scrambler design capable of automatically modulating an excitation mode. A scrambler comprises an excitation generator; the excitation generator generates 32-bit output; the 32-bit output and that of an initial value selection module of a random number generator perform an XOR operation; a result is used as the initial value of a register. The excitation generator is added, and the random number sequence period of the random number generator of the scrambler can be extended to be 8 times of a previous random number sequence period, and thus, the scrambler can be applied to a storage system having larger capacity.

Description

一种可自动调变激励方式的闪存数据扰频器设计Design of a flash data scrambler with automatic modulation excitation method 技术领域Technical field
本发明涉及闪存数据扰频器技术领域，具体为一种可自动调变激励方式的闪存数据扰频器设计。The invention relates to the technical field of flash memory data scramblers, in particular to a design of a flash memory data scrambler that can automatically adjust the excitation mode.
背景技术Background technique
在存储系统中，对输入数据进行扰频的目标是为了降低存储芯片中局部能量集中及由此产生的不利影响。通常由随机数产生器产生的伪随机数序列与输入数据进行异或运算，运算的结果即为保存的数据。In a storage system, the goal of scrambling input data is to reduce local energy concentration in the memory chip and the resulting adverse effects. The pseudo-random number sequence usually generated by the random number generator performs an exclusive OR operation with the input data, and the result of the operation is the saved data.
图2描述了闪存芯片中常见的数据扰频器的电路图，其中，14个异或(XOR)门100到113和用于提供随机数的从r 0到r 31的1个32位寄存器被称为随机数产生器。该随机数产生器和XOR门114到121被称为扰频器。 Figure 2 describes the circuit diagram of a common data scrambler in flash memory chips. Among them, 14 XOR gates 100 to 113 and a 32-bit register from r 0 to r 31 for providing random numbers are called It is a random number generator. The random number generator and XOR gates 114 to 121 are called scramblers.
在图2中从r 0到r 31的32位寄存器与时钟信号同步执行左移用于扰频，这个没有在图2中显示出来。随机数产生器的随机数产生周期是4KB(千字节)，并且和4KB大小的帧(frame)数据相匹配，一定数量的帧组成页(page)。通过XOR门114到121对随机数产生器的8个输出bit0到bit7和1字节输入数据D0到D7进行异或，所得的结果被用作扰频结果。 In Figure 2, the 32-bit registers from r 0 to r 31 perform a left shift in synchronization with the clock signal for scrambling, which is not shown in Figure 2. The random number generation period of the random number generator is 4KB (kilobytes), and matches the frame data of 4KB in size, and a certain number of frames form a page. XOR gates 114 to 121 XOR the 8 output bits 0 to 7 of the random number generator and 1 byte of input data D0 to D7, and the obtained result is used as the scrambling result.
由于调制过程中随机数是为一个frame产生的，为了使相邻frame数据使用的随机数序列有差别，引入了图3所示的随机数初始值选择模块，它通过输入的page地址，frame地址及其他信号计 算得到一个0到66的值，查找寄存器初始化值的表格，在每个frame数据开始扰频时，对随机数产生器中的寄存器初始化，以此产生有别于其他frame数据扰频所用的随机数序列。Since the random number is generated for a frame during the modulation process, in order to make the random number sequence used by the adjacent frame data different, the random number initial value selection module shown in FIG. 3 is introduced, which passes the input page address and frame address. And other signals are calculated to obtain a value of 0 to 66. Look up the table of register initialization values. When the scrambling of each frame data begins, initialize the registers in the random number generator to generate scrambling that is different from other frame data. The random number sequence used.
然而，当需要对大于67page的数据进行扰频时，前面的随机数产生器和利用该产生器的扰频器不能正确作出响应。However, when it is necessary to scramble data larger than 67 pages, the previous random number generator and the scrambler using the generator cannot respond correctly.
发明内容Summary of the invention
本发明的目的在于提供一种可自动调变激励方式的闪存数据扰频器设计，以解决上述背景技术中提出的问题。An object of the present invention is to provide a flash data scrambler design that can automatically modulate an excitation method to solve the problems raised in the background art.
为实现上述目的，本发明提供如下技术方案：一种可自动调变激励方式的闪存数据扰频器设计,包括初始值表单模块、寄存器组、激励值表单模块、寄存器初始值选择模块，所述寄存器组内设有页地址单元、帧地址单元、硬盘函数信号发生器、W/E信号计数单元，所述初始值表单模块、页地址单元、帧地址单元、硬盘函数信号发生器、W/E信号计数单元分别连接寄存器初始值选择模块，所述寄存器初始值选择模块连接激励选择模块，所述激励值表单模块连接激励选择模块。In order to achieve the above object, the present invention provides the following technical solution: A flash data scrambler design with an automatic modulation excitation method, including an initial value form module, a register set, an excitation value form module, and a register initial value selection module, said The register group is provided with a page address unit, a frame address unit, a hard disk function signal generator, a W/E signal counting unit, the initial value form module, a page address unit, a frame address unit, a hard disk function signal generator, W/E The signal counting unit is respectively connected to a register initial value selection module, the register initial value selection module is connected to an excitation selection module, and the excitation value form module is connected to an excitation selection module.
优选的，一种可自动调变激励方式的闪存数据扰频器设计方法包括以下步骤：Preferably, a design method of a flash memory data scrambler with an automatic modulation excitation method includes the following steps:
A、寄存器初始值选择模块通过存储数据的页地址但，帧地址单元及其他信号计算并以此查找初始值表单，得到32位初始值输出；A. The register initial value selection module calculates the page address of the stored data. However, the frame address unit and other signals are calculated and used to find the initial value table to obtain a 32-bit initial value output;
B、激励选择模块通过存储数据的页地址计算并以此查找激励值表单，得到32位激励值输出；B. The incentive selection module calculates the page address of the stored data and uses this to look up the incentive value form to obtain a 32-bit incentive value output;
C、以上两个32位输出信号异或后得到的32位结果，传递随机数产生器模块的寄存器r 0到r 31。 C. The 32-bit result obtained after XORing the above two 32-bit output signals, passing the registers r 0 to r 31 of the random number generator module.
与现有技术相比，本发明的有益效果是：该扰频器有一激励产生器，它产生32位输出，与随机数产生器初始值选择模块的32位输出进行异或操作，结果作为寄存器的初始化值，本发明通过添加一个激励产生器，并可以将扰频器随机数产生器的随机数序列周期扩展至之前的8倍，这样的扰频器可以应用于更大容量的存储系统中。Compared with the prior art, the beneficial effect of the present invention is that the scrambler has an excitation generator, which generates a 32-bit output, and performs an exclusive OR operation with the 32-bit output of the random number generator initial value selection module, and the result is used as a register The initialization value of the invention is to add an excitation generator and extend the random number sequence period of the random number generator of the scrambler to 8 times before. Such a scrambler can be applied to a larger capacity storage system .
附图说明BRIEF DESCRIPTION
图1为本发明系统原理图；Figure 1 is a schematic diagram of the system of the present invention;
图2为闪存芯片中常见的数据扰频器的电路图；Figure 2 is a circuit diagram of a common data scrambler in a flash memory chip;
图3为随机数初始值选择模块框图。Figure 3 is a block diagram of the random number initial value selection module.
具体实施方式detailed description
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。The technical solutions in the embodiments of the present invention will be described clearly and completely in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, but not all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by a person of ordinary skill in the art without making creative efforts fall within the protection scope of the present invention.
请参阅图1，本发明提供一种技术方案：一种可自动调变激励方式的闪存数据扰频器设计,包括初始值表单模块1、寄存器组2、激励值表单模块3、寄存器初始值选择模块4，所述寄存器组2内设有页地址单元5、帧地址单元6、硬盘函数信号发生器7、W/E信号 计数单元8，所述初始值表单模块1、页地址单元5、帧地址单元6、硬盘函数信号发生器7、W/E信号计数单元8分别连接寄存器初始值选择模块4，所述寄存器初始值选择模块4连接激励选择模块3，所述激励值表单模块3连接激励选择模块9。Please refer to FIG. 1, the present invention provides a technical solution: a flash data scrambler design with automatic modulation excitation mode, including initial value form module 1, register group 2, excitation value form module 3, and register initial value selection Module 4, the register group 2 is provided with a page address unit 5, a frame address unit 6, a hard disk function signal generator 7, a W/E signal counting unit 8, the initial value form module 1, a page address unit 5, a frame The address unit 6, the hard disk function signal generator 7, and the W/E signal counting unit 8 are respectively connected to the register initial value selection module 4, the register initial value selection module 4 is connected to the excitation selection module 3, and the excitation value form module 3 is connected to the excitation Select module 9.
一种可自动调变激励方式的闪存数据扰频器设计方法，包括以下步骤：A design method of flash memory data scrambler with automatic modulation excitation method includes the following steps:
A、寄存器初始值选择模块通过存储数据的页地址但，帧地址单元及其他信号计算并以此查找初始值表单，得到32位初始值输出；A. The register initial value selection module calculates the page address of the stored data. However, the frame address unit and other signals are calculated and used to find the initial value table to obtain a 32-bit initial value output;
B、激励选择模块通过存储数据的页地址计算并以此查找下表的激励值表单，得到32位激励值输出；B. The incentive selection module calculates the page address of the stored data and uses this to look up the incentive value table in the following table to obtain a 32-bit incentive value output;
C、以上两个32位输出信号异或后得到的32位结果，传递随机数产生器模块的寄存器r 0到r 31，通过这样做，随机数产生器具有更大的随机数周期，可以应用在更高存储容量的存储系统中。 C. The 32-bit result obtained after the XOR of the above two 32-bit output signals passes the registers r 0 to r 31 of the random number generator module. By doing this, the random number generator has a larger random number period and can be applied In storage systems with higher storage capacity.
激励产生器选择模块的查找表Look-up table of excitation generator selection module
Figure PCTCN2019078466-appb-000001
Figure PCTCN2019078466-appb-000001
综上所述，该扰频器有一激励产生器，它产生32位输出，与随 机数产生器初始值选择模块的32位输出进行异或操作，结果作为寄存器的初始化值，本发明通过添加一个激励产生器，并可以将扰频器随机数产生器的随机数序列周期扩展至之前的8倍，这样的扰频器可以应用于更大容量的存储系统中。In summary, the scrambler has an excitation generator, which generates a 32-bit output, and performs an exclusive OR operation with the 32-bit output of the random number generator initial value selection module, and the result is used as the initial value of the register. Excitation generator, and can extend the random number sequence period of the random number generator of the scrambler to 8 times before, such a scrambler can be applied to a larger capacity storage system.
尽管已经示出和描述了本发明的实施例，对于本领域的普通技术人员而言，可以理解在不脱离本发明的原理和精神的情况下可以对这些实施例进行多种变化、修改、替换和变型，本发明的范围由所附权利要求及其等同物限定。Although the embodiments of the present invention have been shown and described, those of ordinary skill in the art can understand that various changes, modifications, and substitutions can be made to these embodiments without departing from the principles and spirit of the present invention And variations, the scope of the invention is defined by the appended claims and their equivalents.

Claims (2)

  1. 一种可自动调变激励方式的闪存数据扰频器设计,其特征在于：包括初始值表单模块(1)、寄存器组(2)、激励值表单模块(3)、寄存器初始值选择模块(4)，所述寄存器组(2)内设有页地址单元(5)、帧地址单元(6)、硬盘函数信号发生器(7)、W/E信号计数单元(8)，所述初始值表单模块(1)、页地址单元(5)、帧地址单元(6)、硬盘函数信号发生器(7)、W/E信号计数单元(8)分别连接寄存器初始值选择模块(4)，所述寄存器初始值选择模块(4)连接激励选择模块(3)，所述激励值表单模块(3)连接激励选择模块(9)。A flash data scrambler design with automatic modulation excitation method, which is characterized by including an initial value form module (1), a register set (2), an excitation value form module (3), and a register initial value selection module (4 ), the register group (2) is provided with a page address unit (5), a frame address unit (6), a hard disk function signal generator (7), a W/E signal counting unit (8), and the initial value form The module (1), the page address unit (5), the frame address unit (6), the hard disk function signal generator (7), and the W/E signal counting unit (8) are respectively connected to the register initial value selection module (4). The register initial value selection module (4) is connected to the excitation selection module (3), and the excitation value table module (3) is connected to the excitation selection module (9).
  2. 实现权利要求1所述的一种可自动调变激励方式的闪存数据扰频器设计方法，其特征在于：包括以下步骤：The method for designing a flash data scrambler with automatic modulation excitation method according to claim 1, characterized in that it includes the following steps:
    A、寄存器初始值选择模块通过存储数据的页地址但，帧地址单元及其他信号计算并以此查找初始值表单，得到32位初始值输出；A. The register initial value selection module calculates the page address of the stored data. However, the frame address unit and other signals are calculated and used to find the initial value table to obtain a 32-bit initial value output;
    B、激励选择模块通过存储数据的页地址计算并以此查找激励值表单，得到32位激励值输出；B. The incentive selection module calculates the page address of the stored data and uses this to look up the incentive value form to obtain a 32-bit incentive value output;
    C、以上两个32位输出信号异或后得到的32位结果，传递随机数产生器模块的寄存器r 0到r 31。 C. The 32-bit result obtained after XORing the above two 32-bit output signals, passing the registers r 0 to r 31 of the random number generator module.
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