WO2020118935A1 - Display panel and manufacturing method therefor - Google Patents

Display panel and manufacturing method therefor Download PDF

Info

Publication number
WO2020118935A1
WO2020118935A1 PCT/CN2019/078157 CN2019078157W WO2020118935A1 WO 2020118935 A1 WO2020118935 A1 WO 2020118935A1 CN 2019078157 W CN2019078157 W CN 2019078157W WO 2020118935 A1 WO2020118935 A1 WO 2020118935A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
insulating layer
substrate
display panel
thin film
Prior art date
Application number
PCT/CN2019/078157
Other languages
French (fr)
Chinese (zh)
Inventor
赵凯祥
Original Assignee
武汉华星光电半导体显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 武汉华星光电半导体显示技术有限公司 filed Critical 武汉华星光电半导体显示技术有限公司
Publication of WO2020118935A1 publication Critical patent/WO2020118935A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1237—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a different composition, shape, layout or thickness of the gate insulator in different devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78663—Amorphous silicon transistors

Definitions

  • the present application relates to the field of display, in particular to a display panel and a manufacturing method thereof.
  • SiNx and SiOx are usually used between the two layers of metal, because the refractive index of SiNx and SiOx are different, it will cause the loss of the emitted light and total reflection, etc.
  • the light in a place with a large angle cannot be emitted. If it is viewed in a place with a relatively large angle, color cast will occur. In serious cases, even a large-vision character may be biased.
  • the present application relates to a display panel and a manufacturing method thereof, which are used to solve the problem of color shift caused by different reflectances of different film materials in thin film transistors of display panels in the prior art.
  • a display panel provided by the present application includes: a substrate, and a thin film transistor unit on the substrate;
  • the thin film transistor unit includes a first region and a second region
  • the first region includes: an active layer, a first insulating layer, a gate layer, a second insulating layer, a source and drain layer, a via, and a first passivation layer;
  • the second region includes: a third insulating layer and a second passivation layer;
  • the first insulating layer, the second insulating layer and the first passivation layer are all made of SiNx film
  • the third insulating layer and the second passivation layer are made of SiOx film
  • the substrate is a glass substrate, quartz The substrate or resin substrate.
  • the substrate is an LCD substrate or an OLED substrate.
  • the orthographic projection area of the first insulating layer on the substrate is greater than or equal to the orthographic projection area of the gate layer on the substrate.
  • the thin film transistor is a top gate type thin film transistor or a bottom gate type thin film transistor.
  • the second insulating layer and the third insulating layer are provided in the same layer, and the second passivation layer and the first passivation layer are provided in the same layer.
  • the light shielding layer is disposed directly under the active layer.
  • the buffer layer covers the light shielding layer.
  • the material of the gate layer is one or more of molybdenum, aluminum, aluminum-nickel alloy, molybdenum-tungsten alloy, chromium or copper.
  • the materials of the source and the drain are: one of molybdenum, aluminum, aluminum-nickel alloy, molybdenum-tungsten alloy, chromium, copper or titanium aluminum alloy or Multiple.
  • the source electrode and the drain electrode are electrically connected to the active layer through via holes, respectively.
  • the area of the first passivation layer is smaller than the area of the second passivation layer.
  • the second passivation layer covers the third insulating layer.
  • the present application also provides another display panel, including: a substrate, and a thin film transistor unit on the substrate;
  • the thin film transistor unit includes a first region and a second region
  • the first region includes: an active layer, a first insulating layer, a gate layer, a second insulating layer, a source and drain layer, a via, and a first passivation layer;
  • the second region includes: a third insulating layer and a second passivation layer;
  • the first insulating layer, the second insulating layer and the first passivation layer all use SiNx film, and the third insulating layer and the second passivation layer use SiOx film.
  • the substrate is an LCD substrate or an OLED substrate.
  • the orthographic projection area of the first insulating layer on the substrate is greater than or equal to the orthographic projection area of the gate layer on the substrate.
  • the thin film transistor is a top gate type thin film transistor or a bottom gate type thin film transistor.
  • the second insulating layer and the third insulating layer are provided in the same layer, and the second passivation layer and the first passivation layer are provided in the same layer.
  • the light shielding layer is disposed directly under the active layer.
  • the area of the first passivation layer is smaller than the area of the second passivation layer.
  • the present application also provides a method for manufacturing a liquid crystal display panel, including the display panel described in any one of the above, the method includes the following steps:
  • the first insulating layer, the second insulating layer and the first passivation layer of the thin film transistor unit use SiNx film
  • the third insulating layer and the passivation layer use SiOx film.
  • the manufacturing method steps are as follows:
  • the source and drain layers are used as a mask, and the first passivation layer is deposited using SiNx;
  • a second passivation layer is deposited using SiOx.
  • the manufacturing method steps are as follows:
  • the source and drain are used as a mask, and the first insulating layer is deposited using SiNx;
  • a second passivation layer is deposited using SiOx.
  • the present application adopts SiNx for the insulating layer material between the two metal layers inside the thin film transistor, and uses SiOx for the insulating layer material between the two metal layers outside the thin film transistor, so that the thin film transistor The light will not cause light loss and total reflection due to different refractive indexes.
  • FIG. 1 is a schematic structural diagram of a bottom-gate thin film transistor of a display panel provided by an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of a top-gate thin film transistor of a display panel provided by an embodiment of the present application.
  • 1A-1K are process diagrams of a manufacturing method of a bottom-gate thin film transistor provided by an embodiment of the present application.
  • 2A-2K are process drawings of a method for manufacturing a top-gate thin film transistor provided by an embodiment of the present application.
  • FIG. 3 is a flowchart of manufacturing a display panel provided by an embodiment of the present application.
  • FIG. 4 is a flowchart of manufacturing a bottom-gate thin film transistor of a display panel provided by an embodiment of the present application.
  • FIG. 5 is a flowchart of manufacturing a top-gate thin film transistor of a display panel according to an embodiment of the present application.
  • first and second are used for description purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated.
  • features defined as “first” and “second” may explicitly or implicitly include one or more of the features.
  • the meaning of “plurality” is two or more, unless otherwise specifically limited.
  • a display panel provided by the present application includes: a substrate, and a thin film transistor unit on the substrate; the thin film transistor unit includes a first region and a second region; the first region includes: an active layer, a first An insulating layer, a gate layer, a second insulating layer, a source-drain layer, a via, and a first passivation layer; the second region includes: a third insulating layer and a second passivation layer; wherein, the first The insulating layer, the second insulating layer, and the first passivation layer all use SiNx films, and the third insulating layer and the second passivation layer use SiOx films.
  • the substrate is an LCD substrate or an OLED substrate.
  • the thin film transistor is a top-gate thin film transistor or a bottom-gate thin film transistor.
  • FIG. 1 is a schematic structural diagram of a bottom-gate thin film transistor.
  • 1 is substrate
  • 2 is shading layer
  • 3 is buffer layer
  • 4 is active layer
  • 5 is first insulating layer
  • 6 is gate layer
  • 7 is second insulating layer
  • 8 is third insulating layer
  • 9 is over
  • 10 is a source-drain layer
  • 11 is a first passivation layer
  • 12 is a second passivation layer.
  • the substrate 1 may be a glass substrate, a quartz substrate or a resin substrate.
  • the light shielding layer 2 is mainly to prevent the active layer 4 in the thin film transistor from being illuminated, thereby affecting its driving effect.
  • the buffer layer 3 is formed on the light-shielding layer 2 and below the active layer 4 to relieve the pressure between the film layers, and also can block the external water and oxygen to prevent the external water and oxygen from entering the internal film layer in.
  • the active layer 4 is disposed directly above the light-shielding layer 2 and further includes ion-doped doped regions (not shown).
  • the first insulating layer 5, that is, the gate insulating layer, in the embodiment provided by the present application, uses a SiNx film.
  • the gate layer 6 is made of metal such as molybdenum, aluminum, aluminum-nickel alloy, molybdenum-tungsten alloy, chromium, or copper, or a combination of the foregoing metal materials.
  • the orthographic projection area of the first gate insulating layer 5 on the substrate 1 is greater than or equal to the orthographic projection area of the gate layer 6 on the substrate 1.
  • the second insulating layer 7 uses a SiNx film to avoid light loss or total reflection caused by different materials having different refractive indexes.
  • the third insulating layer 8, in the prior art, the via 9 is etched through the reticle after the second insulating layer 7 is deposited, which is different from the prior art.
  • the second insulating layer 7 and the third insulating layer 8 use different materials, so the via 9 here does not need to be etched, but is formed by depositing twice using two different masks.
  • the source-drain layer 10 metals such as molybdenum, aluminum, aluminum-nickel alloy, molybdenum-tungsten alloy, chromium, copper, or titanium-aluminum alloy can be used, or a combination of the foregoing metal materials can also be used.
  • the source-drain layer 10 is electrically connected to the doped region on the active layer 4 through the via 9.
  • the first passivation layer 11 is disposed between the source and drain layers 10, and uses a SiNx film.
  • the second passivation layer 12 is disposed on the source-drain layer 10 and the first passivation layer 11 to balance the flatness of the entire thin film transistor.
  • the area of the first passivation layer 11 is smaller than the area of the second passivation layer 12.
  • the second insulating layer 7 and the third insulating layer 8 are provided in the same layer, and the second passivation layer 12 and the first passivation layer 11 are provided in the same layer.
  • the second insulating layer 7 covers the gate layer 6, the gate layer 6 is disposed above the first insulating layer 5, the first insulating layer 5, The gate layer 6, the second insulating layer 7 and the first passivation layer 11 are surrounded by the thin film transistor via 9 inside the thin film transistor, that is, the first region.
  • the second passivation layer 12 covers the first passivation layer 11 and the source-drain layer 10.
  • the present application also provides a method for manufacturing a liquid crystal display panel.
  • the method includes the following steps: S1, providing a substrate; S2, forming a thin film transistor unit on the substrate;
  • the first insulating layer, the second insulating layer, and the first passivation layer use SiNx films, and the third insulating layer and the passivation layer use SiOx films.
  • the manufacturing method steps are as follows: S1, providing a substrate; S20, using PECVD on the substrate Deposit the base film and amorphous silicon film; S30, deposit the active layer and the first insulating layer, then sputter a metal layer, etched into the gate by photolithography; S40, use the gate as a mask, use SiNx to deposit the first Two insulating layers; S50, using vias and the second insulating layer as a mask, using SiOx to deposit a third insulating layer; S60, sputtering a second metal layer, photolithographic etching into source and drain layers; S70, using the source The drain layer is used as a mask, and the first passivation layer is deposited using SiNx; S80, the second passivation layer is deposited using SiOx.
  • FIG. 1A is a substrate 1
  • FIG. 1B is a light-shielding layer 2 deposited on the substrate 1
  • FIG. 1C is a buffer layer 3 is deposited on the substrate 1 and the light-shielding layer 2
  • FIG. 1D is an active layer 4 deposited on the buffer layer 3
  • shading Layer 3 can shield the active layer 4 exactly.
  • FIG. 1E shows the deposition of the first insulating layer 5 on the active layer 4.
  • FIG. 1F deposits a metal layer on the first insulating layer 5 and sputters into the gate layer 6
  • the orthographic projection area of the gate layer 6 on the substrate 1 is less than or equal to the orthographic projection area of the first insulating layer 5 on the substrate.
  • FIG. 1E shows the deposition of the first insulating layer 5 on the active layer 4.
  • FIG. 1F deposits a metal layer on the first insulating layer 5 and sputters into the gate layer 6
  • the orthographic projection area of the gate layer 6 on the substrate 1 is less than
  • FIG. 1G deposits a second insulating layer 7 on the gate layer 6 through a mask plate, using SiNx thin film material, so that the third insulating layer 7 surrounds the first insulating layer 5 and the gate layer 6 inside the third insulating layer 7,
  • Fig. 1H deposits a third insulating layer 8 through a mask with a via hole shape, using the material SiOx,
  • Fig. 1I deposits a metal layer on the second insulating layer 7 and the third insulating layer 8 and sputters into the source and drain layers 10.
  • FIG. 1J deposits the first passivation layer 11 between the source and drain layers 10, and FIG. 1K continues to deposit the second passivation layer 12 on the source and drain layers 10 and the first passivation layer 11, so that the entire thin film transistor The surface remains flat.
  • FIG. 2 is a schematic structural diagram of a top-gate thin film transistor.
  • 1' is the substrate, 2'is the light shielding layer, 3'is the buffer layer, 4'is the source and drain layers, 5'is the first insulating layer, 6'is the via, 7'is the active layer, and 8'is the first Two insulating layers, 9'is a third insulating layer, 10' is a gate layer, 11' is a first passivation layer, and 12' is a second passivation layer.
  • the substrate 1' which may be a glass substrate, a quartz substrate, or a resin substrate.
  • the light shielding layer 2' is mainly to prevent the active layer 7'in the thin film transistor from being illuminated, thereby affecting its driving effect.
  • the buffer layer 3' is formed on the light-shielding layer 2', under the source-drain layer 4', to relieve the pressure between the film layers, and at the same time, it can also block the external water and oxygen to prevent the external water and oxygen Into the inner membrane.
  • source and drain layers 4' metals such as molybdenum, aluminum, aluminum-nickel alloy, molybdenum-tungsten alloy, chromium, copper, or titanium-aluminum alloy can be used, or a combination of the above-mentioned metal materials can also be used.
  • the source-drain layer 4' is electrically connected to the doped region on the active layer 7'through the via 6'.
  • the first insulating layer 5' that is, the gate insulating layer, in the embodiment provided by the present application, uses a SiNx film.
  • the active layer 7' is disposed above the light-shielding layer 2', and further includes ion-doped doped regions (not shown).
  • the second insulating layer 8 uses a SiNx film to avoid light loss or total reflection caused by different materials having different refractive indexes.
  • the third insulating layer 9' In the prior art, the via 6'is etched through a mask after the first insulating layer 5'is deposited.
  • the top-gate thin film transistor provided in this application.
  • the third insulating layer 9' is deposited, the corresponding mask is used for deposition, and the via 6'is not formed by photolithography.
  • the gate layer 10' is made of metal such as molybdenum, aluminum, aluminum-nickel alloy, molybdenum-tungsten alloy, chromium, or copper, or a combination of the above-mentioned metal materials.
  • the orthographic projection area of the first gate insulating layer 5'on the substrate 1' is greater than or equal to the orthographic projection area of the gate layer 10' on the substrate 1'.
  • the first passivation layer 11' is disposed between the channels of the gate layer 10' and uses a SiNx film.
  • the second passivation layer 12' is provided outside the channel of the gate layer 10' and above the third insulating layer 9', which is used to balance the flatness of the entire thin film transistor.
  • the area of the first passivation layer 11' is smaller than the area of the second passivation layer 12'.
  • the second insulating layer 8' is provided in the same layer as the third insulating layer 9', the second passivation layer 12' and the first passivation layer 11' Set on the same level.
  • the second insulating layer 8' covers the active layer 7'
  • the gate layer 10' is disposed above the second insulating layer 8'
  • the first The insulating layer 5', the active layer 7', the second insulating layer 8'and the first passivation layer 11' are surrounded by the thin film transistor inside the thin film transistor, that is, the first region.
  • the second passivation layer 12' is provided in the same layer as the first passivation layer 11', covering the third insulating layer 9'.
  • the present application also provides a method for manufacturing a liquid crystal display panel.
  • the method includes the following steps: S1, providing a substrate; S2, forming a thin film transistor unit on the substrate;
  • the first gate insulating layer, the second gate insulating layer and the first passivation layer use SiNx thin films, and the third insulating layer and the passivation layer use SiOx thin films.
  • the manufacturing method steps are as follows: S1′, providing a substrate; S20′, on the substrate Use PECVD to deposit the base film and amorphous silicon film; S30', deposit and sputter a metal layer, and etch into the source and drain layers; S40', use the source and drain as a mask, and use SiNx to deposit the first insulating layer ; S50', using the via hole and the first insulating layer as a mask to deposit an active layer; S60', using SiNx to deposit a second insulating layer; S70', using SiOx to deposit a third insulating layer; S80', depositing sputtering Two metal layers, etched into the gate by photolithography; S90', using SiNx to deposit the first passivation layer; S100', using SiOx to deposit the second passivation
  • FIG. 2A is a substrate 1′
  • FIG. 2B is a light-shielding layer 2′ deposited on the substrate 1′
  • FIG. 2C is a buffer layer 3′ is deposited on the substrate 1′ and the light-shielding layer 2′
  • FIG. 2D is on the buffer layer 3′
  • a metal layer is deposited and sputtered into the source-drain layer 4'.
  • FIG. 2E deposits a first insulating layer 5'between the source and drain layers 4'
  • FIG. 2F deposits an active layer 7 on the first insulating layer 5' '
  • Figure 2G deposits a second insulating layer 8'on the active layer 7'
  • Figure 2H deposits a third insulating layer 9'on the outside of the second insulating layer 8'on the buffer layer 3', at this time, the active
  • FIG. 2I deposits the gate layer 10′ above the second insulating layer 8′
  • FIG. 2J deposits the first layer in the channel of the gate layer 10′.
  • a passivation layer 11 ′ In FIG. 2K, a second passivation layer is deposited on the outside of the gate layer 10 ′ and above the third insulating layer 9 ′, so that the entire surface of the thin film transistor remains flat.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Thin Film Transistor (AREA)

Abstract

A display panel, comprising: a substrate, and a thin film transistor unit located on the substrate; the thin film transistor unit comprises a first region and a second region; the first region comprises an active layer, a first insulating layer, a gate layer, a second insulating layer, a source/drain layer, a via hole and a first passivation layer; and the second region comprises a third insulating layer and a second passivation layer; the first insulating layer, the second insulating layer and the first passivation layer use a SiNx thin film, and the third insulating layer and the second passivation layer use a SiOx thin film.

Description

显示面板及其制作方法Display panel and manufacturing method thereof 技术领域Technical field
本申请涉及显示领域，特别是涉及显示面板及其制作方法。The present application relates to the field of display, in particular to a display panel and a manufacturing method thereof.
背景技术Background technique
目前，在LCD（Liquid Crystal Display，液晶显示器）或者底发光OLED（Organic Light-Emitting Diode, 有机发光半导体）显示面板中，两层金属之间通常采用SiNx与SiOx，由于SiNx与SiOx的折射率不一样，会造成发出的光的损失以及全反射等，由于全反射会造成角度较大的地方的光无法射出，如果在角度比较大的地方观看则会产生色偏，严重的甚至是大视角色偏。At present, in LCD (Liquid Crystal Display, liquid crystal display) or bottom-emitting OLED (Organic Light-Emitting Diode (organic light-emitting semiconductor) display panel, SiNx and SiOx are usually used between the two layers of metal, because the refractive index of SiNx and SiOx are different, it will cause the loss of the emitted light and total reflection, etc. The light in a place with a large angle cannot be emitted. If it is viewed in a place with a relatively large angle, color cast will occur. In serious cases, even a large-vision character may be biased.
因此，现有的显示面板技术中，还存在显示面板的薄膜晶体管中因不同的膜层材料反射率不同而造成色偏的问题，急需改进。Therefore, in the existing display panel technology, there is also a problem of color shift caused by different reflectances of different film materials in the thin film transistors of the display panel, and improvements are urgently needed.
技术问题technical problem
本申请涉及一种显示面板及其制作方法，用于解决现有技术中存在的显示面板的薄膜晶体管中因不同的膜层材料反射率不同而造成色偏的问题。The present application relates to a display panel and a manufacturing method thereof, which are used to solve the problem of color shift caused by different reflectances of different film materials in thin film transistors of display panels in the prior art.
技术解决方案Technical solution
为解决上述问题，本申请提供的技术方案如下：To solve the above problems, the technical solutions provided by this application are as follows:
本申请提供的一种显示面板，包括：基板，以及位于所述基板上的薄膜晶体管单元；A display panel provided by the present application includes: a substrate, and a thin film transistor unit on the substrate;
所述薄膜晶体管单元包括第一区域和第二区域；The thin film transistor unit includes a first region and a second region;
所述第一区域包括：有源层、第一绝缘层、栅极层、第二绝缘层、源漏极层、过孔以及第一钝化层；The first region includes: an active layer, a first insulating layer, a gate layer, a second insulating layer, a source and drain layer, a via, and a first passivation layer;
所述第二区域包括：第三绝缘层和第二钝化层；The second region includes: a third insulating layer and a second passivation layer;
其中，所述第一绝缘层、第二绝缘层及第一钝化层均采用SiNx薄膜，所述第三绝缘层和所述第二钝化层采用SiOx薄膜，所述基板为玻璃基板、石英基板或是树脂基板。Wherein, the first insulating layer, the second insulating layer and the first passivation layer are all made of SiNx film, the third insulating layer and the second passivation layer are made of SiOx film, and the substrate is a glass substrate, quartz The substrate or resin substrate.
根据本申请提供的一优选实施例，所述基板为LCD基板或是OLED基板。According to a preferred embodiment provided by the present application, the substrate is an LCD substrate or an OLED substrate.
根据本申请提供的一优选实施例，所述第一绝缘层在所述基板上的正投影面积，大于或等于所述栅极层在所述基板上的正投影面积。According to a preferred embodiment provided by the present application, the orthographic projection area of the first insulating layer on the substrate is greater than or equal to the orthographic projection area of the gate layer on the substrate.
根据本申请提供的一优选实施例，所述薄膜晶体管为顶栅型薄膜晶体管或是底栅型薄膜晶体管。According to a preferred embodiment provided by the present application, the thin film transistor is a top gate type thin film transistor or a bottom gate type thin film transistor.
根据本申请提供的一优选实施例，所述第二绝缘层与所述第三绝缘层同层设置，所述第二钝化层与所述第一钝化层同层设置。According to a preferred embodiment provided by the present application, the second insulating layer and the third insulating layer are provided in the same layer, and the second passivation layer and the first passivation layer are provided in the same layer.
根据本申请提供的一优选实施例，遮光层设置在所述有源层的正下方。According to a preferred embodiment provided by the present application, the light shielding layer is disposed directly under the active layer.
根据本申请提供的一优选实施例，所述缓冲层覆盖在所述遮光层上面。According to a preferred embodiment provided by the present application, the buffer layer covers the light shielding layer.
根据本申请提供的一优选实施例，所述栅极层的材料为：钼、铝、铝镍合金、钼钨合金、铬或铜中的一种或多种。According to a preferred embodiment provided by the present application, the material of the gate layer is one or more of molybdenum, aluminum, aluminum-nickel alloy, molybdenum-tungsten alloy, chromium or copper.
根据本申请提供的一优选实施例，所述薄膜晶体管中，源极和漏极的材料为：钼、铝、铝镍合金、钼钨合金、铬、铜或钛铝合金中的一种或是多种。According to a preferred embodiment provided by the present application, in the thin film transistor, the materials of the source and the drain are: one of molybdenum, aluminum, aluminum-nickel alloy, molybdenum-tungsten alloy, chromium, copper or titanium aluminum alloy or Multiple.
根据本申请提供的一优选实施例，所述源极和所述漏极分别通过过孔与所述有源层电性连接。According to a preferred embodiment provided by the present application, the source electrode and the drain electrode are electrically connected to the active layer through via holes, respectively.
根据本申请提供的一优选实施例，所述第一钝化层的面积小于所述第二钝化层的面积。According to a preferred embodiment provided by the present application, the area of the first passivation layer is smaller than the area of the second passivation layer.
根据本申请提供的一优选实施例，所述第二钝化层覆盖在所述第三绝缘层上面。According to a preferred embodiment provided by the present application, the second passivation layer covers the third insulating layer.
本申请还提供另一种显示面板，包括：基板，以及位于所述基板上的薄膜晶体管单元；The present application also provides another display panel, including: a substrate, and a thin film transistor unit on the substrate;
所述薄膜晶体管单元包括第一区域和第二区域；The thin film transistor unit includes a first region and a second region;
所述第一区域包括：有源层、第一绝缘层、栅极层、第二绝缘层、源漏极层、过孔以及第一钝化层；The first region includes: an active layer, a first insulating layer, a gate layer, a second insulating layer, a source and drain layer, a via, and a first passivation layer;
所述第二区域包括：第三绝缘层和第二钝化层；The second region includes: a third insulating layer and a second passivation layer;
其中，所述第一绝缘层、第二绝缘层及第一钝化层均采用SiNx薄膜，所述第三绝缘层和所述第二钝化层采用SiOx薄膜。Wherein, the first insulating layer, the second insulating layer and the first passivation layer all use SiNx film, and the third insulating layer and the second passivation layer use SiOx film.
根据本申请提供的一优选实施例，所述基板为LCD基板或是OLED基板。According to a preferred embodiment provided by the present application, the substrate is an LCD substrate or an OLED substrate.
根据本申请提供的一优选实施例，所述第一绝缘层在所述基板上的正投影面积，大于或等于所述栅极层在所述基板上的正投影面积。According to a preferred embodiment provided by the present application, the orthographic projection area of the first insulating layer on the substrate is greater than or equal to the orthographic projection area of the gate layer on the substrate.
根据本申请提供的一优选实施例，所述薄膜晶体管为顶栅型薄膜晶体管或是底栅型薄膜晶体管。According to a preferred embodiment provided by the present application, the thin film transistor is a top gate type thin film transistor or a bottom gate type thin film transistor.
根据本申请提供的一优选实施例，所述第二绝缘层与所述第三绝缘层同层设置，所述第二钝化层与所述第一钝化层同层设置。According to a preferred embodiment provided by the present application, the second insulating layer and the third insulating layer are provided in the same layer, and the second passivation layer and the first passivation layer are provided in the same layer.
根据本申请提供的一优选实施例，所述遮光层设置在所述有源层的正下方。According to a preferred embodiment provided by the present application, the light shielding layer is disposed directly under the active layer.
根据本申请提供的一优选实施例，所述第一钝化层的面积小于所述第二钝化层的面积。According to a preferred embodiment provided by the present application, the area of the first passivation layer is smaller than the area of the second passivation layer.
本申请还提供一种液晶显示面板的制作方法，包含上述任一项所述的显示面板，该方法包括如下步骤：The present application also provides a method for manufacturing a liquid crystal display panel, including the display panel described in any one of the above, the method includes the following steps:
S1，提供一基板；S1, provide a substrate;
S2，在所述基板上形成薄膜晶体管单元；S2, forming a thin film transistor unit on the substrate;
其中，所述薄膜晶体管单元的所述第一绝缘层、第二绝缘层及第一钝化层采用SiNx薄膜，所述第三绝缘层和所述钝化层采用SiOx薄膜。Wherein, the first insulating layer, the second insulating layer and the first passivation layer of the thin film transistor unit use SiNx film, and the third insulating layer and the passivation layer use SiOx film.
根据本申请提供的一优选实施例，所述薄膜晶体管为底栅型薄膜晶体管时，其制作方法步骤如下：According to a preferred embodiment provided by the present application, when the thin film transistor is a bottom gate thin film transistor, the manufacturing method steps are as follows:
S1，提供一基板；S1, provide a substrate;
S20，在基板上用PECVD沉积基层薄膜和非晶硅薄膜；S20, depositing a base film and an amorphous silicon film on the substrate by PECVD;
S30，沉积有源层、第一绝缘层，接着溅射一层金属层，光刻刻蚀成栅极；S30, depositing an active layer and a first insulating layer, then sputtering a metal layer, and etching into a gate by photolithography;
S40，利用栅极做掩膜，采用SiNx沉积第二绝缘层；S40, using the gate as a mask, and using SiNx to deposit a second insulating layer;
S50，利用过孔和第二绝缘层做掩膜，采用SiOx沉积第三绝缘层；S50, using the via hole and the second insulating layer as a mask, and using SiOx to deposit a third insulating layer;
S60，溅射第二层金属层，光刻刻蚀成源漏极层；S60, a second metal layer is sputtered, and the source and drain layers are etched by photolithography;
S70，利用源漏极层做掩膜，采用SiNx沉积第一钝化层；S70, the source and drain layers are used as a mask, and the first passivation layer is deposited using SiNx;
S80，采用SiOx沉积第二钝化层。S80, a second passivation layer is deposited using SiOx.
根据本申请提供的一优选实施例，所述薄膜晶体管为顶栅型薄膜晶体管时，其制作方法步骤如下：According to a preferred embodiment provided by the present application, when the thin film transistor is a top gate thin film transistor, the manufacturing method steps are as follows:
S1’，提供一基板；S1’, providing a substrate;
S20’，在基板上用PECVD沉积基层薄膜和非晶硅薄膜；S20', depositing a base film and an amorphous silicon film on the substrate by PECVD;
S30’，沉积溅射一层金属层，光刻刻蚀成源漏极层；S30', a metal layer is deposited and sputtered, and the source and drain layers are etched by photolithography;
S40’，利用源漏极做掩膜，采用SiNx沉积第一绝缘层；S40', the source and drain are used as a mask, and the first insulating layer is deposited using SiNx;
S50’，利用过孔和第一绝缘层做掩膜，沉积有源层；S50’, using the via hole and the first insulating layer as a mask to deposit an active layer;
S60’，采用SiNx沉积第二绝缘层；S60’, a second insulating layer is deposited using SiNx;
S70’，采用SiOx沉积第三绝缘层；S70’, using SiOx to deposit a third insulating layer;
S80’，沉积溅射第二层金属层，光刻刻蚀成栅极；S80', a second metal layer is deposited and sputtered, and etched into the gate by photolithography;
S90’，采用SiNx沉积第一钝化层；S90’, using SiNx to deposit the first passivation layer;
S100’，采用SiOx沉积第二钝化层。S100', a second passivation layer is deposited using SiOx.
有益效果Beneficial effect
有益效果：与现有技术相比，本申请通过将薄膜晶体管内部两金属层之间的绝缘层材料统一采用SiNx，薄膜晶体管外部两金属层之间的绝缘层材料统一采用SiOx，使得通过薄膜晶体管的光线不会因折射率不同而造成光线损失及全反射等问题。Advantageous effects: Compared with the prior art, the present application adopts SiNx for the insulating layer material between the two metal layers inside the thin film transistor, and uses SiOx for the insulating layer material between the two metal layers outside the thin film transistor, so that the thin film transistor The light will not cause light loss and total reflection due to different refractive indexes.
附图说明BRIEF DESCRIPTION
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。In order to more clearly explain the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required in the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those skilled in the art, without paying any creative work, other drawings can be obtained based on these drawings.
图1为本申请实施例提供的显示面板底栅型薄膜晶体管的结构示意图。FIG. 1 is a schematic structural diagram of a bottom-gate thin film transistor of a display panel provided by an embodiment of the present application.
图2为本申请实施例提供的显示面板顶栅型薄膜晶体管的结构示意图。2 is a schematic structural diagram of a top-gate thin film transistor of a display panel provided by an embodiment of the present application.
图1A-1K为本申请实施例提供的底栅型薄膜晶体管的制作方法工艺图。1A-1K are process diagrams of a manufacturing method of a bottom-gate thin film transistor provided by an embodiment of the present application.
图2A-2K为本申请实施例提供的顶栅型薄膜晶体管的制作方法工艺图。2A-2K are process drawings of a method for manufacturing a top-gate thin film transistor provided by an embodiment of the present application.
图3为本申请实施例提供的显示面板制作流程图。FIG. 3 is a flowchart of manufacturing a display panel provided by an embodiment of the present application.
图4为本申请实施例提供的制作显示面板底栅型薄膜晶体管的流程图。FIG. 4 is a flowchart of manufacturing a bottom-gate thin film transistor of a display panel provided by an embodiment of the present application.
图5为本申请实施例提供的制作显示面板顶栅型薄膜晶体管的流程图。FIG. 5 is a flowchart of manufacturing a top-gate thin film transistor of a display panel according to an embodiment of the present application.
本发明的实施方式Embodiments of the invention
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。The technical solutions in the embodiments of the present application will be described clearly and completely in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work fall within the protection scope of the present application.
在本申请的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”、“顺时针”、“逆时针”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。In the description of this application, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", " Back, "Left", "Right", "Vertical", "Horizontal", "Top", "Bottom", "Inner", "Outer", "Clockwise", "Counterclockwise" etc. The positional relationship is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, Therefore, it cannot be understood as a limitation to this application. In addition, the terms “first” and “second” are used for description purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise specifically limited.
本申请提供的一种显示面板包括：基板，以及位于所述基板上的薄膜晶体管单元；所述薄膜晶体管单元包括第一区域和第二区域；所述第一区域包括：有源层、第一绝缘层、栅极层、第二绝缘层、源漏极层、过孔以及第一钝化层；所述第二区域包括：第三绝缘层和第二钝化层；其中，所述第一绝缘层、第二绝缘层及第一钝化层均采用SiNx薄膜，所述第三绝缘层和所述第二钝化层采用SiOx薄膜。A display panel provided by the present application includes: a substrate, and a thin film transistor unit on the substrate; the thin film transistor unit includes a first region and a second region; the first region includes: an active layer, a first An insulating layer, a gate layer, a second insulating layer, a source-drain layer, a via, and a first passivation layer; the second region includes: a third insulating layer and a second passivation layer; wherein, the first The insulating layer, the second insulating layer, and the first passivation layer all use SiNx films, and the third insulating layer and the second passivation layer use SiOx films.
根据本申请提供的一优选实施例，所述基板为LCD基板或是OLED基板。所述薄膜晶体管为顶栅型薄膜晶体管或是底栅型薄膜晶体管。According to a preferred embodiment provided by the present application, the substrate is an LCD substrate or an OLED substrate. The thin film transistor is a top-gate thin film transistor or a bottom-gate thin film transistor.
实施例一Example one
参阅图1，图1为底栅型薄膜晶体管的结构示意图。1为基板，2为遮光层，3为缓冲层，4为有源层，5为第一绝缘层，6为栅极层，7为第二绝缘层，8为第三绝缘层，9为过孔，10为源漏极层，11为第一钝化层，12为第二钝化层。Referring to FIG. 1, FIG. 1 is a schematic structural diagram of a bottom-gate thin film transistor. 1 is substrate, 2 is shading layer, 3 is buffer layer, 4 is active layer, 5 is first insulating layer, 6 is gate layer, 7 is second insulating layer, 8 is third insulating layer, 9 is over The hole, 10 is a source-drain layer, 11 is a first passivation layer, and 12 is a second passivation layer.
基板1，该基板1可以是玻璃基板、石英基板或是树脂基板。The substrate 1 may be a glass substrate, a quartz substrate or a resin substrate.
遮光层2，主要是为了防止薄膜晶体管中的有源层4被光照，从而影响其驱动效果。The light shielding layer 2 is mainly to prevent the active layer 4 in the thin film transistor from being illuminated, thereby affecting its driving effect.
缓冲层3，形成在所述遮光层2上，所述有源层4的下方，缓解膜层之间的压力，同时也可以对外部的水氧等进行阻隔，防止外部水氧进入内部膜层中。The buffer layer 3 is formed on the light-shielding layer 2 and below the active layer 4 to relieve the pressure between the film layers, and also can block the external water and oxygen to prevent the external water and oxygen from entering the internal film layer in.
有源层4设置在所述遮光层2的正上方，其中还包括经离子掺杂的掺杂区（未画出）。The active layer 4 is disposed directly above the light-shielding layer 2 and further includes ion-doped doped regions (not shown).
第一绝缘层5，即栅绝缘层，在本申请提供的实施例中，采用SiNx薄膜。The first insulating layer 5, that is, the gate insulating layer, in the embodiment provided by the present application, uses a SiNx film.
栅极层6，采用钼、铝、铝镍合金、钼钨合金、铬、或铜等金属，也可以使用上述几种金属材料的组合物。所述第一栅绝缘层5在所述基板1上的正投影面积，大于或等于所述栅极层6在所述基板1上的正投影面积。The gate layer 6 is made of metal such as molybdenum, aluminum, aluminum-nickel alloy, molybdenum-tungsten alloy, chromium, or copper, or a combination of the foregoing metal materials. The orthographic projection area of the first gate insulating layer 5 on the substrate 1 is greater than or equal to the orthographic projection area of the gate layer 6 on the substrate 1.
第二绝缘层7，为避免不同材料对光线折射率不同造成光的损失或是全反射，本申请采用SiNx薄膜。The second insulating layer 7 uses a SiNx film to avoid light loss or total reflection caused by different materials having different refractive indexes.
第三绝缘层8，现有技术中，过孔9是在第二绝缘层7沉积之后，通过掩膜版对其光刻刻蚀出来的，与现有技术不同的是，本申请由于特地将第二绝缘层7和第三绝缘层8采用不同的材料，所以此处的过孔9不需要进行刻蚀，而是通过采用两张不同的掩膜版，沉积两次所形成的。The third insulating layer 8, in the prior art, the via 9 is etched through the reticle after the second insulating layer 7 is deposited, which is different from the prior art. The second insulating layer 7 and the third insulating layer 8 use different materials, so the via 9 here does not need to be etched, but is formed by depositing twice using two different masks.
源漏极层10，可以采用钼、铝、铝镍合金、钼钨合金、铬、铜或钛铝合金等金属，也可以使用上述几种金属材料的组合物。源漏极层10通过过孔9与有源层4上的掺杂区电性连接在一起。For the source-drain layer 10, metals such as molybdenum, aluminum, aluminum-nickel alloy, molybdenum-tungsten alloy, chromium, copper, or titanium-aluminum alloy can be used, or a combination of the foregoing metal materials can also be used. The source-drain layer 10 is electrically connected to the doped region on the active layer 4 through the via 9.
第一钝化层11，设置在所述源漏极层10之间，采用SiNx薄膜。The first passivation layer 11 is disposed between the source and drain layers 10, and uses a SiNx film.
第二钝化层12，设置在所述源漏极层10和所述第一钝化层11之上，用于平衡整个薄膜晶体管的平整性。第一钝化层11的面积小于第二钝化层12的面积。The second passivation layer 12 is disposed on the source-drain layer 10 and the first passivation layer 11 to balance the flatness of the entire thin film transistor. The area of the first passivation layer 11 is smaller than the area of the second passivation layer 12.
根据本申请提供的一优选实施例，所述第二绝缘层7与所述第三绝缘层8同层设置，所述第二钝化层12与所述第一钝化层11同层设置。According to a preferred embodiment provided by the present application, the second insulating layer 7 and the third insulating layer 8 are provided in the same layer, and the second passivation layer 12 and the first passivation layer 11 are provided in the same layer.
根据本申请提供的一优选实施例，所述第二绝缘层7覆盖所述栅极层6，所述栅极层6设置在所述第一绝缘层5上面，所述第一绝缘层5，所述栅极层6，所述第二绝缘层7以及第一钝化层11被所述薄膜晶体管的过孔9包围在所述薄膜晶体管的内部，即第一区域。According to a preferred embodiment provided by the present application, the second insulating layer 7 covers the gate layer 6, the gate layer 6 is disposed above the first insulating layer 5, the first insulating layer 5, The gate layer 6, the second insulating layer 7 and the first passivation layer 11 are surrounded by the thin film transistor via 9 inside the thin film transistor, that is, the first region.
根据本申请提供的一优选实施例，所述第二钝化层12覆盖所述第一钝化层11和所述源漏极层10。According to a preferred embodiment provided by the present application, the second passivation layer 12 covers the first passivation layer 11 and the source-drain layer 10.
参阅图3，本申请还提供一种液晶显示面板的制作方法，该方法包括如下步骤：S1，提供一基板；S2，在所述基板上形成薄膜晶体管单元；其中，所述薄膜晶体管单元的所述第一绝缘层、第二绝缘层及第一钝化层采用SiNx薄膜，所述第三绝缘层和所述钝化层采用SiOx薄膜。Referring to FIG. 3, the present application also provides a method for manufacturing a liquid crystal display panel. The method includes the following steps: S1, providing a substrate; S2, forming a thin film transistor unit on the substrate; The first insulating layer, the second insulating layer, and the first passivation layer use SiNx films, and the third insulating layer and the passivation layer use SiOx films.
参阅图4及图1A-1K，根据本申请提供的一优选实施例，所述薄膜晶体管为底栅型薄膜晶体管时，其制作方法步骤如下：S1，提供一基板；S20，在基板上用PECVD沉积基层薄膜和非晶硅薄膜；S30，沉积有源层、第一绝缘层，接着溅射一层金属层，光刻刻蚀成栅极；S40，利用栅极做掩膜，采用SiNx沉积第二绝缘层；S50，利用过孔和第二绝缘层做掩膜，采用SiOx沉积第三绝缘层；S60，溅射第二层金属层，光刻刻蚀成源漏极层；S70，利用源漏极层做掩膜，采用SiNx沉积第一钝化层；S80，采用SiOx沉积第二钝化层。Referring to FIGS. 4 and 1A-1K, according to a preferred embodiment provided by the present application, when the thin-film transistor is a bottom-gate thin-film transistor, the manufacturing method steps are as follows: S1, providing a substrate; S20, using PECVD on the substrate Deposit the base film and amorphous silicon film; S30, deposit the active layer and the first insulating layer, then sputter a metal layer, etched into the gate by photolithography; S40, use the gate as a mask, use SiNx to deposit the first Two insulating layers; S50, using vias and the second insulating layer as a mask, using SiOx to deposit a third insulating layer; S60, sputtering a second metal layer, photolithographic etching into source and drain layers; S70, using the source The drain layer is used as a mask, and the first passivation layer is deposited using SiNx; S80, the second passivation layer is deposited using SiOx.
图1A为一基板1，图1B为在基板1上沉积遮光层2，图1C为在基板1和遮光层2上沉积缓冲层3，图1D为在缓冲层3上沉积有源层4，遮光层3正好可以对有源层4进行遮挡，图1E为在有源层4上沉积第一绝缘层5，图1F在第一绝缘层5上沉积一层金属层，溅射成栅极层6，栅极层6在基板1上的正投影面积小于或等于第一绝缘层5在基板上的正投影面积。图1G通过掩膜版在栅极层6上沉积第二绝缘层7，采用SiNx薄膜材料，使得第三绝缘层7将第一绝缘层5和栅极层6包围在第三绝缘层7里面，图1H通过带有过孔形状的掩膜版，沉积第三绝缘层8，采用材料SiOx，图1I在第二绝缘层7和第三绝缘层8上沉积金属层，溅射成源漏极层10，图1J在源漏极层10之间沉积第一钝化层11，图1K在源漏极层10和第一钝化层11上继续沉积第二钝化层12，使得整个薄膜晶体管的表面保持平整。1A is a substrate 1, FIG. 1B is a light-shielding layer 2 deposited on the substrate 1, FIG. 1C is a buffer layer 3 is deposited on the substrate 1 and the light-shielding layer 2, FIG. 1D is an active layer 4 deposited on the buffer layer 3, shading Layer 3 can shield the active layer 4 exactly. FIG. 1E shows the deposition of the first insulating layer 5 on the active layer 4. FIG. 1F deposits a metal layer on the first insulating layer 5 and sputters into the gate layer 6 The orthographic projection area of the gate layer 6 on the substrate 1 is less than or equal to the orthographic projection area of the first insulating layer 5 on the substrate. FIG. 1G deposits a second insulating layer 7 on the gate layer 6 through a mask plate, using SiNx thin film material, so that the third insulating layer 7 surrounds the first insulating layer 5 and the gate layer 6 inside the third insulating layer 7, Fig. 1H deposits a third insulating layer 8 through a mask with a via hole shape, using the material SiOx, Fig. 1I deposits a metal layer on the second insulating layer 7 and the third insulating layer 8 and sputters into the source and drain layers 10. FIG. 1J deposits the first passivation layer 11 between the source and drain layers 10, and FIG. 1K continues to deposit the second passivation layer 12 on the source and drain layers 10 and the first passivation layer 11, so that the entire thin film transistor The surface remains flat.
实施例二Example 2
参阅图1，图2为顶栅型薄膜晶体管的结构示意图。1’为基板，2’为遮光层，3’为缓冲层，4’为源漏极层，5’为第一绝缘层，6’为过孔，7’为有源层，8’为第二绝缘层，9’为第三绝缘层，10’为栅极层，11’为第一钝化层，12’为第二钝化层。Referring to FIG. 1, FIG. 2 is a schematic structural diagram of a top-gate thin film transistor. 1'is the substrate, 2'is the light shielding layer, 3'is the buffer layer, 4'is the source and drain layers, 5'is the first insulating layer, 6'is the via, 7'is the active layer, and 8'is the first Two insulating layers, 9'is a third insulating layer, 10' is a gate layer, 11' is a first passivation layer, and 12' is a second passivation layer.
基板1’，该基板1’可以是玻璃基板、石英基板或是树脂基板。The substrate 1', which may be a glass substrate, a quartz substrate, or a resin substrate.
遮光层2’，主要是为了防止薄膜晶体管中的有源层7’被光照，从而影响其驱动效果。The light shielding layer 2'is mainly to prevent the active layer 7'in the thin film transistor from being illuminated, thereby affecting its driving effect.
缓冲层3’，形成在所述遮光层2’上，所述源漏极层4’的下方，缓解膜层之间的压力，同时也可以对外部的水氧等进行阻隔，防止外部水氧进入内部膜层中。The buffer layer 3'is formed on the light-shielding layer 2', under the source-drain layer 4', to relieve the pressure between the film layers, and at the same time, it can also block the external water and oxygen to prevent the external water and oxygen Into the inner membrane.
源漏极层4’，可以采用钼、铝、铝镍合金、钼钨合金、铬、铜或钛铝合金等金属，也可以使用上述几种金属材料的组合物。源漏极层4’通过过孔6’与有源层7’上的掺杂区电性连接在一起。For the source and drain layers 4', metals such as molybdenum, aluminum, aluminum-nickel alloy, molybdenum-tungsten alloy, chromium, copper, or titanium-aluminum alloy can be used, or a combination of the above-mentioned metal materials can also be used. The source-drain layer 4'is electrically connected to the doped region on the active layer 7'through the via 6'.
第一绝缘层5’，即栅绝缘层，在本申请提供的实施例中，采用SiNx薄膜。The first insulating layer 5', that is, the gate insulating layer, in the embodiment provided by the present application, uses a SiNx film.
有源层7’设置在所述遮光层2’上方，其中还包括经离子掺杂的掺杂区（未画出）。The active layer 7'is disposed above the light-shielding layer 2', and further includes ion-doped doped regions (not shown).
第二绝缘层8’，为避免不同材料对光线折射率不同造成光的损失或是全反射，本申请采用SiNx薄膜。The second insulating layer 8'uses a SiNx film to avoid light loss or total reflection caused by different materials having different refractive indexes.
第三绝缘层9’，现有技术中，过孔6’是在第一绝缘层5’沉积之后，通过掩膜版对其光刻刻蚀出来的，在本申请提供的顶栅型薄膜晶体管实施例中，在沉积第三绝缘层9’时，采用对应的掩膜版进行沉积，而不采用光刻刻蚀的方式形成过孔6’。The third insulating layer 9'. In the prior art, the via 6'is etched through a mask after the first insulating layer 5'is deposited. The top-gate thin film transistor provided in this application In the embodiment, when the third insulating layer 9'is deposited, the corresponding mask is used for deposition, and the via 6'is not formed by photolithography.
栅极层10’，采用钼、铝、铝镍合金、钼钨合金、铬、或铜等金属，也可以使用上述几种金属材料的组合物。所述第一栅绝缘层5’在所述基板1’上的正投影面积，大于或等于所述栅极层10’在所述基板1’上的正投影面积。The gate layer 10' is made of metal such as molybdenum, aluminum, aluminum-nickel alloy, molybdenum-tungsten alloy, chromium, or copper, or a combination of the above-mentioned metal materials. The orthographic projection area of the first gate insulating layer 5'on the substrate 1'is greater than or equal to the orthographic projection area of the gate layer 10' on the substrate 1'.
第一钝化层11’，设置在所述栅极层10’的沟道之间，采用SiNx薄膜。The first passivation layer 11' is disposed between the channels of the gate layer 10' and uses a SiNx film.
第二钝化层12’，设置在所述栅极层10’的沟道之外，所述第三绝缘层9’之上，用于平衡整个薄膜晶体管的平整性。第一钝化层11’的面积小于第二钝化层12’的面积。The second passivation layer 12' is provided outside the channel of the gate layer 10' and above the third insulating layer 9', which is used to balance the flatness of the entire thin film transistor. The area of the first passivation layer 11' is smaller than the area of the second passivation layer 12'.
根据本申请提供的一优选实施例，所述第二绝缘层8’与所述第三绝缘层9’同层设置，所述第二钝化层12’与所述第一钝化层11’同层设置。According to a preferred embodiment provided by the present application, the second insulating layer 8'is provided in the same layer as the third insulating layer 9', the second passivation layer 12' and the first passivation layer 11' Set on the same level.
根据本申请提供的一优选实施例，所述第二绝缘层8’覆盖所述有源层7’，所述栅极层10’设置在所述第二绝缘层8’上面，所述第一绝缘层5’，所述有源层7’，所述第二绝缘层8’以及第一钝化层11’被所述薄膜晶体管包围在所述薄膜晶体管的内部，即第一区域。According to a preferred embodiment provided by the present application, the second insulating layer 8'covers the active layer 7', the gate layer 10' is disposed above the second insulating layer 8', and the first The insulating layer 5', the active layer 7', the second insulating layer 8'and the first passivation layer 11' are surrounded by the thin film transistor inside the thin film transistor, that is, the first region.
根据本申请提供的一优选实施例，所述第二钝化层12’与所述第一钝化层11’同层设置，覆盖在所述第三绝缘层9’上面。According to a preferred embodiment provided by the present application, the second passivation layer 12' is provided in the same layer as the first passivation layer 11', covering the third insulating layer 9'.
参阅图3，本申请还提供一种液晶显示面板的制作方法，该方法包括如下步骤：S1，提供一基板；S2，在所述基板上形成薄膜晶体管单元；其中，所述薄膜晶体管单元的所述第一栅绝缘层、第二栅绝缘层及第一钝化层采用SiNx薄膜，所述第三绝缘层和所述钝化层采用SiOx薄膜。Referring to FIG. 3, the present application also provides a method for manufacturing a liquid crystal display panel. The method includes the following steps: S1, providing a substrate; S2, forming a thin film transistor unit on the substrate; The first gate insulating layer, the second gate insulating layer and the first passivation layer use SiNx thin films, and the third insulating layer and the passivation layer use SiOx thin films.
参阅图5及图2A-2K，根据本申请提供的一优选实施例，所述薄膜晶体管为顶栅型薄膜晶体管时，其制作方法步骤如下：S1’，提供一基板；S20’，在基板上用PECVD沉积基层薄膜和非晶硅薄膜；S30’，沉积溅射一层金属层，光刻刻蚀成源漏极层；S40’，利用源漏极做掩膜，采用SiNx沉积第一绝缘层；S50’，利用过孔和第一绝缘层做掩膜，沉积有源层；S60’，采用SiNx沉积第二绝缘层；S70’，采用SiOx沉积第三绝缘层；S80’，沉积溅射第二层金属层，光刻刻蚀成栅极；S90’，采用SiNx沉积第一钝化层；S100’，采用SiOx沉积第二钝化层。Referring to FIGS. 5 and 2A-2K, according to a preferred embodiment provided by the present application, when the thin-film transistor is a top-gate thin-film transistor, the manufacturing method steps are as follows: S1′, providing a substrate; S20′, on the substrate Use PECVD to deposit the base film and amorphous silicon film; S30', deposit and sputter a metal layer, and etch into the source and drain layers; S40', use the source and drain as a mask, and use SiNx to deposit the first insulating layer ; S50', using the via hole and the first insulating layer as a mask to deposit an active layer; S60', using SiNx to deposit a second insulating layer; S70', using SiOx to deposit a third insulating layer; S80', depositing sputtering Two metal layers, etched into the gate by photolithography; S90', using SiNx to deposit the first passivation layer; S100', using SiOx to deposit the second passivation layer.
图2A为一基板1’，图2B为在基板1’上沉积遮光层2’，图2 C为在基板1’和遮光层2’上沉积缓冲层3’，图2D在缓冲层3’上沉积一层金属层，溅射成源漏极层4’，图2E在源漏极层4’之间沉积第一绝缘层5’，图2F在第一绝缘层5’上沉积有源层7’，图2G在有源层7’上沉积第二绝缘层8’，图2H在缓冲层3’上面，第二绝缘层8’外侧沉积第三绝缘层9’，此时，要在有源层7’和源漏极层4’之间流出过孔6’的位置，图2I在第二绝缘层8’上方沉积栅极层10’，图2J在栅极层10’的沟道内沉积第一钝化层11’，图2K在栅极层10’外侧以及第三绝缘层9’上面沉积第二钝化层，使得整个薄膜晶体管表面保持平整。FIG. 2A is a substrate 1′, FIG. 2B is a light-shielding layer 2′ deposited on the substrate 1′, FIG. 2C is a buffer layer 3′ is deposited on the substrate 1′ and the light-shielding layer 2′, and FIG. 2D is on the buffer layer 3′ A metal layer is deposited and sputtered into the source-drain layer 4'. FIG. 2E deposits a first insulating layer 5'between the source and drain layers 4', and FIG. 2F deposits an active layer 7 on the first insulating layer 5' ', Figure 2G deposits a second insulating layer 8'on the active layer 7', Figure 2H deposits a third insulating layer 9'on the outside of the second insulating layer 8'on the buffer layer 3', at this time, the active The position of the outflow via 6'between the layer 7'and the source-drain layer 4', FIG. 2I deposits the gate layer 10′ above the second insulating layer 8′, and FIG. 2J deposits the first layer in the channel of the gate layer 10′. A passivation layer 11 ′. In FIG. 2K, a second passivation layer is deposited on the outside of the gate layer 10 ′ and above the third insulating layer 9 ′, so that the entire surface of the thin film transistor remains flat.
以上对本申请实施例所提供的一种显示面板及其制作方法进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。The display panel and the manufacturing method thereof provided by the embodiments of the present application are described in detail above. Specific examples are used in this paper to explain the principle and implementation of the present application. The descriptions of the above embodiments are only used to help understand the present invention. The applied technical solutions and their core ideas; those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or equivalently replace some of the technical features; and these modifications or replacements, The essence of the corresponding technical solutions does not deviate from the scope of the technical solutions of the embodiments of the present application.

Claims (20)

  1. 一种显示面板，其特征在于，包括：基板，以及位于所述基板上的薄膜晶体管单元；A display panel, comprising: a substrate, and a thin film transistor unit on the substrate;
    所述薄膜晶体管单元包括第一区域和第二区域；The thin film transistor unit includes a first region and a second region;
    所述第一区域包括：有源层、第一绝缘层、栅极层、第二绝缘层、源漏极层、过孔以及第一钝化层；The first region includes: an active layer, a first insulating layer, a gate layer, a second insulating layer, a source and drain layer, a via, and a first passivation layer;
    所述第二区域包括：第三绝缘层和第二钝化层；The second region includes: a third insulating layer and a second passivation layer;
    其中，所述第一绝缘层、第二绝缘层及第一钝化层均采用SiNx薄膜，所述第三绝缘层和所述第二钝化层采用SiOx薄膜，所述基板为玻璃基板、石英基板或是树脂基板。Wherein, the first insulating layer, the second insulating layer and the first passivation layer are all made of SiNx film, the third insulating layer and the second passivation layer are made of SiOx film, and the substrate is a glass substrate, quartz The substrate or resin substrate.
  2. 根据权利要求1所述的显示面板，其特征在于，所述基板为LCD基板或是OLED基板。The display panel according to claim 1, wherein the substrate is an LCD substrate or an OLED substrate.
  3. 根据权利要求2所述的显示面板，其特征在于，所述第一绝缘层在所述基板上的正投影面积，大于或等于所述栅极层在所述基板上的正投影面积。The display panel according to claim 2, wherein the orthographic projection area of the first insulating layer on the substrate is greater than or equal to the orthographic projection area of the gate layer on the substrate.
  4. 根据权利要求1所述的显示面板，其特征在于，所述薄膜晶体管为顶栅型薄膜晶体管或是底栅型薄膜晶体管。The display panel according to claim 1, wherein the thin film transistor is a top gate thin film transistor or a bottom gate thin film transistor.
  5. 根据权利要求4所述的显示面板，其特征在于，所述第二绝缘层与所述第三绝缘层同层设置，所述第二钝化层与所述第一钝化层同层设置。The display panel according to claim 4, wherein the second insulating layer is provided in the same layer as the third insulating layer, and the second passivation layer is provided in the same layer as the first passivation layer.
  6. 根据权利要求4所述的显示面板，其特征在于，遮光层设置在所述有源层的正下方。The display panel according to claim 4, wherein the light shielding layer is provided directly below the active layer.
  7. 根据权利要求4所述的显示面板，其特征在于，所述缓冲层覆盖在所述遮光层上面。The display panel according to claim 4, wherein the buffer layer covers the light shielding layer.
  8. 根据权利要求4所述的显示面板，其特征在于，所述栅极层的材料为：钼、铝、铝镍合金、钼钨合金、铬或铜中的一种或多种。The display panel according to claim 4, wherein the material of the gate layer is one or more of molybdenum, aluminum, aluminum-nickel alloy, molybdenum-tungsten alloy, chromium, or copper.
  9. 根据权利要求4所述的显示面板，其特征在于，所述薄膜晶体管中，源极和漏极的材料为：钼、铝、铝镍合金、钼钨合金、铬、铜或钛铝合金中的一种或是多种。The display panel according to claim 4, wherein in the thin film transistor, the source and drain materials are: molybdenum, aluminum, aluminum-nickel alloy, molybdenum-tungsten alloy, chromium, copper or titanium aluminum alloy One or more.
  10. 根据权利要求9所述的显示面板，其特征在于，所述源极和所述漏极分别通过过孔与所述有源层电性连接。The display panel according to claim 9, wherein the source electrode and the drain electrode are electrically connected to the active layer through via holes, respectively.
  11. 根据权利要求1所述的显示面板，其特征在于，所述第一钝化层的面积小于所述第二钝化层的面积。The display panel according to claim 1, wherein the area of the first passivation layer is smaller than the area of the second passivation layer.
  12. 根据权利要求11所述的显示面板，其特征在于，所述第二钝化层覆盖在所述第三绝缘层上面。The display panel according to claim 11, wherein the second passivation layer covers the third insulating layer.
  13. 一种显示面板，其特征在于，包括：基板，以及位于所述基板上的薄膜晶体管单元；A display panel, comprising: a substrate, and a thin film transistor unit on the substrate;
    所述薄膜晶体管单元包括第一区域和第二区域；The thin film transistor unit includes a first region and a second region;
    所述第一区域包括：有源层、第一绝缘层、栅极层、第二绝缘层、源漏极层、过孔以及第一钝化层；The first region includes: an active layer, a first insulating layer, a gate layer, a second insulating layer, a source and drain layer, a via, and a first passivation layer;
    所述第二区域包括：第三绝缘层和第二钝化层；The second region includes: a third insulating layer and a second passivation layer;
    其中，所述第一绝缘层、第二绝缘层及第一钝化层均采用SiNx薄膜，所述第三绝缘层和所述第二钝化层采用SiOx薄膜。Wherein, the first insulating layer, the second insulating layer and the first passivation layer all use SiNx film, and the third insulating layer and the second passivation layer use SiOx film.
  14. 根据权利要求13所述的显示面板，其特征在于，所述基板为LCD基板或是OLED基板。The display panel according to claim 13, wherein the substrate is an LCD substrate or an OLED substrate.
  15. 根据权利要求14所述的显示面板，其特征在于，所述第一绝缘层在所述基板上的正投影面积，大于或等于所述栅极层在所述基板上的正投影面积。The display panel according to claim 14, wherein the orthographic projection area of the first insulating layer on the substrate is greater than or equal to the orthographic projection area of the gate layer on the substrate.
  16. 根据权利要求13所述的显示面板，其特征在于，所述薄膜晶体管为顶栅型薄膜晶体管或是底栅型薄膜晶体管。The display panel according to claim 13, wherein the thin film transistor is a top gate thin film transistor or a bottom gate thin film transistor.
  17. 根据权利要求16所述的显示面板，其特征在于，遮光层设置在所述有源层的正下方。The display panel according to claim 16, wherein the light shielding layer is provided directly below the active layer.
  18. 一种液晶显示面板的制作方法，其特征在于，包含上述任一项所述的显示面板，该方法包括如下步骤：A method for manufacturing a liquid crystal display panel, characterized by comprising the display panel described in any one of the above, the method includes the following steps:
    S1，提供一基板；S1, provide a substrate;
    S2，在所述基板上形成薄膜晶体管单元；S2, forming a thin film transistor unit on the substrate;
    其中，所述薄膜晶体管单元的所述第一栅绝缘层、第二栅绝缘层及第一钝化层采用SiNx薄膜，所述第三绝缘层和所述钝化层采用SiOx薄膜。Wherein, the first gate insulating layer, the second gate insulating layer and the first passivation layer of the thin film transistor unit use SiNx films, and the third insulating layer and the passivation layer use SiOx films.
  19. 根据权利要求18所述的显示面板制作方法，其特征在于，所述薄膜晶体管为底栅型薄膜晶体管时，其制作方法步骤如下：The method for manufacturing a display panel according to claim 18, wherein when the thin film transistor is a bottom gate thin film transistor, the manufacturing method steps are as follows:
    S1，提供一基板；S1, provide a substrate;
    S20，在基板上用PECVD沉积基层薄膜和非晶硅薄膜；S20, depositing a base film and an amorphous silicon film on the substrate by PECVD;
    S30，沉积有源层、第一绝缘层，接着溅射一层金属层，光刻刻蚀成栅极；S30, depositing an active layer and a first insulating layer, then sputtering a metal layer, and etching into a gate by photolithography;
    S40，利用栅极做掩膜，采用SiNx沉积第二绝缘层；S40, using the gate as a mask, and using SiNx to deposit a second insulating layer;
    S50，利用过孔和第二绝缘层做掩膜，采用SiOx沉积第三绝缘层；S50, using the via hole and the second insulating layer as a mask, and using SiOx to deposit a third insulating layer;
    S60，溅射第二层金属层，光刻刻蚀成源漏极层；S60, a second metal layer is sputtered, and the source and drain layers are etched by photolithography;
    S70，利用源漏极层做掩膜，采用SiNx沉积第一钝化层；S70, the source and drain layers are used as a mask, and the first passivation layer is deposited using SiNx;
    S80，采用SiOx沉积第二钝化层。S80, a second passivation layer is deposited using SiOx.
  20. 根据权利要求18所述的显示面板制作方法，其特征在于，所述薄膜晶体管为顶栅型薄膜晶体管时，其制作方法步骤如下：The method for manufacturing a display panel according to claim 18, wherein when the thin film transistor is a top-gate thin film transistor, the manufacturing method steps are as follows:
    S1’，提供一基板；S1’, providing a substrate;
    S20’，在基板上用PECVD沉积基层薄膜和非晶硅薄膜；S20', depositing a base film and an amorphous silicon film on the substrate by PECVD;
    S30’，沉积溅射一层金属层，光刻刻蚀成源漏极层；S30', a metal layer is deposited and sputtered, and the source and drain layers are etched by photolithography;
    S40’，利用源漏极做掩膜，采用SiNx沉积第一绝缘层；S40', the source and drain are used as a mask, and the first insulating layer is deposited using SiNx;
    S50’，利用过孔和第一绝缘层做掩膜，沉积有源层；S50’, using the via hole and the first insulating layer as a mask to deposit an active layer;
    S60’，采用SiNx沉积第二绝缘层；S60’, a second insulating layer is deposited using SiNx;
    S70’，采用SiOx沉积第三绝缘层；S70’, using SiOx to deposit a third insulating layer;
    S80’，沉积溅射第二层金属层，光刻刻蚀成栅极；S80', a second metal layer is deposited and sputtered, and etched into the gate by photolithography;
    S90’，采用SiNx沉积第一钝化层；S90’, using SiNx to deposit the first passivation layer;
    S100’，采用SiOx沉积第二钝化层。S100', a second passivation layer is deposited using SiOx.
PCT/CN2019/078157 2018-12-10 2019-03-14 Display panel and manufacturing method therefor WO2020118935A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201811504350.6A CN109659319B (en) 2018-12-10 2018-12-10 Display panel and manufacturing method thereof
CN201811504350.6 2018-12-10

Publications (1)

Publication Number Publication Date
WO2020118935A1 true WO2020118935A1 (en) 2020-06-18

Family

ID=66113824

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/078157 WO2020118935A1 (en) 2018-12-10 2019-03-14 Display panel and manufacturing method therefor

Country Status (2)

Country Link
CN (1) CN109659319B (en)
WO (1) WO2020118935A1 (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20160009220A (en) * 2014-07-15 2016-01-26 엘지디스플레이 주식회사 OXIDE SEMlCONDUCTOR THIN FILM TRANSISTOR AND ARRAY SUBSTRATE FOR DISPLAY DEVICE HAVING THE SAME
CN107946321A (en) * 2017-12-12 2018-04-20 京东方科技集团股份有限公司 Array base palte and preparation method thereof, display panel, display device
CN108470749A (en) * 2018-03-07 2018-08-31 深圳市华星光电半导体显示技术有限公司 Display panel and its manufacturing method

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4252297B2 (en) * 2002-12-12 2009-04-08 株式会社日立製作所 LIGHT EMITTING ELEMENT AND DISPLAY DEVICE USING THE LIGHT EMITTING ELEMENT
CN100353244C (en) * 2004-01-17 2007-12-05 统宝光电股份有限公司 Liquid crystal display device, and its manufacturing method anbd transistor array substrate and manufacturing method
KR102455093B1 (en) * 2016-01-11 2022-10-14 쑤저우 레킨 세미컨덕터 컴퍼니 리미티드 Tft substrate, display panel and display device having the same
CN106972033B (en) * 2017-05-25 2021-02-19 厦门天马微电子有限公司 Array substrate, manufacturing method thereof, display panel and display device
CN107910355A (en) * 2017-11-27 2018-04-13 信利（惠州）智能显示有限公司 Array base palte and preparation method thereof and organic electroluminescence display device and method of manufacturing same
CN107833894B (en) * 2017-11-27 2020-11-10 合肥鑫晟光电科技有限公司 Top gate TFT substrate, display device and preparation method of TFT substrate

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20160009220A (en) * 2014-07-15 2016-01-26 엘지디스플레이 주식회사 OXIDE SEMlCONDUCTOR THIN FILM TRANSISTOR AND ARRAY SUBSTRATE FOR DISPLAY DEVICE HAVING THE SAME
CN107946321A (en) * 2017-12-12 2018-04-20 京东方科技集团股份有限公司 Array base palte and preparation method thereof, display panel, display device
CN108470749A (en) * 2018-03-07 2018-08-31 深圳市华星光电半导体显示技术有限公司 Display panel and its manufacturing method

Also Published As

Publication number Publication date
CN109659319B (en) 2021-01-01
CN109659319A (en) 2019-04-19

Similar Documents

Publication Publication Date Title
CN109671726B (en) Array substrate, manufacturing method thereof, display panel and display device
US10502994B2 (en) Color filter on array substrate and fabricating method thereof as well as a display device
KR101783352B1 (en) Flat panel display apparatus and manufacturing method of the same
US8305528B2 (en) Liquid crystal display and manufacturing method thereof
US7439090B2 (en) Method for manufacturing a lower substrate of a liquid crystal display device
WO2018233405A1 (en) Thin-film transistor and manufacturing method therefor, array substrate, and display panel
JP6342132B2 (en) Array substrate, display panel, and array substrate manufacturing method
US20110299004A1 (en) Array substrate and manufacturing method thereof
WO2019228457A1 (en) Thin-film transistor, manufacturing method therefor, array substrate, and manufacturing method therefor
WO2016173027A1 (en) Thin film transistor array substrate and manufacturing method therefor
US20120280239A1 (en) Thin film transistor array substrate and method for fabricating the thin film transistor array substrate
WO2018214485A1 (en) Thin-film transistor, manufacturing method thereof, array substrate, and display panel
US8405788B2 (en) TFT-LCD array substrate and manufacturing method thereof
WO2015043268A1 (en) Array substrate, manufacturing method therefor, and display apparatus
US8193534B2 (en) Array substrate of thin film transistor liquid crystal display and method of manufacturing the same
WO2018120691A1 (en) Array substrate and method for manufacturing same, and display device
US20120113366A1 (en) Array substrate and liquid crystal display
KR20150063767A (en) Thin Film Transistor Substrate Having Metal Oxide Semiconductor and Manufacturing Method Thereof
WO2020211259A1 (en) Display back plate and manufacturing method therefor
US20150214286A1 (en) Array substrate, method for manufacturing the same, display device and electronic product
US7193679B2 (en) Liquid crystal display with photosensitive organic film having first, second and third thicknesses is corresponding its transmission, reflective and terminal regions
WO2016065851A1 (en) Array substrate, display panel, and display device
KR20080063708A (en) Method for manufacturing array substrate
US20210223639A1 (en) Array substrate, display device, and fabricating method thereof
WO2019218822A1 (en) Thin-film transistor and manufacturing method therefor, array substrate, and display device

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19896954

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19896954

Country of ref document: EP

Kind code of ref document: A1