WO2020118522A1

WO2020118522A1 - Novel dielectric ceramic low-pass filter

Info

Publication number: WO2020118522A1
Application number: PCT/CN2018/120302
Authority: WO
Inventors: 梁启新; 卓群飞; 付迎华; 马龙; 陈琳玲
Original assignee: 深圳市麦捷微电子科技股份有限公司
Priority date: 2018-12-11
Filing date: 2018-12-11
Publication date: 2020-06-18

Abstract

A novel dielectric ceramic low-pass filter relates to a dielectric ceramic low-pass filter and comprises a base body. Five circuit layers are provided inside the base body; a fourth-order low-pass filter circuit is constituted by equivalent circuits on the circuit layers and has a left-right symmetrical structure; a transmission zero point is generated in a high frequency band by means of parallel resonance of an inductor L1 and a capacitor C2, another transmission zero point is generated in the high frequency band by means of parallel resonance of an inductor L2 and a capacitor C7, and zero points are generated in the high frequency band by means of parallel resonance respectively between a transmission line SL1 and a capacitor C4 and between a transmission line SL2 and a capacitor C5, so that four zero points are formed at a high end to achieve a high suppression effect; a 3dB cut-off frequency point of the low-pass filter can be controlled by adjusting parallel resonators constituted by the transmission line SL1 and the capacitor C4 and the transmission line SL2 and the capacitor C5, and the steepness of the low-pass filter can be controlled by adjusting the coupling degree between the transmission line SL1 and the transmission line SL2 and a capacitor C9. The novel dielectric ceramic low-pass filter has the advantages of low loss, high reliability, low cost, and being suitable for large-scale production.

Description

A new type of dielectric ceramic low-pass filter

Technical field

The invention relates to a dielectric ceramic low-pass filter, in particular to a dielectric ceramic low-pass filter applied to a satellite television high frequency head LNB (Low Noise Block).

Background technique

Low Temperature Co-fired Ceramic (LTCC) technology has unique advantages in the field of electronic components and packaging, due to its high reliability, low insertion loss, high suppression, small size, light weight, easy integration, low The advantages of cost and suitability for large-scale production are widely used in the fields of communications, automobiles and medical equipment.

With the improvement of people's living standards, the demand for live TV is increasing and the requirements are getting higher and higher. As an indispensable key component in the satellite TV receiving module, the LNB tuner is critical to the signal quality, and the filter in the LNB tuner is especially critical.

technical problem

In summary, the purpose of the present invention is to solve the technical problem of the lack of high-performance dielectric ceramic low-pass filters based on low-temperature co-fired ceramic technology in the existing LNB high-frequency heads, and to propose a new dielectric ceramic low-pass filter filter.

Technical solution

In order to solve the technical problems proposed by the present invention, the technical solutions adopted are:

A novel dielectric ceramic low-pass filter includes a base, a first port P1, a second port P2, and a third port P3 are provided at the bottom of the base, and a circuit layer is provided inside the base; the characteristics are as follows: There are five layers in the circuit layer, namely:

In the first layer, three mutually insulated metal plane conductors are printed on the ceramic dielectric substrate, namely: the thirtieth plane conductor (30), the thirty-third plane conductor (33) and the first plane conductor (1); Thirty plane conductors (30) and first plane conductors (1) are distributed on both sides of the thirty-third plane conductor (33); three mutually insulated metal plane conductors correspond to the first port P1, the second port P2 and The third port P3; wherein, the thirtieth plane conductor (30) is connected to the twenty-sixth point post (26), the first plane conductor (1) is connected to the second point post (2), the thirty-third plane conductor (33) The thirty-two-point post (32), thirty-fourth point post (34) and thirty-fifth point post (35) are connected;

In the second layer, an insulating metal plane conductor is printed on the ceramic dielectric substrate. The insulating metal plane conductor includes: a third capacitor substrate (3), a twenty-fifth capacitor substrate (25), and a sixth capacitor substrate The chip (6) and the thirty-first capacitor substrate (31); the sixth capacitor substrate (6) and the thirty-first capacitor substrate (31) are overlapped on one side to form an “8” shape structure, and the twenty-fifth capacitor The substrate (25) and the third capacitor substrate (3) are distributed on both sides of the "8" shape structure; the first common capacitor common to the sixth capacitor substrate (6) and the thirty-first capacitor substrate (31) The substrate (6c) is connected to the thirty-two-point column (32), the thirty-fourth point column (34) and the thirty-fifth point column (35);

In the third layer, four metal planar conductors are printed on the ceramic dielectric substrate, namely: the fourth capacitor substrate (4), the seventh capacitor substrate (7), the twenty-fourth capacitor substrate (24) and The twenty-eighth capacitor substrate (28); the seventh capacitor substrate (7) and the twenty-eighth capacitor substrate (28) are relatively distributed, and the fourth capacitor substrate (4) and the twenty-fourth capacitor substrate (28) 24) Relatively distributed; one end of the fourth capacitor substrate (4) is connected to the eighth point column (8), and the opposite end is connected to the second point column (2); one end of the seventh capacitor substrate (7) Connected to the twenty-third point post (23), the other end is connected to the thirteenth point post (13); one end of the twenty-fourth capacitor substrate (24) is connected to the seventeenth point post (17), the other end The twenty-sixth point column (26) is connected; the twenty-eighth capacitor substrate (28) is connected to the twenty-first point column (21) and the twenty-ninth point column (29);

In the fourth layer, three mutually insulated metal plane conductors are printed on the ceramic dielectric substrate, of which the two metal plane conductors are the fifth capacitor substrate (5) and the twenty-second capacitor substrate (22), respectively. A metal plane conductor is a combination of a ninth capacitor substrate (9), a tenth capacitor substrate (10) and a twenty-seventh capacitor substrate (27); a fifth capacitor substrate (5) and a twentieth The two capacitor substrates (22) are distributed on both sides of the assembly; the tenth capacitor substrate (10) is distributed between the ninth capacitor substrate (9) and the twenty-seventh capacitor substrate (27); the fifth capacitor One end of the substrate (5) is connected to the eleventh pole (11), and the other end is connected to the twenty-ninth pole (29); one end of the twenty-second capacitor substrate (22) is connected to the first Twenty-three point column (23), the other end is connected to the nineteenth point column (19); the ninth capacitor substrate (9) is connected to the fifteenth point column (15); the twenty-seventh capacitor substrate (27) ) Connected to the twentieth column (20);

On the fifth layer, four mutually insulated metal coils are printed on the ceramic dielectric substrate, namely the twelfth inductance coil (12), the sixteenth inductance coil (16), the eighteenth inductance coil (18) and the tenth Four inductance coils (14); the two ends of the twelfth inductance coil (12) are respectively connected to the eleventh pole (11) and the eighth pole (8); the two ends of the sixteenth inductance coil (16) Connect the fifteenth point column (15) and the thirteenth point column (13) respectively; the two ends of the eighteenth inductance coil (18) are respectively connected to the seventeenth point column (17) and the nineteenth point The two ends of the fourteenth inductance coil (14) are respectively connected to the twentieth-point pillar (20) and the twenty-first-point pillar (21).

The twelfth inductor coil (12) and the eighteenth inductor coil (18) are symmetrically distributed on the left and right sides of the ceramic dielectric substrate, and the sixteenth inductor coil (16) and the fourteenth inductor coil (14) are symmetrically distributed on the ceramic The sixteenth inductance coil (16) and the fourteenth inductance coil (14) have a U-shaped structure with opposite opening directions in the front and back positions of the middle part of the dielectric substrate.

Beneficial effect

The beneficial effects of the present invention are: the present invention is based on low-temperature co-fired ceramic technology and uses a semi-lumped parameter model design to realize the high-performance requirements of a new dielectric ceramic low-pass filter. The present invention effectively achieves high out-of-band suppression, has the advantages of low loss, high reliability, low cost, and is suitable for large-scale production. In addition, it also adapts to the new development trend of miniaturization of electronic components.

BRIEF DESCRIPTION

1 is a schematic diagram of the equivalent circuit of the novel dielectric ceramic low-pass filter of the present invention;

2 is a three-dimensional schematic diagram of the appearance structure of the novel dielectric ceramic low-pass filter of the present invention;

3 is a schematic diagram of the bottom port of the new dielectric ceramic low-pass filter of the present invention;

4 is a schematic diagram of the internal structure of the novel dielectric ceramic low-pass filter of the present invention;

5 is a schematic diagram of the planar structure of the first circuit layer of the present invention;

6 is a schematic diagram of a planar structure of a dot-pillar connection between the first layer and the second layer of the present invention;

7 is a schematic diagram of the planar structure of the second layer circuit of the present invention;

8 is a schematic view of the plane structure of the dot-pillar connection between the second layer and the third layer of the present invention;

9 is a schematic diagram of the plane structure of the third layer circuit of the present invention;

10 is a schematic diagram of the plane structure of the dot-pillar connection between the third layer and the fourth layer of the present invention

11 is a schematic diagram of the planar structure of the fourth layer circuit of the present invention;

12 is a schematic diagram of a planar structure of a dot-pillar connection between the fourth layer and the fifth layer of the present invention;

13 is a schematic diagram of the planar structure of the fifth layer circuit of the present invention.

Best Mode of the Invention

The structure of the present invention will be further described below with reference to the drawings and preferred specific embodiments of the present invention.

Referring to FIGS. 1 to 3, the novel dielectric ceramic low-pass filter of the present invention includes a base, a first port P1, a second port P2, and a third port P3 are provided at the bottom of the base, and a circuit layer is provided inside the base; The equivalent circuit diagram on the circuit layer is shown in FIG. 1, which is composed of an inductor L1, an inductor L2, a transmission line SL1, a transmission line SL2, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, a capacitor C6, a capacitor C7, a capacitor C8 The fourth-order low-pass filter circuit formed by capacitor C9 has a symmetrical structure, and generates a transmission zero point in the high frequency band through the parallel resonance of inductor L1 and capacitor C2, and generates another transmission in the high frequency band through the parallel resonance of inductor L2 and capacitor C7. At the same time, the transmission line SL1 and the capacitor C4, and the transmission line SL2 and the capacitor C5 respectively resonate in parallel to generate a zero point in the high frequency band, so that the high end of the low-pass filter forms four zero points to achieve a high suppression effect. And the 3dB cut-off frequency point of the low-pass filter can be controlled by adjusting the parallel resonator composed of the transmission line SL1 and the capacitor C4, the transmission line SL2 and the capacitor C5, and in addition, the coupling degree of the transmission line SL1 and the transmission line SL2 and the capacitor C9 can control the low-pass filter Steepness. Among them, ① is an input/output port, corresponding to the first port P1 in FIG. 3, and ② is an output/input port, corresponding to the third port P3 in FIG. 3, and the second port P2 is a ground port.

Referring to FIGS. 3 to 13, there are five circuit layers inside the substrate, which are:

In the first layer, three mutually insulated metal plane conductors are printed on the ceramic dielectric substrate, respectively: the thirty-thirteen plane conductor 30, the thirty-third plane conductor 33 and the first plane conductor 1; The first planar conductor 1 is distributed on both sides of the thirty-third plane conductor 33; three mutually insulated metal planar conductors respectively correspond to the first port P1, the second port P2 and the third port P3; wherein, the thirtieth plane conductor 30 is connected to a twenty-sixth point post 26, a first plane conductor 1 is connected to a second point post 2, a thirty-third plane conductor 33 is connected to a thirty-second point post 32, a thirty-fourth point post 34 and a third Thirty-five point post 35;

In the second layer, an insulated metal plane conductor is printed on the ceramic dielectric substrate. The insulated metal plane conductor includes: a third capacitor substrate 3, a twenty-fifth capacitor substrate 25, a sixth capacitor substrate 6 and a third Thirty-one capacitor substrate 31; the sixth capacitor substrate 6 and the thirty-first capacitor substrate 31 are overlapped on one side to form an "8" shape structure, and the twenty-fifth capacitor substrate 25 and the third capacitor substrate 3 are distributed in Both sides of the "8" shape structure; the first common capacitor substrate 6c common to the sixth capacitor substrate 6 and the thirty-first capacitor substrate 31 is connected to the thirty-two-point pillar 32 and the thirty-fourth point Column 34 and 35th column 35;

In the third layer, four metal plane conductors are printed on the ceramic dielectric substrate, which are: fourth capacitor substrate 4, seventh capacitor substrate 7, twenty-fourth capacitor substrate 24 and twenty-eight capacitor substrate Film 28; the seventh capacitor substrate 7 is distributed relative to the twenty-eighth capacitor substrate 28, the fourth capacitor substrate 4 is distributed relatively to the twenty-fourth capacitor substrate 24; one end 4a of the fourth capacitor substrate 4 is connected to The eighth point post 8, the opposite end 4b is connected to the second point post 2; one end 7a of the seventh capacitor substrate 7 is connected to the 23rd point post 23, and the other end 7b is connected to the 13th point post 13; one end 24a of the twenty-fourth capacitor substrate 24 is connected to the seventeenth pole 17 and the other end 24b is connected to the twenty-sixth pole 26; the upper right end 28a of the twenty-eighth capacitor substrate 28 A twenty-first point post 21 and a twenty-ninth point post 29 are connected to the right lower end 28b;

In the fourth layer, three mutually insulated metal plane conductors are printed on the ceramic dielectric substrate, of which two metal plane conductors are the fifth capacitor substrate 5 and the twenty-second capacitor substrate 22, respectively, and the remaining one metal plane conductor It is a combination of a ninth capacitor substrate 9, a tenth capacitor substrate 10 and a twenty-seventh capacitor substrate 27; a fifth capacitor substrate 5 and a twenty-second capacitor substrate 22 are distributed on both sides of the combination The tenth capacitor substrate 10 is distributed between the ninth capacitor substrate 9 and the twenty-seventh capacitor substrate 27; one end of the fifth capacitor substrate 5 is connected to the eleventh pole 11 and the other end is connected to the first Twenty-nine-point column 29; one end of the twenty-second capacitor substrate 22 is connected to the twenty-third point column 23, and the other end is connected to the nineteenth point column 19; the ninth capacitor substrate 9 is connected to the tenth Five-point column 15; the twenty-seventh capacitor substrate 27 is connected to the twentieth-point column 20;

On the fifth layer, four mutually insulated metal coils are printed on the ceramic dielectric substrate, namely the twelfth inductance coil 12, the sixteenth inductance coil 16, the eighteenth inductance coil 18 and the fourteenth inductance coil 14; The twelfth inductance coil 12 and the eighteenth inductance coil 18 are symmetrically distributed on the left and right sides of the ceramic dielectric substrate, the sixteenth inductance coil 16 and the fourteenth inductance coil 14 are symmetrically distributed in the front and back positions of the middle of the ceramic dielectric substrate, the sixteenth The inductor coil 16 and the fourteenth inductor coil 14 have a U-shaped structure with opposite opening directions;

The head and tail ends 12a and 12b of the twelfth inductor coil 12 are respectively connected to the eleventh pole 11 and the eighth pole 8; the head and tail ends 16a and 16b of the sixteenth inductor coil 16 are respectively connected to the fifteenth Point column 15 and thirteenth point column 13; the head and tail ends 18a and 18b of the eighteenth inductor coil 18 are connected to the seventeenth point column 17 and the nineteenth point column 19; the head and tail of the fourteenth inductor coil 14 The two ends 14a and 14b are connected to the twentieth-point post 20 and the twenty-first-point post 21, respectively.

The correspondence between the components in the circuit layer and the components in the equivalent circuit inside the substrate are: the first planar conductor 1 is the input and output port P3 of the low-pass filter, and the third capacitor substrate 3 is one of the capacitors C8 The substrate, the fourth capacitor substrate 4 is a common capacitor substrate of capacitor C7 and capacitor C8, the fifth capacitor substrate 5 is one of the capacitor substrates of capacitor C7, and the sixth capacitor substrate 6 is one of the capacitor substrates of capacitor C3 The seventh capacitor substrate 7 is a common capacitor substrate of capacitor C3 and capacitor C4, the ninth capacitor substrate 9 is one of the capacitor substrates of capacitor C4, and the tenth capacitor substrate 10 is one of the capacitor substrates of capacitor C9. The twelfth inductor coil 12 is an inductive metal coil of the inductor L2, the fourteenth inductor coil 14 is a metal transmission line SL1, the sixteenth inductor coil 16 is a metal transmission line SL1, and the eighteenth inductor coil 18 is an inductive metal coil of the inductor L1, The twenty-second capacitor substrate 22 is one of the capacitor C5, the twenty-fourth capacitor substrate 24 is the common capacitor substrate of the capacitor C1 and the capacitor C2; the twenty-fifth capacitor substrate 25 is one of the capacitor C1 A capacitor substrate, the twenty-seventh capacitor substrate 27 is one of the capacitors C5; the twenty-eighth capacitor substrate 28 is a common capacitor substrate of the capacitors C5 and C6, and the thirty-third plane conductor 30 is The low-pass filter input/output port P1; the thirty-first capacitor substrate 31 is one of the capacitor substrates of the capacitor C6, and the thirty-third plane conductor 33 is the low-pass filter ground layer port P2.

The invention is integrated into the same component by using the LTCC molding technology, and then co-fired at a low temperature of 900°C, which effectively achieves high out-of-band suppression, and has the advantages of low loss, high reliability, low cost and suitable for large-scale production. In addition, it has adapted to the new trend of miniaturization of electronic components.

Claims

A novel dielectric ceramic low-pass filter includes a base, a first port P1, a second port P2, and a third port P3 are provided at the bottom of the base, and a circuit layer is provided inside the base; the characteristics are as follows: There are five layers in the circuit layer, namely:

In the first layer, three mutually insulated metal plane conductors are printed on the ceramic dielectric substrate, namely: the thirtieth plane conductor (30), the thirty-third plane conductor (33) and the first plane conductor (1); Thirty plane conductors (30) and first plane conductors (1) are distributed on both sides of the thirty-third plane conductor (33); three mutually insulated metal plane conductors correspond to the first port P1, the second port P2 and The third port P3; wherein, the thirtieth plane conductor (30) is connected to the twenty-sixth point post (26), the first plane conductor (1) is connected to the second point post (2), the thirty-third plane conductor (33) The thirty-two-point post (32), thirty-fourth point post (34) and thirty-fifth point post (35) are connected;

In the second layer, an insulating metal plane conductor is printed on the ceramic dielectric substrate. The insulating metal plane conductor includes: a third capacitor substrate (3), a twenty-fifth capacitor substrate (25), and a sixth capacitor substrate The chip (6) and the thirty-first capacitor substrate (31); the sixth capacitor substrate (6) and the thirty-first capacitor substrate (31) are overlapped on one side to form an “8” shape structure, and the twenty-fifth capacitor The substrate (25) and the third capacitor substrate (3) are distributed on both sides of the "8" shape structure; the first common capacitor common to the sixth capacitor substrate (6) and the thirty-first capacitor substrate (31) The substrate (6c) is connected to the thirty-two-point column (32), the thirty-fourth point column (34) and the thirty-fifth point column (35);

In the third layer, four metal planar conductors are printed on the ceramic dielectric substrate, namely: the fourth capacitor substrate (4), the seventh capacitor substrate (7), the twenty-fourth capacitor substrate (24) and The twenty-eighth capacitor substrate (28); the seventh capacitor substrate (7) and the twenty-eighth capacitor substrate (28) are relatively distributed, and the fourth capacitor substrate (4) and the twenty-fourth capacitor substrate (28) 24) Relatively distributed; one end of the fourth capacitor substrate (4) is connected to the eighth point column (8), and the opposite end is connected to the second point column (2); one end of the seventh capacitor substrate (7) Connected to the twenty-third point post (23), the other end is connected to the thirteenth point post (13); one end of the twenty-fourth capacitor substrate (24) is connected to the seventeenth point post (17), the other end The twenty-sixth point column (26) is connected; the twenty-eighth capacitor substrate (28) is connected to the twenty-first point column (21) and the twenty-ninth point column (29);

In the fourth layer, three mutually insulated metal plane conductors are printed on the ceramic dielectric substrate, of which the two metal plane conductors are the fifth capacitor substrate (5) and the twenty-second capacitor substrate (22), respectively. A metal plane conductor is a combination of a ninth capacitor substrate (9), a tenth capacitor substrate (10) and a twenty-seventh capacitor substrate (27); a fifth capacitor substrate (5) and a twentieth The two capacitor substrates (22) are distributed on both sides of the assembly; the tenth capacitor substrate (10) is distributed between the ninth capacitor substrate (9) and the twenty-seventh capacitor substrate (27); the fifth capacitor One end of the substrate (5) is connected to the eleventh pole (11), and the other end is connected to the twenty-ninth pole (29); one end of the twenty-second capacitor substrate (22) is connected to the first Twenty-three point column (23), the other end is connected to the nineteenth point column (19); the ninth capacitor substrate (9) is connected to the fifteenth point column (15); the twenty-seventh capacitor substrate (27) ) Connected to the twentieth column (20);

On the fifth layer, four mutually insulated metal coils are printed on the ceramic dielectric substrate, namely the twelfth inductance coil (12), the sixteenth inductance coil (16), the eighteenth inductance coil (18) and the tenth Four inductance coils (14); the two ends of the twelfth inductance coil (12) are respectively connected to the eleventh pole (11) and the eighth pole (8); the two ends of the sixteenth inductance coil (16) Connect the fifteenth point column (15) and the thirteenth point column (13) respectively; the two ends of the eighteenth inductance coil (18) are respectively connected to the seventeenth point column (17) and the nineteenth point The two ends of the fourteenth inductance coil (14) are respectively connected to the twentieth-point pillar (20) and the twenty-first-point pillar (21).
A novel dielectric ceramic low-pass filter according to claim 1, characterized in that the twelfth inductance coil (12) and the eighteenth inductance coil (18) are symmetrically distributed on the left and right sides of the ceramic dielectric substrate, The sixteenth inductance coil (16) and the fourteenth inductance coil (14) are symmetrically distributed in the front and back of the middle of the ceramic dielectric substrate. The sixteenth inductance coil (16) and the fourteenth inductance coil (14) are U with opposite opening directions形结构。 Shaped structure.