WO2020114431A1 - 基于PCIe接口的FPGA升级方法 - Google Patents

基于PCIe接口的FPGA升级方法 Download PDF

Info

Publication number
WO2020114431A1
WO2020114431A1 PCT/CN2019/123069 CN2019123069W WO2020114431A1 WO 2020114431 A1 WO2020114431 A1 WO 2020114431A1 CN 2019123069 W CN2019123069 W CN 2019123069W WO 2020114431 A1 WO2020114431 A1 WO 2020114431A1
Authority
WO
WIPO (PCT)
Prior art keywords
fpga
pcie
host
state
upgrade
Prior art date
Application number
PCT/CN2019/123069
Other languages
English (en)
French (fr)
Inventor
相剑波
张波
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP19892179.3A priority Critical patent/EP3882763B1/en
Publication of WO2020114431A1 publication Critical patent/WO2020114431A1/zh
Priority to US17/339,299 priority patent/US11500650B2/en

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/445—Program loading or initiating
    • G06F9/44505—Configuring for program initiating, e.g. using registry, configuration files
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/60—Software deployment
    • G06F8/61—Installation
    • G06F8/62—Uninstallation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
    • G06F11/3027—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/3055—Monitoring arrangements for monitoring the status of the computing system or of the computing system component, e.g. monitoring if the computing system is on, off, available, not available
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3466—Performance evaluation by tracing or monitoring
    • G06F11/349—Performance evaluation by tracing or monitoring for interfaces, buses
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/60—Software deployment
    • G06F8/65—Updates
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express

Definitions

  • the present invention relates to the field of communication technology, and in particular to an FPGA upgrade method based on PCIe interface.
  • FPGA Field Programmable Logic Gate Array
  • FPGA Field Programmable Logic Gate Array
  • FIG. 1 it is a schematic structural diagram of a PCIe interface card connected to a host in a server.
  • the FPGA board 1, FPGA board 2, graphics processing card, and solid-state drive in FIG. 1 may all be PCIe interface cards, which are connected through PCIe interfaces. Connect to the host.
  • a special FPGA configuration memory that is, a memory used to store FPGA configuration data, usually a non-volatile memory chip, such as a flash memory chip
  • FPGA upgrade a special FPGA configuration memory (that is, a memory used to store FPGA configuration data, usually a non-volatile memory chip, such as a flash memory chip) is used to perform FPGA upgrade.
  • Online upgrade that is, the host first writes the configuration data into the FPGA configuration memory through the PCIe interface between the FPGA and the interface between the FPGA and the FPGA configuration memory (such as the SPI interface), and then triggers the FPGA to start loading, so the FPGA uses the SPI The interface reads data from the FPGA configuration memory. After loading, the FPGA outputs a reset signal to warm reset itself. After the reset process is completed, the FPGA can enable new functions.
  • This application provides an FPGA upgrade method, an FPGA board, a host, and electronic equipment to alleviate the problem that the host is prone to downtime or restart during the FPGA upgrade process in the existing technology, thereby affecting the business.
  • this application provides a method for upgrading an FPGA, which is performed by a host and an FPGA in cooperation, wherein the host and the FPGA are connected by a PCIe link, the FPGA is connected to an FPGA configuration memory, and the FPGA configuration The memory stores configuration data required for the FPGA upgrade.
  • the method includes: the host issues an upgrade instruction to the FPGA; the host uninstalls the PCIe driver corresponding to the FPGA to make the PCIe link The state of becomes a disconnected state; the host continuously detects whether the state of the PCIe link becomes a connected state within the first timeout period; if it is detected that the state of the PCIe link becomes the connected state, then Reloading the PCIe driver; the method further includes: after the FPGA receives the upgrade instruction, the FPGA continuously detects whether the state of the PCIe link becomes a disconnected state within a second timeout period , Where the disconnected state is the state of the PCIe link after the host uninstalls the PCIe driver corresponding to the FPGA; if it is detected that the PCIe link becomes In the disconnected state, the FPGA loads the configuration data from the FPGA configuration memory for upgrade; after the upgrade is completed, the FPGA negotiates with the host to restore the state of the PCIe link to be used by all After the host detects the connection status of the PCIe driver and
  • the PCIe link is in an unavailable state, and at the same time, the application or PCIe driver on the host may be accessing the FPGA. Because the PCIe link is in an unavailable state, the application on the host Or the PCIe driver will report an error or hang, causing the operating system in the host to be abnormal, causing downtime or restart.
  • the FPGA when the FPGA is upgraded, it will detect that the host has uninstalled the PCIe driver corresponding to the FPGA before upgrading, so that the application or PCIe driver in the host will not be interfered by the FPGA upgrade, and there will be no abnormalities such as downtime.
  • the host can reload the PCIe driver corresponding to the FPGA, so there is no need to restart and will not interrupt other PCIe devices.
  • the FPGA only waits within the timeout period to avoid business interruption caused by waiting for the host error, and by detecting the PCIe link status to trigger the detection of whether the host has uninstalled the PCIe driver can be based on PCIe
  • the mainstream hardware implementation in the form of slots requires no hardware changes and lower hardware costs.
  • the host suspends one or more application programs that use the PCIe link to access the FPGA before uninstalling the PCIe driver.
  • the host can prevent data loss by first suspending the application program. At the same time, the suspending does not terminate the program, so that it can continue to quickly process business after subsequent recovery.
  • the host resumes operation of the one or more application programs after reloading the PCIe driver.
  • the PCIe driver By loading the PCIe driver and then restoring the application, you can continue to process business without restarting, speeding up the processing of business.
  • the first timeout time is a predetermined time required for the FPGA to complete the upgrade.
  • the first timeout period may include the time when the FPGA completes loading configuration data required for upgrade from the FPGA configuration memory, and performs initialization and reset operations after loading plus a margin time. The first timeout period can ensure that the FPGA can complete the upgrade under normal conditions, and does not wait too much to affect the host.
  • the second timeout period is a predetermined time required by the host from issuing the upgrade instruction to completing uninstalling the PCIe driver.
  • the second timeout period may include the time from the time when the host issues the upgrade instruction until the uninstallation of the PCIe driver is completed plus the margin time. The second timeout period can not only ensure that the host can uninstall the driver under normal circumstances, but also does not wait too much to affect the FPGA.
  • the continuous detection of whether the status of the PCIe link becomes the connected state within the first timeout period includes: The link status register in the host continuously detects whether the PCIe link becomes the connected state.
  • the host uses the link status register located in the host to detect the PCIe link status, which is simple to implement and reduces the implementation cost.
  • the FPGA continuously detecting whether the state of the PCIe link becomes a disconnected state within a second timeout period includes: the FPGA passes within the second timeout period Continuously detect the link status register located in the FPGA to continuously detect whether the PCIe link becomes the disconnected state.
  • the FPGA detects the PCIe link status through the link status register in the FPGA, which is simple to implement and reduces the implementation cost.
  • the upgrade process is exited.
  • the FPGA is located on a PCIe card, and the PCIe card is installed on a PCIe expansion slot of the host.
  • This method is now a mainstream implementation method for connecting a PCIe device to a host. Therefore, this method can be applied to mainstream implementation methods without changing hardware, and the implementation cost is lower.
  • the FPGA configuration memory is a flash memory chip, and the flash memory chip is connected to the FPGA through a serial peripheral interface (SPI).
  • SPI serial peripheral interface
  • Flash memory is a very common type of memory, so it is easy to use and reduces the implementation cost.
  • the user circuit of the FPGA when loading, specifically issues a low-level command to the loading circuit that comes with the FPGA when the FPGA is shipped from the factory to start.
  • the user circuit is the circuit formed by the FPGA user by purchasing the FPGA chip and loading the configuration data; the circuit that comes with the FPGA when shipped from the factory is the circuit that the manufacturer comes with when the FPGA is shipped, and the circuit will be solidified in Inside, it will not change because the user configuration data is loaded or disappeared.
  • the bottom-level command is a command defined by the manufacturer that the user can interact with the loading circuit that comes with the FPGA. This startup method can ensure that the FPGA can load configuration data from the FPGA configuration memory.
  • the disconnected state and the connected state of the PCIe link are both the result of negotiation between the FPGA and the PCIe interface circuit of the host through the PCIe link.
  • the negotiation methods are all existing technologies, so there is no need to change the protocol, and the implementation is simpler.
  • the configuration data stored in the FPGA configuration memory is stored by the host through the FPGA before sending the issuing upgrade instruction. That is, the host may save a copy of configuration data in advance, and then the FPGA receives the configuration data sent by the host and saves the configuration data to the FPGA configuration memory through an interface with the FPGA configuration memory. Also known as "online" loading, no human involvement is required, so upgrades are more convenient.
  • the link anomaly is shielded by setting the AER register, that is, the host will not respond to abnormal events on the link. In this way, the host will not cause abnormal situations such as downtime because the link becomes disconnected.
  • the AER register can be configured to enable the link abnormal reporting function, that is, the host can respond to abnormal events on the link.
  • the present application discloses a method for online upgrading of FPGA, which is executed by FPGA, the FPGA communicates with a host through a PCIe link, the FPGA is also connected to an FPGA configuration memory, and the FPGA configuration memory stores The configuration data required for FPGA upgrade, the method includes: receiving an upgrade instruction issued by the host; continuously detecting whether the state of the PCIe link becomes a disconnected state within a timeout period, wherein the disconnected The state is the state of the PCIe link after the host uninstalls the PCIe driver corresponding to the FPGA; if it is detected that the PCIe link becomes disconnected within the timeout period, configure from the FPGA The configuration data is loaded in the memory for upgrade; after the upgrade is completed, the state of the PCIe link is restored to the connected state by negotiating with the FPGA; the connected state is used to be reloaded after being detected by the host Describe the PCIe driver.
  • the second aspect of this application is based on the same inventive concept as the first aspect, except that the main body of the application is replaced with an FPGA. Therefore, the various implementations in the second aspect can also refer to the various implementations performed by the FPGA in the first aspect Ways, the second aspect and the various implementations in the second aspect can also achieve similar effects as the first aspect and the various implementations in the first aspect.
  • the present application discloses a method for upgrading an FPGA, which is executed by a host, the host is connected to the FPGA through a PCIe link, the FPGA is connected to an FPGA configuration memory, and the FPGA configuration memory stores
  • the method includes: the host computer issues an upgrade instruction to the FPGA; uninstalls the PCIe driver corresponding to the FPGA, so that the status of the PCIe link becomes a disconnected state; Continuously detect whether the status of the PCIe link becomes the connected status within a timeout period; if it is detected that the status of the PCIe link becomes the connected status, reload the PCIe driver; wherein, the upgrade The instruction is an instruction for the FPGA to perform the following operation after receiving it: continuously detect whether the state of the PCIe link becomes the disconnected state within a second timeout period, wherein the disconnected state is the PCIe The state of the link after the host uninstalls the PCIe driver corresponding to the FPGA; if it is
  • the third aspect in this application is based on the same inventive concept as the first aspect, except that the main body of the application is replaced with a host. Therefore, various implementations in the third aspect can also refer to various implementations performed by the host in the first aspect The third aspect and the various implementations in the third aspect can also achieve similar effects as the first aspect and the various implementations in the first aspect.
  • the present application discloses an FPGA board including an FPGA chip and an FPGA configuration memory (such as non-volatile memory such as flash memory).
  • the FPGA performs the second aspect by loading configuration data stored in the FPGA configuration memory and
  • the operations performed by the FPGA in various implementations of the second aspect can achieve the same effects as the second aspect.
  • there may be a circuit (such as a configuration loading circuit) provided by the manufacturer in the FPGA.
  • the circuit defined by the configuration data can be combined with the circuit provided by the manufacturer to complete the second aspect And operations performed by the FPGA in various implementations of the second aspect.
  • the FPGA and the host may be connected only by a PCIe link.
  • the FPGA and the host may also use reserved tubes
  • the feet are connected to transmit information used to indicate working status.
  • the FPGA performs the operations performed by the FPGA in Embodiments 2 and 3 by loading configuration data stored in the FPGA configuration memory.
  • the present application discloses a host device.
  • the host device includes a processor (such as a CPU) and a memory capable of software instructions, where the memory may include a non-volatile memory (such as a magnetic disk, flash memory, etc.) and Non-volatile memory (such as memory), through the cooperation of the processor and the memory, the processor can execute the instructions stored in the memory and complete the operations performed by the host in the second aspect and various implementations of the second aspect, so that The second aspect and the effects corresponding to the various implementations of the second aspect are obtained.
  • the host can also execute the host execution in the second and third embodiments by executing instructions stored in the memory Operation.
  • the present application discloses an electronic device including the FPGA board described in the fourth aspect and the host device described in the fifth aspect.
  • the present application discloses a computer storage medium that stores a plurality of instructions for execution by a processor, where the instructions are for the processor to execute the third aspect and various aspects of the third aspect after reading The instruction of the operation performed by the host in the implementation mode.
  • the third to seventh aspects and the possible implementation manners in each aspect are based on the same invention concept as the first aspect and the various possible implementation manners in the first aspect, therefore, the first aspect and In the first aspect, various possible implementations have the same effect.
  • FIG. 1 is a schematic diagram of a host in a server connected to a PCIe device through a PCIe link;
  • Figure 2 is a schematic diagram of FPGA and host connection
  • Figure 3 is a schematic diagram of the structure of the host computer and the FPGA board in the computing device
  • FIG. 4 is a schematic diagram of the structure of the FPGA board connected to the processor and memory in the host through the PCIe slot;
  • FIG. 5 is a schematic structural diagram of a host and an FPGA board in an electronic device in Embodiment 1 of the present application;
  • FIG. 6 is a flowchart of a method executed by a host in Embodiment 1 of the present application.
  • step S65 is a flowchart of step S65 in the method shown in FIG. 6 to detect whether the status of the PCIe link is link up within the timeout period;
  • step S65 is another flowchart of step S65 in the method shown in FIG. 6 to detect whether the status of the PCIe link is link up within the timeout period;
  • FIG. 9 is a schematic structural diagram of a host computer and an FPGA board in a computing device in Embodiment 2 of this application;
  • FIG. 11 is a flowchart of a method executed by an FPGA in Embodiment 2 of this application;
  • FIG. 13 is a flowchart of a method executed by an FPGA in Embodiment 3 of this application;
  • FIG. 14 is a schematic structural diagram of an FPGA board in Embodiment 4 of the present application.
  • Embodiment 15 is a schematic structural diagram of a host device in Embodiment 5 of the present application.
  • FIG. 16 is a schematic structural diagram of an electronic device in Embodiment 6 of the present application.
  • the FPGA upgrade method disclosed in this application can be applied to FPGA-based devices. See FIG. 3 for a schematic diagram of an electronic device.
  • the electronic device here may refer to a computing device with computing capabilities, such as a personal computer or a server. , Workstations and other equipment.
  • this application is not limited to other electronic devices, such as various network devices (such as gateways, routers, switches, etc.).
  • the computing device may include a host computer and an FPGA board, where the host computer may generally include a general-purpose processor (such as an x86 instruction set-based or ARM instruction set-based CPU) capable of executing software. It also includes non-volatile memory (such as a hard disk, flash memory) for storing software instructions and various data, and memory (such as memory) for storing software instructions and temporary data required for the processor to operate.
  • the processor can read the software instructions stored in the non-volatile memory to complete the corresponding functions.
  • the host usually includes an operating system (such as Windows operating system, Linux operating system, etc.) and various application programs running based on the operating system.
  • the host may also include various dedicated processing circuits (such as various ASICs), such as bridges, image processors, and so on.
  • various processing circuits on the host can be packaged into one chip or multiple chips.
  • the bridge chip and the CPU can be packaged into a chip
  • the image processor can be packaged into a chip separately. limited.
  • the computing device also includes an FPGA board.
  • the FPGA board here refers to a board based on the PCB form, which can be physically connected and communicated with the host through a PCIe slot provided on the electronic device.
  • the FPGA board includes an FPGA chip (referred to simply as "FPGA” in this application), an FPGA configuration memory for storing FPGA upgrade data, the FPGA configuration memory may be a non-volatile memory such as flash memory, and in addition, Including cache chips (such as SDRAM) and other devices.
  • the FPGA configuration memory is flash memory
  • the FPGA and FPGA configuration memory can communicate through the SPI interface. Referring to FIG.
  • the electronic device may further include a PCIe slot (located in the PCB of an electronic device), the physical pin on the PCIe slot used to implement the PCIe link and the processor on the host (such as CPU); at the same time, the FPGA board can also include a gold finger that is adapted to the PCIe slot and is used to implement the PCIe protocol. The gold finger is connected to the FPGA through the PCB trace; in this way, by inserting the gold finger into the PCIe The slot can realize the physical connection and communication between the FPGA and the host.
  • a PCIe slot located in the PCB of an electronic device
  • the physical pin on the PCIe slot used to implement the PCIe link
  • the processor on the host Such as CPU
  • the FPGA board can also include a gold finger that is adapted to the PCIe slot and is used to implement the PCIe protocol.
  • the gold finger is connected to the FPGA through the PCB trace; in this way, by inserting the gold finger into the PCIe
  • the slot can realize
  • the basic working principle of FPGA is to change the content of the configuration RAM inside the FPGA by loading a configuration data (for example, in the form of a configuration file), thereby changing the configuration of various logic resources inside the FPGA to achieve Different circuit functions, and the configuration data can be loaded multiple times, so that the FPGA can complete different functions by loading different configuration data, which has good flexibility.
  • a configuration data for example, in the form of a configuration file
  • the configuration data can be loaded multiple times, so that the FPGA can complete different functions by loading different configuration data, which has good flexibility.
  • This process is called FPGA. Upgrade process.
  • the FPGA leaves the factory it will have a configuration loading circuit for loading configuration data.
  • This configuration loading circuit can be used to ensure that after the user-defined circuit function (that is, the function defined by the configuration data) fails
  • the FPGA configuration memory can store two copies of configuration data.
  • One is the basic version, which is used to provide basic FPGA functions and is generally not modified by the user.
  • the other is the normal business version, which is the current The latest business version is used to provide FPGA with the functions required for normal business.
  • the FPGA starts, it will first check the offset address of the header (data header) part of the basic version. If the offset address points to the service version, the service version will be loaded starting from the offset address. If you want to upgrade the FPGA later, the host can communicate with the FPGA first, and replace the original service version with the new configuration data that needs to be upgraded.
  • the host can access the FPGA on the FPGA board by running software.
  • the application program in the host can use the PCIe driver that comes with the operating system or the PCIe driver that the user installs independently after installing the operating system to use the PCIe protocol to communicate with the FPGA.
  • the control operations related to upgrades in this application can be provided through third-party applications, for example, FPGA board manufacturers can provide
  • FPGA board manufacturers can provide For the adapted application program, when the server user needs to use the FPGA board, he can install the application provided by the FPGA board manufacturer into the host computer to realize the control operation of the FPGA.
  • This embodiment introduces an FPGA upgrade method based on an application scenario where an FPGA board is connected to a host through a PCIe slot.
  • FIG. 5 which is a structural block diagram of an application scenario of this embodiment, based on FIG. 5, the following describes the execution flow of the host side and the FPGA board side, respectively.
  • each method step in the process can be specifically executed by a processor (such as a CPU) in the host by reading instructions in the memory in the form of software, which can be a production FPGA
  • the upgrade program provided by the manufacturer of the board for upgrading the FPGA board.
  • the upgrade program may be a third-party application program (that is, not provided by the operating system, but an additional one after the operating system is installed. Application), of course, can also be a program that comes with the operating system.
  • the host executes the following methods:
  • the host can interact with the user through an upgrade software (such as GUI-based or command-line-based software) and complete the loading of new configuration data.
  • the upgrade software can be a separate software that can be provided to other software to call the interface , So that other software can call the software to complete the FPGA upgrade.
  • the upgraded software may also be one software or multiple software modules in other software, which is not limited in this application.
  • the user is allowed to select the new configuration data located locally or remotely from the host and the target FPGA to be upgraded, and then click the "Load” button set in the software to load the selected new configuration data into the FPGA configuration memory, and then later Complete other steps by clicking other buttons (such as performing subsequent operations by clicking the set "Upgrade” button).
  • the new configuration data can be loaded into the FPGA configuration memory by other methods.
  • pause refers to a temporary stop, that is, the software is not closed, and it does not need to restart execution after resuming, but can resume execution from the position where it was paused.
  • the pause operation can be completed by calling some APIs provided by the operating system, and the specific implementation is the existing technology, which will not be repeated in this application.
  • the benefit of the suspension is that there is no need to close the application, which can minimize the interference to the business.
  • saving the site may include saving the data in the host, and may also include saving the data during the operation of the FPGA.
  • the host can save the intermediate data obtained during the execution of the host application (compression program) (such as the compressed data transmitted from the FPGA), or the application itself.
  • compression program such as the compressed data transmitted from the FPGA
  • Data can also save various data involved in FPGA operation (such as location information indicating that the FPGA is currently compressing/or completed data).
  • the host usually needs to interact with the FPGA, that is, the host notifies the FPGA to report according to the content to be saved.
  • the specific implementation of the storage site can be implemented by those skilled in the art according to different storage requirements, which will not be repeated in this application. It should be noted that this step is not a required step. If there is no running application, you can not perform this step; or if the user does not need to save the site (such as it can be determined in advance that even if the site is not saved, it will not Cause data loss, or even if it is acceptable), it is not necessary to save the scene.
  • the host sends an upgrade instruction to the FPGA.
  • the host can send an upgrade instruction to the FPGA through the PCIe interface through the installed upgrade program, and the upgrade instruction is used to notify the FPGA to upgrade.
  • the upgrade data may specifically be new configuration data of the FPGA.
  • the new configuration data can be transmitted to the FPGA through the PCIe interface through the host, and then the FPGA can be transmitted to the FPGA configuration memory through an interface (such as an SPI interface or a customized other interface). Transmission in this way can achieve remote online loading, that is, the host can be controlled to load the new configuration data into the FPGA configuration memory through the network, and the new configuration data can be loaded without manual operations on site.
  • the host uninstalls the PCIe driver corresponding to the FPGA.
  • the PCIe driver can be uninstalled by upgrading the software to call the operating system API.
  • the PCIe interface on the host side will be reset. Therefore, after uninstalling the PCIe driver, the link status of the PCIe interface will change from link up to link down. This change can be detected by the FPGA, thus Trigger its upgrade operation (load new configuration data from FPGA configuration memory).
  • the host should keep a file of the PCIe driver for the FPGA locally (in a non-volatile storage medium such as a hard disk). Specifically, The host can keep a copy before the upgrade starts, or download it online from the Internet before it needs to be reloaded.
  • the specific uninstallation of the PCIe driver may include the following steps: 1) through a command similar to rmmod xxx.ko Complete the uninstallation of the driver file. 2) The link anomaly is shielded by the AER register, that is, the host will not respond to the abnormal event on the link. 3) Disable the link control register (link control register). 4) Remove (remove) the device.
  • the status of the PCIe link can be changed to the disconnected state under the Linux operating system, so that the FPGA can detect it.
  • the link control register can be enabled later (for example, it can be enabled after a preset time, which can be less than the loading time of the FPGA).
  • a preset time which can be less than the loading time of the FPGA.
  • continuous detection refers to the continuous detection action during the detection process to be able to complete effective detection within a predetermined time (such as the first timeout period in this step), that is, to be able to complete this predetermined time If the status of the PCIe link becomes connected, it must be detected. Instead of arbitrarily selecting a time point to detect it once, it may not be able to effectively detect the change of the PCIe link state (such as the detection time point is set closer, the detection does not become the connection state, and the connection state is changed after the detection At this time, since only one test is performed, an effective test cannot be completed). Specifically, the continuous detection may be performed periodically or multiple times through a custom aperiodic method.
  • the detection may be set only once (that is, the period of continuous detection is considered to be equal to the predetermined time), that is, the detection is performed once when the reservation is about to end.
  • whether the link is up can be determined by querying PCIe related registers (such as PCIe link register specified in the PCIe protocol) located in the host.
  • PCIe related registers such as PCIe link register specified in the PCIe protocol
  • the status of the PCIe link will become a link down (link down).
  • the status of the PCIe link will become link up again. Therefore, in this embodiment, whether the link becomes up is used to determine whether the FPGA has completed the upgrade and starts to work normally.
  • This embodiment only judges within the first time-out time to prevent the situation that the host has been waiting due to an FPGA error, that is, in this embodiment, the host only waits for the first time-out time at most.
  • the completion of the upgrade indicates that there may be a problem on the FPGA side. It is not worth waiting for the host to wait.
  • the host can use a warning or other means to remind the user that there may be a problem with the FPGA upgrade.
  • the host does not need to perform step S65 to save the host Resources.
  • the "first timeout time” can be regarded as "the predetermined time required for the peer FPGA to complete the upgrade".
  • the completion of the upgrade refers to the operations required by the FPGA to complete the configuration data loading (which may include loading the basic version after loading the new configuration data fails), warm reset, etc.
  • the technician can set the first timeout time in combination with the operation time required for the FPGA to complete the upgrade.
  • this time will include at least the following main time "the time when the FPGA loads the new configuration data from the FPGA configuration memory + margin time", because the loading operation is necessary, and because the loading time cannot be estimated very accurately, Therefore, there will be a certain margin.
  • main time the time when the FPGA loads the new configuration data from the FPGA configuration memory + margin time
  • it will also include other times, such as the time when the PCIe link status changes from link down to link up, the time the FPGA detects the state change, and the FPGA reset time after loading, etc., but these times The weight is small and can be ignored, or the margin time can be set larger to replace these times.
  • the existing FPGA after failing to load the new configuration data, the existing FPGA usually loads a copy of the configuration data of the basic version. If the FPGA has such an operation, the first timeout period may also include the time required to load the basic version.
  • the time for the FPGA to load new configuration data from the FPGA configuration memory is the main time, which can be estimated according to the formula "new configuration data size/FPGA configuration rate", where the new configuration data size is known
  • the FPGA configuration rate is equal to the clock frequency of the FPGA configuration interface (for example, the clock frequency of the SPI interface).
  • the specific size of the margin time can be determined by those skilled in the art in combination with the actual application requirements. For example, in order to be more secure, the margin time can generally be set to be larger.
  • S653' Detect whether the status of the PCIe link is link, if it is S66; otherwise, execute S654'.
  • the host reloads the PCIe driver, and then resumes the suspended application or applications and resumes the scene.
  • the upgrade program When the upgrade program confirms that the status of the PCIe link has changed from link down to link up, it re-executes the PCIe link scanning and device enumeration operations to find the upgraded FPGA, and reloads the PCIe driver. Finally, the previously suspended applications are resumed, allowing them to access the upgraded FPGA and resume the site.
  • the specific reloading of the PCIe driver may include the following steps: 1) through similar insmod The xxx.ko command completes the loading of the driver file. 2) Configure the AER register to enable the link abnormal reporting function, that is, allow the host to respond to abnormal events on the link.
  • the above specific operation under the Linux operating system is just an example, and those skilled in the art can implement similar functions in other specific application scenarios based on the above method.
  • the existing FPGA usually automatically loads the basic version after the loading fails. Although it can also communicate with the host normally, it cannot meet the normal business requirements, that is, although the PFGA "upgrade completed" (loaded a configuration data , Does not limit whether the basic version or new configuration data), but does not mean “upgrade successful” (loaded new configuration data), therefore, after reloading the PCIe driver and after resuming the operation of one or more applications and recovery site Before, the host can further query the logical version number of the FPGA (corresponding to the version of the configuration data) to determine whether the upgrade is successful (that is, whether new configuration data is loaded), if it is judged that the upgrade is successful (that is, the logical version number is the new configuration data Corresponding version number), then follow normal business; if it fails, you can perform various failure processing, such as re-upgrade, or load a new piece of configuration data to upgrade, or alarm and other operations.
  • the host can alert to let the user understand the abnormal information in order to Perform subsequent processing.
  • FIG. 8 for a flowchart of the method executed by the FPGA, including:
  • the instruction transmitted on the PCIe link can be received through the PCIe interface circuit 5211 in the FPGA 521. After receiving the instruction, it can be placed in a register, and then the host instruction parsing circuit 5212 can be used to analyze whether the instruction in the register is The upgrade instruction, if it is, can send a message to the control circuit 5213 to inform the control circuit to control the upgrade process.
  • the detection of the link state can be completed by the PCIe link state detection circuit 5216. After the detection, the result can be sent to the control circuit 5213, and the control circuit 5213 can perform subsequent processing.
  • step S65 This step checks whether the status of the PCIe link changes from link up to link down to confirm whether the host has uninstalled the driver. Only after the driver is uninstalled, the FPGA will begin to perform the upgrade operation, otherwise it may cause host abnormalities (such as downtime Or restart).
  • Continuous detection within a certain timeout period is to prevent the abnormality of the host from affecting the operation of the FPGA, that is, the FPGA only waits for the third timeout period. If the timeout is not completed, it means that the host is abnormal and the FPGA is no longer Wait and perform other operations.
  • the third time-out time can be regarded as "the time required for the scheduled host to complete the uninstallation of the PCIe driver after issuing the upgrade instruction", for example, based on the above-described process performed by the host side, the time may include "required for the host to uninstall the driver Time + margin time".
  • the sequence of the two steps S62 and S63 executed by the host side can also be interchanged.
  • the third timeout period can be adjusted adaptively, that is, plus the suspension of the application and
  • the time to save the scene that is, in this case, the third time-out time may include "time required to suspend the application and save the scene + time required for the host to uninstall the driver + margin time".
  • the control circuit 5213 notifies the configuration loading circuit 5215 to load new configuration data from the FPGA configuration memory 522, thereby completing the FPGA upgrade.
  • the configuration loading circuit 5215 is a circuit that the FPGA comes with when it is shipped from the factory. This circuit will always exist and will not be lost due to the loss of data in the configuration RAM (such as power failure or artificial removal). Users can use the custom circuit (defined by configuration data) in the FPGA process to load the configuration before the failure (ie, there is an operation to clear the internal logic circuit before loading the FPGA, for example, to clear the internal configuration RAM for circuit configuration) The circuit sends a relevant signal to instruct it to load new configuration data into the FPGA configuration memory, so that the subsequent configuration loading circuit can complete the loading of the new configuration data.
  • the configuration loading circuit can interact with the configuration loading circuit through the control circuit (user-defined circuit).
  • the specific message format can be the message method specified by the FPGA manufacturer.
  • the messages are roughly divided into four categories according to function. There are device synchronization messages 2. Configure load address message, configure load command message and device desynchronization message.
  • the hexadecimal data composition of the message sequence is related to the configuration loading circuit provided by the specific FPGA manufacturer. Taking Xilinx as an example, the specific message sequence composition between the FPGA control circuit and the configuration loading circuit is as follows:
  • Configuration load address message Hexadecimal data 0x30020001/load start address/0x20000000/0x20000000 is used. This message is used by the FPGA control circuit to tell the configuration load circuit that the FPGA configuration data to be loaded is located in the FPGA configuration memory. starting address.
  • Configuration load command message Hexadecimal data 0x30008001/0x0000000F/0x20000000/0x20000000 is used. This message is used by the control circuit of the FPGA to control the configuration loading circuit to start loading FPGA configuration data from the FPGA configuration memory.
  • Device desynchronization message Use hexadecimal data 0x30008001/0x0000000D/0x20000000/0x20000000. This message is used to release the synchronization state between the configuration loading circuit and the FPGA control circuit.
  • the configuration loading circuit will verify the data during the loading process. If the verification is passed, it indicates that the loading is successful, otherwise, the loading fails. In order to prevent the situation that the FPGA fails to work due to loading failure, in one implementation, multiple versions of configuration data can be saved in the FPGA configuration memory, at least one of which is the verified basic version, which is used for this upgrade After the new configuration data fails to load, the FPGA can automatically load the basic version through the configuration loading circuit, thereby ensuring that the FPGA can still work normally. At the same time, because the host uninstalls the PCIe driver before the upgrade, and after uninstalling the PCIe driver, combined with the change in the state of the PCIe link, the FPGA can know when to start the upgrade. In addition, after the configuration data is successfully loaded, the FPGA usually performs a warm reset to complete tasks such as initializing the FPGA internal registers.
  • the "end of process” in this step refers to the end of the upgrade-related process.
  • the FPGA will work based on the existing working method, for example, through mutual negotiation with the host to establish a PCIe link, let The status of the PCIe link becomes link and then communicates with the host for various services.
  • the host before the FPGA is upgraded, the host will uninstall the PCIe driver within a predetermined time, and only upgrade after the uninstall is completed. In this way, since there is no PCIe driver corresponding to the FPGA, the host is not affected by the FPGA upgrade. In order to avoid abnormal situations such as host crashes during the FPGA upgrade process. In addition, in this embodiment, both the FPGA and the host only judge the state of the other party within a predetermined time, so that the influence caused by abnormal death of the peer device can be prevented.
  • this embodiment discloses another FPGA upgrade method, referring to FIG. 9, which is a hardware architecture diagram based on this embodiment.
  • the difference between this embodiment and the first embodiment is that the FPGA and the host may not determine the state of the other party by detecting the change of the PCIe link state, but interact through reserved physical pins.
  • the reserved pin can also be a pin that can be used for bidirectional communication. It can be used by time-division multiplexing, that is, it is used for communication between the host and the FPGA in a certain moment, and is used in another moment. FPGA communication towards the host. The following flow is described based on the case of two pins.
  • FIG. 10 it is a flowchart of processing on the host side, and each step is executed by the host, including:
  • it can be sent through the reserved RSV1 pin or through the PCIe link.
  • S102 and S103 can be reversed, that is, S103 can be executed first, and then S102 can be executed.
  • the peer FPGA can upgrade after receiving the message to prevent the host from being abnormal due to premature upgrade.
  • This step is similar to the step S65 in the first embodiment, and is used to determine whether the peer has completed the upgrade. The difference is that in this embodiment, the signal sent by the reserved pin is used to judge, not the status of the PCIe link. To judge.
  • the setting of the first time-out time in step S65 is the same as the setting of the first time-out time in this step, and those skilled in the art can make adaptive adjustments according to the detailed discussion in step S65 (for example, removing the PCIe link Time of state change, etc.), this step will not repeat them.
  • the method described in the first embodiment can still be used to determine whether the upgrade is successful, and take corresponding measures when the judgment is successful or unsuccessful.
  • the host receives the upgrade completion message instead of the PCIe link status detection method in Embodiment 1, and can also know whether the FPGA has completed the upgrade.
  • receiving the upgrade completion message can be completed through the reserved pin, for example, through another reserved pin RSV2.
  • RSV1 is time-multiplexed, the host can also use RSV1 to receive it.
  • FIG. 11 is a flowchart of processing on the FPGA side. Each step is executed by the FPGA, including:
  • S113 Determine whether the uninstall complete message is received within the second timeout period, and if so, execute S114; otherwise, the execution process ends, and then continue to wait for the received instruction, and continue to execute S111 if the instruction is received.
  • step S83 For the setting of the second timeout period in this step, refer to the setting of the third timeout period in S83.
  • an upgrade complete message can be sent to the host through RSV2, which can be specifically completed by the control circuit 8213.
  • dedicated hardware (reserved pins) is used to send various information, and it is not necessary to detect the status of the PCIe link, which is simpler in software implementation.
  • this embodiment provides another FPGA upgrade method.
  • S102 in the second embodiment may be executed first, then S104, and then S103.
  • the FPGA does not need to wait for a preset time, but can start the upgrade directly.
  • FIG. 12 it is a flowchart of processing on the host side. Each step is executed by the host, including:
  • Each step is performed by the FPGA, including:
  • S132 Determine whether it is an upgrade instruction. If yes, perform S133; if no, perform operations corresponding to other instructions.
  • the FPGA can directly upgrade after receiving the upgrade instruction, reducing the waiting time.
  • this embodiment discloses an FPGA board 14.
  • the FPGA board includes an FPGA chip 141 and an FPGA configuration memory 142.
  • the FPGA chip 141 and the FPGA configuration memory 142 please refer to the introduction above, and no more details are provided here.
  • the FPGA 141 and the host can be connected in the manner described in the first embodiment, that is, they can be connected through a PCIe link (excluding reserved pins).
  • the FPGA performs the operations performed by the FPGA 141 in Embodiment 1 by loading the configuration data stored in the FPGA configuration memory 142.
  • the version loaded by the FPGA before the upgrade is the old version. After the upgrade is completed, the old The version will be replaced by the new version (that is, the new configuration data).
  • the new version can continue to retain the part of the old version that is used to implement the upgrade function, so that it can continue to upgrade later.
  • the FPGA 141 and the host can be connected in the manner described in the foregoing second embodiment, that is, connected through a PCIe link, and also connected through reserved pins to transmit, for example, upgrade instructions and instructions for indicating working status information.
  • the FPGA 141 performs the operations performed by the FPGA 141 in Embodiments 2 and 3 by loading configuration data stored in the FPGA configuration memory 142.
  • the specific structure of the FPGA board can be referred to the foregoing introduction, for example, it can be a PCIe board inserted into the PCIe slot.
  • this embodiment discloses a host device 15 which may be the host part of the aforementioned computing device or other data processing device.
  • the host device 15 includes a host capable of executing software instructions Processor 151 (such as CPU) and memory 152, wherein the memory 152 may include non-volatile memory 1521 (such as magnetic disk, flash memory, etc.) and volatile memory 1522 (such as memory), through the processor 151 and the memory 152 Cooperating, the processor 151 can execute instructions stored in the memory and complete the operations performed by the host in the foregoing embodiments.
  • this embodiment discloses an electronic device 16 including the FPGA board described in Embodiment 4 and the host device described in Embodiment 5, the electronic device may be the aforementioned Computing equipment or other equipment for data processing.
  • this embodiment discloses a computer storage medium that stores a plurality of instructions for the processor to execute, where the instructions are for the processor to read and execute the host in the foregoing embodiments Instructions for the operation performed.
  • this embodiment also discloses a computer storage medium that stores configuration data for configuring the FPGA, where the configuration data is the FPGA that enables the FPGA to execute the foregoing embodiments after loading Configuration data for the operation performed.
  • the modifiers such as “first”, “second”, and “third” in this application are only used to distinguish the use of the same noun in different scenarios, and do not represent a strict order. It does not mean that the terms “first” and “second” in the claims have the same meaning.
  • the storage medium may be a magnetic disk, an optical disk, a read-only memory (Read-Only Memory, ROM) or a random access memory (Random Access Memory, RAM), etc.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • General Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Quality & Reliability (AREA)
  • Computer Security & Cryptography (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • Stored Programmes (AREA)

Abstract

一种FPGA升级方法，包括：主机向FPGA下发升级指令；所述主机卸载所述FPGA对应的PCIe驱动程序，使所述PCIe链路的状态变为所述断开状态；所述主机在第一超时时间内持续检测所述PCIe链路的状态是否变成连接状态；如果是，则重新加载所述PCIe驱动程序；所述方法还包括：所述FPGA在收到所述升级指令后，所述FPGA在第二超时时间内持续检测所述PCIe链路的状态是否变为断开状态，其中，所述断开状态为所述PCIe链路在所述主机卸载完成所述FPGA对应的PCIe驱动程序后的状态；如果是，所述FPGA从所述FPGA配置存储器中加载所述配置数据进行升级；升级完成后，所述FPGA通过跟所述主机协商以将所述PCIe链路的状态恢复为用于被所述主机检测到后重新加载所述PCIe驱动程序的连接状态。

Description

基于PCIe接口的FPGA升级方法
本申请要求于2018年12月5日提交中国国家知识产权局、申请号为201811480823.3、发明名称为“基于PCIe接口的FPGA升级方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及通信技术领域，尤其涉及基于PCIe接口的FPGA升级方法。
背景技术
由于FPGA(现场可编程逻辑门阵列)具有处理能力强、使用便捷性以及可重配置的特点，因此，在越来越多的业务场景中(如在服务器上)扮演类似于协处理器的重要角色。而基于通用性的考虑，当FPGA作为协处理器来加速主机的数据时，大部分是以标准PCIe接口卡的形式与主机相连。例如，参见图1，为一个服务器中PCIe接口卡与主机相连的结构示意图，图1中的FPGA板卡1、FPGA板卡2、图形处理卡以及固态硬盘均可以是PCIe接口卡，通过PCIe接口与主机相连。
在运行维护阶段，通常需要对FPGA的配置进行升级，在一些环境比较复杂或者恶劣的情况下，不适合工作人员去现场进行升级，就需要利用PCIe总线对FPGA进行在线升级。
参见图2，现有的一种FPGA升级方法中，通过增加专门的FPGA配置存储器(即用于存储FPGA配置数据的存储器，通常一个非易失性存储器芯片，如一个闪存芯片)来对FPGA进行在线升级，即主机先通过与FPGA之间的PCIe接口以及FPGA与FPGA配置存储器之间的接口(如SPI接口)将配置数据烧写到FPGA配置存储器中，然后触发FPGA启动加载，于是FPGA通过SPI接口从FPGA配置存储器中读取数据，完成加载后FPGA输出复位信号将自己热复位，复位过程结束后FPGA即可启用新功能。
通过上述方法进行升级时，由于FPGA的PCIe接口在加载过程中不可用，主机会产生PCIe链路状态异常，容易出现宕机或重启。为了保证FPGA加载完成后主机能够正常运行，一般都要求主机重新启动，但是这样处理会中断其他PCIe设备(例如图1所示的其他FPGA板卡或者图形处理卡)的运行，对业务造成影响。
发明内容
本申请提供FPGA升级方法、FPGA板卡、主机以及电子设备，用于缓解现有技术存在着的FPGA升级过程中主机容易出现宕机或者重启，从而对业务造成影响的问题。
第一方面，本申请提供了一种升级FPGA的方法，由主机以及FPGA配合执行，其中，所述主机与所述FPGA通过PCIe链路相连，所述FPGA与FPGA配置存储器相连，所述FPGA配置存储器中保存有所述FPGA升级所需的配置数据，所述方法包括：所述主机向所述FPGA下发升级指令；所述主机卸载所述FPGA对应的PCIe驱动程序，使所述PCIe链路的状态变为断开状态；所述主机在第一超时时间内持续检测所述PCIe链路的状态是否 变成连接状态；如果检测到所述PCIe链路的状态变为所述连接状态，则重新加载所述PCIe驱动程序；所述方法还包括：所述FPGA在收到所述升级指令后，所述FPGA在第二超时时间内持续检测所述PCIe链路的状态是否变为断开状态，其中，所述断开状态为所述PCIe链路在所述主机卸载完成所述FPGA对应的PCIe驱动程序后的状态；如果在所述第二超时时间内检测到所述PCIe链路变为断开状态，所述FPGA从所述FPGA配置存储器中加载所述配置数据进行升级；升级完成后，所述FPGA通过跟所述主机协商以将所述PCIe链路的状态恢复为用于被所述主机检测到后重新加载所述PCIe驱动程序的连接状态。
现有技术中，在FPGA升级过程中，PCIe链路处于不可用状态，同时，主机上的应用程序或者PCIe驱动程序有可能在访问FPGA，由于PCIe链路处于不可用状态，主机上的应用程序或者PCIe驱动程序会报错或者挂死，导致主机中的操作系统出现异常，引起宕机或者重启。而本方法FPGA升级时，会检测主机卸载完FPGA对应的PCIe驱动程序后才进行升级，这样，主机中的应用程序或者PCIe驱动程序就不会受到FPGA升级的干扰，不会出现宕机等异常情况，并且，在FPGA升级后，主机可以重新加载FPGA对应的PCIe驱动程序，从而不需要重启，不会中断其他PCIe设备。此外，本方法中，FPGA只在超时时间内等待，可以避免因主机出错而一直等待所造成的业务中断，并且，通过检测PCIe链路状态来触发检测主机是否卸载完PCIe驱动程序可以通过基于PCIe插槽形式的主流硬件实现，无需改动硬件，硬件成本更低。
在第一方面一种可能的实现方式中，所述主机在卸载所述PCIe驱动程序之前，暂停使用PCIe链路对FPGA进行访问的一个或多个应用程序。主机通过先暂停应用程序可以防止数据丢失，同时，暂停并不会终止程序，便于后续恢复后能够继续快速处理业务。
在第一方面一种可能的实现方式中，所述主机在重新加载所述PCIe驱动程序之后，恢复所述一个或多个应用程序运行。通过在加载PCIe驱动程序后再恢复应用程序，可以继续处理业务，无需重新启动，加快了处理业务的速度。
在第一方面一种可能的实现方式中，所述第一超时时间为预定的所述FPGA完成升级所需的时间。例如，所述第一超时时间可以包括所述FPGA完成从所述FPGA配置存储器中加载升级所需的配置数据、执行加载后的初始化和复位操作的时间加上裕量时间。该第一超时时间既能够保证FPGA在正常情况下能够完成升级，又不会过多地等待而对主机造成影响。
在第一方面一种可能的实现方式中，所述所述第二超时时间为预定的所述主机从发出所述升级指令后到完成卸载所述PCIe驱动程序所需的时间。例如，所述第二超时时间可以包括所述主机从发出所述升级指令后一直到卸载完成所述PCIe驱动程序的时间加上裕量时间。该第二超时时间既能够保证主机在正常情况下能够完成驱动的卸载，又不会过多地等待而对FPGA造成影响。
在第一方面一种可能的实现方式中，所述主机在第一超时时间内持续检测所述PCIe链路的状态是否变成连接状态包括：在所述第一超时时间内通过持续检测位于所述主机中的链路状态寄存器来持续检测所述PCIe链路是否变为所述连接状态。所述主机通过位于所述主机中的链路状态寄存器来检测PCIe链路状态实现简单，降低了实现成本。
在第一方面一种可能的实现方式中，所述FPGA在第二超时时间内持续检测所述 PCIe链路的状态是否变为断开状态包括：所述FPGA在所述第二超时时间内通过持续检测位于所述FPGA中的链路状态寄存器来持续检测所述PCIe链路是否变为所述断开状态。所述FPGA通过位于所述FPGA中的链路状态寄存器来检测PCIe链路状态实现简单，降低了实现成本。
在第一方面一种可能的实现方式中，如果所述PCIe链路的状态在所述预定时间内未变为断开状态，则退出升级流程。通过退出升级流程，可以重新执行其他的操作，避免因一直等待主机状态变化而无法处理其他业务所造成的影响。
在第一方面一种可能的实现方式中，所述FPGA位于PCIe插卡上，所述PCIe插卡安装在所述主机的PCIe扩展槽上。这种方式是现在一种主流的PCIe设备与主机相连的实现方式，因此，本方法可以应用于主流的实现方式，无需改动硬件，实现成本更低。
在第一方面一种可能的实现方式中，所述FPGA配置存储器为闪存芯片，闪存芯片通过串行外设接口(SPI)与所述FPGA相连。闪存为当前很常见的一种存储器，因此，使用简单，降低了实现成本。
在第一方面一种可能的实现方式中，在加载时，具体由所述FPGA的用户电路向FPGA出厂时自带的加载电路发出底层命令来启动。其中，所述用户电路即FPGA使用者通过购买FPGA芯片，并加载配置数据后形成的电路；FPGA出厂时自带的电路为生产厂家生产FPGA发货时就自带的电路，该电路会固化在里面，不会因为用户配置数据的加载或者消失而改变。底层命令即厂家定义的用户可以与FPGA自带的加载电路交互的命令，通过这种启动方式，可以确保FPGA能够从所述FPGA配置存储器中加载配置数据。
在第一方面一种可能的实现方式中，所述PCIe链路的断开状态和连接状态都是所述FPGA与主机的PCIe接口电路经过PCIe链路协商后的结果。协商方式都会现有技术，因此，无需改动协议，实现更加简单。
在第一方面一种可能的实现方式中，存储在所述FPGA配置存储器中的所述配置数据是所述主机在发送所述下发升级指令前通过所述FPGA进行存储的。也即所述主机可以事先保存一份配置数据，然后所述FPGA接收所述主机发送的配置数据，并通过与所述FPGA配置存储器的接口将配置数据保存到所述FPGA配置存储器，这种方式也称“在线”加载，不需要人工参与，因此，升级更方便。
在第一方面一种可能的实现方式中，在所述主机卸载PCIe驱动程序的过程中，通过设置AER寄存器来屏蔽链路异常，即让所述主机不会响应链路上的异常事件，这样，所述主机就不会因为链路变成断开状态而出现宕机等异常情况。后续需要在恢复PCIe驱动程序的过程中，可以配置AER寄存器使能链路异常上报功能，即让所述主机能够响应链路上的异常事件。
第二方面，本申请公开了一种在线升级FPGA的方法，由FPGA执行，所述FPGA与主机通过PCIe链路通信，所述FPGA还与FPGA配置存储器相连，所述FPGA配置存储器中保存有所述FPGA升级所需的配置数据，所述方法包括：接收所述主机下发的升级指令；在超时时间内持续检测所述PCIe链路的状态是否变为断开状态，其中，所述断开状态为所述PCIe链路在所述主机卸载完成所述FPGA对应的PCIe驱动程序后的状态；如果在所述超时时间内检测到所述PCIe链路变为断开状态，从所述FPGA配置存储器中 加载所述配置数据进行升级；升级完成后，通过与所述FPGA协商以将所述PCIe链路的状态恢复为连接状态；所述连接状态用于被所述主机检测到后重新加载所述PCIe驱动程序。
本申请中的第二方面跟第一方面基于同一个发明构思，只是执行主体换成了FPGA，因此，第二方面中的各种实现方式也可以参考第一方面中由FPGA执行的各种实现方式，第二方面及第二方面中的各种实现方式也能取得跟第一方面以及第一方面各种实现方式的相似的效果。
第三方面，本申请公开了一种升级FPGA的方法，由主机执行，所述主机与所述FPGA通过PCIe链路相连，所述FPGA与FPGA配置存储器相连，所述FPGA配置存储器中保存有所述FPGA升级所需的配置数据，所述方法包括：主机向所述FPGA下发升级指令；卸载所述FPGA对应的PCIe驱动程序，使所述PCIe链路的状态变为断开状态；在第一超时时间内持续检测所述PCIe链路的状态是否变成连接状态；如果检测到所述PCIe链路的状态变为所述连接状态，则重新加载所述PCIe驱动程序；其中，所述升级指令为让所述FPGA收到后执行如下操作的指令：在第二超时时间内持续检测所述PCIe链路的状态是否变为所述断开状态，其中，所述断开状态为所述PCIe链路在所述主机卸载完成所述FPGA对应的PCIe驱动程序后的状态；如果在所述第二超时时间内检测到所述PCIe链路变为断开状态，从所述FPGA配置存储器中加载所述配置数据进行升级；升级完成后，通过跟所述主机协商以将所述PCIe链路的状态恢复为用于被所述主机检测到后重新加载所述PCIe驱动程序的连接状态。
本申请中的第三方面跟第一方面基于同一个发明构思，只是执行主体换成了主机，因此，第三方面中的各种实现方式也可以参考第一方面中由主机执行的各种实现方式，第三方面及第三方面中的各种实现方式也能取得跟第一方面以及第一方面各种实现方式的相似的效果。
第四方面，本申请公开了一种FPGA板卡，包括FPGA芯片以及FPGA配置存储器(如闪存等非易失性存储器)，FPGA通过加载存储在FPGA配置存储器中的配置数据来执行第二方面以及第二方面的各种实现方式中的FPGA执行的操作，可以取得跟第二方面相同的效果。可以理解，FPGA可能会存在厂家自带的电路(如配置加载电路)，在这种情况下，本申请中，由配置数据定义的电路可以通过与厂家自带的电路相配合来完成第二方面以及第二方面的各种实现方式中的FPGA执行的操作。
在前述几个方面及各种可能的实现方式中，所述FPGA与所述主机可以仅通过PCIe链路连接，在另一种实现方式中，所述FPGA与所述主机还通过预留的管脚进行连接以传输用于表示工作状态的信息。在实现方式中，所述FPGA通过加载存储在FPGA配置存储器中的配置数据来执行实施例二、三中的FPGA执行的操作。
第五方面，本申请公开了一种主机设备，该主机设备包括一个能够软件指令的处理器(如CPU)以及存储器，其中，存储器可以包括非易失性存储器(如磁盘、闪存等)以及易失性存储器(如内存)，通过处理器与存储器的配合，处理器可以执行存储在存 储器中指令，并完成第二方面及第二方面各种实现方式中的所述主机执行的操作，从而可以取得第二方面及第二方面各种实现方式对应的效果。在另一种所述FPGA与所述主机还通过预留的管脚进行连接的方式中，所述主机还可以通过执行存储在存储器中的指令来执行实施例二、三中的所述主机执行的操作。
第六方面，本申请公开了一种电子设备，该电子设备包括第四方面所述的FPGA板卡以及第五方面所述的主机设备。
第七方面，本申请公开了一种计算机存储介质，该存储介质存储有用于处理器执行的多个指令，其中，这些指令为能够让处理器读取后执行第三方面及第三方面各种实现方式中主机所执行的操作的指令。
其中，第三至第七方面以及各方面中的可能的实现方式跟第一方面以及第一方面中各种可能的实现方式都是基于同一个发明构思，因此，也能取得跟第一方面以及第一方面中各种可能的实现方式相同的效果。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为服务器中主机通过PCIe链路与PCIe设备连接的示意图；
图2为FPGA与主机连接示意图；
图3为计算设备中主机与FPGA板卡的结构示意图；
图4为FPGA板卡通过PCIe插槽与主机中的处理器、存储器连接的结构示意图；
图5为本申请实施例一中电子设备中主机与FPGA板卡的结构示意图；
图6为本申请实施例一中主机执行的方法的流程图；
图7A为图6所示的方法中的步骤S65的一种在超时时间内检测PCIe链路的状态是否是link up的流程图；
图7B为图6所示的方法中的步骤S65的另一种在超时时间内检测PCIe链路的状态是否是link up的另一流程图；
图8为本申请实施例一中FPGA执行的方法的流程图；
图9为本申请实施例二中计算设备中主机与FPGA板卡的结构示意图；
图10为本申请实施例二中主机执行的方法的流程图；
图11为本申请实施例二中FPGA执行的方法的流程图；
图12为本申请实施例三中主机执行的方法的流程图；
图13为本申请实施例三中FPGA执行的方法的流程图；
图14为本申请实施例四中FPGA板卡的结构示意图；
图15为本申请实施例五中主机设备的结构示意图；
图16为本申请实施例六中电子设备的结构示意图。
具体实施方式
下面结合各附图，对本发明的各个实施例进行描述。
本申请公开的FPGA升级方法可以应用于基于FPGA的设备中，参见图3，为一种应用于电子设备的示意图，这里的电子设备可以是指具有计算能力的计算设备，例如，个人电脑、服务器、工作站等设备。当然，本申请也不限定用于其他的电子设备，如各种网络设备(如网关、路由器、交换机等)。
以图3为例，计算设备可以包括主机以及FPGA板卡，其中，主机在硬件上通常可以包括具有执行软件处理能力的通用处理器(如基于x86指令集或者基于ARM指令集的CPU)，此外，还包括用于存储软件指令以及各种数据的非易失性存储器(如硬盘、闪存)以及存储处理器运行所需的软件指令及临时数据的存储器(如内存)。处理器能够读取存储在非易失性存储器中的软件指令来完成相应的功能。在软件层面，主机通常包括操作系统(如Windows操作系统、Linux操作系统等)以及基于操作系统运行的各种应用程序。此外，主机还可以包括各种专用处理电路(如各种ASIC)，例如，桥片，图像处理器等。主机上的各种处理电路中的一个或多个可以封装成一个芯片或多个芯片，例如，可以将桥片与CPU封装成一个芯片，将图像处理器单独封装成一个芯片，本申请并不限定。
计算设备还包括FPGA板卡，这里的FPGA板卡是指基于PCB形态，能够通过设置在电子设备上的PCIe插槽与主机进行物理上相连并进行通信的板卡。FPGA板卡包括一个FPGA芯片(本申请中简称为“FPGA”)，用于存储FPGA升级数据的FPGA配置存储器，该FPGA配置存储器可以是如闪存之类的非易失性存储器，此外，还可以包括缓存芯片(如SDRAM)等器件。当FPGA配置存储器为闪存时，FPGA与FPGA配置存储器之间可以通过SPI接口进行通信。参见图4，本申请中，电子设备还可以包括一个PCIe插槽(位于一个电子设备的PCB中的)，PCIe插槽上的用于实现PCIe链路的物理引脚与主机上的处理器(如CPU)相连；同时，FPGA板卡还可以包括与PCIe插槽相适配的用于实现PCIe协议的金手指，金手指通过PCB上的走线与FPGA相连；这样，通过将金手指插入PCIe插槽，就能够实现FPGA与主机的物理连接以及通信。
本领域技术人员可以理解，FPGA的基本工作原理是通过加载一个配置数据(例如，以配置文件形式存在)来改变FPGA内部的配置RAM的内容，从而改变FPGA内部各种逻辑资源的配置，以实现不同的电路功能，并且，配置数据可以多次加载，从而使得FPGA能够通过加载不同的配置数据来完成不同的功能，具有很好的灵活性。本实际应用中，常常需要更新FPGA的功能，此时，可以将新配置数据事先加载到FPGA配置存储器，然后让FPGA加载新配置数据来实现新配置数据所定义的功能，这个过程被称为FPGA的升级过程。同时，FPGA在出厂时，会自带有一个用于加载配置数据的配置加载电路，该配置加载电路可用于在用户自定义的电路功能(即由配置数据定义的功能)失效后，仍然能够保证最基本的加载操作。
实际中，为了增加系统的稳定性，FPGA配置存储器可以存两份配置数据，一份是基 础版本，用于提供FPGA基本功能，一般不会被用户修改；另一个是正常的业务版本，即当前最新的业务版本，用于为FPGA提供正常业务所需的功能。FPGA启动时，会先检查基础版本的header(数据头)部分的偏移地址，如果该偏移地址指向业务版本，则从偏移地址开始加载业务版本。后续如果要升级FPGA，主机可以先与FPGA通信，将需要升级的新配置数据替换掉原先的业务版本，这样，当升级成功后，后续当FPGA再次启动时，从偏移地址加载的就是新配置数据；如果升级失败(即从偏移地址处加载业务版本失败)，FPGA可以通过加载基础版本来让FPGA进行工作。
FPGA板卡与主机相连后，主机可以通过运行软件来访问FPGA板卡上的FPGA。本申请中，主机中的应用程序可以通过操作系统自带的PCIe驱动程序或者用户在安装完操作系统后再独立安装的PCIe驱动程序来使用PCIe协议与FPGA进行通信。同时，本申请中有关升级的控制操作(如启动升级、暂停/恢复应用程序运行、卸载PCIe驱动程序等)可通过第三方应用程序提供，例如，可由FPGA板卡的生产厂家提供与FPGA板卡适配的应用程序，服务器用户需要使用FPGA板卡时，可以将FPGA板卡厂家提供的应用程序安装到主机中以实现对FPGA的控制操作。
实施例一
本实施例基于FPGA板卡通过PCIe插槽与主机相连的应用场景对FPGA升级方法进行介绍。参见图5，为本实施例的应用场景的结构框图，基于图5，下面分别对主机侧以及FPGA板卡侧的执行流程进行具体介绍。
参见图6，为主机侧的流程图，流程中的各个方法步骤具体可由主机中的处理器(如CPU)通过读取存储器中的指令以软件的方式来执行，该软件可以是一个由生产FPGA板卡的厂家提供的、用于提供对FPGA板卡进行升级的升级程序，该升级程序可以是一个第三方应用程序(即非操作系统自带，而是装完操作系统后再额外安装的一个应用程序)，当然，也可以是操作系统自带的程序。具体的，主机执行如下方法：
S61、加载新配置数据到FPGA配置存储器。
主机可以通过一个升级软件(如基于GUI或者命令行的软件)来与用户进行交互，并完成新配置数据的加载，其中，升级软件可以是单独的一个软件，该软件可以提供给其他软件调用接口，使得其他软件能够调用该软件完成FPGA升级。此外，升级软件也可以是其他软件中的一个软件或多个软件模块，本申请并不限定。
例如，通过升级软件让用户选择位于主机本地或者远程的新配置数据以及待升级的目标FPGA，然后点击一个软件中设置的“加载”按钮让选择的新配置数据加载到FPGA配置存储器中，后续再通过点击其他按钮来完成其他步骤(如通过点击设置的“升级”按钮来执行后续操作)。或者，也可以将“加载”操作与“升级”操作合并，例如，只点击“升级”按钮，此时，跳出一个对话框来选择需要加载的新配置数据，用户选择完后自动执行后续的步骤。当然，以上只是几种简单的示例，实际中，可以通过其他方法来将新配置数据加载到FPGA配置存储器。
S62、暂停使用PCIe链路对FPGA进行访问的一个或多个应用程序，并保存现场。
本申请中，暂停是指暂时停止，也即软件并未关闭，恢复后不需要重头开始执行，而是可以重新从暂停时的位置继续执行。暂停操作可以通过调用操作系统自带的一些 API来完成，具体实现为现有技术，本申请不再赘述。暂停的好处在于不需要关闭应用，可以尽量减少对业务的干扰。
保存现场在通信技术、软件技术领域的意思是公知的，主要是指当一些业务需要暂停时，将业务涉及的一些数据进行保存，以供业务恢复时能够根据之前的数据继续执行。本申请中，保存现场既可以包括保存主机中的数据，还可以包括保存FPGA运行过程中的数据。例如，针对一个FPGA协助主机完成压缩工作的场景，此时，主机可以保存主机应用程序(压缩程序)执行过程中得到的中间数据(如FPGA传过来的压缩后的数据)，或者应用程序本身的数据(如压缩程序加载到内存的数据)，还可以保存FPGA运行过程中涉及的各种数据(如用于指示FPGA当前正在压缩/或已完成的数据的位置信息)。
保存现场如果涉及到FPGA，通常需要主机与FPGA进行交互，也即主机根据需要保存的内容来通知FPGA上报。保存现场的具体实现本领域技术人员可以根据不同的保存需求来实现，本申请并不赘述。需要说明的是事，本步骤并不是必选的步骤，如果没有正在运行的应用程序，可以不执行本步骤；或者如果用户无保存现场的需求(如事先能确定即使不保存现场，也不会造成数据丢失，或者即使丢失也可接受)，则也可以不保存现场。
S63、主机向FPGA发送升级指令。
主机可以通过安装的升级程序通过PCIe接口向FPGA发送升级指令，该升级指令用于通知FPGA进行升级。需要说明的是，为了能够让FPGA进行升级，需要预先在FPGA配置存储器中存储用于FPGA升级的升级数据，该升级数据具体可为FPGA的新配置数据。具体的，可以通过主机将新配置数据通过PCIe接口传输至FPGA，然后再由FPGA通过一个接口(如SPI接口或者自定义的其他接口)传输至FPGA配置存储器。通过这种方式传输可以实现远程的在线加载，即可通过网络来控制主机将新配置数据加载至FPGA配置存储器，而不需要现场的手工操作就完成新配置数据的加载。
S64、主机卸载FPGA对应的PCIe驱动程序。
具体的，可以通过升级软件来调用操作系统API来卸载PCIe驱动程序。在卸载PCIe驱动程序时，主机侧的PCIe接口将被复位，因此，在卸载完PCIe驱动程序后，PCIe接口的链路状态会从link up变为link down，这个变化可被FPGA检测到，从而触发它的升级操作(从FPGA配置存储器加载新配置数据)。此外，需要说明的是，为了后续能够重新加载FPGA对应的PCIe驱动程序，主机应该在本地(如硬盘等非易失性存储介质中)保留一份针对FPGA的PCIe驱动程序的文件，具体的，主机可以在升级开始前就保留一份，或者通过在线的方式在需要重新加载之前从网上下载得到。
如何卸载PCIe驱动本领域技术人员可以结合现有的技术基于不同的应用场景来实现，例如，在Linux操作系统下，具体的卸载PCIe驱动程序可以包括以下步骤：1)通过类似rmmod xxx.ko命令完成驱动文件的卸载。2)通过AER寄存器屏蔽链路异常，即让所述主机不会响应链路上的异常事件。3)去使能(disable)链路控制寄存器(link control register)。4)删除(remove)设备。通过上述步骤，即可在Linux操作系统下，让PCIe链路的状态变成断开状态，从而让FPGA检测到。后续可以再使能(enable)链路控制寄存器(例如可以等一个预设时间再使能，预设时间可以为小于FPGA的加载时间)。以上在Linux操作系统下的具体操作只是一个示例，本领域技术人员可以基于 上述方法在其他具体的应用场景实现类似的功能。
S65、在第一超时时间内持续检测PCIe链路的状态是否是连接状态(link up)，如果是，执行S66，否则执行S67。
本申请中，“持续检测”是指在检测过程中有持续的检测动作以在预定时间(如本步骤中的第一超时时间内)能够完成有效的检测，也即能够在这段预定时间内PCIe链路的状态如果会变成连接状态，那么就要检测到。而不是任意选取一个时间点检测一次，这样就有可能无法有效地检测到PCIe链路状态的变化(如检测时间点设置得比较靠近，检测时并没有变成连接状态，检测后才变连接状态，此时，由于只进行了一次检测，就无法完成有效的检测)。具体的，持续检测可以周期性地进行或者也可以通过自定义的非周期性的方式来进行多次检测，检测周期越小，越能更快地发现PCIe链路的状态是否变成连接状态，当然，在极端情况下，也可以仅设置一次检测(即可认为持续检测的周期等于预定时间)，即在预定即将结束时进行一次检测。
具体如何检测链路状态为现有技术，例如，可以通过查询位于主机中的PCIe相关的寄存器(如PCIe协议规定的PCIe link status register)来判断是否是link up。本实施例中，在执行完S64后，PCIe链路的状态会变成断开状态(link down)，后续FPGA执行完升级再次与主机协商后，PCIe链路的状态又会变成link up，所以本实施例检测是否变成link up是用于判断FPGA是否完成升级并开始正常工作。
本实施例只在第一超时时间内判断是为了防止因FPGA出错而造成主机一直等待的情况，也即本实施例中，主机最多只等待第一超时时间，如果第一超时时间到了FPGA还未完成升级，说明FPGA侧可能已经出问题了，不值得主机再等下去，主机此时可以通过告警等手段来提醒用户FPGA升级有可能出了问题，同时，主机不需要再执行S65步骤以节省主机资源。
其中，“第一超时时间”可以认为是“预定的对端FPGA完成升级所需的时间”。其中，本申请中，完成升级(或者说“升级完成”)是指FPGA完成了加载配置数据(可以包括加载新配置数据失败后再加载基础版本)、热复位等升级所需的操作，本领域技术人员可以结合FPGA完成升级时所需的操作时间来设定第一超时时间。
例如，这个时间至少会包括以下主要时间“FPGA从FPGA配置存储器加载新配置数据的时间+裕量时间”，因为加载操作是必备的，同时，由于加载的时间无法做到非常精确地估计，因此，也会留有一定的裕量。在实际中，还会包括其他时间，例如，PCIe链路的状态从link down变成link up的时间、FPGA检测到该状态变化的时间、FPGA在加载完后进行复位时间等，但这些时间所占权重很小，可以忽略，或者将裕量时间设置得大一点来代替这些时间。
此外，现有的FPGA在加载新配置数据失败后，通常都会加载一份基础版本的配置数据，如果FPGA有这种操作，第一超时时间还可以包括加载基础版本所需的时间。
本领域技术人员可以结合理论分析、实验测试等手段来确定这个时间。例如，通常情况下，“FPGA从FPGA配置存储器加载新配置数据的时间”为主要的时间，该时间可以根据公式“新配置数据大小/FPGA配置速率”来估算，其中新配置数据大小是已知的，FPGA配置速率等于FPGA配置接口的时钟频率(例如SPI接口的时钟频率)。裕量时间的具体大小本领域技术人员可以结合实际应用的需求来定，例如，为了更保险起见，通常 可以将裕量时间设置得大一点。
本步骤具体实现可以通过不同的方法来实现，下面对其中两种方法进行介绍：
方法一：
可以通过启动一个定时器，在第一超时时间内持续检测PCIe链路的状态是否为link up来实现，具体的，参见图7A，包括：
S651、启动一个定时器，其中，定时器的超时时间设置为上述“第一超时时间”。
S652、检测PCIe链路的状态是否是link up，如果是执行S66，否则，执行S653；
S653、判断定时器是否到达设置的第一超时时间，如果否，执行S652，如果是，执行S67。
方法二：
可以先等一段时间，再通过启动定时器来检测PCIe链路的状态是否为link up来实现。也即由于FPGA加载必须需要一定的时间，因此，没有必要马上去检测PCIe链路的状态是否为link up(刚开始肯定不会是link up)，而可以先等一会儿再去检测，具体的，参见图7B，包括：
S651’、等待第一预设时间，其中，第一超时时间为FPGA在正常情况下快要完成升级的时间，用户可以结合分析、实验来得出该时间，为了保证可靠性，可以留有一定的裕量。
S652’、启动一个定时器，其中，定时器的第二超时时间可设置为上述“第一超时时间-第一预设时间”。此时，相比方法一，由于已经等待了第一预设时间，因此，定时器超时时间不需要等待第一超时时间这么长，而是可以再减去第一预设时间。
S653’、检测PCIe链路的状态是否是link up，如果是执行S66；否则，执行S654’。
S654’、判断定时器是否到达设置的超时时间，如果否，执行S653’；如果是，执行S67。
S66、主机重新加载PCIe驱动程序，然后恢复运行暂停的一个或多个应用程序以及恢复现场。
当升级程序确认PCIe链路的状态从link down变为link up，则重新执行PCIe链路的扫描和设备枚举操作，可以找到升级后的FPGA，于是重新加载PCIe驱动程序。最后，将此前暂停运行的应用程序恢复运行，允许它们访问升级后的FPGA，并恢复现场。
如何进行重新加载PCIe驱动程序本领域技术人员可以结合现有的技术基于不同的应用场景来实现，例如，在Linux操作系统下，具体的重新加载PCIe驱动程序可以包括以下步骤：1)通过类似insmod xxx.ko命令完成驱动文件的加载。2)配置AER寄存器使能链路异常上报功能，即让所述主机能够响应链路上的异常事件。以上在Linux操作系统下的具体操作只是一个示例，本领域技术人员可以基于上述方法在其他具体的应用场景实现类似的功能。
需要说明的是，现有的FPGA在加载失败后通常会自动加载基础版本，虽然也能跟主机正常通信，但不能满足正常的业务要求，也即虽然PFGA“升级完成”(加载了一个配置数据，不限定是基础版本还是新配置数据)，但并不表示“升级成功”(加载了新配置数据)，因此，在重新加载PCIe驱动程序之后并且在恢复运行一个或多个应用程序以及恢复现场之前，主机还可以进一步通过主动查询FPGA的逻辑版本号(对应于配置数 据的版本)来判断升级是否成功(即是否加载了新配置数据)，如果判断升级成功(即逻辑版本号是新配置数据对应的版本号)，则后续进行正常的业务；如果失败，则可以进行各种失败处理，例如，重新升级、或者再加载一份新的配置数据来升级、或者告警等各种操作。
S67、主机告警。
如果在第一超时时间内，PCIe链路的状态没有变为link up，说明很可能是FPGA加载出了问题(例如FPGA配置数据不正确)，此时，主机可以告警，让用户了解异常信息以便进行后续处理。
参见图8，为FPGA执行的方法流程图，包括：
S81、获取来自主机的主机指令。
S82、判断获取的主机指令是否是升级指令，如果是，执行S83；如果否，执行与该指令对应的操作。
具体的，可以通过FPGA521中的PCIe接口电路5211来接收PCIe链路上传输的指令，接收完指令后可以放在一个寄存器中，然后可以通过主机指令解析电路5212来解析该寄存器中的指令是否为升级指令，如果是，则可以给控制电路5213发消息以通知控制电路来控制升级流程。
S83、在第三超时时间内持续检测PCIe链路的状态是否变为断开状态(link down)，如果是，执行S84；如果否，流程结束，后续再等待接收指令，如果收到指令再继续执行S81。
链路状态的检测可由PCIe链路状态检测电路5216来完成，检测完之后可以将结果发送给控制电路5213，由控制电路5213进行后续处理。检测的具体方法可参见针对S65步骤的详细描述。本步骤通过检测PCIe链路的状态是否从link up变成link down来确认主机是否卸载完驱动，只有在卸载完驱动后，FPGA才会开始执行升级操作，否则可以会引起主机异常(如宕机或重启)。
在一定的超时时间(即第三超时时间)内持续检测是为了防止主机出现的异常影响FPGA的运行，也即FPGA只等待第三超时时间，如果超时未完成，说明主机存在异常，FPGA不再等待而执行其他操作。
第三超时时间可以认为是“预定的主机从发出升级指令后到完成卸载PCIe驱动程序所需的时间”，例如，基于上述主机侧执行的流程，该时间可以包括“主机卸载完驱动所需的时间+裕量时间”。
具体如何在第三超时时间内持续检测PCIe链路的状态是否变为link down可以参见S651-S653以及S651’-S654’所示的方法，也即既可以通过启动一个定时器5214，在第三超时时间内持续检测PCIe链路的状态是否为link down来实现，或者也可以先等一段时间(主机快卸载完驱动的时间)，再通过启动定时器5214来检测PCIe链路的状态是否为link down来实现。
需要说明的是，本申请中，主机侧执行的S62与S63两个步骤的顺序也可以互换，在这种情况下，第三超时时间可以进行适应性调整，也即再加上暂停应用以及保存现场的时间，即在这种情况下，第三超时时间可以包括“暂停应用以及保存现场所需的时间 +主机卸载完驱动所需的时间+裕量时间”。
S84、从FPGA配置存储器加载新配置数据，判断是否加载成功，如果是，流程结束。
具体的，控制电路5213通知配置加载电路5215从FPGA配置存储器522中加载新配置数据，从而完成FPGA的升级。配置加载电路5215是FPGA在出厂时自带的电路，该电路会一直存在，不会因为配置RAM的数据的丢失(如掉电，或者人为清除)而丢失。用户使用FPGA过程中自定义的电路(由配置数据来定义)可以在失效前(即加载FPGA之前有一个清除内部逻辑电路的操作，例如，清除内部用于进行电路配置的配置RAM)给配置加载电路发送相关信号以指示其去FPGA配置存储器加载新配置数据，这样，后续配置加载电路便可完成新配置数据的加载。
例如，可通过控制电路(用户自定义的电路)与配置加载电路进行交互，具体的报文形式可以采用FPGA厂家规定的报文方式，报文按功能大致分为四类，有设备同步报文、配置加载地址报文、配置加载命令报文和设备解同步报文。
报文序列的十六进制数据组成与具体FPGA厂家提供的配置加载电路相关，以厂家Xilinx为例，FPGA的控制电路与配置加载电路之间具体的报文序列组成如下:
1)设备同步报文：采用十六进制数据0xFFFFFFFF/0x000000BB/0x11220044/0xFFFFFFFF/0xAA995566/0x20000000。该报文用于先检测SPI总线的位宽，再将配置加载电路与FPGA的控制电路进行设备同步。
2)配置加载地址报文：采用十六进制数据0x30020001/加载起始地址/0x20000000/0x20000000，该报文用于FPGA的控制电路告诉配置加载电路要加载的FPGA配置数据位于FPGA配置存储器的加载起始地址。
3)配置加载命令报文：采用十六进制数据0x30008001/0x0000000F/0x20000000/0x20000000，该报文用于FPGA的控制电路控制配置加载电路开始从FPGA配置存储器加载FPGA配置数据。
4)设备解同步报文：用十六进制数据0x30008001/0x0000000D/0x20000000/0x20000000，该报文用于解除配置加载电路与FPGA的控制电路之间的同步状态。
配置加载电路在加载过程中会对数据进行校验，如果校验通过，则表示加载成功，否则，加载失败。为了防止加载失败导致FPGA无法工作的情况，在一种实现方式中，可以在FPGA配置存储器中保存多个版本的配置数据，其中至少有一个是已经验证过的基础版本，当用于本次升级的新配置数据加载失败后，FPGA可以通过配置加载电路自动加载基础版本，从而可以保证FPGA仍然可以正常工作。同时，由于通过在升级前主机卸载PCIe驱动程序，并且在卸载完PCIe驱动程序后，结合PCIe链路的状态的变化能够让FPGA知道什么时候开始升级。此外，在加载配置数据成功后，FPGA通常还会进行热复位来完成例如将FPGA内部寄存器初始化等工作。
需要说明的是，本步骤中的“流程结束”是指升级相关的流程结束，接下来，FPGA都会基于现有的工作方式进行工作，例如，通过与主机进行相互协商以建立PCIe链路，让PCIe链路的状态变为link up，然后与主机进行各种业务通信。
本实施例在FPGA升级之前，会先在预定时间内等主机卸载完PCIe驱动程序，只有在卸载完后才升级，这样，由于没有FPGA对应的PCIe驱动程序，主机就可以不受FPGA升级的影响，从而可以避免在FPGA升级过程中主机出现死机等异常情况。此外，本实 施例FPGA、主机都只在预定时间内判断对方的状态，从而可以防止因对端设备异常而死等造成的影响。另外，本实施例中，通过检测PCIe链路状态的变化来判断对方的进展状态，可以不需要预留带外通信的管脚(即利用PCIe链路以外的通道进行通信的管脚)，非常适合应用于基于PCIe扩展卡的应用场景，无需进行硬件改动，从而减少成本，实现更加简单。
实施例二
基于以上各实施例，本实施例公开了另一种FPGA升级方法，参见图9，为本实施例所基于的硬件架构图。本实施例与实施例一不同的是，FPGA、主机可以不通过检测PCIe链路状态的变化来判断对方的状态，而是通过预留的物理管脚来进行交互。其中，预留的管脚的可以是两个，其中一个用于主机往FPGA方向的通信；另一个用于FPGA往主机方向的通信。预留的管脚也可以是一个可以双向通信的管脚，可以通过分时复用的方法来使用该管脚，即在某一时刻用于主机往FPGA方向的通信，在另一时刻用于FPGA往主机方向的通信。下面流程基于两个管脚的情况进行说明。
本实施例中的一些步骤跟实施例一中的类似，如无特殊说明，本领域技术人员可以参见实施例一的相关步骤来了解其具体实现。
参见图10，为主机侧处理的流程图，各步骤由主机执行，包括：
S101、加载新配置数据到FPGA配置存储器。
S102、暂停使用PCIe链路对FPGA进行访问的一个或多个应用程序，并保存现场。
S103、向FPGA发送升级指令。
具体可以通过预留的RSV1管脚，或者通过PCIe链路发送。
S104、卸载FPGA对应的PCIe驱动程序。
需要说明的是，S102以及S103的顺序可以调换，也即可以先执行S103，再执行S102。
S105、卸载完成后，发送用于指示卸载完成的卸载完成消息。
具体的，通过预留的管脚(如RSV1)来发送。通过发送卸载完成消息，使得对端FPGA可以收到消息后才进行升级，防止因过早升级而导致主机异常的情况发生。
S106、在第一超时时间内判断是否接收到来自FPGA的用于指示升级完成的升级完成消息，如果接收到，则执行S107；否则，执行S108。
该步骤与实施例一中的S65步骤类似，都是用来判断对端是否完成升级，区别在于本实施例中是通过预留的管脚发送的信号来判断，而不是通过PCIe链路的状态来判断。S65步骤中的第一超时时间的设置跟本步骤中的第一超时时间的设置的原理相同，本领域技术人员可以根据S65步骤中的详细论述来进行适应性调整(例如，去除掉PCIe链路状态变化的时间等)，本步骤不再赘述。
在升级成功后，仍然可以像前述实施例一所述的方法来判断是否升级成功，并在判断成功或者不成功时采取对应的措施。
本实施例中，主机通过接收升级完成消息的方式来取代实施例一中的通过检测PCIe链路状态的方式，也可以了解FPGA是否完成升级。其中，接收升级完成消息可以通过预留的管脚来完成，例如，通过另一个预留的管脚RSV2。当然，如果时分复用RSV1，主机也可以使用RSV1来接收。
S107、重新加载PCIe驱动程序，然后恢复暂停的一个或多个应用程序以及恢复现场。
S108、告警。
参见图11，为FPGA侧处理的流程图，各步骤由FPGA执行，包括：
S111、通过预留的管脚接收主机发送的指令。
S112、判断是否是升级指令，如果是，执行113；如果否，执行其他指令对应的操作。
S113、在第二超时时间内判断是否接收到卸载完成消息，如果是，执行S114；否则，执行流程结束，后续继续等待接收指令，如果收到指令再继续执行S111。
该步骤可参见实施例一中的S83步骤，本步骤中的第二超时时间的设定可以参考S83中的第三超时时间的设定。
S114、从FPGA配置存储器加载新配置数据，判断是否加载成功，如果是，执行S115；如果否，可以按实施例一中所述的加载一个验证过的基础版本来保证正常工作。在加载配置数据成功后，FPGA通常还会进行热复位来完成例如将FPGA内部寄存器初始化等工作。
S115、向主机发送升级完成消息，流程结束。
例如，可以通过RSV2向主机发送升级完成消息，具体可以由控制电路8213来完成。
本实施例通过专用的硬件(预留的管脚)来发送各种信息，不需要通过检测PCIe链路的状态，在软件实现上更加简单。
实施例三
基于实施例二，本实施例提供了另一种FPGA升级方法，本实施例中，可以先执行实施例二中的S102，再执行S104，再执行S103。相应地，在这种情况下，FPGA不需要在预设时间内等待，而是可以直接开始升级。
下面分别对主机以及FPGA具体执行的方法进行介绍。
参见图12，为主机侧处理的流程图，各步骤由主机执行，包括：
S121、加载新配置数据到FPGA配置存储器。
S122、暂停使用PCIe链路对FPGA进行访问的一个或多个应用程序，并保存现场。
S123、卸载FPGA对应的PCIe驱动程序。
S124、向FPGA发送升级指令。
此时，由于PCIe驱动程序被卸载，无法通过PCIe链路来发送升级指令，可以使用预留的管脚来发送。
S125、在第一超时时间内判断是否接收到来自FPGA的用于指示升级完成的升级完成消息，如果接收到，则执行S126；否则，执行S127。
S126、重新加载PCIe驱动程序，然后恢复暂停的一个或多个应用程序以及恢复现场。
S127、告警。
参见图13，为FPGA侧处理的流程图，各步骤由FPGA执行，包括：
S131、通过预留管脚接收主机发送的指令。
S132、判断是否是升级指令，如果是，执行S133；如果否，执行其他指令对应的操作。
S133、从FPGA配置存储器加载新配置数据，判断是否加载成功，如果是，执行S134；如果否，可以按实施例一中所述的加载一个验证过的基础版本来保证正常工作。
S134、向主机发送升级完成消息，流程结束。具体的，通过预留的管脚(如RSV2)向主机发送。
本实施例中，由于主机已经做了暂停应用、保护现场以及卸载PCIe驱动程序等动作，因此，FPGA收到升级指令后就可以直接升级，减少了等待时间。
实施例四
基于上述各实施例，本实施例公开了一种FPGA板卡14，FPGA板卡包括FPGA芯片141以及FPGA配置存储器142，有关FPGA芯片141以及FPGA配置存储器142可参见前文的介绍，这里不再赘述。本实施例中，FPGA141与主机可以通过前述实施例一中的方式连接，即可以通过PCIe链路连接(不包括预留的管脚)。在该实施例中，FPGA通过加载存储在FPGA配置存储器142中的配置数据来执行实施例一中的FPGA141执行的操作，可以理解，升级之前FPGA加载的版本为旧版本，在升级完成后，旧版本会被新版本(即新配置数据)取代，当然，新版本中可以继续保留有旧版本中用于实现升级功能的部分，使之后续能够继续升级。
在另一个实施例中，FPGA141与主机可以通过前述实施例二中的方式连接，即通过PCIe链路连接，同时还通过预留的管脚进行连接以传输例如升级指令以及用于表示工作状态的信息。在该实施例中，FPGA141通过加载存储在FPGA配置存储器142中的配置数据来执行实施例二、三中的FPGA141执行的操作。
FPGA板卡的具体结构可参见前述介绍，例如，可以是插入到PCIe插槽中PCIe板卡。
实施例五
基于上述各实施例，本实施例公开了一种主机设备15，该主机设备15可以是前述提到的计算设备或者其他进行数据处理的设备中的主机部分，主机设备15包括一个能够执行软件指令的处理器151(如CPU)以及存储器152，其中，存储器152可以包括非易失性存储器1521(如磁盘、闪存等)以及易失性存储器1522(如内存)，通过处理器151与存储器152的配合，处理器151可以执行存储在存储器中指令，并完成前述各实施例中主机执行的操作。
实施例六
基于上述各实施例，本实施例公开了一种电子设备16，该电子设备16包括实施例四所述的FPGA板卡以及实施例五所述的主机设备，该电子设备可以是前述提到的计算设备或者其他进行数据处理的设备。
实施例七
基于上述各实施例，本实施例公开了一种计算机存储介质，该存储介质存储有用于 处理器执行的多个指令，其中，这些指令为能够让处理器读取后执行前述各实施例中主机所执行的操作的指令。
基于上述各实施例，本实施例还公开了一种计算机存储介质，该存储介质存储有用于配置FPGA的配置数据，其中，该配置数据为能够让FPGA在加载后执行前述各实施例中FPGA所执行的操作的配置数据。
需要说明的是，本申请中的“第一”、“第二”、“第三”等修饰语仅用于对同一名词出现在不同场景时的使用进行区分，而不代表严格的顺序，也不代表与权利要求中的“第一”、“第二”等用语的含义相同。本领域普通技术人员可以理解实现上述实施例方法中的全部或部分流程，是可以通过计算机程序来指令相关的硬件来完成，所述的程序可存储于一计算机可读取存储介质中，该程序在执行时，可包括如上述各方法的实施例的流程。其中，所述的存储介质可为磁碟、光盘、只读存储记忆体(Read-Only Memory，ROM)或随机存储记忆体(Random Access Memory，RAM)等。
上举较佳实施例，对本发明的目的、技术方案和优点进行了进一步详细说明，所应理解的是，以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (24)

  1. 一种升级FPGA的方法，其特征在于，所述方法由主机以及FPGA配合执行，其中，所述主机与所述FPGA通过PCIe链路相连，所述FPGA与FPGA配置存储器相连，所述FPGA配置存储器中保存有所述FPGA升级所需的配置数据，所述方法包括：
    所述主机向所述FPGA下发升级指令；
    所述主机卸载所述FPGA对应的PCIe驱动程序，使所述PCIe链路的状态变为断开状态；
    所述主机在第一超时时间内持续检测所述PCIe链路的状态是否变成连接状态；
    如果检测到所述PCIe链路的状态变为所述连接状态，则重新加载所述PCIe驱动程序；
    所述方法还包括：
    所述FPGA在收到所述升级指令后，所述FPGA在第二超时时间内持续检测所述PCIe链路的状态是否变为断开状态，其中，所述断开状态为所述PCIe链路在所述主机卸载完成所述FPGA对应的PCIe驱动程序后的状态；
    如果在所述第二超时时间内检测到所述PCIe链路变为断开状态，所述FPGA从所述FPGA配置存储器中加载所述配置数据进行升级；
    升级完成后，所述FPGA通过跟所述主机协商以将所述PCIe链路的状态恢复为用于被所述主机检测到后重新加载所述PCIe驱动程序的连接状态。
  2. 如权利要求1所述的方法，其特征在于，所述方法还包括：
    所述主机在卸载所述PCIe驱动程序之前，暂停使用PCIe链路对FPGA进行访问的一个或多个应用程序。
  3. 如权利要求2所述的方法，其特征在于，所述方法还包括：所述主机在重新加载所述PCIe驱动程序之后，恢复所述一个或多个应用程序运行。
  4. 如权利要求1-3任一所述的方法，其特征在于，所述主机在第一超时时间内持续检测所述PCIe链路的状态是否变成连接状态包括：
    在所述第一超时时间内通过持续检测位于所述主机中的链路状态寄存器来持续检测所述PCIe链路是否变为所述连接状态。
  5. 如权利要求1-4任一所述的方法，其特征在于，所述FPGA在第二超时时间内持续检测所述PCIe链路的状态是否变为断开状态包括：
    所述FPGA在所述第二超时时间内通过持续检测位于所述FPGA中的链路状态寄存器来持续检测所述PCIe链路是否变为所述断开状态。
  6. 如权利要求1-5任一所述的方法，其特征在于，所述第一超时时间为预定的所述FPGA完成升级所需的时间。
  7. 如权利要求1-6任一所述的方法，其特征在于，所述第二超时时间为预定的所述主机从发出所述升级指令后到完成卸载所述PCIe驱动程序所需的时间。
  8. 如权利要求1-7任一所述的方法，其特征在于，所述FPGA位于PCIe插卡上，所述PCIe插卡安装在所述主机的PCIe扩展槽上。
  9. 一种升级FPGA的方法，其特征在于，由FPGA执行，所述FPGA与主机通过PCIe链路通信，所述FPGA还与FPGA配置存储器相连，所述FPGA配置存储器中保存有所述FPGA升级所需的配置数据，所述方法包括：
    接收所述主机下发的升级指令；
    在超时时间内持续检测所述PCIe链路的状态是否变为断开状态，其中，所述断开状态为所述PCIe链路在所述主机卸载完成所述FPGA对应的PCIe驱动程序后的状态；
    如果在所述超时时间内检测到所述PCIe链路变为断开状态，从所述FPGA配置存储器中加载所述配置数据进行升级；
    升级完成后，通过与所述FPGA协商以将所述PCIe链路的状态恢复为连接状态；所述连接状态用于被所述主机检测到后重新加载所述PCIe驱动程序。
  10. 如权利要求9所述的方法，其特征在于，所述断开状态为所述PCIe链路在所述主机先暂停一个或多个应用程序，再卸载完成所述FPGA对应的PCIe驱动程序后的状态，其中所述一个或多个应用程序为使用PCIe链路对FPGA进行访问的一个或多个应用程序。
  11. 如权利要求10所述的方法，其特征在于，所述连接状态还用于被所述主机检测到后在重新加载所述PCIe驱动程序后恢复所述一个或多个应用程序运行。
  12. 如权利要求9-11任一所述的方法，其特征在于，所述超时时间为预定的所述主机从发出所述升级指令后到完成卸载所述PCIe驱动程序所需的时间。
  13. 如权利要求9-12任一所述的方法，其特征在于：所述在超时时间内持续检测所述PCIe链路是否变为断开状态包括：
    在所述超时时间内通过持续检测位于所述FPGA中的链路状态寄存器来持续检测所述PCIe链路是否变为所述断开状态。
  14. 如权利要求9-13任一所述的方法，其特征在于，如果所述PCIe链路的状态在所述超时时间内未变为断开状态，则退出升级流程。
  15. 如权利要求9-14任一所述的方法，其特征在于，所述FPGA位于PCIe插卡上，所述PCIe插卡安装在所述主机的PCIe扩展槽上。
  16. 一种升级FPGA的方法，其特征在于，由主机执行，所述主机与所述FPGA通过PCIe链路相连，所述FPGA与FPGA配置存储器相连，所述FPGA配置存储器中保存有所述FPGA升级所需的配置数据，所述方法包括：
    所述主机向所述FPGA下发升级指令；
    卸载所述FPGA对应的PCIe驱动程序，使所述PCIe链路的状态变为断开状态；
    在第一超时时间内持续检测所述PCIe链路的状态是否变成连接状态；
    如果检测到所述PCIe链路的状态变为所述连接状态，则重新加载所述PCIe驱动程序；
    其中，所述升级指令为让所述FPGA收到后执行如下操作的指令：
    在第二超时时间内持续检测所述PCIe链路的状态是否变为所述断开状态，其中，所述断开状态为所述PCIe链路在所述主机卸载完成所述FPGA对应的PCIe驱动程序后的状态；
    如果在所述第二超时时间内检测到所述PCIe链路变为断开状态，从所述FPGA配置存储器中加载所述配置数据进行升级；
    升级完成后，通过跟所述主机协商以将所述PCIe链路的状态恢复为用于被所述主机检测到后重新加载所述PCIe驱动程序的连接状态。
  17. 如权利要求16所述的方法，其特征在于，还包括：
    在卸载所述PCIe驱动程序之前，暂停使用PCIe链路对FPGA进行访问的一个或多个应用程序。
  18. 如权利要求17所述的方法，其特征在于，还包括：在重新加载所述PCIe驱动程序之后，恢复所述一个或多个应用程序运行。
  19. 如权利要求16-18任一所述的方法，其特征在于，所述在超时时间内持续检测所述PCIe链路的状态是否变成连接状态包括：
    在所述超时时间内通过持续检测位于所述主机中的链路状态寄存器来持续检测所述PCIe链路是否变为所述连接状态。
  20. 如权利要求16-19任一所述的方法，其特征在于，所述超时时间为预定的所述FPGA完成升级所需的时间。
  21. 如权利要求16-20任一所述的方法，其特征在于，所述FPGA位于PCIe插卡上，所述PCIe插卡安装在所述主机的PCIe扩展槽上。
  22. 一种FPGA板卡，其特征在于，包括：FPGA以及FPGA配置存储器，所述FPGA通过加载存储在FPGA配置存储器中的配置数据来执行权9-权15任一所述的方法。
  23. 一种主机设备，其特征在于，包括：处理器以及存储器，其中，所述处理器用 于执行存储在所述存储器中的指令，来实现权利要求16-21任一所述的方法。
  24. 一种电子设备，其特征在于，包括如权利要求22所述的FPGA板卡以及如权利要求23所述的主机设备。
PCT/CN2019/123069 2018-12-05 2019-12-04 基于PCIe接口的FPGA升级方法 WO2020114431A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP19892179.3A EP3882763B1 (en) 2018-12-05 2019-12-04 Fpga upgrading method based on pcie interface
US17/339,299 US11500650B2 (en) 2018-12-05 2021-06-04 FPGA upgrade method based on PCIe interface

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201811480823.3A CN111273923B (zh) 2018-12-05 2018-12-05 基于PCIe接口的FPGA升级方法
CN201811480823.3 2018-12-05

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US17/339,299 Continuation US11500650B2 (en) 2018-12-05 2021-06-04 FPGA upgrade method based on PCIe interface

Publications (1)

Publication Number Publication Date
WO2020114431A1 true WO2020114431A1 (zh) 2020-06-11

Family

ID=70974981

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/123069 WO2020114431A1 (zh) 2018-12-05 2019-12-04 基于PCIe接口的FPGA升级方法

Country Status (4)

Country Link
US (1) US11500650B2 (zh)
EP (1) EP3882763B1 (zh)
CN (1) CN111273923B (zh)
WO (1) WO2020114431A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111984288A (zh) * 2020-07-29 2020-11-24 深圳市拔超科技有限公司 一种基于mcu和fpga的远程电子系统升级装置及方法

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111857303B (zh) * 2020-06-30 2022-05-17 浪潮电子信息产业股份有限公司 一种fpga复位方法、装置、系统和电子设备
CN111953753B (zh) * 2020-07-31 2023-07-21 西安广和通无线软件有限公司 通信设备连接方法、装置、计算机设备和存储介质
CN114253877B (zh) * 2020-09-25 2024-01-26 大唐移动通信设备有限公司 Liunx系统下的高速外围组件互联PCIE设备扫描方法及装置
CN112559419A (zh) * 2020-12-21 2021-03-26 厦门市美亚柏科信息股份有限公司 一种pcie存储模块的固件升级保护方法、装置
CN114172803B (zh) * 2021-10-12 2023-08-01 四川恒湾科技有限公司 基于以太网交换技术的多fpga版本控制和配置系统及方法
CN114461559A (zh) * 2021-12-17 2022-05-10 飞腾信息技术有限公司 热插拔方法、片上系统及计算机设备

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090119659A1 (en) * 2007-11-06 2009-05-07 Shanghai Mobilepeak Semiconductor Co., Ltd. Method of Computer Based Data Card Software Downloading and Updating
CN102053850A (zh) * 2010-12-17 2011-05-11 天津曙光计算机产业有限公司 一种在线升级fpga逻辑的方法
CN107038040A (zh) * 2016-11-01 2017-08-11 中国人民解放军国防科学技术大学 基于pcie的fpga更新系统及更新方法
CN107656776A (zh) * 2017-10-31 2018-02-02 郑州云海信息技术有限公司 一种fpga加速卡的固件更新方法、装置及介质
CN107797816A (zh) * 2017-09-15 2018-03-13 西南电子技术研究所（中国电子科技集团公司第十研究所） Fpga程序在线更新电路
CN108400899A (zh) * 2018-06-08 2018-08-14 山东超越数控电子股份有限公司 一种fpga的远程升级系统及方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012106912A1 (zh) * 2011-07-21 2012-08-16 华为技术有限公司 对芯片进行动态升级的方法、系统及基板管理控制器
CN103513994B (zh) * 2012-06-19 2017-10-20 记忆科技(深圳)有限公司 一种通过pcie 进行fpga 在线升级的方法和系统
US9658977B2 (en) * 2013-03-15 2017-05-23 Micron Technology, Inc. High speed, parallel configuration of multiple field programmable gate arrays
US9940123B1 (en) * 2015-12-29 2018-04-10 Amazon Technologies, Inc. Updating device code through a bus
US10860357B1 (en) * 2017-04-18 2020-12-08 Amazon Technologies, Inc. Secure reconfiguring programmable hardware with host logic comprising a static portion and a reconfigurable portion
US10880137B2 (en) * 2017-05-12 2020-12-29 Intel Corporation Bypassing equalization at lower data rates
US10031993B1 (en) * 2017-06-12 2018-07-24 Intel Corporation Application store model for dynamic reconfiguration of a field-programmable gate array (FPGA)
US11210084B2 (en) * 2018-03-09 2021-12-28 Samsung Electronics Co., Ltd. Integrated single FPGA and solid state disk controller

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090119659A1 (en) * 2007-11-06 2009-05-07 Shanghai Mobilepeak Semiconductor Co., Ltd. Method of Computer Based Data Card Software Downloading and Updating
CN102053850A (zh) * 2010-12-17 2011-05-11 天津曙光计算机产业有限公司 一种在线升级fpga逻辑的方法
CN107038040A (zh) * 2016-11-01 2017-08-11 中国人民解放军国防科学技术大学 基于pcie的fpga更新系统及更新方法
CN107797816A (zh) * 2017-09-15 2018-03-13 西南电子技术研究所（中国电子科技集团公司第十研究所） Fpga程序在线更新电路
CN107656776A (zh) * 2017-10-31 2018-02-02 郑州云海信息技术有限公司 一种fpga加速卡的固件更新方法、装置及介质
CN108400899A (zh) * 2018-06-08 2018-08-14 山东超越数控电子股份有限公司 一种fpga的远程升级系统及方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111984288A (zh) * 2020-07-29 2020-11-24 深圳市拔超科技有限公司 一种基于mcu和fpga的远程电子系统升级装置及方法
CN111984288B (zh) * 2020-07-29 2024-04-16 深圳市拔超科技股份有限公司 一种基于mcu和fpga的远程电子系统升级装置及方法

Also Published As

Publication number Publication date
EP3882763B1 (en) 2023-10-25
CN111273923B (zh) 2022-04-12
US11500650B2 (en) 2022-11-15
EP3882763A4 (en) 2022-01-05
US20210294615A1 (en) 2021-09-23
EP3882763A1 (en) 2021-09-22
CN111273923A (zh) 2020-06-12

Similar Documents

Publication Publication Date Title
WO2020114431A1 (zh) 基于PCIe接口的FPGA升级方法
KR101782246B1 (ko) 독립적으로 동작가능한 프로세서들 간에 에러 정보의 제어된 복구를 위한 방법들 및 장치들
CN106257417B (zh) 引导程序升级方法、嵌入式设备、控制设备及嵌入式系统
CN107209671B (zh) 计算机中启动操作的动态自动监测和控制
US9652216B2 (en) System and method for providing out-of-band software or firmware upgrades for a switching device
JP6064237B2 (ja) メモリデータを移行するための方法、コンピュータ、および装置
US9946553B2 (en) BMC firmware recovery
WO2018120213A1 (zh) 一种固件更新方法及控制器
WO2018095107A1 (zh) 一种bios程序的异常处理方法及装置
CN112947977B (zh) 一种软件在线升级方法及系统
TW200426571A (en) Policy-based response to system errors occurring during os runtime
JP2018116648A (ja) 情報処理装置、その制御方法、及びプログラム
KR20090120541A (ko) 운영체제(ｏｓ) 자동복구기능을 갖는 임베디드 시스템 및운영체제 자동복구 방법
JP5163744B2 (ja) 機能拡張装置、情報処理装置および制御方法
TWI786871B (zh) 電腦和系統啓動方法
KR101369430B1 (ko) 행 현상 관리 장치 및 방법
CN117289963A (zh) 在线更新服务器平台服务固件的目标区域的方法及设备
CN112052108A (zh) 并行处理设备
WO2011158367A1 (ja) 実行中のプログラムの更新技術
US20200026682A1 (en) Techniques of accessing serial console of bmc using host serial port
CN104268026A (zh) 嵌入式系统的监控管理方法和装置
JP2006106914A (ja) ファームウェアで動作する処理装置およびファームウェア更新方法
JP6424134B2 (ja) 計算機システム及び計算機システムの制御方法
TWI554876B (zh) 節點置換處理方法與使用其之伺服器系統
TWI742430B (zh) 自動回復基板管理控制器之韌體的方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19892179

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

ENP Entry into the national phase

Ref document number: 2019892179

Country of ref document: EP

Effective date: 20210616