WO2020113790A1 - 像素补偿电路及像素补偿方法 - Google Patents

像素补偿电路及像素补偿方法 Download PDF

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Publication number
WO2020113790A1
WO2020113790A1 PCT/CN2019/072213 CN2019072213W WO2020113790A1 WO 2020113790 A1 WO2020113790 A1 WO 2020113790A1 CN 2019072213 W CN2019072213 W CN 2019072213W WO 2020113790 A1 WO2020113790 A1 WO 2020113790A1
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Prior art keywords
transistor
drain
source
gate
level
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English (en)
French (fr)
Inventor
李骏
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to US16/489,440 priority Critical patent/US10878755B2/en
Publication of WO2020113790A1 publication Critical patent/WO2020113790A1/zh
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/027—Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements

Definitions

  • the present invention relates to the field of display technology, and in particular to a pixel compensation circuit of a pixel driving circuit.
  • Organic light emitting diode Organic Light Emitting Diode
  • OLED Organic Light Emitting Diode
  • TFT thin film transistor
  • AMOLED active matrix organic light-emitting diodes
  • the basic driving circuit 10 for driving AMOLED is composed of two thin film transistors (T1 and T2) and a storage capacitor Cst.
  • the thin film transistor T1 is a switching transistor, and the gate of the thin film transistor T1 is connected to the SCAN signal.
  • the source is connected to the data signal Data, and when the gate receives the high-level SCAN signal, the thin film transistor T1 turns on the data signal Data.
  • the thin film transistor T2 is a driving transistor, and the current supplied to the organic light emitting diode OLED is controlled by the thin film transistor T2.
  • the source of the thin film transistor T2 is connected to the voltage source VDD.
  • the gate of the thin film transistor T2 is connected to the drain of the thin film transistor T1.
  • the thin film transistor T1 turns on the data signal Data, and the thin film transistor T2 will also be turned on.
  • the current amplification factor, the value of k is determined by the characteristics of the thin film transistor T2 itself
  • Vth is the threshold voltage of the thin film transistor T2
  • Vgs is the voltage difference between the gate and source of the thin film transistor T2. Since the threshold voltage of the thin film transistor T2 is easy to drift, which makes the driving current of the organic light emitting diode OLED unstable, which affects the display quality of the OLED panel, a threshold voltage compensation circuit is needed to reduce the phenomenon of threshold voltage drift.
  • FIG. 2 shows a 7T1C pixel compensation circuit 20 that is currently common, and is composed of seven transistors T21-T27 and a storage capacitor Cst2.
  • the 7T1C pixel compensation circuit 20 is used to compensate the organic light emitting diode OLED, wherein the first transistor T21 is a driving transistor.
  • the gates of the second transistor T22, the third transistor T23, and the seventh transistor T27 are connected to the scan signal SCAN(n) of the current stage, and the gate of the fourth transistor T24 is connected to the scan signal SCAN(n-1) of the previous stage
  • the source of the fourth transistor T24 is connected to the source of the second transistor T22, and the drain of the fourth transistor T24 is connected to the source of the seventh transistor T27 and the low level Vi, respectively.
  • FIG. 3 is a timing diagram of the 7T1C pixel compensation circuit 20 in FIG.
  • the function of the 7T1C pixel compensation circuit 20 can be divided into a reset phase S1, a compensation phase S2, and a light-emitting phase S3.
  • the scanning signal SCAN(n-1) of the previous stage is low level
  • the scanning signal SCAN(n) and the light emitting signal EM of this stage are high level
  • the fourth transistor T24 is turned on, so that The gate of the first transistor T21 is reset to the low level Vi.
  • the light-emitting signal EM is also at a high level, while the scanning signal SCAN(n-1) at the previous stage becomes a high level, and the scanning signal SCAN(n) at this stage becomes a low level, Therefore, the third transistor T23 is turned on to connect the source of the first transistor T21 to the data signal Data. Since the gate and drain of the first transistor T21 are short-circuited at this time, the first transistor T21 forms a diode structure, so after the source of the first transistor is connected to the data signal Data, the gate of the first transistor T21 will be charged to The first potential Vdata-Vth, where Vdata is the level of the data signal Data, and Vth is the threshold voltage of the first transistor T21.
  • the level of the gate of the first transistor T21 will be equal to the voltage difference between the data signal Data and the threshold voltage of the first transistor.
  • the second transistor T22 and the seventh transistor T27 are also connected to the low-level scan signal SCAN(n), so the seventh transistor T27 is turned on to reset the anode of the organic light emitting diode OLED to the low level Vi.
  • ) 2 k(VDD-Vdata) 2
  • the current driving the organic light emitting diode OLED is independent of the threshold voltage Vth of the first transistor T21, the problem of poor display quality of the panel caused by the threshold voltage drift of the driving transistor can be avoided.
  • the above 7T1C pixel compensation circuit still has the problem of non-uniformity of sub-threshold voltage and leakage area. For example, when the display gray level of the pixel display electrode is zero, there is still current generated by the driving transistor, so there will be a current through the organic light emitting diode to make it emit light. The value is different from the expected value, causing the contrast of the display panel to deteriorate.
  • a pixel compensation circuit is needed to solve the problem that the leakage current of the driving transistor affects the display grayscale when the display grayscale is low, causing the contrast to deteriorate.
  • the invention provides a pixel compensation circuit, including an organic light emitting diode, a first transistor, a compensation transistor, a storage capacitor, a second transistor, a third transistor, and a seventh transistor.
  • the cathode of the organic light emitting diode is connected to the first reference level.
  • the source of the first transistor is connected to the high level and the data signal, and the drain of the first transistor is connected to the anode of the organic light emitting diode.
  • the source and gate of the compensation transistor are connected to the second reference level, and the drain of the compensation transistor is connected to the drain of the first transistor, so that the potential of the drain of the first transistor is equal to or less than The sum of the second reference level and the threshold voltage of the compensation transistor.
  • the storage capacitor is disposed between the high level and the gate of the first transistor.
  • the gate of the second transistor is connected to the current scan signal, the source of the second transistor is connected to the gate of the first transistor, and the drain of the second transistor is connected to the drain of the first transistor And the drain of the compensation transistor.
  • the gate of the third transistor is connected to the current scan signal, the source of the third transistor is connected to the data signal, and the drain of the third transistor is connected to the source of the first transistor .
  • the gate of the seventh transistor is connected to the current scan signal.
  • the second transistor When the current scan signal is at a low level, the second transistor is turned on, so that the gate and drain of the first transistor are short-circuited, and the third transistor is turned on to transmit the data signal to all The source of the first transistor, the seventh transistor is turned on to transfer the third reference level to the source of the first transistor.
  • the pixel compensation circuit includes a fourth transistor, the gate of which is connected to the scan signal of the previous stage, the source of which is connected to the gate of the first transistor, and the drain of which is connected to the third reference level, when When the scan signal of the previous stage is at a low level, the fourth transistor is turned on to transmit the third reference level to the gate of the first transistor, so that the level of the gate of the first transistor is reset To the third reference level.
  • the pixel compensation circuit includes a fifth transistor and a sixth transistor, the gates of the fifth transistor and the sixth transistor are connected to a light-emitting signal, and the source of the fifth transistor is connected to the first A drain of a transistor, a drain of the fifth transistor is connected to an anode of the organic light emitting diode, a source of the sixth transistor is connected to the high level, and a drain of the sixth transistor is connected to The source of the first transistor, when the light emitting signal is at a low level, the sixth transistor is turned on to transmit the high level to the source of the first transistor, so that the organic light emitting diode emits light .
  • the invention also provides a pixel compensation circuit, which includes an organic light emitting diode, a first transistor, a compensation transistor, a storage capacitor, and a second transistor.
  • the cathode of the organic light emitting diode is connected to the first reference level.
  • the source of the first transistor is connected to the high level and the data signal, and the drain of the first transistor is connected to the anode of the organic light emitting diode.
  • the source and gate of the compensation transistor are connected to the second reference level, and the drain of the compensation transistor is connected to the drain of the first transistor, so that the potential of the drain of the first transistor is equal to or less than The sum of the second reference level and the threshold voltage of the compensation transistor.
  • the storage capacitor is disposed between the high level and the gate of the first transistor.
  • the gate of the second transistor is connected to the current scan signal, the source of the second transistor is connected to the gate of the first transistor, and the drain of the second transistor is connected to the drain of the first transistor And the drain of the compensation transistor.
  • the pixel compensation circuit includes a third transistor whose gate is connected to the scan signal of the current stage, its source is connected to the data signal, and its drain is connected to the source of the first transistor, When the current scan signal is at a low level, the third transistor is turned on to transmit the data signal to the source of the first transistor.
  • the pixel compensation circuit includes a fourth transistor, the gate of which is connected to the scan signal of the previous stage, the source of which is connected to the gate of the first transistor, and the drain of which is connected to the third reference level, when When the scan signal of the previous stage is at a low level, the fourth transistor is turned on to transmit the third reference level to the gate of the first transistor, so that the level of the gate of the first transistor is reset To the third reference level.
  • the pixel compensation circuit includes a fifth transistor and a sixth transistor, the gates of the fifth transistor and the sixth transistor are connected to a light-emitting signal, and the source of the fifth transistor is connected to the first A drain of a transistor, a drain of the fifth transistor is connected to an anode of the organic light emitting diode, a source of the sixth transistor is connected to the high level, and a drain of the sixth transistor is connected to The source of the first transistor, when the light emitting signal is at a low level, the sixth transistor is turned on to transmit the high level to the source of the first transistor, so that the organic light emitting diode emits light .
  • the pixel compensation circuit includes a seventh transistor whose gate is connected to the scan signal of the current stage, and when the scan signal of the current stage is low, the seventh transistor turns on to turn the third transistor on The reference level is transferred to the source of the first transistor.
  • the invention also provides a pixel compensation method, which comprises connecting the cathode of the organic light emitting diode to the first reference level.
  • the source of the first transistor is connected to the high level and the data signal, and the drain of the first transistor is connected to the anode of the organic light emitting diode.
  • the storage capacitor is set between the high level and the gate of the first transistor.
  • the pixel compensation method provided by the present invention includes connecting the gate of the third transistor to the current scanning signal, connecting the source of the third transistor to the data signal, and connecting the third transistor The drain of is connected to the source of the first transistor.
  • the third transistor is turned on to transmit the data signal to the source of the first transistor.
  • the pixel compensation method provided by the present invention includes connecting the gate of the fourth transistor to the scan signal of the previous stage, connecting the source of the fourth transistor to the gate of the first transistor, and connecting the first The drains of the four transistors are connected to the third reference level, and when the scan signal of the previous stage is low, the fourth transistor is turned on to transmit the third reference level to the gate of the first transistor To reset the level of the gate of the first transistor to the third reference level.
  • the pixel compensation method provided by the present invention includes connecting the gates of the fifth transistor and the sixth transistor to a light-emitting signal, connecting the source of the fifth transistor to the drain of the first transistor, and connecting all the The drain of the fifth transistor is connected to the anode of the organic light emitting diode, the source of the sixth transistor is connected to the high level, and the drain of the sixth transistor is connected to the first transistor When the light-emitting signal is at a low level, the sixth transistor turns on and transmits the high level to the source of the first transistor, causing the organic light-emitting diode to emit light.
  • the pixel compensation method provided by the present invention includes connecting a gate of a seventh transistor to the scan signal of the current stage, when the scan signal of the current stage is low, the seventh transistor is turned on to turn the The third reference level is transferred to the source of the first transistor.
  • the advantage of the present invention is that the pixel compensation circuit and method of the present invention can improve the phenomenon of aging of the driving transistor and improve the uniformity of the driving transistor.
  • FIG. 1 shows a pixel driving circuit
  • FIG. 2 illustrates the existing 7T1C pixel compensation circuit
  • FIG. 3 is a timing diagram of a conventional 7T1C pixel compensation circuit
  • FIG. 5 illustrates the drain and gate test curves of the driving transistor in the existing 7T1C pixel compensation circuit
  • FIG. 6 illustrates the drain and gate test curves of the driving transistor in the 7T1C pixel compensation circuit of the present invention.
  • the pixel compensation circuit 40 includes a compensation transistor T40, seven transistors T41-T47, a storage capacitor Cst3, and an organic light emitting diode OLED, wherein the first transistor T41 is a driving transistor.
  • the source and gate of the compensation transistor T40 are connected to the reference level Vref, and the drain of the compensation transistor T40 is connected to the drain of the first transistor T41.
  • the source of the first transistor T41 is connected to the high level VDD through the sixth transistor T46, while the source of the first transistor T41 is connected to the data signal Data through the third transistor T43, and the gate of the first transistor T41 is connected to high through the storage capacitor Cst3 Level VDD, the drain of the first transistor T41 is connected to the reference level VSS through the fifth transistor T45.
  • the gates of the second transistor T42, the third transistor T43, and the seventh transistor T47 are connected to the scan signal SCAN(n) of this stage, the source of the third transistor T43 is connected to the Data signal, and the gate of the fourth transistor T44 is connected to Scan signal SCAN(n-1) of the previous level.
  • the source and drain of the second transistor T42 are respectively connected to the gate and drain of the first transistor T21, so when the scan signal SCAN(n) of this stage is at a low level, the gate and drain of the first transistor T21 The short circuit causes the first transistor T21 to operate in the form of a diode.
  • the source and drain of the third transistor T43 are connected to the data signal Data and the source of the first transistor T41 respectively. Therefore, when the scan signal SCAN(n) of the current stage is low, the data signal Data is transmitted to the first transistor The source of T41.
  • the source of the fourth transistor T44 is connected to the source of the second transistor T42, and the drain of the fourth transistor T44 is connected to the source of the seventh transistor T47 and the low level Vi, respectively. Therefore, in the reset phase, when the scan signal SCAN(n-1) of the previous stage is low, the gate of the first transistor T41 is reset to low Vi, and the anode of the organic light emitting diode OLED is connected to low Level Vi, so during the reset phase, the organic light emitting diode OLED will not emit light.
  • the reference level Vref is set between -20V and -30V, which is low
  • the level Vi is set between 6V and 10V. Therefore, the level of the drain of the first transistor T41 is approximately equal to or less than Vref+
  • the gates of the fifth transistor T45 and the sixth transistor T46 are connected to the light-emitting signal EM. Therefore, when the light-emitting signal EM is at a low level, the high-level VDD is transmitted to the organic through the sixth transistor T46, the first transistor T41, and the fifth transistor T45 The anode of the light emitting diode makes the organic light emitting diode OLED emit light.
  • the driving transistor ie, the first transistor T41
  • the first transistor T41 since the voltage difference between the gate and the drain of the first transistor T41 exceeds 30V, the driving transistor (ie, the first transistor T41) does not display when the gray scale is low Because the voltage difference between the gate and the drain is too small, the first transistor T41 is turned on, ensuring that the organic light emitting diode OLED does not emit light when the light emitting signal EM is at a high level.
  • FIG. 5 illustrates a test curve of the drain and gate of the driving transistor T21 in the existing 7T1C pixel compensation circuit (that is, as shown in FIG. 2).
  • FIG. 6 illustrates the drain and gate test curves of the driving transistor T41 in the 7T1C pixel compensation circuit of the present invention (ie, FIG. 4).
  • the horizontal axis of FIGS. 5 and 6 represents the magnitude of the gate voltage of the drive transistor, and the vertical axis represents the magnitude of the leakage current of the drive transistor.
  • the driving transistor T21 has poor uniformity due to transistor aging.
  • the gate of the driving transistor T21 is connected to the low level Vi, and the drain is connected to the compensation transistor T40 to connect a power equal to or less than Vref+
  • the voltage difference between the gate and drain of the driving transistor T41 exceeds 30V, which can effectively improve the phenomenon of transistor aging and improve the uniformity of the driving transistor.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
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Abstract

一种像素补偿电路（40）包含有机发光二极管（OLED）、第一晶体管（T41）、补偿晶体管（T40）、存储电容（Cst3）以及第二晶体管（T42）。所述有机发光二极管（OLED）的阴极连接至第一参考电平（VSS）。所述第一晶体管（T41）的源极连接至高电平（VDD）以及数据信号（DATA）。所述补偿晶体管（T40）的源极与栅极连接至第二参考电平（Vref），所述补偿晶体管（T40）的漏极连接至所述第一晶体管（T41）的漏极，使所述第一晶体管（T41）漏极的电位等于或小于所述第二参考电平（Vref）与所述补偿晶体管（T40）阈值电压的总和。所述存储电容（Cst3）设置于所述高电平（VDD）与所述第一晶体管（T41）的栅极之间。利用该像素补偿电路（40）可以改善驱动晶体管老化的现象，提升驱动晶体管的均匀度。

Description

像素补偿电路及像素补偿方法 技术领域
本发明涉及显示技术领域，尤其是涉及像素驱动电路的像素补偿电路。
 背景技术
有机发光二极管(Organic Light Emitting Diode, OLED)显示器具有色域广、对比度高、亮度高、反应快、耗能低、具柔软性等优点，因此逐渐成为显示领域发展的重点技术。因上述优点，与薄膜晶体管(Thin film transistor, TFT)显示器相比，OLED显示器更适合用于制备大尺寸、薄型、柔性、透明及双面显示的显示器。其中主动矩阵有机发光二极管(Active-Matrix Organic Light-Emitting Diode, AMOLED)相较于一般薄膜晶体管更具有厚度薄的优势，因此AMOLED成为有机发光二极管应用的重点技术。
如图1所示，驱动AMOLED的基础驱动电路10是由两个薄膜晶体管(T1与T2)及一个存储电容Cst所组成，薄膜晶体管T1为开关晶体管，薄膜晶体管T1的栅极接入SCAN信号，源极接入数据信号Data，当栅极接收到高电平的SCAN信号时，薄膜晶体管T1导通数据信号Data。薄膜晶体管T2为驱动晶体管，提供给有机发光二极管OLED的电流由薄膜晶体管T2控制，薄膜晶体管T2的源极接入电压源VDD，薄膜晶体管T2的栅极与薄膜晶体管T1的漏极相连，因此当薄膜晶体管T1导通数据信号Data，薄膜晶体管T2也将被导通，此时流经有机发光二极管OLED的电流I OLED大小为I OLED=k(Vgs-Vth) 2，其中k为薄膜晶体管T2的电流放大系数，k的数值由薄膜晶体管T2本身的特性决定，Vth为薄膜晶体管T2的阈值电压，Vgs为薄膜晶体管T2的栅极与源极之间的电压差。由于薄膜晶体管T2的阈值电压容易漂移使得有机发光二极管OLED的驱动电流不稳定而影响OLED面板的显示品质，因此需要阈值电压补偿电路来减少阈值电压飘移的现象。
图2所示为目前常见的7T1C像素补偿电路20，由7个晶体管T21-T27、一个存储电容Cst2组成。7T1C像素补偿电路20用于补偿有机发光二极管OLED，其中第一晶体管T21为驱动晶体管。第二晶体管T22、第三晶体管T23以及第七晶体管T27的栅极接入本级的扫描信号SCAN(n)，第四晶体管T24的栅极接入上一级的扫描信号SCAN(n-1)，第四晶体管T24的源极连接第二晶体管T22的源极，第四晶体管T24的漏极分别连接第七晶体管T27的源极与低电平Vi。
如图3所示，图3为图2中7T1C像素补偿电路20的时序图。7T1C像素补偿电路20的作用可分为复位阶段S1、补偿阶段S2与发光阶段S3。在复位阶段S1中，上一级的扫描信号SCAN(n-1)为低电平，本级的扫描信号SCAN(n)与发光信号EM为高电平，因此第四晶体管T24导通，使得第一晶体管T21的栅极复位为低电平Vi。
在电压补偿阶段S2中，发光信号EM一样为高电平，而上一级的扫描信号SCAN(n-1)变为高电平，本级的扫描信号SCAN(n)变为低电平，因此第三晶体管T23导通使第一晶体管T21的源极接入数据信号Data。由于此时第一晶体管T21的栅极和漏极短接，因此第一晶体管T21形成二极管结构，因此在第一晶体管的源极接入数据信号Data后，第一晶体管T21的栅极会充电至第一电位Vdata-Vth，其中Vdata为数据信号Data 的电平，Vth为第一晶体管T21的阈值电压。即第一晶体管T21的栅极的电平会等于数据信号Data与第一晶体管阈值电压之间的电压差。同时第二晶体管T22与第七晶体管T27也接入低电平的本级扫描信号SCAN(n)，因此第七晶体管T27导通使得有机发光二极管OLED的阳极复位至低电平Vi。
在发光阶段S3中，发光信号EM为低电平，上一级的扫描信号SCAN(n-1)与本级的扫描信号SCAN(n)皆为高电平，因此第二晶体管T22、第三晶体管T23、第四晶体管T24与第七晶体管T27皆为不导通，电压源VDD通过第一晶体管T21及第五晶体管T25传输到有机发光二极管OLED的阳极，此时通过有机发光二极管OLED的电流I OLED为：I OLED=k(VDD-(Vdata-|Vth|)-|Vth|) 2=k(VDD-Vdata) 2
技术问题
因此，驱动有机发光二极管OLED的电流虽然与第一晶体管T21的阈值电压Vth无关，可以避免驱动晶体管阈值电压漂移造成面板显示品质不良的问题。然而上述的7T1C像素补偿电路仍存在亚阈值电压与漏电区域不均匀的问题。比如在像素显示电极的显示灰阶为零时，驱动晶体管仍有电流产生，因此会有电流通过有机发光二极管使其发光，因此在像素显示低灰阶的情况下，会因为漏电流使得灰阶值与期望值不同，导致显示面板的对比度变差。
因此，需要一种像素补偿电路，来解决在低显示灰阶时，驱动晶体管的漏电流会影响显示灰阶，造成对比度变差的问题。
 技术解决方案
本发明提供一种像素补偿电路，包含有机发光二极管、第一晶体管、补偿晶体管、存储电容、第二晶体管、第三晶体管以及第七晶体管。所述有机发光二极管的阴极连接至第一参考电平。所述第一晶体管的源极连接至高电平以及数据信号，所述第一晶体管的漏极连接至所述有机发光二极管的阳极。所述补偿晶体管的源极与栅极连接至第二参考电平，所述补偿晶体管的漏极连接至所述第一晶体管的漏极，使所述第一晶体管漏极的电位等于或小于所述第二参考电平与所述补偿晶体管阈值电压的总和。所述存储电容设置于所述高电平与所述第一晶体管的栅极之间。所述第二晶体管的栅极连接本级扫描信号，所述第二晶体管的源极连接至所述第一晶体管的栅极，所述第二晶体管的漏极连接至所述第一晶体管的漏极与补偿晶体管的漏极。所述第三晶体管的栅极连接至所述本级扫描信号，所述第三晶体管的源极连接至所述数据信号，所述第三晶体管的漏极连接至所述第一晶体管的源极。所述第七晶体管的栅极连接至所述本级扫描信号。当所述本级扫描信号为低电平时，所述第二晶体管导通，使得所述第一晶体管的栅极与漏极短接，所述第三晶体管导通将所述数据信号传送至所述第一晶体管的源极，所述第七晶体管导通将所述第三参考电平传送至所述第一晶体管的源极。
较佳地，所述像素补偿电路包含第四晶体管，其栅极连接至上一级扫描信号，其源极连接至所述第一晶体管的栅极，其漏极连接至第三参考电平，当所述上一级扫描信号为低电平时，所述第四晶体管导通将所述第三参考电平传送至所述第一晶体管的栅极，使所述第一晶体管栅极的电平复位至所述第三参考电平。
较佳地，所述像素补偿电路包含第五晶体管及第六晶体管，所述第五晶体管及所述第六晶体管的栅极接入发光信号，所述第五晶体管的源极连接至所述第一晶体管的漏极，所述第五晶体管的漏极连接至所述有机发光二极管的阳极，所述第六晶体管的源极连接至所述高电平，所述第六晶体管的漏极连接至所述第一晶体管的源极，当所述发光信号为低电平时，所述第六晶体管导通将所述高电平传送至所述第一晶体管的源极，使所述有机发光二极管发光。
本发明还提供一种像素补偿电路，包含有机发光二极管、第一晶体管、补偿晶体管、存储电容以及第二晶体管。所述有机发光二极管的阴极连接至第一参考电平。所述第一晶体管的源极连接至高电平以及数据信号，所述第一晶体管的漏极连接至所述有机发光二极管的阳极。所述补偿晶体管的源极与栅极连接至第二参考电平，所述补偿晶体管的漏极连接至所述第一晶体管的漏极，使所述第一晶体管漏极的电位等于或小于所述第二参考电平与所述补偿晶体管阈值电压的总和。所述存储电容设置于所述高电平与所述第一晶体管的栅极之间。所述第二晶体管的栅极连接本级扫描信号，所述第二晶体管的源极连接至所述第一晶体管的栅极，所述第二晶体管的漏极连接至所述第一晶体管的漏极与补偿晶体管的漏极。
较佳地，所述像素补偿电路包含第三晶体管，其栅极连接至所述本级扫描信号，其源极连接至所述数据信号，其漏极连接至所述第一晶体管的源极，当所述本级扫描信号为低电平时，所述第三晶体管导通将所述数据信号传送至所述第一晶体管的源极。
较佳地，所述像素补偿电路包含第四晶体管，其栅极连接至上一级扫描信号，其源极连接至所述第一晶体管的栅极，其漏极连接至第三参考电平，当所述上一级扫描信号为低电平时，所述第四晶体管导通将所述第三参考电平传送至所述第一晶体管的栅极，使所述第一晶体管栅极的电平复位至所述第三参考电平。
较佳地，所述像素补偿电路包含第五晶体管及第六晶体管，所述第五晶体管及所述第六晶体管的栅极接入发光信号，所述第五晶体管的源极连接至所述第一晶体管的漏极，所述第五晶体管的漏极连接至所述有机发光二极管的阳极，所述第六晶体管的源极连接至所述高电平，所述第六晶体管的漏极连接至所述第一晶体管的源极，当所述发光信号为低电平时，所述第六晶体管导通将所述高电平传送至所述第一晶体管的源极，使所述有机发光二极管发光。
较佳地，所述像素补偿电路包含第七晶体管，其栅极连接至所述本级扫描信号，当所述本级扫描信号为低电平时，所述第七晶体管导通将所述第三参考电平传送至所述第一晶体管的源极。
本发明还提供一种像素补偿方法，包含将有机发光二极管的阴极连接至第一参考电平。将第一晶体管的源极连接至高电平以及数据信号，将所述第一晶体管的漏极连接至所述有机发光二极管的阳极。将补偿晶体管的源极与栅极连接至第二参考电平，将补偿晶体管的漏极连接至所述第一晶体管的漏极，使所述第一晶体管漏极的电位等于或小于所述第二参考电平与所述补偿晶体管阈值电压的总和。将存储电容设置于所述高电平与所述第一晶体管的栅极之间。以及将第二晶体管的栅极连接本级扫描信号，将所述第二晶体管的源极连接至所述第一晶体管的栅极，将所述第二晶体管的漏极连接至所述第一晶体管的漏极与补偿晶体管的漏极。其中当所述本级扫描信号为低电平时，所述第二晶体管导通，使得所述第一晶体管的栅极与漏极短接。
较佳地，本发明提供的像素补偿方法包含将第三晶体管的栅极连接至所述本级扫描信号，将所述第三晶体管的源极连接至所述数据信号，将所述第三晶体管的漏极连接至所述第一晶体管的源极，当所述本级扫描信号为低电平时，所述第三晶体管导通将所述数据信号传送至所述第一晶体管的源极。
较佳地，本发明提供的像素补偿方法包含将第四晶体管的栅极连接至上一级扫描信号，将所述第四晶体管的源极连接至所述第一晶体管的栅极，将所述第四晶体管的漏极连接至第三参考电平，当所述上一级扫描信号为低电平时，所述第四晶体管导通将所述第三参考电平传送至所述第一晶体管的栅极，使所述第一晶体管栅极的电平复位至所述第三参考电平。
较佳地，本发明提供的像素补偿方法包含将第五晶体管及第六晶体管的栅极接入发光信号，将所述第五晶体管的源极连接至所述第一晶体管的漏极，将所述第五晶体管的漏极连接至所述有机发光二极管的阳极，将所述第六晶体管的源极连接至所述高电平，将所述第六晶体管的漏极连接至所述第一晶体管的源极，当所述发光信号为低电平时，所述第六晶体管导通将所述高电平传送至所述第一晶体管的源极，使所述有机发光二极管发光。
较佳地，本发明提供的像素补偿方法包含将第七晶体管的栅极连接至所述本级扫描信号，当所述本级扫描信号为低电平时，所述第七晶体管导通将所述第三参考电平传送至所述第一晶体管的源极。
 有益效果
本发明的优点在于，利用本发明的像素补偿电路及方法，可以改善驱动晶体管老化的现象，提升驱动晶体管的均匀度。
 附图说明
图1绘示像素驱动电路；
图2绘示现有7T1C的像素补偿电路；
图3绘示现有7T1C的像素补偿电路的时序图；
图4绘示本发明7T1C的像素补偿电路；
图5绘示现有的7T1C像素补偿电路中驱动晶体管的漏极与栅极测试曲线；
图6绘示本发明7T1C像素补偿电路中驱动晶体管的漏极与栅极测试曲线。
 本发明的最佳实施方式
下面结合附图对本发明提供的显示面板及显示装置做详细说明。具体实施方式中的纵向、横向、上、下、左、右、前、后仅是为了便于描述各部件之间的相对关系，而非用来限定本发明的实施方式。显然，所描述的实施例仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参考图4，图4所示为本发明7T1C的像素补偿电路。像素补偿电路40包含一个补偿晶体管T40、七个晶体管T41-T47、一个存储电容Cst3以及一个有机发光二极管OLED，其中第一晶体管T41为驱动晶体管。
在本发明的像素补偿电路40中，补偿晶体管T40的源极与栅极连接至参考电平Vref，补偿晶体管T40的漏极连接至第一晶体管T41的漏极。第一晶体管T41的源极通过第六晶体管T46连接至高电平VDD，同时第一晶体管T41的源极通过第三晶体管T43连接至数据信号Data，第一晶体管T41的栅极通过存储电容Cst3连接至高电平VDD，第一晶体管T41的漏极通过第五晶体管T45连接至参考电平VSS。
第二晶体管T42、第三晶体管T43以及第七晶体管T47的栅极接入本级的扫描信号SCAN(n) ，第三晶体管T43的源极接入Data信号，第四晶体管T44的栅极接入上一级的扫描信号SCAN(n-1)。第二晶体管T42的源极与漏极分别连接到第一晶体管T21的栅极与漏极，因此当本级的扫描信号SCAN(n)为低电平时，第一晶体管T21的栅极与漏极会短接使得第一晶体管T21以二极管的形式运作。第三晶体管T43的源极与漏极分别连接到数据信号Data与第一晶体管T41的源极，因此当本级的扫描信号SCAN(n)为低电平时，数据信号Data会传送至第一晶体管T41的源极。
第四晶体管T44的源极连接第二晶体管T42的源极，第四晶体管T44的漏极分别连接第七晶体管T47的源极与低电平Vi。因此在复位阶段中，当上一级的扫描信号SCAN(n-1)为低电平时，第一晶体管T41的栅极会被复位为低电平Vi，同时有机发光二极管OLED的阳极连接低电平Vi，因此在复位阶段中，有机发光二极管OLED不会发光。与现有技术不同的是，由于补偿晶体管T40源极与栅极皆连接至参考电平Vref，在本发明较佳的实施例中，参考电平Vref设置于-20V至-30V之间，低电平Vi设置于6V至10V间。因此第一晶体管T41的漏极所连接的电平约等于或小于Vref+|Vth0|，其中Vth0为补偿晶体管T40的阈值电压，因此第一晶体管T41的栅极与漏极之间的电压差超过30V。
第五晶体管T45与第六晶体管T46的栅极连接发光信号EM，因此当发光信号EM为低电平时，高电平VDD会通过第六晶体管T46、第一晶体管T41与第五晶体管T45传送到有机发光二极管的阳极，使有机发光二极管OLED发光。通过本发明的像素补偿电路40，由于第一晶体管T41的栅极与漏极之间的电压差超过30V，因此在显示灰阶较低的情况下，驱动晶体管(即，第一晶体管T41)不会因为栅极与漏极之间的电压差太小使得第一晶体管T41导通，确保在发光信号EM为高电平时有机发光二极管OLED不会发光。
图5绘示现有(即图2所示)的7T1C像素补偿电路中驱动晶体管T21的漏极与栅极测试曲线。图6绘示本发明(即图4)的7T1C像素补偿电路中驱动晶体管T41的漏极与栅极测试曲线。其中图5与图6的横轴表示驱动晶体管的栅极电压大小，纵轴为驱动晶体管漏电流的大小。如图5所示，在现有的7T1C像素补偿电路中，驱动晶体管T21由于晶体管老化导致均匀性不佳。接着请参考图6，利用本发明的7T1C像素补偿电路，驱动晶体管T21的栅极接入低电平Vi、漏极通过与补偿晶体管T40相连而接入约等于或小于Vref+|Vth0|大小的电平，使得驱动晶体管T41栅极与漏极之间的电压差超过30V，如此一来可以有效改善晶体管老化的现象，提高驱动晶体管的均匀性。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (13)

  1. 一种像素补偿电路，包含：
    有机发光二极管，其阴极连接至第一参考电平；
    第一晶体管，其源极连接至高电平以及数据信号，其漏极连接至所述有机发光二极管的阳极；
    补偿晶体管，其源极与栅极连接至第二参考电平，其漏极连接至所述第一晶体管的漏极，使所述第一晶体管漏极的电位等于或小于所述第二参考电平与所述补偿晶体管阈值电压的总和；
    存储电容，设置于所述高电平与所述第一晶体管的栅极之间；
    第二晶体管，其栅极连接本级扫描信号，其源极连接至所述第一晶体管的栅极，其漏极连接至所述第一晶体管的漏极与补偿晶体管的漏极；
    第三晶体管，其栅极连接至所述本级扫描信号，其源极连接至所述数据信号，其漏极连接至所述第一晶体管的源极；以及
    第七晶体管，其栅极连接至所述本级扫描信号；
    其中当所述本级扫描信号为低电平时，所述第二晶体管导通，使得所述第一晶体管的栅极与漏极短接，所述第三晶体管导通将所述数据信号传送至所述第一晶体管的源极，所述第七晶体管导通将所述第三参考电平传送至所述第一晶体管的源极。
  2. 如权利要求1所述的像素补偿电路，其中所述像素补偿电路包含第四晶体管，其栅极连接至上一级扫描信号，其源极连接至所述第一晶体管的栅极，其漏极连接至第三参考电平，当所述上一级扫描信号为低电平时，所述第四晶体管导通将所述第三参考电平传送至所述第一晶体管的栅极，使所述第一晶体管栅极的电平复位至所述第三参考电平。
  3. 如权利要求1所述的像素补偿电路，其中所述像素补偿电路包含第五晶体管及第六晶体管，所述第五晶体管及所述第六晶体管的栅极接入发光信号，所述第五晶体管的源极连接至所述第一晶体管的漏极，所述第五晶体管的漏极连接至所述有机发光二极管的阳极，所述第六晶体管的源极连接至所述高电平，所述第六晶体管的漏极连接至所述第一晶体管的源极，当所述发光信号为低电平时，所述第六晶体管导通将所述高电平传送至所述第一晶体管的源极，使所述有机发光二极管发光。
  4. 一种像素补偿电路，包含：
    有机发光二极管，其阴极连接至第一参考电平；
    第一晶体管，其源极连接至高电平以及数据信号，其漏极连接至所述有机发光二极管的阳极；
    补偿晶体管，其源极与栅极连接至第二参考电平，其漏极连接至所述第一晶体管的漏极，使所述第一晶体管漏极的电位等于或小于所述第二参考电平与所述补偿晶体管阈值电压的总和；
    存储电容，设置于所述高电平与所述第一晶体管的栅极之间；以及
    第二晶体管，其栅极连接本级扫描信号，其源极连接至所述第一晶体管的栅极，其漏极连接至所述第一晶体管的漏极与补偿晶体管的漏极；
    其中当所述本级扫描信号为低电平时，所述第二晶体管导通，使得所述第一晶体管的栅极与漏极短接。
  5. 如权利要求4所述的像素补偿电路，其中所述像素补偿电路包含第三晶体管，其栅极连接至所述本级扫描信号，其源极连接至所述数据信号，其漏极连接至所述第一晶体管的源极，当所述本级扫描信号为低电平时，所述第三晶体管导通将所述数据信号传送至所述第一晶体管的源极。
  6. 如权利要求4所述的像素补偿电路，其中所述像素补偿电路包含第四晶体管，其栅极连接至上一级扫描信号，其源极连接至所述第一晶体管的栅极，其漏极连接至第三参考电平，当所述上一级扫描信号为低电平时，所述第四晶体管导通将所述第三参考电平传送至所述第一晶体管的栅极，使所述第一晶体管栅极的电平复位至所述第三参考电平。
  7. 如权利要求4所述的像素补偿电路，其中所述像素补偿电路包含第五晶体管及第六晶体管，所述第五晶体管及所述第六晶体管的栅极接入发光信号，所述第五晶体管的源极连接至所述第一晶体管的漏极，所述第五晶体管的漏极连接至所述有机发光二极管的阳极，所述第六晶体管的源极连接至所述高电平，所述第六晶体管的漏极连接至所述第一晶体管的源极，当所述发光信号为低电平时，所述第六晶体管导通将所述高电平传送至所述第一晶体管的源极，使所述有机发光二极管发光。
  8. 如权利要求6所述的像素补偿电路，其中所述像素补偿电路包含第七晶体管，其栅极连接至所述本级扫描信号，当所述本级扫描信号为低电平时，所述第七晶体管导通将所述第三参考电平传送至所述第一晶体管的源极。
  9. 一种像素补偿方法，包含：
    将有机发光二极管的阴极连接至第一参考电平；
    将第一晶体管的源极连接至高电平以及数据信号，将所述第一晶体管的漏极连接至所述有机发光二极管的阳极；
    将补偿晶体管的源极与栅极连接至第二参考电平，将补偿晶体管的漏极连接至所述第一晶体管的漏极，使所述第一晶体管漏极的电位等于或小于所述第二参考电平与所述补偿晶体管阈值电压的总和；
    将存储电容设置于所述高电平与所述第一晶体管的栅极之间；以及
    将第二晶体管的栅极连接本级扫描信号，将所述第二晶体管的源极连接至所述第一晶体管的栅极，将所述第二晶体管的漏极连接至所述第一晶体管的漏极与补偿晶体管的漏极；
    其中当所述本级扫描信号为低电平时，所述第二晶体管导通，使得所述第一晶体管的栅极与漏极短接。
  10. 如权利要求9所述的像素补偿方法，其包含将第三晶体管的栅极连接至所述本级扫描信号，将所述第三晶体管的源极连接至所述数据信号，将所述第三晶体管的漏极连接至所述第一晶体管的源极，当所述本级扫描信号为低电平时，所述第三晶体管导通将所述数据信号传送至所述第一晶体管的源极。
  11. 如权利要求9所述的像素补偿方法，其包含将第四晶体管的栅极连接至上一级扫描信号，将所述第四晶体管的源极连接至所述第一晶体管的栅极，将所述第四晶体管的漏极连接至第三参考电平，当所述上一级扫描信号为低电平时，所述第四晶体管导通将所述第三参考电平传送至所述第一晶体管的栅极，使所述第一晶体管栅极的电平复位至所述第三参考电平。
  12. 如权利要求9所述的像素补偿方法，其包含将第五晶体管及第六晶体管的栅极接入发光信号，将所述第五晶体管的源极连接至所述第一晶体管的漏极，将所述第五晶体管的漏极连接至所述有机发光二极管的阳极，将所述第六晶体管的源极连接至所述高电平，将所述第六晶体管的漏极连接至所述第一晶体管的源极，当所述发光信号为低电平时，所述第六晶体管导通将所述高电平传送至所述第一晶体管的源极，使所述有机发光二极管发光。
  13. 如权利要求11所述的像素补偿方法，其包含将第七晶体管的栅极连接至所述本级扫描信号，当所述本级扫描信号为低电平时，所述第七晶体管导通将所述第三参考电平传送至所述第一晶体管的源极。
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