WO2020110647A1

WO2020110647A1 - Electronic control unit

Info

Publication number: WO2020110647A1
Application number: PCT/JP2019/043643
Authority: WO
Inventors: 英斗塚越; 小林　徹; 村松　直樹
Original assignee: 株式会社ケーヒン
Priority date: 2018-11-26
Filing date: 2019-11-07
Publication date: 2020-06-04
Also published as: JP2020088603A

Abstract

As a time period included in a time period from releasement of a connection state in which a multiplexor (131a) is connected to signal lines (L1, L2, L3) until setting of a connection state in which the multiplexor (131a) becomes connected to the signal lines (L1, L2, L3) next time, an electronic control unit (1) sets a conversion halt time period for securing a return time for the charges of capacitors (C1, C2, C3) to return to charges corresponding to the voltages (Vin1, Vin2, Vin3) of analog signals inputted to the signal lines (L1, L2, L3) and for halting the operation of the A/D conversion of an A/D converter (131b).

Description

Electronic control unit

The present invention relates to a control device that controls electric parts of a vehicle, and particularly to an electronic control device that includes an analog/digital converter that converts an analog signal into a digital signal.

In recent years, various electric parts are mounted on vehicles such as automobiles, and in order to control such electric parts with high accuracy, analog signals from various sensors for detecting a physical quantity indicating an operating state of an internal combustion engine of the vehicle are transmitted. A control device equipped with an analog/digital converter (hereinafter, referred to as an A/D converter) that performs analog/digital conversion (hereinafter, referred to as A/D conversion) for converting to a digital signal has been used.

In such a control device, input voltages for a plurality of A/D conversion channels to which analog output voltages from various sensors, which are a plurality of analog signal sources, are correspondingly input are continuously A/D converted, It is required to quickly obtain the control data necessary for controlling the electrical parts such as the actuators to be controlled, but so-called crosstalk occurs in which this A/D conversion is affected by the previous A/D conversion. As a result, there is a tendency that an error occurs in the A/D conversion.

Under such circumstances, Patent Document 1 relates to a sampling device, and relates to channels CH-2 and CH-3 to which an analog voltage is input, a sample & hold unit 2 having a sampling capacitor Cs for detecting the analog voltage, and a channel. A multiplexer unit 1 for switching between the connection between the CH-2 and the sample & hold unit 2 and the connection between the channel CH-3 and the sample & hold unit 2, and the filter capacitor Cf is connected to the channel CH-3, A sampling device, which includes a dummy circuit (consisting of a resistor R2 and a capacitor Cf2) for setting the channel CH-2 to the same voltage as the channel CH-3, and the multiplexer unit 1 connects the sample & hold unit 2 to the channel CH-2. It discloses a configuration for connecting to channel CH-3 after connection.

Further, Patent Document 2 relates to an analog input module, in which an analog input is channel-input to a multiplexer 1 through a CR input filter 4, and an analog input of a channel selected by the multiplexer is converted through a buffer 2 into a digital amount by an A/D converter 3. In the output analog input module, the selection signal generation circuit 5 of the multiplexer discloses a configuration in which the “0” input channel is temporarily selected for each channel selection.

JP 2007-235244A JP, 2004-080281, A

However, according to the study by the present inventor, the configuration of Patent Document 1 intends to prevent erroneous detection of an analog voltage due to sampling by setting the same voltage on the channel CH-2 and the channel CH-3. However, since it is necessary to add a dummy circuit and the configuration becomes complicated, there is room for improvement.

Further, according to the study by the present inventor, in the configuration of Patent Document 2, by discharging the capacitor C of the filter, when the next analog input is selected, a conduction path is formed between the current input and the analog input selected immediately before. It is intended to prevent the capacitor from being recharged by preventing the voltage from being formed, but when the next analog input is selected, the voltage input to the multiplexer 1 is different from the value itself of the voltage of the analog input. There may be cases where the values differ, so there is room for improvement.

The present invention has been made through the above-described studies, and has a simple structure with no additional circuit provided, and an A/D with an appropriate accuracy obtained by performing A/D conversion with reduced error. An object of the present invention is to provide an electronic control device capable of performing control processing using converted data.

In order to achieve the above object, the present invention provides a plurality of signal lines including a first signal line to which a first analog signal, which is one of a plurality of analog signals, is input, and the plurality of signal lines. A multiplexer sequentially connected to each of the plurality of analog signals and sequentially inputting each of the plurality of analog signals, and each of the plurality of analog signals sequentially input to the multiplexer being input to a second signal line to sequentially output digital signals. An A/D converter for converting to, a first capacitor connected between the first signal line and a ground potential, and a second capacitor connected between the second signal line and a ground potential, Within a period from when the connection state in which the multiplexer is connected to the first signal line is released to when the connection state in which the multiplexer is next connected to the first signal line is set. As a period included, a recovery time is ensured for the charge of the first capacitor to return to the charge corresponding to the voltage of the first analog signal input to the first signal line, and the A/D A first aspect is that a predetermined conversion stop period for stopping the conversion operation of the converter is set.

In the present invention, in addition to the first aspect, the predetermined conversion stop period is set as a period following a time point at which each of the plurality of analog signals is sequentially converted into a digital signal by the A/D converter. This is referred to as a second aspect.

According to the electronic control device of the first aspect of the present invention, the multiplexer is connected to the first signal line after the connection state in which the multiplexer is connected to the first signal line is released. As a period included in the period until the connection state is set, a recovery time for recovering the charge of the first capacitor to the charge corresponding to the voltage of the first analog signal input to the first signal line. And a predetermined conversion stop period for stopping the conversion operation of the A/D converter is set. Therefore, the error is reduced by a simple configuration without an additional circuit. The control processing can be performed using the A/D conversion data with appropriate accuracy obtained by performing the /D conversion.

Further, according to the electronic control device of the second aspect of the present invention, the predetermined conversion stop period is a period subsequent to a time point at which each of the plurality of analog signals is sequentially converted into a digital signal by the A/D converter. Since it is set, it is possible to complete one cycle of the plurality of A/D conversions this time for a plurality of analog signals to obtain a set of A/D conversion values required for control of the electronic control unit. The required control can be appropriately executed by using the control data based on the /D conversion value.

FIG. 1 is a block diagram showing a configuration of an electronic control device according to an embodiment of the present invention. FIG. 2A is a time chart showing the flow of the A/D conversion process of the comparative example in the present embodiment. FIG. 2B is a time chart showing the flow of A/D conversion processing in this embodiment.

Hereinafter, the electronic control device according to the present embodiment will be described in detail with reference to the drawings as appropriate.

〔Constitution〕
First, the configuration of an electronic control device according to an embodiment of the present invention will be described with reference to FIG.

FIG. 1 is a block diagram showing the configuration of the electronic control device according to the present embodiment.

As shown in FIG. 1, the electronic control unit 1 according to the present embodiment is typically configured by an electronic control unit such as an ECU (Electronic Control Unit), and is an electric component of a vehicle such as a motorcycle or a four-wheeled vehicle. It is used as a control device for controlling the.

The electronic control unit 1 includes a first ECU terminal 11a, a second ECU terminal 11b, a third ECU terminal 11c, a fourth ECU terminal 11d, a fifth ECU terminal 11e, a sixth ECU terminal 11f, a seventh ECU terminal 11g, an eighth ECU terminal 11h, and an internal power supply circuit 12. , And a microcomputer 13.

One end of the first ECU terminal 11 a is connected to the positive electrode of the battery 21 installed outside the electronic control unit 1, and the other end of the first ECU terminal 11 a is connected to the internal power supply circuit 12.

One end of the second ECU terminal 11b is connected to the negative electrode of the battery 21, and the other end of the second ECU terminal 11b is connected to the ground potential.

One end of the third ECU terminal 11c is connected to a first analog signal source Vin1 which is a sensor such as a temperature sensor or a pressure sensor, and the other end of the third ECU terminal 11c is connected to the microcomputer 13 via a signal line L1. It is connected to the input channel CH1. Also, a protective resistance element R1 is connected to the signal line L1, and a noise removing capacitor C1 is connected between the signal line L1 between the resistance element R1 and the input channel CH1 and the ground potential. .. In the figure, a connection point between the capacitor C1 and the signal line L1 is indicated by a point P1.

One end of the fourth ECU terminal 11d is connected to a second analog signal source Vin2 which is a sensor such as a temperature sensor or a pressure sensor, and the other end of the fourth ECU terminal 11d is connected to the microcomputer 13 via a signal line L2. It is connected to the input channel CH2. Further, a protective resistance element R2 is connected to the signal line L2, and a noise removing capacitor C2 is connected between the signal line L2 and the ground potential between the resistance element R2 and the input channel CH2. .. In the figure, a connection point between the capacitor C2 and the signal line L2 is indicated by a point P2.

One end of the fifth ECU terminal 11e is connected to a third analog signal source Vin3 which is a sensor such as a temperature sensor and a pressure sensor, and the other end of the fifth ECU terminal 11e is connected to the microcomputer 13 via a signal line L3. It is connected to the input channel CH3. Further, a protective resistance element R3 is connected to the signal line L3, and a noise removing capacitor C3 is connected between the signal line L3 between the resistance element R3 and the input channel CH3 and the ground potential. .. In the figure, a connection point between the capacitor C3 and the signal line L3 is indicated by a point P3.

One end of the sixth ECU terminal 11f is connected to the crank pulse sensor 22, and the other end of the sixth ECU terminal 11f is connected to the control unit 132 in the microcomputer 13 via the input circuit 14.

One end of the seventh ECU terminal 11g is connected to the control unit 132 in the microcomputer 13 via the output circuit 15a, and the other end of the seventh ECU terminal 11g is installed outside the electronic control unit 1. It is connected to a first actuator 23a such as a motor.

One end of the eighth ECU terminal 11h is connected to the control unit 132 in the microcomputer 13 via the output circuit 15b, and the other end of the eighth ECU terminal 11h is installed outside the electronic control unit 1. It is connected to a second actuator 23b such as a motor.

The internal power supply circuit 12 uses the voltage supplied from the battery 21 via the first ECU terminal 11a to generate the reference voltage signal AVref.

The microcomputer 13 includes an A/D conversion unit 131, a control unit 132, and a timer 133.

The A/D conversion unit 131 includes a multiplexer (MPX) 131a, an A/D converter (ADC) 131b, and a 1/2 reference voltage generation circuit 131c.

The multiplexer (MPX) 131a has a terminal T1 connected to the input channel CH1, a terminal T2 connected to the input channel CH2, a terminal T3 connected to the input channel CH3, and a voltage half the reference voltage signal AVref. A terminal T4 to which a 1/2 reference voltage signal 1/2AVref which is a signal is supplied, a terminal T5 connected to the A/D converter 131b via a signal line L4, and a terminal T5 among the terminals T1 to T4. A switch element S for electrically switching the connected terminals is provided. A sampling capacitor CIN is connected between the signal line L4 and the ground potential. Note that the capacitance of the sampling capacitor CIN is set to be one digit to two digits smaller than the capacitance of each of the capacitors C1, C2, and C3. Further, in the figure, a connection point between the sampling capacitor CIN and the signal line L4 is indicated by a point P4.

The reference voltage signal AVref is supplied to the A/D converter 131b via the signal line L5. The A/D converter 131b uses the voltage of the reference voltage signal AVref as a reference voltage (reference voltage) to A/D-convert the voltage of the sampling capacitor CIN, and A/D-converts the voltage signal after A/D conversion. The converted data is output to the control unit 132.

The ½ reference voltage generation circuit 131c is connected to the signal line L6 branched from the signal line L5 to generate the ½ reference voltage signal ½AVref, and the generated ½ reference voltage signal ½AVref as a terminal. Supply to T4.

The control unit 132 generates a control signal for each of the first actuator 23a and the second actuator 23b based on the A/D conversion data output from the A/D converter 131b, and the generated control signal is the first actuator. By outputting to 23a and the 2nd actuator 23b, operation of the 1st actuator 23a and the 2nd actuator 23b is controlled.

The timer 133 executes a timekeeping process according to a control signal from the control unit 132, and outputs a signal that can be referred to when the control unit 132 instructs the A/D converter 131b about the timing regarding A/D conversion, for example. Output to.

The electronic control unit 1 having such a configuration has a simple configuration without providing an additional circuit, and outputs A/D conversion data with appropriate accuracy obtained by performing A/D conversion with reduced error. A control process is performed by using. The operation of the electronic control unit 1 when executing the A/D conversion process will be described below with reference to FIG.

[A/D conversion processing]
FIG. 2A is a time chart showing the flow of A/D conversion processing of the comparative example in the present embodiment, and FIG. 2B is a time chart showing the flow of A/D conversion processing in the present embodiment. In the following description, it is assumed that the capacitors C1, C2 and C3 are charged in the initial state so as to correspond to the same voltages as the input voltages VCH1, VCH2 and VCH3 to the input channels CH1, CH2 and CH3, respectively. To do. Here, the input voltage VCH1 is the voltage at which the output voltage of the first analog signal source Vin1 is applied to the capacitor C1 via the resistance element R1 at the point P1, and the input voltage VCH2 is the output voltage of the second analog signal source Vin2. Is the voltage applied to the capacitor C2 at the point P2 via the resistance element R2, and the input voltage VCH3 is the voltage at which the second analog signal source Vin13 output voltage is applied to the capacitor C3 at the point P3 via the resistance element R3. .

First, with reference to FIG. 2A, a flow of A/D conversion processing of a comparative example in the present embodiment will be described.

As shown in FIG. 2A, in the A/D conversion process of the comparative example, first, in the A/D conversion AD1, the multiplexer 131a controls the switch element S to connect the terminals T1 and T5, Select the input channel CH1. As a result, the sampling capacitor CIN is charged so that its voltage becomes equal to the input voltage VCH1 to the input channel CH1. Then, the A/D converter 131b uses the reference voltage signal AVref as the reference voltage to A/D-convert the voltage of the sampling capacitor CIN to generate A/D-converted data. As a result, the A/D conversion AD1 can A/D convert the input voltage VCH1 to the input channel CH1.

Next, in the A/D conversion AD2 subsequent to the A/D conversion AD1, the multiplexer 131a controls the switch element S to disconnect the terminals T1 and T5 from each other and disconnect the terminals T1 and T5 from each other. The input channel CH2 is selected by connecting to the terminal T5. As a result, the sampling capacitor CIN is charged so that its voltage becomes equal to the input voltage VCH2 to the input channel CH2, and the capacitor C1 is in the process of being charged so that its voltage approaches the applied voltage VCH1. .. Then, the A/D converter 131b uses the reference voltage signal AVref as the reference voltage to A/D-convert the voltage of the sampling capacitor CIN to generate A/D-converted data. As a result, the A/D conversion AD2 can A/D convert the input voltage VCH2 to the input channel CH2.

Next, in the A/D conversion AD3 subsequent to the A/D conversion AD2, the multiplexer 131a controls the switch element S to disconnect the terminals T2 and T5 from each other and disconnect the terminals T3 and T5 from each other. The input channel CH3 is selected by connecting to the terminal T5. As a result, the sampling capacitor CIN is charged so that its voltage becomes equal to the input voltage VCH3 to the input channel CH3, and the capacitor C2 is in the process of being charged so that its voltage approaches the applied voltage VCH2. . Then, the A/D converter 131b uses the reference voltage signal AVref as a reference voltage to A/D-convert the voltage of the sampling capacitor CIN at a predetermined sampling cycle to generate A/D-converted data. As a result, the A/D conversion AD3 can A/D convert the input voltage VCH3 to the input channel CH3. The A/D conversion data generated in the A/D conversions AD1 to AD3 are collectively input to the control unit 132 for each software reference period. In the A/D conversion AD1 after the second time, the multiplexer 131a controls the switch element S to disconnect (disconnect) the terminals T3 and T5 while connecting the terminals T1 and T5. By doing so, the input channel CH1 is selected. As a result, the sampling capacitor CIN is charged so that its voltage becomes equal to the input voltage VCH1 to the input channel CH1, and the capacitor C3 is charged so that its voltage approaches the input voltage VCH3 to the input channel CH3. It will be in the middle of the state. Thereafter, similarly, the second and subsequent A/D conversions AD2 and AD3 are executed.

Here, in such an A/D conversion process of the comparative example, a charge as an initial value exists in the sampling capacitor CIN after the first A/D conversion or thereafter, or a conversion of the A/D conversion immediately adjacent thereto is performed. Since the time may be insufficient and the electric charge at that time may remain, in the case of the A/D conversion AD1 after the first time, between the points P1 and P4 shown in FIG. 1, the A/D after the first time. A potential difference may occur between points P2 and P4 during conversion AD2 and between points P3 and P4 during the first and subsequent A/D conversions AD3. According to such a potential difference, between the capacitor C1 and the sampling capacitor CIN in the case of A/D conversion AD1, between the capacitor C2 and the sampling capacitor CIN in the case of A/D conversion AD2, A/ In the case of D conversion AD3, a current will flow between the capacitor C3 and the sampling capacitor CIN.

Therefore, in the case of A/D conversion AD1, the capacitor C1 and the sampling capacitor CIN are charged and discharged, and in the case of A/D conversion AD2, the capacitor C2 and the sampling capacitor CIN are charged and discharged, and the A/D conversion AD3. In this case, the capacitor C3 and the sampling capacitor CIN are charged and discharged. As a result, the voltage of the capacitor C1 and the voltage of the sampling capacitor CIN deviate from the voltage VCH1 of the input channel CH1 in the A/D conversion AD1, and the voltage of the capacitor C2 and the sampling capacitor CIN in the A/D conversion AD2. Of the input channel CH2 deviates from the voltage VCH2 of the input channel CH2, and in the case of A/D conversion AD3, the voltage of the capacitor C3 and the voltage of the sampling capacitor CIN tend to deviate from the voltage VCH3 of the input channel CH3. The phenomenon in which such voltage deviation occurs is called crosstalk, and causes an error in the A/D conversion processing.

Therefore, in the A/D conversion processing according to the present embodiment, the influence of crosstalk is suppressed as described below, and A/D conversion data with appropriate accuracy is generated. Hereinafter, the flow of the A/D conversion process in this embodiment will be described with reference to FIG. 2B.

As shown in FIG. 2B, in the A/D conversion process according to the present embodiment, first, the multiplexer 131a controls the switch element S in the A/D conversion AD1 (time length tAD1) in response to the conversion start trigger. The input channel CH1 is selected by connecting the terminal T1 and the terminal T5 with each other. As a result, the sampling capacitor CIN is charged so that its voltage becomes equal to the input voltage VCH1 to the input channel CH1. Then, the A/D converter 131b uses the reference voltage signal AVref as the reference voltage to A/D-convert the voltage of the sampling capacitor CIN to generate A/D-converted data. As a result, the A/D conversion AD1 can A/D convert the input voltage VCH1 to the input channel CH1.

Next, in the A/D conversion 1/2 Vcc (time length tVcc) following the A/D conversion AD1, the multiplexer 131a controls the switch element S to disconnect (disconnect) the terminals T1 and T5. The ½ reference voltage signal ½ AVref is selected by connecting the terminal T4 and the terminal T5 in this state. As a result, the sampling capacitor CIN is charged so that its voltage becomes equal to the ½ reference voltage signal ½ AVref, and the capacitor C1 follows the voltage at the point P1 to input to the input channel CH1. The battery is in the process of being charged so as to approach the voltage VCH1. Then, the A/D converter 131b performs A/D conversion on the voltage of the sampling capacitor CIN using the reference voltage signal AVref as the reference voltage. Although the A/D conversion 1/2Vcc following the A/D conversion AD1 has the advantages described below, it is not essential and can be omitted. If omitted, the A/D conversion AD1 as described below is executed subsequently to the A/D conversion AD1.

Next, in the A/D conversion AD2 (time length tAD2) subsequent to the A/D conversion 1/2 Vcc, the multiplexer 131a disconnects (disconnects) the terminals T4 and T5 by controlling the switch element S. The input channel CH2 is selected by connecting the terminal T2 and the terminal T5 while keeping the state. As a result, the sampling capacitor CIN is charged so that its voltage becomes equal to the input voltage VCH2 to the input channel CH2. At this time, the capacitor C1 remains in the state of being charged so that its voltage approaches the input voltage VCH1 to the input channel CH1. Further, when the terminal T2 and the terminal T5 are connected, the capacitor C2 has a charge due to being charged so as to have the same voltage as the input voltage VCH2 to the input channel CH2, and the sampling capacitor. Since electric charges due to the voltage of the 1/2 reference voltage signal 1/2 AVref may remain in CIN, a potential difference occurs between the points P2 and P4. According to such a potential difference, the capacitor C2 A current flows between the sampling capacitor CIN and the sampling capacitor CIN to charge and discharge them. As a result, the voltage of the capacitor C2 and the voltage of the sampling capacitor CIN tend to deviate from the voltage VCH2 of the input channel CH2 once. C2 is charged so that its voltage becomes the same voltage as the input voltage VCH2 to the input channel CH2, and the sampling capacitor CIN has a fixed value and is a predetermined positive value. Since it is discharged so as to have a voltage dropped from the voltage of 1/2 AVref, it takes time until the voltage of the sampling capacitor CIN is newly appropriately charged so as to be equal to the input voltage VCH2 to the input channel CH2. It becomes easier to assume, and the setting of the timing for starting the A/D conversion AD2 becomes simple and reliable. Then, the A/D converter 131b uses the reference voltage signal AVref as the reference voltage to A/D-convert the voltage of the sampling capacitor CIN to generate A/D-converted data. As a result, in the A/D conversion AD2, the input voltage VCH2 to the input channel CH2 can be more appropriately A/D converted. When the A/D conversion 1/2Vcc following the A/D conversion AD1 is not provided, the potential difference between the capacitor C2 and the sampling capacitor CIN when the terminal T2 and the terminal T5 are connected. May be larger, but since the capacitor C2 is charged so that its voltage becomes the same voltage as the input voltage VCH2 to the input channel CH2, when the capacitor C2 is not charged in this way Compared with the above, there is a significance that it is easier to estimate the time until the voltage of the sampling capacitor CIN is newly charged so that it becomes equal to the input voltage VCH2 to the input channel CH2.

Next, in the A/D conversion 1/2 Vcc (time length tVcc) following the A/D conversion AD2, the 1/2 reference voltage signal 1/ is obtained in the same manner as the A/D conversion 1/2 Vcc following the A/D conversion AD1. 2 AVref is A/D converted. At this time, the capacitor C1 remains in the state of being charged so that its voltage approaches the input voltage VCH1 to the input channel CH1, and the capacitor C2 follows its voltage at the point P2 to the input channel CH2. It is in the state of being charged so as to approach the input voltage VCH2. The A/D conversion 1/2Vcc following the A/D conversion AD2 is not essential as in the case of the A/D conversion 1/2Vcc following the A/D conversion AD1 and may be omitted. If such an omission is made, the A/D conversion AD3 as described below is executed subsequently to the A/D conversion AD2.

Next, in the A/D conversion AD3 (time length tAD3) subsequent to the A/D conversion 1/2 Vcc, the multiplexer 131a disconnects (disconnects) the terminals T4 and T5 by controlling the switch element S. The input channel CH3 is selected by connecting the terminal T3 and the terminal T5 while keeping the state. As a result, the sampling capacitor CIN is charged so that its voltage becomes equal to the input voltage VCH3 to the input channel CH3. At this time, the capacitor C1 remains in the state of being charged so that its voltage approaches the input voltage VCH1 to the input channel CH1, and the capacitor C2 charges so that its voltage approaches the input voltage VCH2 to the input channel CH2. It is still in the process of being processed. Further, when the terminals T3 and T5 are connected, the capacitor C3 has a charge due to being charged so as to have the same voltage as the input voltage VCH3 to the input channel CH3, and the sampling capacitor. Since electric charges due to the voltage of the 1/2 reference voltage signal 1/2AVref may remain in CIN, a potential difference occurs between the points P3 and P4. According to such a potential difference, the capacitor C3 A current flows between the sampling capacitor CIN and the sampling capacitor CIN to charge and discharge them. As a result, the voltage of the capacitor C2 and the voltage of the sampling capacitor CIN tend to deviate from the voltage VCH3 of the input channel CH3 once. C3 is charged so that its voltage becomes the same voltage as the input voltage VCH3 to the input channel CH3, and the sampling capacitor CIN has a fixed reference voltage value of 1/2 reference voltage signal. Since it is discharged so as to have a voltage lower than the voltage of 1/2 AVref, it takes time until the voltage of the sampling capacitor CIN is newly appropriately charged so as to be equal to the input voltage VCH3 to the input channel CH3. It becomes easier to assume, and the setting of the timing for starting the A/D conversion AD2 becomes simple and reliable. Then, the A/D converter 131b uses the reference voltage signal AVref as the reference voltage to A/D-convert the voltage of the sampling capacitor CIN to generate A/D-converted data. As a result, in the A/D conversion AD3, the input voltage VCH2 to the input channel CH3 can be more appropriately A/D converted. When the A/D conversion 1/2Vcc subsequent to the A/D conversion AD3 is not provided, the potential difference between the capacitor C2 and the sampling capacitor CIN when the terminal T3 and the terminal T5 are connected. May be larger, but since the capacitor C3 is charged so that its voltage becomes the same voltage as the input voltage VCH3 to the input channel CH3, the case where the capacitor C3 is not charged in this way Compared with the above, it becomes easier to estimate the time until the voltage of the sampling capacitor CIN is newly charged so as to become equal to the input voltage VCH3 to the input channel CH3, and the timing of starting the A/D conversion AD2 is set. Has the significance of being simple and reliable.

Next, during the conversion stop period (time length tS), the A/D conversion unit 131 uses the time measurement by the timer 133 to stop the A/D conversion operation during the predetermined conversion stop period. At this time, the multiplexer 131a may control the switch element S to connect any one of the terminals T1 to T4 and the terminal T5, or disconnect all the terminals T1 to T4 and the terminal T5. May be. Then, the A/D conversion unit 131 uses the timing at which the conversion stop period has elapsed based on the timing of the timer 133 as a conversion start trigger, A/D conversion AD1, A/D conversion 1/2 Vcc, A/D conversion AD2, The processes of A/D conversion 1/2 Vcc and A/D conversion AD3 are sequentially executed again. Here, the conversion stop period is for stopping the A/D conversion operation of the A/D converter 131b, but the charges of the capacitors C1, C2 and C3 correspond to the charges of the next A/D conversion. By the start, the time length is set to secure a recovery time necessary to recover the charges corresponding to the voltages VCH1, VCH2 and VCH3 of the input channels CH1, CH2 and CH3, respectively. More specifically, during the conversion stop period, the maximum values of the voltages VCH1, VCH2 and VCH3 of the input channels CH1, CH2 and CH3, the resistances of the corresponding protection resistive elements R1, R2 and R3, and the noise removing capacitor C1 are provided. , C2 and C3 considering the magnitude of the capacitance, etc., even if the capacitor takes the longest time to restore the charge, from the end of this A/D conversion to the start of the next A/D conversion By the time, that is, from the time when the corresponding terminal of the multiplexer 131a is disconnected to the time when it is next connected, the length of time that the charge can be returned to the charge amount corresponding to the input voltage to the input channel. It is set to a predetermined value that can secure the height. In other words, during the conversion stop period, for all of the capacitors C1, C2 and C3, the corresponding charges in the multiplexer 131a are transferred to the input channel from the non-connected state to the next connected state. Is set to a predetermined value capable of ensuring a time length capable of returning to the amount of electric charge corresponding to the input voltage. As a result, the capacitors C1, C2 and C3 are charged at the same voltage as the input voltages VCH1, VCH2 and VCH3 to the input channels CH1, CH2 and CH3, respectively, at the start of the corresponding A/D conversion. Therefore, it is possible to perform the A/D conversion each time in the charged state of the capacitors C1, C2 and C3 similar to the initial state in which they are started. Further, the conversion stop period has its time length tS and the time lengths of A/D conversion AD1, A/D conversion 1/2 Vcc, A/D conversion AD2, A/D conversion 1/2 Vcc, and A/D conversion AD3. The time length t1 that is a combination of tR and tR is set to a time length that is less than the software reference period t2. As a result, the control unit 132 can collectively acquire the A/D conversion data generated in the A/D conversions AD1 to AD3 for each software reference period t2. If necessary, the time length of the conversion stop period tS may be set only for the required one of the input channels CH1, CH2, and CH3. Further, if necessary, after the A/D conversion 1/2 Vcc, the conversion stop period may be divided and inserted continuously or instead of the respective A/D conversion 1/2 Vcc, and the conversion stop period may be dispersed. Good.

As is clear from the above description, in the electronic control unit 1 according to the present embodiment, the multiplexer 131a is not connected to the signal line L1 (L2, L3), and then the connection state is released. The charge of the capacitor C1 (C2, C3) is included in the period until the connection state connected next to L3) is set, and the charge of the capacitor C1 (C2, C3) of the analog signal input to the signal line L1 (L2, L3) A conversion stop period for ensuring a recovery time for recovering the charges corresponding to the voltage Vin1 (Vin2, Vin3) and for stopping the A/D conversion operation of the A/D converter 131b is set. With such a configuration, the input voltage that is not affected by the voltage of the sampling capacitor CIN by the previous A/D conversion process can be reliably set for this A/D conversion process. In this A/D conversion process, it is possible to reduce an error due to so-called crosstalk caused by the influence of the previous A/D conversion process. As a result, the control process can be performed using the A/D conversion data with appropriate accuracy obtained by performing the A/D conversion with reduced error, with a simple configuration without providing an additional circuit. it can.

Further, in the electronic control unit 1 in the present embodiment, the conversion stop period continues after the analog signals input to the input channels CH1, CH2, and CH3 are sequentially converted into digital signals by the A/D converter 131b. Since it is set as the period, the plurality of A/D conversions of the analog signals input to the input channels CH1, CH2, and CH3 are cycled to obtain the A/D conversion value necessary for the control of the electronic control unit 1. A complete set can be obtained, and required control can be appropriately executed using the control data based on the A/D conversion value.

It should be noted that the present invention is not limited to the type, shape, arrangement, number, etc. of the members described above in the embodiment, and appropriately replaces the constituent elements thereof with those having the same operational effect. Of course, it is possible to make appropriate changes without departing from the scope.

As described above, the present invention uses the A/D conversion data of appropriate accuracy obtained by performing the A/D conversion with a reduced error with a simple configuration without providing an additional circuit, It is possible to provide an electronic control device that can perform control processing, and it is expected that it can be widely applied to electronic control devices for vehicles such as motorcycles and four-wheeled vehicles because of its general-purpose universal character. It

Claims

A plurality of signal lines including a first signal line to which a first analog signal, which is one of the plurality of analog signals, is input;
A multiplexer that is sequentially connected to each of the plurality of signal lines and sequentially receives each of the plurality of analog signals,
An A/D converter that converts each of the plurality of analog signals sequentially input to the multiplexer into a second signal line and sequentially converts the analog signals into digital signals;
A first capacitor connected between the first signal line and the ground potential;
A second capacitor connected between the second signal line and the ground potential;
Equipped with
A period included in a period from the release of the connection state in which the multiplexer is connected to the first signal line to the setting of the connection state in which the multiplexer is next connected to the first signal line. As a result, the recovery time for the charge of the first capacitor to return to the charge corresponding to the voltage of the first analog signal input to the first signal line is secured, and the A/D converter An electronic control device, wherein a predetermined conversion stop period for stopping the conversion operation is set.
The electronic device according to claim 1, wherein the predetermined conversion stop period is set as a period subsequent to a time point at which each of the plurality of analog signals is sequentially converted into a digital signal by the A/D converter. Control device.