WO2020109924A1

WO2020109924A1 - Charge preamplifier device and radiation detecting apparatus comprising the device

Info

Publication number: WO2020109924A1
Application number: PCT/IB2019/059931
Authority: WO
Inventors: Filippo MELE; Giuseppe BERTUCCIO
Original assignee: Politecnico Di Milano
Priority date: 2018-11-29
Filing date: 2019-11-19
Publication date: 2020-06-04
Also published as: IT201800010671A1; EP3888243A1; JP2022509203A; US11604292B2; US20210396893A1; CN113261205A; CA3120666A1

Abstract

A charge preamplifier device (100) integrated in a chip (200) of semiconductive material comprising: an input (IN) for an input signal (ii_N) and an output (OUT) for an output signal (_VOUT); a substrate (202) of semiconductive material doped according to a first type of conductivity; an electrically insulating layer (204) placed on said substrate (202); a feedback capacitor (C_f) integrated in the chip (200) and comprising a first electrode (3) connected to the input (IN) and a second electrode (2) connected to the output (OUT). The second electrode (2) is formed by a doped conductive region (205) having a second type of conductivity, opposite to the first type of conductivity, and integrated in the substrate (202) in order to face the first electrode (3).

Description

"CHARGE PREAMPLIFIER DEVICE AND RADIATION DETECTING APPARATUS COMPRISING THE DEVICE"

k k k k k

D E S C R I P T I O N

TECHNICAL FIELD

The present invention refers to charge pream plifiers and radiation detecting apparatuses using a charge preamplifier.

STATE OF THE ART

As it is known, the charge amplifier (aka Charge Sensitive Amplifier, CSA) can be seen as a low noise operational amplifier having a feedback capacitance placed between the input and output of the amplifier itself, and such to operate as an in tegrator of a current signal at its input.

In conventional applications, the charge ampli fier is used in radiation measuring apparatuses and, consequently, is fed at the input by the cur rent signal generated by a radiation sensor. When a radiation passes through such sensor, it generates a charge signal proportional to the energy of the absorbed radiation. Typically, the charge amount generated by these sensors, for example a X ray sensor, is substantially limited (from hundreds to few tenths of thousands of electrons) . The charge preamplifier is fed, at the input, by this charge signal and converts it into a voltage signal. Such voltage signal is used by further processing stag es, in order to generate, for example, an energy spectrum and/or a time radiation distribution.

It is observed the noise generated by the oper^¬ ational amplifier is represented at the input as a voltage or current equivalent noise generator, gen erating an equivalent noise charge (ENC) , propor tional to the total capacitance at the input of the preamplifier comprising, among them, the input ca pacitance of the preamplifier C_±n itself.

In this regard, the document E. Gatti, P.F. Manfredi, M. Sampietro, V. Speziali, "Suboptimal filtering of l//-noise in detector charge measure ments", Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment"; volume 297, 3rd Edition 1990, pp . 467-478, ISSN 0168-9002, https://doi.org/10.1016/0168-9002 (90) 91331-5 de scribes some noise processing modes in charge de tectors .

Therefore, a decrease of the input capacitance

Ci_n of the charge preamplifier causes ENC to de crease of, and consequently an improvement of the signal/noise ratio and of the energy or time reso lution of the measuring apparatus.

In more sophisticated arrangements, the charge preamplifier is an integrated circuit (IC) made on a ("p" or "n" doped) semiconductor substrate. The preamplifier input is connected to the output of the sensor by a bonding wire. The bonding wire is connected to the input of the preamplifier by a conductive pad which should be sufficiently large to enable an interconnection operation, and to en sure a mechanical gripping strength. Therefore, such conductive pad is directly or indirectly con nected to the amplifier input by a specific metal lization, to which the first electrode of the feed back capacitance, formed by a conductive plate (of metal or polysilicon) is connected.

The second electrode of the feedback capaci tance consists of a second conductive plate placed in proximity of the first electrode and insulated from the substrate by an insulating film. The sec ond electrode is connected to the amplifier output by a metal connection, in order to obtain a capaci tive feedback. With reference to the prior art, this type of implementation is for example de scribed in document US-A-2018/0006613 (Figure 3) . In this conventional structure, the input pad forms also the first electrode of a parasitic ca pacitance C_pad at the input of the amplifier, the second electrode thereof consists of the substrate of the integrated circuit. Since the parasitic ca pacitance Cp_ad is a substantial component of the in put capacitance Ci_n of the preamplifier, it should be reduced in order to decrease the ENC.

The following documents of the prior art dis cuss the problems regarding the noise in CMOS tech nology charge preamplifiers:

- P. O'Connor, G. Gramegna, P. Rehak, F. Corsi, C. Marzocca, "CMOS Preamplifier with High Linearity and Ultra Low Noise for X-Ray Spectroscopy", IEEE Trans. Nucl. Sci., vol. 44, pp . 318-325, June 1997.

- G. Bertuccio, S. Caccia, "Noise Minimization of MOSFET Input Charge Amplifiers based on DN and Dm 1/f Models", IEEE Transactions on Nuclear Sci ence, Vol. 56, no. 3, 2009, pp . 1511-1520.

In addition, document US-A-2018/0006613 de scribes an integrated charge preamplifier having a conductive layer placed below the input pad (or part of it) for making one of the electrodes of the feedback capacitance. Such conductive layer is made above an insulating layer placed on the substrate in order to keep the electric insulation between the amplifier output and substrate.

The Applicant has observed that this solution does not seem satisfying with reference to a reduc tion of the parasitic capacitance and consequently of the equivalent noise charge, ENC.

Document US6484054 describes deep trench semi conductor capacitors having reverse bias diodes to be employed in implantable medical devices.

Document US4211941 describes an integrated cir cuit including low-leakage capacitance.

Document WO2012/156748 charge pre-amplifier in cluding a field effect transistor.

SUMMARY OF THE INVENTION

The present invention addresses the problem of providing a charge preamplifier, integrated in a chip of semi-conductive material, of a type differ ent from the known ones and which, according to a particular aspect, has a smaller input capacitance than the one obtainable according to the solutions of the above cited prior art, with a consequent im provement of the equivalent noise charge, ENC.

The Applicant has observed that a charge pream plifier integrated in a semi-conductive material chip, alternative to the known ones, can be ob- tained by making a feedback capacitor comprising an electrode, connected to the output of the preampli fier device, formed by a doped conductive well in tegrated in the substrate of the semi-conductive chip and having a conductivity opposite to the one of the substrate. This way of implementing an elec trode of the feedback capacitance enables to ob tain, if such well at least partially faces the in put pad, a charge preamplifier with an input capac itance less than the one of the prior art devices.

According to an aspect, the object of the pre sent invention is a charge preamplifier integrated in a chip of semi-conductive material as described in claim 1, and preferred embodiments thereof as defined in claims from 2 to 13.

The object of the present invention is also a detecting apparatus as described in claim 14 and a particular embodiment thereof defined in claim 15.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be particularly de scribed in the following in an exemplifying non limiting way, with reference to the attached draw ings, in which:

Figure 1 shows the circuital scheme of a charge preamplifier comprising an operational am- plifier and a feedback capacitance;

- Figure 2 shows a cross-section of a chip of semi-conductive material in which said charge pre amplifier is integrated;

- Figure 3 schematically shows a detecting ap paratus comprising a radiation sensor and said charge preamplifier.

DETAILED DESCRIPTION

Even though the invention can be implemented by several alternative variants and arrangements, some particular embodiments thereof are shown in the drawings and will be particularly described in the following. In the present description, analogous or identical elements or components will be indicated in the figures by the same identifying symbol.

Figure 1 shows, according to an example, the circuital scheme of a charge preamplifier 100 com prising an operational amplifier 1 and a feedback capacitor C_f. According to the shown example, the operational amplifier 1 is a low noise operational amplifier and comprises an input IN connected to a node N, in turn connected to an input terminal of the operational amplifier 1 (e.g.: a relative in verting terminal and an output terminal OUT.

The operational amplifier 1 has a further input terminal, for example the non-inverting terminal "+" connected to a ground terminal GND.

The feedback capacitor C_f is connected between the output terminal OUT and node N, connected to the input terminal IN. A feedback resistance R_f, parallel connected to the feedback capacitor, rep resents for example a discharge path of the feed back capacitor in a continuous resetting architec ture, or an equivalent resistance of a reset switch in pulsed resetting architectures. Particularly, the capacitor C_f has a first electrode 3 connected to the input IN by the node N and a second elec trode 2 connected to the output OUT.

The charge preamplifier 100 operates as an in tegrator capable of integrating a current signal ii_N present at the input IN by providing at the output OUT a voltage signal V_0UT having an amplitude pro portional to the electric charge at the input IN.

The charge preamplifier 100 can be implemented in a semi-conductive material chip according to the CMOS (Complementary - Metal-Oxide Semiconductor) technology, or according to the BiCMOS (Bipolar Complementary Metal-Oxide Semiconductor) technology or according to the BCD (bipolar-CMOS - DMOS) tech nology. The DMOS technology comprises the Vertical Diffused MOS (VDMOS) and Lateral Diffused MOS (LDMOS) technologies.

Figure 2 illustrates (with a vertical cross- section) a semi-conductive material chip 200 in which the amplifier 100 is integrated. Particular ly, in a first portion 201 of the chip 200 some components of the amplifier 100 are integrated (by the CMOS technology) , among them the feedback ca pacitor C_f is integrated. The amplifier 1 is inte grated in a second portion 209 of the chip 200, which is only schematically shown in Figure 2, be cause its implementation is known to a person skilled in the art and its implementation can vary according to the applicative requirements.

Chip 200 comprises a substrate 202 of semi- conductive material doped with a first type of con ductivity. For example, the substrate 202 is made of silicon, and is of a p-type conductivity and de fines an internal surface 203.

A well 205 doped with a second type of conduc tivity, opposed to the first type one, is made in side the silicon substrate 202. According to the example, a n-type well is made. The well 205 ex tends from the inside of the substrate 202 and de fines a further surface 211 placed at the level of the internal surface 203. The well 205, from a cir cuit point of view, is the second electrode 2 of the feedback capacitor C_f. The typical doping of the well 205 is comprised between 10¹⁴ and 10¹⁶ cnr³.

A layer 204 of an electrically insulating mate rial, such as for example a layer of S1O2, is placed on the internal surface 203 of the substrate 202 and on the well 205.

For example, the S1O2 layer 204 has a thickness comprised between 1 pm and 10 pm.

It is observed the well 205 is connected to the output OUT of the amplifier 1. Particularly, a first interconnecting layer 206 made of a metal ma terial or polysilicon is provided inside the S1O2 layer. The first interconnecting layer 206 has an end connected to a lateral zone 207 of the well 205 by a first contact element 208. Such first contact element 208 comprises, for example, an area doped with a material of a n-type conductivity, extending from the first interconnecting layer 206 to the well 205 along a direction normal to the one de fined by the semiconductor material substrate 202. Another end of the interconnecting layer 206 is connected to the output OUT of the preamplifier

100. Particularly, the first interconnecting layer 206 has a thread-like shape (with a square or rec tangular cross-section) and for example has a width (along the direction normal to the one defined by the plane of Figure 2) equal to about 1 pm.

In addition, the chip 200 is provided with a connecting conductive pad 212 at the input IN of the preamplifier 100 made in proximity of a surface of the chip 211 (e.g. a passivation layer) of the electrically insulating layer 204, opposite to the one contacting the semiconductive substrate 202. Such pad 212 is at least partially integrated in the insulating material layer 204 and is connected to a conductor 213, such as a bonding wire, which can form the input IN of the preamplifier. As an alternative to the bonding wire, a bump-bonding connection can be used. Preferably, the bonding wire 213 is welded to the pad 212.

The pad 212 comprises at least one first con ductive layer 214 (for example of metal) but which can be also provided, as shown in figure, with a second conductive layer 215 electrically connected to the first conductive layer 214 by second contact elements (known also as via-holes or holes) 216 made of conductive material, typically of metal.

The size of the second conductive layer 215 is identical or analogous to the one of the first con ductive layer 214 and faces this latter, inside the electrically insulating layer 204. Moreover, the pad 212 can comprise more than two conductive lay ers 215 facing and connected to each other.

Moreover, the chip 200 includes at least one second interconnecting layer 210 particularly made of a conductive material such as, for example, alu minum or another metal material. The second inter connecting layer 210 has a portion connected to the pad 212, and another portion connected to the in verting terminal of the amplifier 1. Particu larly, the second interconnecting layer 210 is con nected to the second conductive layer 215 (for ex ample, is part of the same metallization layer) and extends parallel to this latter but has a thread like shape analogous to the one of the first inter connecting layer 206.

The charge preamplifier 100 integrated in the chip 200 can be made, for example, in order to have a plan view analogous to the one shown in Figure 5 of document US2018-A-0006613.

In operation, the junction formed by the ip- type) semi-conductive substrate 202 and (n-type) well 205 is inversely biased under the condition in which the output voltage V_0UT remains greater than or equal to the voltage of the semi-conductive sub strate 202. In this inverted junction (illustra tively shown in Figure 2 by a p-n diode 219), due to the development of a depression area at the p-n junction, an electric insulation is formed between the substrate 202 and well 205 connected to the output OUT of the amplifier 1.

According to a preferred embodiment, the pad 212 faces the well 205 and extends parallel to such well. Advantageously, the well 205 defines a sur face 211 larger than or equal to the area of the orthogonal projection on the substrate 202 of the pad 212. Particularly, the dimensions of the well 205 are equal to or slightly greater than the ones of the pad 212 e.g., for example, than the ones of the first conductive layer 214. In other words, the well 205 includes the projection area of the pad 212 on the substrate 202. The pad 212 is spaced from the well 205 and is separated from the well itself by the material of the electrically insulat ing layer 204 forming a dielectric material. Ac cording to this preferred embodiment, the feedback capacitor C_f is formed by the first electrode 3

(made by the pad 212), by the second electrode 2 (made by the well 205) , and by the portion of the electrically insulating layer 204 interposed be tween them.

Preferably, the values of the feedback capaci tance C_f range for example from IfF and to lOpF.

For example, the distance between the well 205 and a lower face of the pad 212 is comprised be tween 1 pm and 10 pm.

It is observed the above described feedback ca pacitor C_f has a capacitance (also indicated by C_f) including a capacitive component Cl (schematically shown in Figure 2 by a capacitor Cl) which is pro portional to the pad 212 area and is generated by the orthogonal component of the electric field pre sent between the pad 212 and the well 205.

According to a particular embodiment, the well 205 is made in the substrate 202 so that it extends (as also shown in Figure 2) besides the orthogonal projection of the pad 212 on the substrate 202 it^¬ self, with an area sufficient to intercept the edge electric field lines which, originating from the pad 212 edge, form a perimetral component of the parasitic capacitance of the pad 212.

Consequently, the capacitance of the feedback capacitor C_f includes also a second component C2 (illustratively indicated in Figure 2 by a capaci tor C2) proportional to the pad 212 perimeter and generated by the edge component of the electric field present between the pad 212 and well 205. Therefore, in this case, the feedback capacitor C_f has a capacitance given by summing the first compo nent Cl to the second component C2.

Therefore, while in a charge preamplifier made according to the traditional techniques the capaci tance associated to the input pad is a parasitic capacitance causing an equivalent noise charge, in the above given description the capacitance associ ated to the pad 212 is used for obtaining the feed capacitance C_f.

It is observed the embodiment hereinbefore de scribed with reference to Figures 1 and 2 is also advantageous with respect to the one implemented in the device of document US2018-A-0006613. Indeed, as hereinbefore discussed, the device of document US2018-A-0006613 has a conductive layer placed be low the input pad (or part of it) for obtaining the feedback capacitance. Such conductive layer is made above an insulating layer placed above or made in side the chip substrate, in order to keep the elec- trie insulation between the output of the amplifier and the substrate. The main disadvantage of this configuration of the prior art consists of deposit ing the insulating layer and conductive layer above the substrate, this determines a higher feedback capacitance than the parasitic capacitance generat ed by the pad in the conventional devices.

Indeed, the capacitance is inversely propor tional to the distance between the conductive plates containing the electric field and, in the configuration shown in document US2018-A-0006613, the presence of the insulating layer and conductive layer, cause an unavoidable reduction of such dis tance, and a conseguent increase of the pad para sitic capacitance (converted into a feedback capac itance) and therefore an increase of the total ca pacitance at the input node of the preamplifier.

On the contrary, in the described solution re garding Figures 1 and 2, the pad 212 parasitic ca pacitance is not increased since the arrangement of the well 205 prevents the two electrodes 2 and 3 enclosing the electric field from approaching each other. This enables to minimize the input capaci tance of the amplifier 1 with a consequent improve ment of the performance.

In addition, it is observed the herein de- scribed solution, for the same dimensions of the pad, enables to obtain values of the feedback ca pacitance C_f less than the ones obtainable according to the above discussed prior art document. Since the transform gain of the preamplifier 100, defined as the ratio of the charged injected at the input IN to the voltage V_0UT at the output OUT, is in versely proportional to the feedback capacitance C_f, the decrease of the capacitance C_f entails an in crease of such gain, enabling a more substantial decrease of the noise generated by the following stages of the signal processing chain.

A further advantage offered by the present so lution is the possibility, for the same feedback capacitance, to have an input pad 212 larger than the ones of the above given document, consequently increasing the reliability of the connection of the bonding wire 213 to the pad 212, and the mechanical resistance of the pad itself.

The Applicant performed simulations of the charge preamplifier 100 made according to what is described with reference to the chip 200. Such op erative simulations, performed by CAD and by numer ically extracting the values of the parasitic ca pacitance by the Cadence "QRC Field Solver" soft- ware (electromagnetic simulation of the electric field on a circuit made by the technology CMOS 0.35 pm) , have shown a reduction of the total capaci tance (in some cases, to 40%) of a standard pad of lOOxlOOpm, with respect to the solution introduced in the above indicated prior art document.

It is observed the charge preamplifier 100 can be made by a semi-conductive material chip 200 hav ing a n-type substrate 202, in other words having a conductivity opposite to the one above described with reference to Figure 2. In this case, the n- type substrate 202 is, in operation, biased to the higher voltage of the chip 200. According to this implementation, the well 205 is made by a p-type doping and has a position and functionality identi cal to the ones described with reference to the n- type well. The electric contact between the p-type well 205 and the second interconnecting layer 210 can be made by the first contact element 208 which comprises, for example, a doped material and with a p-type conductivity. In this case, the electric in sulation between the p-type well 205 and n-type substrate 202 is kept provided that the n-type sub strate 202 is biased at a higher voltage than the one of the p-type well. Moreover, a first possible variant in addition to the one hereinbefore described with reference to Figure 2, refers to the fact the well 205, facing the pad 212, has an area of the surface 211 less than the pad 212 area. In other words, the well 205 is included in the projection area of the pad 212 on the substrate 202, however it occupies just a portion. This solution enables to obtain a feedback capacitance C_f equal to fractions of the pad 212 parasitic capacitance.

According to a second variant, it is possible to provide the well 205 completely or partially outside the projection area on the substrate 202 of the pad 212. In this case, the well 205 is made in order to (at least partially) face the second in terconnecting layer 210, which in turn forms the first electrode 3 of the feedback capacitor C_f. Such second variant can be used, for example, if the de sired feedback capacitance C_f has the same value of the parasitic capacitance present in the second in terconnecting layer 210 (e.g. having a value not greater than 2fF) .

Figure 3 shows a detecting apparatus 300 com prising a radiation sensor 301 (RAD-DET) and the charge preamplifier 100. A sensor output 302 of the radiation sensor 301 is connected to the input IN of the charge preamplifier 100 and consequently is connected to the bonding wire 213 shown in Figure

2.

The radiation sensor 301, if hit by an electro magnetic radiation, generates a charge signal S_CH proportional to the energy of the absorbed radia tion. The charge preamplifier 100 receives, at the input IN, this charge signal S_CH and converts it in to a voltage signal V_0UT. Such voltage signal V_0UT can be used by further processing stages in order to generate, for example, an energy spectrum and/or a radiation time distribution.

As an example, the radiation sensor 301 can be a detector of the Semiconductor (or Silicon) Drift Detector (SDD) type or of the Pixel Detector type. Such types of detectors require charge preamplifi ers having a very low input capacitance in order to have the greatest performance in terms of sig^¬ nal/noise ratio, response speed and time stability. Typically, the charge amount generated by the de tectors, for example for X or gamma rays, is ex tremely limited (from few hundreds to few tenths of thousands of electrons) . The hereinbefore described charge preamplifier 100 is particularly adapted to be used in the detecting apparatus 200 due to the offered performance enabling to increase the energy or time resolution of the detecting apparatus it self.

The detecting apparatus 300 can be used for scientific type applications such as for example: nuclear physics and particles instrumentation (syn chrotrons, accelerators, etc.); astrophysics in strumentation; medical and chemical instrumentation for radiographs and spectroscopies. Further, the detecting apparatus 300 can be used for industrial- type applications such as, for example: controlling the manufacturing of food for identifying contami nants; safety and control for the detection of ex plosives and explosive precursors; analysis of ma terials by X-Ray Fluorescence (XRF) .

It is well to remember the charge preamplifier 100 enables, contrary to the prior art, to increase the available area on the pad 212 for connecting it to the bonding wire, enabling also connections formed by plural bonding wires, and does not only increase the reliability and lifetime of the de tecting apparatus 300 but also enables it to oper ate in environments subjected to strong mechanical vibrations. Such improvement is particularly useful in astrophysics and space applications, where the step of launching satellites and probes, and possi bly of landing rovers, subjects the scientific in strumentation to strong vibrations and mechanical stresses .

It is observed, as partially already said, that the described charge preamplifier 100 enables to obtain the following advantages:

reduction of the equivalent noise charge (ENC) of the preamplifier 100, as a consequence of the decrease of the input capacitance C_±n, and a consequent improvement of the energy or time reso^¬ lution of the measuring system in which the pream plifier is inserted;

- an increase of the feedback loop gain of the preamplifier 100 and consequently an increase of the time stability of the transformation gain;

an increase, for the same feedback capaci tance C_f, of the response speed of the preamplifier 100 for reducing the ascent/descent times of the preamplifier itself as a response to an input sig nal;

- an increase, for the same dimensions of the input pad 212, of the closed loop transformation gain of the preamplifier 100 and a consequent de- crease of the noise produced by the following stag es of the processing chain;

an increase, for the same feedback capaci tance C_f, of the area or number of metallizations of the input pad 212 and consequently an increase of the reliability of the bonding wire 212 fixed to the pad 212 and an increase of the mechanical strength of the pad itself;

- a decrease of the noise, through the parasit ic capacitance of the pad 212 towards the substrate 212, injected by the voltage fluctuations of the substrate itself towards the input IN of the pream plifier 100, due to the shielding offered by the well 205, piloted by the low output impedance of the amplifier 1.

List of the numbers in the drawings

- charge preamplifier 100

- operational amplifier 1

- feedback capacitor C_f

- input IN

- node N

- inverting terminal

- output terminal OUT

- non-inverting terminal "+"

- ground terminal GND - feedback resistor R_f

- second electrode 2

- first electrode 3

- current signal ii_N

- voltage signal VOUT

- semi-conductive material chip 200

- first portion 201

- second portion 209

- semi-conductive material substrate 202

- internal surface 203

- well 205

- electrically insulating material layer 204

- first interconnecting layer 206

- lateral zone 207

- first contact element 208

- second interconnecting layer 210

- further surface 211

- conductive pad 212

- conductor 213

- first conductive layer 214

- second conductive layer 215

- second contact elements 216

- surface of the chip 217

- diode 219

- detecting apparatus 300 - radiation sensor 301

- sensor output 302

Claims

1. Charge preamplifier device (100) integrated in a chip of semiconductive material (200) compris ing :

an input (IN) for an input signal (im) and an output (OUT) for an output signal (V_OUT) ;

a substrate (202) of semiconductive material doped according to a first type of conductivity; an electrically insulating layer (204) placed on said substrate (202);

a feedback capacitor (C_f) integrated in the chip (200) and comprising a first electrode (3) connect^¬ ed to the input (IN) and a second electrode (2) connected to the output (OUT) ,

characterized in that the second electrode (2) is formed by a doped conductive region (205) having a second type of conductivity, opposite to the first type of conductivity, and integrated in the substrate (202) in order to face the first elec^¬ trode ( 3 ) .

2. Device (100) according to claim 1, wherein the first electrode (3) comprises a pad (212) con nected to the input (IT) and integrated in said electrically insulating layer (204); said pad fac ing the doped conductive region (205) and being separated from the doped conductive region (205) by an interposed portion of said electrically insulat ing layer.

3. Device (100) according to claim 2, wherein the doped conductive region (205) is made in the substrate (202) in order to include a projection area defined by an orthogonal projection of the pad (212) on the substrate (202) and in order to extend besides said projection area.

4. Device (100) according to claim 1, further comprising: an operational amplifier (1) integrated in the chip of semiconductive material (200) and having: an output terminal connected to said output (OUT), a first input terminal ("-") electrically connected to the first electrode (3) and a second input terminal ("+") .

5. Device (100) according to claim 1, further comprising :

a first interconnecting layer (206) integrated in said electrically insulating layer (204) and having a first portion connected to the doped con ductive region (205) and a second portion connected to said output (OUT) ;

a first electric contact element (208) inter posed between said first portion of the first in- terconnecting layer (206) and the doped conductive region (205) .

6. Device (100) according to claims 2 and 4, further comprising: a second interconnecting layer (210) integrated in said electrically insulating layer (204) and having a portion connected to the pad (212) and a further portion connected to the first input terminal ("-") of the operational am plifier ( 1 ) .

7. Device (100) according to claim 2, wherein the pad (212) comprises at least one first conduc tive layer (214) and said input (IN) is made by a bonding wire (213) or by a bump-bonding fixed to said first conductive layer.

8. Device (100) according to claim 7, wherein the pad (212) further comprises:

a second conductive layer (215) integrated in the electrically insulating layer (204) in order to face the first conductive layer;

at least one second electric contact element (216) connecting the first conductive layer (214) to the second conductive layer (215) .

9. Device (100) according to claim 1, wherein said feedback capacitor (C_f) has a capacitance value comprised between IfF - lOpF.

10. Device (100) according to claim 1, said am plifier is made according to one of the technolo gies selected among: CMOS technology, BiCMOS tech nology, BCD technology.

11. Device (100) according to claim 2, made so that a distance from said pad (212) to said doped conductive region (205) evaluated according to a direction orthogonal to the substrate (202) is com prised between 1 pm and 10 pm.

12. Device (100) according to claim 2, wherein the doped conductive region (205) has a respective surface (211) facing the pad (212) having an area smaller than a corresponding area of the pad (212) .

13. Device (100) according to claim 4, wherein the doped conductive region (205) is made in the substrate (202) in order to face at least partially an interconnecting layer (210) integrated in said electrically insulating layer (204) and having a portion connected to the input (IN) of the device and a further portion connected to the first input terminal ("-") of the operational amplifier (1) .

14. Sensing apparatus (300), comprising:

a radiation sensor (301) configured to convert an electromagnetic radiation into an electric charge signal (SCH) to be supplied to an associated output of the radiation sensor;

a charge preamplifier device (100) connected to the output of the radiation sensor (301) for re ceiving the charge signal (S_CH) and for supplying a voltage signal (VOU_T) correlated to the electric charge signal (SC_H) ;

characterized by the fact said charge preampli fying device (100) is made according to at least one of the preceding claims.

15. Sensing apparatus (300) according to claim 14, wherein said radiation sensor is a sensor se lected among: semiconductor drift detector, pixel detector .