WO2020108429A1 - 阵列基板及显示装置 - Google Patents

阵列基板及显示装置 Download PDF

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Publication number
WO2020108429A1
WO2020108429A1 PCT/CN2019/120580 CN2019120580W WO2020108429A1 WO 2020108429 A1 WO2020108429 A1 WO 2020108429A1 CN 2019120580 W CN2019120580 W CN 2019120580W WO 2020108429 A1 WO2020108429 A1 WO 2020108429A1
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WIPO (PCT)
Prior art keywords
line
sub
line segment
signal line
pixel unit
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PCT/CN2019/120580
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English (en)
French (fr)
Inventor
马永达
郝学光
吴新银
乔勇
Original Assignee
京东方科技集团股份有限公司
北京京东方技术开发有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方技术开发有限公司 filed Critical 京东方科技集团股份有限公司
Priority to EP19889318.2A priority Critical patent/EP3890027A4/en
Priority to JP2020548955A priority patent/JP2022509894A/ja
Priority to US16/762,888 priority patent/US20210225876A1/en
Publication of WO2020108429A1 publication Critical patent/WO2020108429A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/16—Constructional details or arrangements
    • G06F1/18—Packaging or power distribution
    • G06F1/181—Enclosures
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/40—Arrangements for improving the aperture ratio
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/52—RGB geometrical arrangements

Definitions

  • the present disclosure relates to the technical field of displays, and particularly to an array substrate and a display device.
  • the light exit surface of the pixel restricts the light exit area of the pixel through the light-shielding layer, resulting in a decrease in the aperture ratio. If the aperture ratio is ensured and the light output area of different sub-pixels is taken into account, the related art needs to set vertical signal lines with different pitches, so that there is a case where the wiring density between the vertical signal lines and the lead lines connecting the terminals is too large, thereby increasing The difficulty in etching when fabricating the array substrate causes an increase in the defect rate.
  • the purpose of the technical solution of the present disclosure is to provide an array substrate and a display device.
  • an array substrate including:
  • the substrate body includes a display area and a non-display area
  • each of the first signal lines includes a first line segment, a second line segment, and is located between and connected to the first line segment and the second line segment Describe the first line segment and the third line segment of the second line segment,
  • a plurality of the first signal lines are spaced along the first direction; along a second direction perpendicular to the first direction, a first spaced area is formed between two adjacent first line segments, A second spaced region is formed between two adjacent second line segments, and a third spaced region is formed between two adjacent third line segments; at least a portion of the sub-pixel unit is disposed on the first In a spaced area and a third spaced area, at the edge position adjacent to the display area in the non-display area of the substrate body, the second line segment is connected to the terminal connection lead;
  • At least two adjacent second spacing regions have the same width in the first direction, and for each of two adjacent first signal lines in at least one group of two adjacent first signal lines A first spacing area and a second spacing area formed by the first signal line, the width of the first spacing area in the first direction is different from the width of the second spacing area in the first direction.
  • all the second spacing regions on the substrate body have the same width in the first direction.
  • the set first signal line is one of two adjacent first signal lines, and the other first signal line is along the The second direction extends a straight line.
  • each of the two adjacent first signal lines is formed as the set first signal line.
  • the width of the first line segment of the set first signal line is greater than the width of the second line segment of the set first signal line.
  • a first sub-pixel unit and a second sub-pixel unit are respectively provided on both sides of the set first signal line, wherein the area of the first sub-pixel unit is smaller than the The area of the second sub-pixel unit, the first line segment and the third line segment of the set first signal line are closer to the position of the first sub-pixel unit than the second line segment of the set first signal line The direction protrudes.
  • the first line segment setting the first signal line is oriented toward the position of the first sub-pixel unit compared to the second line segment setting the first signal line
  • the width of the protrusion is directly related to the area ratio between the second sub-pixel unit and the first sub-pixel unit.
  • the array substrate further includes a third sub-pixel unit disposed on a side of the second sub-pixel unit away from the first sub-pixel unit, wherein the area and the first sub-pixel unit
  • the ratio between the areas of the two sub-pixel units is positively related to the value of the following relationship:
  • W1 represents the width of the second spaced region in the first direction
  • C1 represents the distance between the first and second sub-pixel units that sets the second line segment of the first signal line away from the first sub-pixel
  • C2 represents the second and third sub-units
  • a1 represents the width of the second line segment between the first and second sub-pixel units that sets the first signal line
  • b1 represents the width between the first and second sub-pixel units
  • the width of the first line segment of the first signal line between the pixel units is set
  • b2 represents the width of the first line segment of the first signal line between the second and third sub-pixel units.
  • the second line segment and the third line segment serve as a light shielding layer between two adjacent sub-pixel units.
  • a plurality of connection terminals are further provided on the array substrate, and the plurality of connection terminals are connected to the plurality of terminal connection leads of the first signal line in a one-to-one correspondence;
  • the plurality of connection terminals are arranged at intervals in the first direction, and the total length of the plurality of connection terminals arranged in the first direction is less than the plurality of first signal lines arranged in the first direction The total length.
  • the array base further includes:
  • a plurality of second signal lines located on the substrate body and crossing the first signal line, wherein the second line segment setting the first signal line spans the second signal line, and the setting The width of the second line segment of a signal line is smaller than the width of the first line segment of the set first signal line.
  • the extending direction of the second signal line is the second direction.
  • the first signal line is a data line or a VDD power line
  • the second signal line is a gate line
  • an embodiment of the present disclosure also provides a display device, including the array substrate as described in any one of the above.
  • 1 is a schematic structural diagram of an array substrate in the related art
  • FIG. 2 is a schematic diagram of a part of the structure of an array substrate according to an embodiment of the present disclosure
  • FIG. 3 is a second schematic diagram of a part of the structure of the array substrate according to an embodiment of the present disclosure
  • FIG. 4 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure.
  • cross-arranged signal lines are fabricated on the substrate body 1 of the array substrate, wherein the plurality of first signal lines 2 are arranged horizontally and the plurality of second signal lines 3 are respectively vertical Straightly arranged, a rectangular area formed by the intersection of the plurality of first signal lines 2 and the plurality of second signal lines 3 is formed as a light-transmitting area of the sub-pixels.
  • the first signal line 2 is a gate line
  • the second signal line 3 is a data line or a VDD power line.
  • the second signal lines 3 have different separation distances at the lead-out end connected to the lead-out line 4, so that one of the lead-out lines 4 connecting the second signal line 3 and the connection terminal 5 The wiring density between is greater.
  • FIG. 4 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure. As shown in FIG. 4, a display area and a non-display area are provided on the substrate body of the array substrate, and sub-pixel units sp1-sp6, a first signal line, and a second signal line are provided on the display area and the non-display area Connect lead and other components to the terminal. As shown in FIG. 4, a display area and a non-display area are provided on the substrate body of the array substrate, and sub-pixel units sp1-sp6, a first signal line, and a second signal line are provided on the display area and the non-display area Connect lead and other components to the terminal. As shown in FIG.
  • the sub-pixel units sp1, sp2, and sp3 can be combined into one RGB pixel unit, and the sub-pixel units sp4, sp5, and sp6 can be combined into one RGB pixel unit, or the sub-pixel units sp1, sp2, sp3, and sp4 can be combined into one RGBW pixel unit; alternatively, the sub-pixel unit sp1 can be a dummy subpixel (dummy subpixel).
  • the subpixel units sp2, sp3, and sp4 can be combined into one RGB pixel unit, or subpixel
  • the units sp2, sp3, sp4 and sp5 can be combined into one RGBW pixel unit.
  • the sizes of the sub-pixel units sp1-sp4 are different.
  • the array substrate according to an embodiment of the present disclosure includes:
  • Substrate body 100
  • the first signal line The portion of 110 in the middle of the two short dashed lines is the third line segment 231, which is located between and connecting the first line segment 211 and the second line segment 221); along the second direction perpendicular to the first direction a b, a first spacing area 210 is formed between two adjacent first line segments 211, a second spacing area 220 is formed between two adjacent second line segments 221, and two adjacent third line segments A third space area 230 is formed between the portions 231; at least a part of the sub-pixel unit 300 is disposed in the first space area 210 and the third space area 230, an edge adjacent to the display area in the non-display area of the substrate body 100 At the position, the second line segment 221 is connected to the terminal connection lead 120;
  • the width of the second spacing region 220 of each adjacent two second line segments 221 is the same; in at least one group of two adjacent first signal lines 110, along the first direction a, the width of the first spacing region 210 is equal to The width of the second spacing area 220 is different; and the third spacing area 230 is a transition area between the first spacing area 210 and the second spacing area 220, and the length of the side adjacent to the first spacing area 210 may be equal to the first The width of the space area 210 in the first direction a, and the length of the side adjacent to the second space area 220 may be equal to the width of the second space area 220 in the first direction a.
  • the first spacing region 210 and the third spacing portion 230 are set according to the area size of the sub-pixel unit; At the edge position adjacent to the display area in the area, the second line segment 221 is connected to the terminal connection lead 120, and the width of each adjacent two second spacing regions 220 is a fixed value, so that each adjacent two first signal lines 110 At the connection with the terminal connection lead 120, the separation distance is equal, and will not change due to the area size of the sub-pixel unit, to solve the problem that when the separation distance between the second line segments on the array substrate of the related art is different, the lead line of the signal line If the density is too large, it will increase the difficulty of etching and increase the defect rate.
  • the array substrate further includes a plurality of second signal lines 130 on the substrate body 100, the second signal lines 130 cross the first signal lines 110, and the second signal lines
  • the area formed by the intersection of 130 and the first signal line 110 is formed as a pixel setting area, that is, corresponding to the display area of the array substrate, and each pixel setting area is provided with a sub-pixel unit 300.
  • the second signal line 130 and the first signal line 110 are vertically arranged, of course, it is not limited to this, and the angle between the second signal line 130 and the first signal line 110 may be non-90 degrees, as long as a plurality of second
  • the signal lines 130 and the plurality of first signal lines 110 may be formed as a plurality of pixel installation regions by crossing each other.
  • the first signal line 110 is a data line or a VDD power line
  • the second signal line 130 is a gate line.
  • the plurality of first signal lines 110 are respectively arranged vertically and arranged at intervals in the horizontal direction;
  • the plurality of second signal lines 130 are arranged horizontally and arranged at intervals in the vertical direction, that is, the first direction a is the horizontal direction,
  • the second direction b is the vertical direction.
  • the set first signal line 111 includes at least two lines that respectively extend along the second direction b and are located on different straight lines. Two of the lines are the first lines that set the first signal line 111 to form the first space area 210. The segment 211 and the second line segment 221 forming the second space area 220.
  • the first signal line 111 used to form the corresponding sub-pixel unit includes at least two first line segments 211 and second line segments located on different straight lines 221, and a third line segment 231 connecting the first line segment 211 and the second line segment 221, that is, constituted as a curve; wherein, the first signal line 111 is set to form the first line segment 211 of the first spacing region 210 and adjacent
  • the first signal line 110 is set according to the area setting of the sub-pixel unit, and the first signal line 111 is set to form a second line segment 221 of the second space area 220 connected to the terminal connection lead 120 and to the adjacent first signal line 110
  • the distance between them is set according to a preset spacing distance, so that the spacing distance between each adjacent two first signal lines 110 and the connection point of the terminal connection lead 120 is equal, and will not change due to the area size of the sub-pixel unit.
  • the adjacent first sub-pixel unit 10, second sub-pixel unit 20 and third sub-pixel unit 30 form the first sub-pixel unit 10 Of the two first signal lines 110, one of the first signal lines 110 is a line extending in a straight line along the second direction b, and the other first signal line 110 is a curve formed as the above-mentioned set first signal line 111 ;
  • the two first signal lines 110 respectively forming the second sub-pixel unit 20 and the third sub-pixel unit 30 are formed as curves, that is, each of the first two signal lines 111 in the adjacent two first signal lines 111 Both are formed as the above-mentioned set first signal line 111.
  • the third line segment 231 in each set first signal line 111 is connected to a thin film transistor (TFT) in the corresponding pixel unit 10, 20 or 30.
  • TFT thin film transistor
  • the width along the first direction a at each position point is equal.
  • the width of the first line segment 211 forming the first signal line 111 to form the first space area 210 is greater than the setting of the first signal line 111 forms the width of the second line segment 221 of the second spacing region 220.
  • the width of the first line segment 211 forming the first interval region is b1, forming the first
  • the width of the second line segment 221 of the two spaced regions 220 is a1, where b1 is greater than a1.
  • the width of the first line segment 211 forming the first spacing region 210 is also greater than the width of the second line segment 221 forming the second spacing region 220, as shown in FIG.
  • the b2 in 2 is greater than a2, and b3 is greater than a3. Based on this method, the resistance of the first signal line is reduced.
  • the widths of the second line segments 221 forming the second spacing region 220 are all equal.
  • each setting of the first signal line 111 further includes a plurality of portions that span the second signal line 130.
  • each setting The width of the first signal line 111 crossing the second signal line 130 is smaller than the width of the first line segment 211 forming the first space region 210.
  • the second line segment 221 forming the second space area 220 also spans the second signal line 130; and the first signal line 111 is set to span each second signal
  • Each line of the line 130 is located on the same straight line and has the same width.
  • sub-pixel units are provided on both sides of the first signal line 111, as shown in FIG. 3 are the first sub-pixel unit 10 and the second sub-pixel unit 20, Wherein the area of the first sub-pixel unit 10 is smaller than that of the second sub-pixel unit 20, then the first signal line 111 is set to form the first line segment 211 and the third line segment 231 of the first spacing region 210 and the third spacing region 230 are compared The second line segment 221 forming the second space region 220 protrudes toward the position of the first sub-pixel unit 10.
  • the area of the third sub-pixel unit 30 is smaller than the area of the second sub-pixel unit 20, and the two sub-pixel units It is assumed that the first signal line 111 protrudes toward the position of the second sub-pixel unit 20 with a smaller area.
  • the first signal line 111 when both sides of the first signal line 111 are set as the first sub-pixel unit and the second sub-pixel unit with different areas, the first signal line 111 is set to form the first spaced area
  • the width of the first line segment 211 of 210 protruding toward the position of the first sub-pixel unit (that is, the sub-pixel unit with a smaller area) compared to the second line segment 221 forming the second spacing region 220 in other words, the Compared to the distance that the first line segment 211 translates in the opposite direction of the direction a compared to the second line segment 221, it is positively related to the area ratio between the second sub-pixel unit and the first sub-pixel unit.
  • the areas of the three sub-pixel units are S1, S2, and S3, respectively, where S1 is less than S2, And the ratio of S1 and S2 is M; S2 is greater than S3, and the ratio of S2 and S3 is N.
  • the first signal line 111 is set between the first subpixel unit 10 and the second subpixel unit 20, and the first signal line 111 is set between the second subpixel unit 20 and the third subpixel unit 30.
  • the widths of the second line segments 221 forming the second spacing region 220 are respectively a1 and a2, and the widths of the first line segments 211 forming the first spacing region 210 are b1 and b2, respectively.
  • the first line segment 211 forming the first spacing region 210 is compared to the second line segment forming the second spacing region 220 221, the distance protruding toward the direction of the first sub-pixel unit 10 is C1-a1; for the setting of the first signal line 111 between the second sub-pixel unit 20 and the third sub-pixel unit 30, a first interval region is formed Compared with the second line segment 221 forming the second space region 220, the first line segment 211 of 210 protrudes toward the third sub-pixel unit 30 by a distance C2-a2.
  • C represents the vertical distance between the extension line of one edge in the length direction of the first signal line and the opposite edge.
  • the above-mentioned distance C1 is an extension line between the first and second sub-pixel units 10 and 20 that sets the right edge of the second line segment 221 of the first signal line 111 and this setting
  • the vertical distance between the left edge of the first line segment 211 of the first signal line 111 is determined
  • the above distance C2 is the set first signal line 111 between the second and third sub-pixel units 20 and 30
  • the vertical distance between the extension line of the left edge of the second line segment 221 and the right edge of the first line segment 211 of the first signal line 111 is set.
  • the ratio between the area S1 of the first sub-pixel unit 10 and the area of the second sub-pixel unit S2 is positively related to the value of the following relationship:
  • W1 is the width of the second spacing region 220 in the first direction a. According to the above, the width of the second interval region 220 is a fixed value between every two adjacent first signal lines 110.
  • the ratio between the area S1 of the first sub-pixel unit 10 and the area of the second sub-pixel unit S2, and the width of the first sub-pixel unit 10 in the first direction a and The ratio of the width of the two sub-pixel units 20 in the first direction a is positively correlated.
  • connection terminals 400 are further provided on the array substrate, and the plurality of connection terminals 400 are connected to the terminal connection leads 120 of the plurality of first signal lines 110 in one-to-one correspondence;
  • the plurality of connection terminals 400 are spaced apart along the first direction a, and the total length of the plurality of connection terminals 400 arranged along the first direction a is smaller than the total length of the plurality of first signal lines 110 arranged along the first direction a.
  • the first signal line 110 forms the first line segment 211 of the first spacing region 210 as a light shielding layer between two adjacent sub-pixel units, which is used to shield the adjacent sub-pixel units The role of light transmitted between.
  • the density of the lead lines of the signal lines is too large, resulting in The difficulty of etching increases and the defect rate increases.
  • Another aspect of the present disclosure also provides a display device including the above-mentioned array substrate.
  • a display device including the above-mentioned array substrate.
  • FIGS. 2 and 3 and the detailed description in the above those skilled in the art should be able to understand the display device employing the array substrate according to the embodiments of the present disclosure. The specific structure will not be described in detail here.

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Abstract

一种阵列基板及显示装置。该阵列基板包括：基板本体（100）；以及位于所述基板本体（100）上的多个第一信号线（110），每个所述第一信号线（110）包括第一线段（211）、第二线段（221）、以及连接这两者的第三线段（231）。多个所述第一信号线（110）沿第一方向（a）间隔设置；沿与所述第一方向（a）垂直的第二方向（b），相邻的两个所述第一线段（211）之间形成有第一间隔区域（210），相邻的两个所述第二线段（221）之间形成有第二间隔区域（220），并且相邻的两个所述第三线段（231）之间形成有第三间隔区域（230）。子像素单元的至少一部分设置在所述第一间隔区域（210）和第三间隔区域（230）内，在所述基板本体（100）的非显示区中的与显示区邻接的边缘位置处，所述第二线段（221）与端子连接引线（120）连接。至少两个相邻的所述第二间隔区域（220）在所述第一方向（a）上的宽度相同。

Description

阵列基板及显示装置
相关申请的交叉引用
本申请主张在2018年11月26日在中国提交的中国专利申请No.201821952246.9的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示器技术领域，尤其是指一种阵列基板及显示装置。
背景技术
相关技术中的显示面板中，像素出光面通过遮光层限制像素的出光面积，造成开口率降低。如果保证开口率的同时兼顾不同的子像素出光面积，相关技术需要设置不同间距的纵向信号线，使得出现连接纵向信号线与连接端子的引出线之间存在走线密度过大的情况，从而增加阵列基板制作时的刻蚀难度，造成不良率提高。
发明内容
本公开技术方案的目的是提供一种阵列基板及显示装置。
一方面，本公开提供一种阵列基板，包括：
基板本体包括显示区和非显示区；以及
位于所述基板本体显示区的多个第一信号线，每个所述第一信号线包括第一线段、第二线段、以及位于所述第一线段和第二线段之间并且连接所述第一线段和第二线段的第三线段，
其中，多个所述第一信号线沿第一方向间隔设置；沿与所述第一方向垂直的第二方向，相邻的两个所述第一线段之间形成有第一间隔区域，相邻的两个所述第二线段之间形成有第二间隔区域，并且相邻的两个所述第三线段之间形成有第三间隔区域；子像素单元的至少一部分设置在所述第一间隔区域和第三间隔区域内，在所述基板本体的非显示区中的与显示区邻接的边缘位置处，所述第二线段与端子连接引线连接；
至少两个相邻的所述第二间隔区域在所述第一方向上的宽度相同，而针对至少一组相邻的两个所述第一信号线中的每组相邻的两个所述第一信号线所形成的第一间隔区域和第二间隔区域，所述第一间隔区域在所述第一方向上的宽度与所述第二间隔区域在所述第一方向上的宽度不同。
可选地，在所述阵列基板中，所述基板本体上的所有所述第二间隔区域在所述第一方向上的宽度均相同。
可选地，在所述的阵列基板中，在所形成的第一间隔区域在所述第一方向上的宽度与所形成的第二间隔区域在所述第一方向上的宽度不同的每组相邻的两个所述第一信号线中，设定第一信号线包括的第一线段和第二线段分别沿所述第二方向延伸、并且位于不同直线上。
可选地，在所述阵列基板中，所述设定第一信号线为相邻两个所述第一信号线的其中一第一信号线，另一所述第一信号线为沿所述第二方向延伸呈一直线的线路。
可选地，在所述阵列基板中，相邻两个所述第一信号线中的每一所述第一信号线均形成为所述设定第一信号线。
可选地，在所述阵列基板中，所述设定第一信号线的第一线段的宽度大于所述设定第一信号线的第二线段的宽度。
可选地，在所述阵列基板中，所述设定第一信号线的两侧分别设置有第一子像素单元和第二子像素单元，其中所述第一子像素单元的面积小于所述第二子像素单元的面积，所述设定第一信号线的第一线段和第三线段相较于该设定第一信号线的第二线段，朝所述第一子像素单元的位置方向凸出。
可选地，在所述阵列基板中，所述设定第一信号线的第一线段相较于该设定第一信号线的第二线段，朝所述第一子像素单元的位置方向凸出的宽度，与所述第二子像素单元与所述第一子像素单元之间的面积比正相关。
可选地，所述阵列基板还包括设置于所述第二子像素单元的远离所述第一子像素单元一侧的第三子像素单元，其中，所述第一子像素单元的面积与第二子像素单元的面积之间的比值与如下关系式的值正相关：
(W1-(C1-a1))/(W1+(C1-b1)+(C2-b2))，
其中，W1表示所述第二间隔区域在第一方向上的宽度，C1表示位于第 一和第二子像素单元之间的设定第一信号线的第二线段的远离所述第一子像素单元的一侧边缘的延伸线与该设定第一信号线的第一线段的远离所述第二子像素单元的一侧的边缘之间的垂直距离，C2表示位于第二和第三子像素单元之间的设定第一信号线的第二线段的远离所述第三子像素单元的一侧边缘的延伸线与该设定第一信号线的第一线段的远离所述第二子像素单元的一侧的边缘之间的垂直距离，a1表示位于第一和第二子像素单元之间的设定第一信号线的第二线段的宽度，b1表示位于第一和第二子像素单元之间的设定第一信号线的第一线段的宽度，并且b2表示位于第二和第三子像素单元之间的设定第一信号线的第一线段的宽度。
可选地，在所述阵列基板中，所述第二线段和第三线段用作相邻两个子像素单元之间的遮光层。
可选地，在所述阵列基板中，所述阵列基板上还设置有多个连接端子，多个所述连接端子与多个所述第一信号线的端子连接引线一一对应连接；
其中，多个所述连接端子沿所述第一方向间隔设置，且多个所述连接端子沿所述第一方向排列的总长度小于多个所述第一信号线沿所述第一方向排列的总长度。
可选地，所述阵列基还包括：
位于所述基板本体上且与所述第一信号线交叉设置的多个第二信号线，其中所述设定第一信号线的第二线段跨越所述第二信号线，并且该设定第一信号线的第二线段的宽度小于该设定第一信号线的第一线段的宽度。
可选地，在所述阵列基板中，所述第二信号线的延伸方向为所述第二方向。
可选地，在所述阵列基板中，所述第一信号线为数据线或VDD电源线，所述第二信号线为栅线。
另一方面，本公开实施例还提供一种显示装置，包括如上任一项所述的阵列基板。
附图说明
图1为相关技术中的阵列基板的结构示意图；
图2为本公开实施例所述阵列基板的部分结构示意图之一；
图3为本公开实施例所述阵列基板的部分结构示意图之二；
图4为本公开实施例所述阵列基板的结构示意图；。
具体实施方式
为使本公开要解决的技术问题、技术方案和优点更加清楚，下面将结合附图及具体实施例进行详细描述。
在相关技术中，如图1所示，在阵列基板的基板本体1上制作有交叉设置的信号线，其中多个第一信号线2分别呈水平排列，多个第二信号线3分别呈竖直排列，多个第一信号线2和多个第二信号线3相交叉所构成的矩形区域，形成为子像素的透光区域。通常第一信号线2为栅线，第二信号线3为数据线或VDD电源线。
根据图1，当多个第二信号线3之间的间隔距离不同时，子像素的透光区域的面积S1、S2和S3不同。而由于多个第二信号线3的间隔距离不同，第二信号线3在与引出线4连接的引出端处，间隔距离不同，使得连接第二信号线3与连接端子5的引出线4之间的走线密度较大。
图4为本公开实施例所述阵列基板的结构示意图。如图4所示，该阵列基板的基板本体上设置有显示区和非显示区，在所述显示区和非显示区上设置有子像素单元sp1-sp6、第一信号线、第二信号线和端子连接引线等元件。如图4中所示，例如子像素单元sp1、sp2和sp3可以组合为一个RGB像素单元，子像素单元sp4、sp5和sp6可以组合为一个RGB像素单元，或者子像素单元sp1、sp2、sp3和sp4可以组合为一个RGBW像素单元；或者，子像素单元sp1可以为哑子像素(dummy subpixel)，在这种情况下，例如子像素单元sp2、sp3和sp4可以组合为一个RGB像素单元，或者子像素单元sp2、sp3、sp4和sp5可以组合为一个RGBW像素单元。上述例如子像素单元sp1-sp4的大小不同。
图2和3均为图4所示的阵列基板的虚线框所指示的部分的结构示意图。参阅图2所示，本公开实施例所述阵列基板，包括：
基板本体100；
位于基板本体100上的多个第一信号线110，多个第一信号线110沿第一方向a间隔设置，每个所述第一信号线110包括第一线段211、第二线段221、以及位于所述第一线段211和第二线段221之间并且连接所述第一线段211和第二线段221的第三线段231(具体地，如图2中所示，第一信号线110中的位于两条短虚线中间的部分即为第三线段231，其位于第一线段211和第二线段221之间并且连接这两者)；沿与第一方向a垂直的第二方向b，相邻的两个第一线段211之间形成有第一间隔区域210，相邻的两个第二线段221之间形成有第二间隔区域220，并且相邻的两个第三线段部分231之间形成有第三间隔区域230；子像素单元300的至少一部分设置在第一间隔区域210和第三间隔区域230内，在基板本体100的非显示区中的与显示区邻接的边缘位置处，所述第二线段221与端子连接引线120连接；
其中，每相邻两个第二线段221的第二间隔区域220的宽度相同；至少一组相邻的两个第一信号线110中，沿第一方向a，第一间隔区域210的宽度与第二间隔区域220的宽度不同；而第三间隔区域230作为位于第一间隔区域210和第二间隔区域220之间的过渡区域，其与第一间隔区域210邻接的一边的长度可以等于第一间隔区域210的沿第一方向a的宽度，并且其与第二间隔区域220邻接的一边的长度可以等于第二间隔区域220的沿第一方向a的宽度。
本公开实施例所述阵列基板，在相邻的两个第一信号线110之间，第一间隔区域210和第三间隔部分230依据子像素单元的面积大小设置；在基板本体100的非显示区中的与显示区邻接的边缘位置处，第二线段221与端子连接引线120连接，每相邻两个第二间隔区域220的宽度为固定值，使得每相邻两个第一信号线110在与端子连接引线120连接处，间隔距离相等，不会因为子像素单元的面积大小而变化，以解决相关技术的阵列基板上的第二线段之间的间隔距离不同时，信号线的引出线的密度过大，造成刻蚀难度增加，不良率提高的问题。
本公开实施例中，如图2所示，阵列基板还包括位于基板本体100上的多个第二信号线130，该第二信号线130与第一信号线110交叉设置，且第二信号线130与第一信号线110交叉部分所形成的区域形成为像素设置区域， 也即对应为阵列基板的显示区，每一像素设置区域内设置有一子像素单元300。
可选地，第二信号线130与第一信号线110垂直设置，当然并不限于此，第二信号线130与第一信号线110之间可以呈非90度的角度，只要多个第二信号线130与多个第一信号线110相互交叉能够形成为多个像素设置区域即可。
本公开实施例中，可选地，第一信号线110为数据线或VDD电源线，第二信号线130为栅线。且进一步，多个第一信号线110分别为竖直设置，沿水平方向间隔排列；多个第二信号线130为水平设置，沿竖直方向间隔排列，也即第一方向a为水平方向，第二方向b为竖直方向。
如图2所示，相邻的两个第一信号线110中，沿第一方向a，第一间隔区域210的宽度与第二间隔区域220的宽度不同时，两个第一信号线110中的设定第一信号线111包括至少两段分别沿第二方向b延伸、位于不同直线的线路，其中的两个线路分别为设定第一信号线111形成第一间隔区域210的第一线段211和形成第二间隔区域220的第二线段221。
基于上述设置方式，当相邻两个子像素单元的面积大小不同时，用于形成对应子像素单元的设定第一信号线111包括至少两个位于不同直线的第一线段211和第二线段221、以及连接第一线段211和第二线段221的第三线段231，也即构成为曲线；其中，设定第一信号线111形成第一间隔区域210的第一线段211与相邻的第一信号线110之间依据子像素单元的区域设置，设定第一信号线111形成第二间隔区域220的第二线段221与端子连接引线120连接，与相邻的第一信号线110之间依据预设间隔距离设置，使得每相邻两个第一信号线110与端子连接引线120连接处之间的间隔距离相等，不会因为子像素单元的面积大小而变化。
本公开实施例中，结合图2和图3所示，可选地，相邻的第一子像素单元10、第二子像素单元20和第三子像素单元30，形成第一子像素单元10的两个第一信号线110，其中一第一信号线110为沿第二方向b延伸呈一直线的线路，另一第一信号线110为曲线，形成为上述的设定第一信号线111；分别形成第二子像素单元20和第三子像素单元30的两个第一信号线110，均形成为曲线，也即相邻两个第一信号线111中的每一第一信号线111均形成 为上述的设定第一信号线111。如图2和图3中所示，每条设定第一信号线111中的第三线段231均连接到相应的像素单元10、20或30中的薄膜晶体管(Thin Film Transistor，TFT)。
本公开实施例中，可选地，对于形成直线的第一信号线110，在每一位置点沿第一方向a的宽度均相等。
另一方面，本公开实施例中，如图2所示，沿第一方向a，设定第一信号线111形成第一间隔区域210的第一线段211的宽度大于设定第一信号线111形成第二间隔区域220的第二线段221的宽度。
举例说明，如图3所示，对于形成第一子像素单元10的设定第一信号线111，沿第一方向a，形成第一间隔区域的第一线段211的宽度为b1，形成第二间隔区域220的第二线段221的宽度为a1，其中b1大于a1。同理，对于形成其他子像素单元的设定第一信号线111，形成第一间隔区域210的第一线段211的宽度也大于形成第二间隔区域220的第二线段221的宽度，如图2中的b2大于a2，b3大于a3。基于该方式以降低第一信号线的电阻。
可选地，本公开实施例中，对于阵列基板上的每一设定第一信号线111，形成第二间隔区域220的第二线段221的宽度均相等。
进一步地，由于第一信号线111与第二信号线130交叉设置，每一设定第一信号线111还包括多个跨越第二信号线130的部分，本公开实施例中，每一设定第一信号线111跨越第二信号线130的线路的宽度，小于形成第一间隔区域210的第一线段211的宽度。另外，如图2所示，对于设定第一信号线111，形成第二间隔区域220的第二线段221也跨越第二信号线130；而且设定第一信号线111跨越每一第二信号线130的每一线路位于同一直线，且宽度相等。
另外，本公开实施例中，如图3所示，设定第一信号线111的两侧分别设置有子像素单元，如图3中的第一子像素单元10和第二子像素单元20，其中第一子像素单元10的面积小于第二子像素单元20，则设定第一信号线111形成第一间隔区域210和第三间隔区域230的第一线段211和第三线段231相较于形成第二间隔区域220的第二线段221，朝第一子像素单元10的位置方向凸出。
同理，对于第二子像素单元20与第三子像素单元30之间的设定第一信号线111，第三子像素单元30的面积小于第二子像素单元20的面积，两个子像素单元之间的设定第一信号线111朝面积较小的第二子像素单元20的位置方向凸出。
进一步地，本公开实施例中，当设定第一信号线111的两侧分别为面积不同的第一子像素单元和第二子像素单元时，设定第一信号线111形成第一间隔区域210的第一线段211相较于形成第二间隔区域220的第二线段221，朝第一子像素单元(也即面积较小的子像素单元)的位置方向凸出的宽度(换言之，所述第一线段211相较于第二线段221沿所述方向a的反方向平移的距离)，与第二子像素单元与第一子像素单元之间的面积比正相关。
举例说明，如图3所示，对于第一子像素单元10、第二子像素单元20和第三子像素单元30，三个子像素单元的面积分别为S1、S2和S3，其中S1小于S2，且S1与S2的比值为M；S2大于S3，且S2与S3的比值为N。
另外，对于第一子像素单元10与第二子像素单元20之间的设定第一信号线111、第二子像素单元20与第三子像素单元30之间的设定第一信号线111，形成第二间隔区域220的第二线段221的宽度分别为a1、a2，形成第一间隔区域210的第一线段211的宽度分别为b1、b2。对于第一子像素单元10与第二子像素单元20之间的设定第一信号线111，形成第一间隔区域210的第一线段211相较于形成第二间隔区域220的第二线段221，朝第一子像素单元10的方向凸出的距离为C1-a1；对于第二子像素单元20与第三子像素单元30之间的设定第一信号线111，形成第一间隔区域210的第一线段211相较于形成第二间隔区域220的第二线段221，朝第三子像素单元30的方向凸出的距离为C2-a2。其中C表示设定第一信号线的长度方向上的一侧边缘与相对的另一侧的边缘的延伸线之间的垂直距离。例如，如图3所示，上述的距离C1为位于第一和第二子像素单元10和20之间的设定第一信号线111的第二线段221的右侧边缘的延伸线与该设定第一信号线111的第一线段211的左侧边缘之间的垂直距离，而上述的距离C2为位于第二和第三子像素单元20和30之间的设定第一信号线111的第二线段221的左侧边缘的延伸线与该设定第一信号线111的第一线段211的右侧边缘之间的垂直距离。
具体地，第一子像素单元10的面积S1与第二子像素单元S2的面积之间的比值与如下关系式的值正相关：
(W1-(C1-a1))/(W1+(C1-b1)+(C2-b2))。
其中W1为在第一方向a上，第二间隔区域220的宽度。根据以上，每相邻两个第一信号线110之间，第二间隔区域220的宽度为固定值。
也即，根据以上公式，具体地，第一子像素单元10的面积S1与第二子像素单元S2的面积之间的比值，与第一子像素单元10在第一方向a上的宽度和第二子像素单元20在第一方向a上的宽度的比值正相关。
本公开实施例中，如图2和图3所示，阵列基板上还设置有多个连接端子400，多个连接端子400与多个第一信号线110的端子连接引线120一一对应连接；
其中，多个连接端子400沿第一方向a间隔设置，且多个连接端子400沿第一方向a排列的总长度小于多个第一信号线110沿第一方向a排列的总长度。
本公开实施例中，可选地，第一信号线110形成第一间隔区域210的第一线段211为相邻两个子像素单元之间的遮光层，用于起到屏蔽相邻子像素单元之间所透过光的作用。
本公开实施例所述阵列基板，当阵列基板上子像素单元的面积不同时，所设置第一信号线向子像素单元面积小的方向凸出，但每相邻两个第一信号线在与端子连接引线连接处，间隔距离相等，不会因为子像素单元的面积大小而变化，以解决相关技术阵列基板上信号线之间的间隔距离不同时，信号线的引出线的密度过大，造成刻蚀难度增加，不良率提高的问题。
本公开另一方面还提供一种包括上述阵列基板的显示装置，根据图2和图3以及上述中的详细描述，本领域技术人员应该能够了解采用本公开实施例所述阵列基板的显示装置的具体结构，在此不再详细说明。
以上所述的是本公开的优选实施方式，应当指出对于本技术领域的普通人员来说，在不脱离本公开所述原理前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (15)

  1. 一种阵列基板，包括：
    基板本体包括显示区和非显示区；以及
    位于所述基板本体显示区的多个第一信号线，每个所述第一信号线包括第一线段、第二线段、以及位于所述第一线段和第二线段之间并且连接所述第一线段和第二线段的第三线段，
    其中，多个所述第一信号线沿第一方向间隔设置；沿与所述第一方向垂直的第二方向，相邻的两个所述第一线段之间形成有第一间隔区域，相邻的两个所述第二线段之间形成有第二间隔区域，并且相邻的两个所述第三线段之间形成有第三间隔区域；子像素单元的至少一部分设置在所述第一间隔区域和第三间隔区域内，在所述基板本体的非显示区中的与显示区邻接的边缘位置处，所述第二线段与端子连接引线连接；
    至少两个相邻的所述第二间隔区域在所述第一方向上的宽度相同，而针对至少一组相邻的两个所述第一信号线中的每组相邻的两个所述第一信号线所形成的第一间隔区域和第二间隔区域，所述第一间隔区域在所述第一方向上的宽度与所述第二间隔区域在所述第一方向上的宽度不同。
  2. 根据权利要求1所述的阵列基板，其中，所述基板本体上的所有所述第二间隔区域在所述第一方向上的宽度均相同。
  3. 根据权利要求2所述的阵列基板，其中，在所形成的第一间隔区域在所述第一方向上的宽度与所形成的第二间隔区域在所述第一方向上的宽度不同的每组相邻的两个所述第一信号线中，设定第一信号线包括的第一线段和第二线段分别沿所述第二方向延伸、并且位于不同直线上。
  4. 根据权利要求3所述的阵列基板，其中，所述设定第一信号线为相邻两个所述第一信号线的其中一第一信号线，另一所述第一信号线为沿所述第二方向延伸呈一直线的线路。
  5. 根据权利要求3所述的阵列基板，其中，相邻两个所述第一信号线中的每一所述第一信号线均形成为所述设定第一信号线。
  6. 根据权利要求3所述的阵列基板，其中，所述设定第一信号线的第一 线段的宽度大于所述设定第一信号线的第二线段的宽度。
  7. 根据权利要求3所述的阵列基板，其中，所述设定第一信号线的两侧分别设置有第一子像素单元和第二子像素单元，其中所述第一子像素单元的面积小于所述第二子像素单元的面积，所述设定第一信号线的第一线段和第三线段相较于该设定第一信号线的第二线段，朝所述第一子像素单元的位置方向凸出。
  8. 根据权利要求7所述的阵列基板，其中，所述设定第一信号线的第一线段相较于该设定第一信号线的第二线段，朝所述第一子像素单元的位置方向凸出的宽度，与所述第二子像素单元与所述第一子像素单元之间的面积比正相关。
  9. 根据权利要求7所述的阵列基板，还包括设置于所述第二子像素单元的远离所述第一子像素单元一侧的第三子像素单元，其中，所述第一子像素单元的面积与第二子像素单元的面积之间的比值与如下关系式的值正相关：
    (W1-(C1-a1))/(W1+(C1-b1)+(C2-b2))，
    其中，W1表示所述第二间隔区域在第一方向上的宽度，C1表示位于第一和第二子像素单元之间的设定第一信号线的第二线段的远离所述第一子像素单元的一侧边缘的延伸线与该设定第一信号线的第一线段的远离所述第二子像素单元的一侧的边缘之间的垂直距离，C2表示位于第二和第三子像素单元之间的设定第一信号线的第二线段的远离所述第三子像素单元的一侧边缘的延伸线与该设定第一信号线的第一线段的远离所述第二子像素单元的一侧的边缘之间的垂直距离，a1表示位于第一和第二子像素单元之间的设定第一信号线的第二线段的宽度，b1表示位于第一和第二子像素单元之间的设定第一信号线的第一线段的宽度，并且b2表示位于第二和第三子像素单元之间的设定第一信号线的第一线段的宽度。
  10. 根据权利要求2所述的阵列基板，其中，所述第二线段和第三线段用作相邻两个子像素单元之间的遮光层。
  11. 根据权利要求2所述的阵列基板，其中，所述阵列基板上还设置有多个连接端子，多个所述连接端子与多个所述第一信号线的端子连接引线一一对应连接；
    其中，多个所述连接端子沿所述第一方向间隔设置，且多个所述连接端子沿所述第一方向排列的总长度小于多个所述第一信号线沿所述第一方向排列的总长度。
  12. 根据权利要求3所述的阵列基板，还包括：
    位于所述基板本体上且与所述第一信号线交叉设置的多个第二信号线，其中所述设定第一信号线的第二线段跨越所述第二信号线，并且该设定第一信号线的第二线段的宽度小于该设定第一信号线的第一线段的宽度。
  13. 根据权利要求12所述的阵列基板，其中，所述第二信号线的延伸方向为所述第二方向。
  14. 根据权利要求12或13所述的阵列基板，其中，所述第一信号线为数据线或VDD电源线，所述第二信号线为栅线。
  15. 一种显示装置，包括权利要求1至14任一项所述的阵列基板。
PCT/CN2019/120580 2018-11-26 2019-11-25 阵列基板及显示装置 WO2020108429A1 (zh)

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