WO2020103450A1

WO2020103450A1 - Programmable on-chip self-calibrating balanced attenuator

Info

Publication number: WO2020103450A1
Application number: PCT/CN2019/093041
Authority: WO
Inventors: Nima RAZMEHR; Gerrit Groenewold; Lars Henrik Mucke
Original assignee: Huawei Technologies Co., Ltd.
Priority date: 2018-11-21
Filing date: 2019-06-26
Publication date: 2020-05-28

Abstract

The disclosure relates to technology for attenuator circuits suitable for use at millimeter wavelength frequencies (super high to extremely high frequencies, such 60GHz for example). An input signal is received at a first hybrid coupler to generate two intermediate waveform signals, each of which is attenuated by a variable resistance and then recombined by a second hybrid coupler to provide the output signal for the attenuator. The first hybrid coupler isolates the variable resistors from the attenuator's input and the second hybrid coupler isolates the variable resistors from the attenuator's output. The variable resistors can be configured to provide wide range of attenuation values, such as from 0dB to 12dB. The value of the variable resistors can be controlled by a resistor calibration circuit configured to provide constant attenuation across process and temperature variations.

Description

PROGRAMMABLE ON-CHIP SELF-CALIBRATING BALANCED ATTENUATOR

CROSS REFERENCE TO RELATED APPLICATION

This application claims priority to U.S. provisional patent application Serial No. 62/770,439, filed on November 21, 2018 and entitled “Programmable On-Chip Self-Calibrating Balanced Attenuator” , which is incorporated herein by reference as if reproduced in its entirety.

FIELD

The disclosure generally relates to attenuation circuits that can provide a programmable level of attention

BACKGROUND

An attenuator is an electronic device that reduces the power of a signal without appreciably distorting its waveform and find use in situations when circuit elements need to be protected from signals with too great an amplitude or other situations where a waveform may be too powerful. A number of architectures exist for attenuators that can provide a given level of attenuation. However, these architectures cannot easily maintain stable input and output impedances without having significant loss at millimeter wavelength frequencies (super high to extremely high frequencies, such 60GHz for example) . In addition to controlling the input and output impedances, it is very difficult to generate constant attenuation in the presence of temperature variations and process deviations.

BRIEF SUMMARY

According to a first aspect of the present disclosure, a radio frequency (RF) integrated circuit comprises an attenuator having a first variable resistor, a second variable resistor, a first 90 degree hybrid coupler, and a second 90 degree hybrid coupler. The first variable resistor is configured to provide a settable amount of attenuation for a first internal signal. The second variable resistor is configured to provide a settable amount of attenuation for a second internal signal. The first 90 degree hybrid coupler is configured to receive an RF input signal at a first input port and generate the first internal signal and the second internal signal, wherein the first 90 degree hybrid coupler isolates the first variable resistor and the second variable resistor from the first input port. The second 90 degree hybrid coupler is configured to receive the first internal signal at the first input port and the second internal signal at a second input port and output an RF output signal from a combination of the first internal signal and the second internal signal at a first output port, wherein the second 90 degree hybrid coupler isolates the first variable resistor and the second variable resistor from the first output port.

Optionally, in a second aspect and in furtherance of the first aspect, the RF integrated circuit further comprises a control circuit configured to control a value of the resistance of the first variable resistor and the second variable resistor to provide constant attenuation across process and temperature variations.

Optionally, in a third aspect and in furtherance of the second aspect, the first variable resistor and the second variable resistor are configurable to provide from 0dB to 12dB attenuation for an RF input signal in the millimeter range.

Optionally, in a fourth aspect and in furtherance of any of the second and third aspects, the first variable resistor is connected between a first internal transmission line, through which the second 90 degree hybrid coupler is configured to receive the first internal signal, and ground. The second variable resistor is connected between a second internal transmission line, through which the second 90 degree hybrid coupler is configured to receive the second internal signal, and ground. Each of the first variable resistor and the second variable resistor comprise one or more transistors having a gate configured to receive a control voltage from the control circuit.

Optionally, in a fifth aspect and in furtherance of the preceding aspect, the control circuit is configured to receive a reference voltage and a reference current and to generate the control voltage in response to the reference voltage and the reference current.

Optionally, in a sixth aspect and in furtherance of the preceding aspect, the control circuit comprises: a current source configured to provide the reference current; a first transistor connected between the current source and ground; a second transistor through which the first transistor is connected to ground, wherein a control gate of the second transistor is connected between current source and first transistor, the control voltage corresponding to a voltage level on the control gate of the second transistor; and a difference amplifier having a first input connected to the reference voltage, a second input connected between the first transistor and the second transistor, and having an output connected to a gate of the first transistor.

Optionally, in a seventh aspect and in furtherance of the preceding aspect, the one or more transistors of the first variable resistor and second variable resistor are formed to be sized the same as the second transistor of the control circuit.

Optionally, in an eighth aspect and in furtherance to any of the sixth and the seventh aspect, the RF integrated circuit further comprises a band gap circuit configured to provide the reference voltage.

Optionally, in a ninth aspect and in furtherance of any of the fourth through eighth aspects, the first variable resistor comprises a plurality of transistors connected in parallel between the first internal transmission line and ground, each having a gate selectively connectable to receive the control voltage; and the second variable resistor comprises a plurality of transistors connected in parallel between the second internal transmission line and ground, each having a gate selectively connectable to receive the control voltage.

Optionally, in a tenth aspect and in furtherance of any of the preceding aspects, the attenuator is part of a receiver circuit.

Optionally, in an eleventh aspect and in furtherance of any of the preceding aspects, the attenuator is part of a transmitter circuit.

According to one other aspect of the present disclosure, a programmable attenuator includes a first leg and a resistor calibration circuit. The first leg includes first and second hybrid couplers and first and second variable resistors. The first hybrid coupler has a first input connected to receive a first input waveform and generate therefrom a first intermediate waveform and a second intermediate waveform having a phase difference relative to the first intermediate waveform. The second hybrid coupler is configured to receive the first intermediate waveform and the second intermediate waveform, the second hybrid coupler configured to generate at a first output a first output waveform combining the first intermediate waveform in phase with the second intermediate waveform. The first variable resistor is connected between ground and a line through which the first intermediate waveform is supplied from the first hybrid coupler to the second hybrid coupler. The second variable resistor is connected between ground and a line through which the second intermediate waveform is supplied from the first hybrid coupler to the second hybrid coupler. The resistor calibration circuit is configured to set a resistance value for the first variable resistor and a resistance value for the second variable resistor to provide constant attenuation across process and temperature variations.

According to one other aspect of the present disclosure, a method includes receiving an input waveform and splitting the input waveform into a first intermediate waveform and a second intermediate waveform, the second intermediate wave having a phase difference relative to the first intermediate waveform. The first intermediate waveform and the second intermediate waveform are recombined, including removing the phase difference, to generate an output waveform. The first intermediate waveform is attenuated by a first resistor connected to ground and the second intermediate waveform is attenuated by a second resistor connected to ground. A value of the first resistor and a value of the second resistor are set according to a reference value.

Embodiments of the present technology described herein provide improvements to existing attenuators. These include achieving a wide range (e.g., 0 dB to 12 dB) of on-chip programmable signal attenuation at millimeter wavelengths without changing the input and output impedances. The described embodiments can also provide constant attenuation in the presence of temperature variations and process deviations.

This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter. The claimed subject matter is not limited to implementations that solve any or all disadvantages noted in the Background.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are illustrated by way of example and are not limited by the accompanying figures for which like references indicate elements.

FIG. 1 illustrates an example of a wireless network for communicating data.

FIG. 2 illustrates an example of the details of an instance of user equipment (UE) introduced in FIG. 1.

FIG. 3 illustrates an example of the details of an instance of a base station (BS) introduced in FIG. 1.

FIG. 4 illustrates an example of the details of a receiver included in UE or a BS shown in FIGS. 2 and 3.

FIG. 5 illustrates an example of the details of a transmitter included in UE or a BS shown in FIGS. 2 and 3.

FIG. 6 illustrates a single-ended embodiment of an attenuation circuit.

FIG. 7 adds a resistor calibration circuit to the embodiment of FIG. 6.

FIG. 8 illustrates embodiments of a calibration circuit that can be incorporated in order to eliminate the influence of process and temperature variations of the variable resistors.

FIG. 9 illustrates an embodiment with four couplers for a differential input design.

FIG. 10 is a high-level flow diagram that is used to summarize methods for operating of a self-calibrating balanced attenuator.

DETAILED DESCRIPTION

The present disclosure will now be described with reference to the figures, which in general relate to attenuator circuits suitable for use at millimeter wavelength frequencies (super high to extremely high frequencies, such 60GHz for example) . An input signal is received at a first hybrid coupler to generate two intermediate waveform signals, each of which is attenuated by a variable resistance and then recombined by a second hybrid coupler to provide the output signal for the attenuator. The first hybrid coupler isolates the variable resistors from the attenuator’s input and the second hybrid coupler isolates the variable resistors from the attenuator’s output. The variable resistors can be configured to provide wide range of attenuation values, such as from 0dB to 12dB. The value of the variable resistors can be controlled by a resistor calibration circuit. The described embodiments can provide attenuator circuits that maintain stable input and output impedances without having significant loss when operating at millimeter wavelength frequencies. Embodiments for the resistor calibration circuit can acheive constant attenuation across process and temperature variations.

It is understood that the present embodiments of the disclosure may be implemented in many different forms and that scope of the claims should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts to those skilled in the art. Indeed, the disclosure is intended to cover alternatives, modifications and equivalents of these embodiments, which are included within the scope and spirit of the disclosure as defined by the appended claims. Furthermore, in the following detailed description of the present embodiments of the disclosure, numerous specific details are set forth in order to provide a thorough understanding. However, it will be clear to those of ordinary skill in the art that the present embodiments of the disclosure may be practiced without such specific details.

Before providing additional details for transmit-receive switches, FIG. 1 is used to describe an example of a wireless network for communicating data, FIG. 2 is used to describe details of an example of user equipment (UE) introduced in FIG. 1, and FIG. 3 is used to describe details of an example of a base station (BS) introduced in FIG. 1. Additionally, FIGS. 4 and 5 are respectively used to describe details of examples of a receiver and of a transmitter included a UE or a BS.

Referring to FIG. 1, illustrated therein is an example of a wireless network for communicating data. The communication system 100 includes, for example,

user equipment

110A, 110B, and 110C, radio access networks (RANs) 120A and 120B, a core network 130, a public switched telephone network (PSTN) 140, the Internet 150, and other networks 160, such as short-range wireless networks. Additional or alternative networks include private and public data-packet networks including corporate intranets. While certain numbers of these components or elements are shown in the figure, any number of these components or elements may be included in the system 100.

In one embodiment, the wireless network may be a fifth generation (5G) network including at least one 5G base station which employs orthogonal frequency-division multiplexing (OFDM) and/or non-OFDM and a transmission time interval (TTI) shorter than 1 ms (e.g. 100 or 200 microseconds) , to communicate with the communication devices. In general, a base station may also be used to refer any of the eNB and the 5G BS (gNB) . In addition, the network may further include a network server for processing information received from the communication devices via the at least one eNB or gNB.

System 100 enables multiple wireless users to transmit and receive data and other content. The system 100 may implement one or more channel access methods, such as but not limited to code division multiple access (CDMA) , time division multiple access (TDMA) , frequency division multiple access (FDMA) , orthogonal FDMA (OFDMA) , or single-carrier FDMA (SC-FDMA) .

The user equipment (UE) 110A, 110B, and 110C, which can be referred to individually as an UE 110, or collectively as the UEs 110, are configured to operate and/or communicate in the system 100. For example, a UE 110 can be configured to transmit and/or receive wireless signals or wired signals. Each UE 110 represents any suitable end user device and may include such devices (or may be referred to) as a user equipment/device, wireless transmit/receive unit (UE) , mobile station, fixed or mobile subscriber unit, pager, cellular telephone, personal digital assistant (PDA) , smartphone, laptop, computer, touchpad, wireless sensor, wearable devices, such as virtual reality headsets, or consumer electronics device.

In the depicted embodiment, the

RANs

120A, 120B include one or more base stations (BSs) 170A, 170B, respectively. The

RANs

120A and 120B can be referred to individually as a RAN 120, or collectively as the RANs 120. Similarly, the base stations (BSs) 170A and 170B can be referred individually as a base station (BS) 170, or collectively as the base stations (BSs) 170. Each of the BSs 170 is configured to wirelessly interface with one or more of the UEs 110 to enable access to the core network 130, the PSTN 140, the Internet 150, and/or the other networks 160. For example, the base stations (BSs) 170 may include one or more of several well-known devices, such as a base transceiver station (BTS) , a Node-B (NodeB) , an evolved NodeB (eNB) , a next (fifth) generation (5G) NodeB (gNB) , a Home NodeB, a Home eNodeB, a site controller, an access point (AP) , or a wireless router, or a server, router, switch, or other processing entity with a wired or wireless network.

In one embodiment, the BS 170A forms part of the RAN 120A, which may include one or more other BSs 170, elements, and/or devices. Similarly, the BS 170B forms part of the RAN 120B, which may include one or more other BSs 170, elements, and/or devices. Each of the BSs 170 operates to transmit and/or receive wireless signals within a particular geographic region or area, sometimes referred to as a “cell. ” In some embodiments, multiple-input multiple-output (MIMO) technology may be employed having multiple transceivers for each cell.

The BSs 170 communicate with one or more of the UEs 110 over one or more air interfaces (not shown) using wireless communication links. The air interfaces may utilize any suitable radio access technology.

It is contemplated that the system 100 may use multiple channel access functionality, including for example schemes in which the BSs 170 and UEs 110 are configured to implement the Long Term Evolution wireless communication standard (LTE) , LTE Advanced (LTE-A) , and/or LTE Multimedia Broadcast Multicast Service (MBMS) . In other embodiments, the base stations 170 and user equipment 110A-110C are configured to implement UMTS, HSPA, or HSPA+ standards and protocols. Of course, other multiple access schemes and wireless protocols may be utilized.

The RANs 120 are in communication with the core network 130 to provide the UEs 110 with voice, data, application, Voice over Internet Protocol (VoIP) , or other services. As appreciated, the RANs 120 and/or the core network 130 may be in direct or indirect communication with one or more other RANs (not shown) . The core network 130 may also serve as a gateway access for other networks (such as PSTN 140, Internet 150, and other networks 160) . In addition, some or all of the UEs 110 may include functionality for communicating with different wireless networks over different wireless links using different wireless technologies and/or protocols.

The RANs 120 may also include millimeter and/or microwave access points (APs) . The APs may be part of the BSs 170 or may be located remote from the BSs 170. The APs may include, but are not limited to, a connection point (an mmW CP) or a BS 170 capable of mmW communication (e.g., a mmW base station) . The mmW APs may transmit and receive signals in a frequency range, for example, from 24 GHz to 100 GHz, but are not required to operate throughout this range. As used herein, the term base station is used to refer to a base station and/or a wireless access point.

Although FIG. 1 illustrates one example of a communication system, various changes may be made to FIG. 1. For example, the communication system 100 could include any number of user equipment, base stations, networks, or other components in any suitable configuration. It is also appreciated that the term user equipment may refer to any type of wireless device communicating with a radio network node in a cellular or mobile communication system. Non-limiting examples of user equipment are a target device, device-to-device (D2D) user equipment, machine type user equipment or user equipment capable of machine-to-machine (M2M) communication, laptops, PDA, iPad, Tablet, mobile terminals, smart phones, laptop embedded equipped (LEE) , laptop mounted equipment (LME) and USB dongles.

FIG. 2 illustrates example details of an UE 110 that may implement the methods and teachings according to this disclosure. The UE 110 may for example be a mobile telephone, but may be other devices in further examples such as a desktop computer, laptop computer, tablet, hand-held computing device, automobile computing device and/or other computing devices. As shown in the figure, the example UE 110 is shown as including at least one transmitter 202, at least one receiver 204, memory 206, at least one processor 208, and at least one input/output device 212. The processor 208 can implement various processing operations of the UE 110. For example, the processor 208 can perform signal coding, data processing, power control, input/output processing, or any other functionality enabling the UE 110 to operate in the system 100 (FIG. 1) . The processor 208 may include any suitable processing or computing device configured to perform one or more operations. For example, the processor 208 may include a microprocessor, microcontroller, digital signal processor, field programmable gate array, or application specific integrated circuit.

The transmitter 202 can be configured to modulate data or other content for transmission by at least one antenna 210. The transmitter 202 can also be configured to amplify, filter and a frequency convert RF signals before such signals are provided to the antenna 210 for transmission. The transmitter 202 can include any suitable structure for generating signals for wireless transmission.

The receiver 204 can be configured to demodulate data or other content received by the at least one antenna 210. The receiver 204 can also be configured to amplify, filter and frequency convert RF signals received via the antenna 210. The receiver 204 can include any suitable structure for processing signals received wirelessly. The antenna 210 can include any suitable structure for transmitting and/or receiving wireless signals. The same antenna 210 can be used for both transmitting and receiving RF signals, or alternatively, different antennas 210 can be used for transmitting signals and receiving signals.

It is appreciated that one or multiple transmitters 202 could be used in the UE 110, one or multiple receivers 204 could be used in the UE 110, and one or multiple antennas 210 could be used in the UE 110. Although shown as separate blocks or components, at least one transmitter 202 and at least one receiver 204 could be combined into a transceiver. Accordingly, rather than showing a separate block for the transmitter 202 and a separate block for the receiver 204 in FIG. 2, a single block for a transceiver could have been shown.

The UE 110 further includes one or more input/output devices 212. The input/output devices 212 facilitate interaction with a user. Each input/output device 212 includes any suitable structure for providing information to or receiving information from a user, such as a speaker, microphone, keypad, keyboard, display, or touch screen.

In addition, the UE 110 includes at least one memory 206. The memory 206 stores instructions and data used, generated, or collected by the UE 110. For example, the memory 206 could store software or firmware instructions executed by the processor (s) 208 and data used to reduce or eliminate interference in incoming signals. Each memory 206 includes any suitable volatile and/or non-volatile storage and retrieval device (s) . Any suitable type of memory may be used, such as random access memory (RAM) , read only memory (ROM) , hard disk, optical disc, subscriber identity module (SIM) card, memory stick, secure digital (SD) memory card, and the like.

FIG. 3 illustrates an example BS 170 that may implement the methods and teachings according to this disclosure. As shown in the figure, the BS 170 includes at least one processor 308, at least one transmitter 302, at least one receiver 304, one or more antennas 310, and at least one memory 306. The processor 308 implements various processing operations of the BS 170, such as signal coding, data processing, power control, input/output processing, or any other functionality. Each processor 308 includes any suitable processing or computing device configured to perform one or more operations. Each processor 308 could, for example, include a microprocessor, microcontroller, digital signal processor, field programmable gate array, or application specific integrated circuit.

Each transmitter 302 includes any suitable structure for generating signals for wireless transmission to one or more UEs 110 or other devices. Each receiver 304 includes any suitable structure for processing signals received wirelessly from one or more UEs 110 or other devices. Although shown as separate blocks or components, at least one transmitter 302 and at least one receiver 304 could be combined into a transceiver. Each antenna 310 includes any suitable structure for transmitting and/or receiving wireless signals. While a common antenna 310 is shown here as being coupled to both the transmitter 302 and the receiver 304, one or more antennas 310 could be coupled to the transmitter (s) 302, and one or more separate antennas 310 could be coupled to the receiver (s) 304. Each memory 306 includes any suitable volatile and/or non-volatile storage and retrieval device (s) .

Certain embodiments of the present technology described herein can be implemented using hardware, software, or a combination of both hardware and software. The software used is stored on one or more of the processor readable storage devices described above to program one or more of the processors to perform the functions described herein. The processor readable storage devices can include computer readable media such as volatile and non-volatile media, removable and non-removable media. By way of example, and not limitation, computer readable media may comprise computer readable storage media and communication media. Computer readable storage media may be implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. Examples of computer readable storage media include RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. A computer readable medium or media does (do) not include propagated, modulated or transitory signals.

Communication media typically embodies computer readable instructions, data structures, program modules or other data in a propagated, modulated or transitory data signal such as a carrier wave or other transport mechanism and includes any information delivery media. The term “modulated data signal” means a signal that has one or more of its characteristics set or changed in such a manner as to encode information in the signal. By way of example, and not limitation, communication media includes wired media such as a wired network or direct-wired connection, and wireless media such as RF and other wireless media. Combinations of any of the above are also included within the scope of computer readable media.

In alternative embodiments, some or all of the software can be replaced by dedicated hardware logic components. For example, and without limitation, illustrative types of hardware logic components that can be used include Field-programmable Gate Arrays (FPGAs) , Application-specific Integrated Circuits (ASICs) , Application-specific Standard Products (ASSPs) , System-on-a-chip systems (SOCs) , Complex Programmable Logic Devices (CPLDs) , special purpose computers, etc. In one embodiment, software (stored on a storage device) implementing one or more embodiments is used to program one or more processors. The one or more processors can be in communication with one or more computer readable media/storage devices, peripherals and/or communication interfaces.

FIG. 4 illustrates details for an example of a receiver 404, which can be the receiver 204 included in the UE 110 (shown in FIG. 2) or the receiver 304 included in the BS 170 (shown in FIG. 3) , but is not limited thereto. Referring to FIG. 4, the receiver 404 is shown as including an input 406 at which is received as a radio frequency (RF) signal, and thus, the input 406 can also be referred to as the RF input 406. The RF input 406 can be coupled to an antenna or a coupler, but is not limited thereto. The RF signal received by the RF input 406 is provided to a low noise amplifier (LNA) 408, which may have an adjustable gain. The LNA 408 amplifies the relatively low-power RF signal it receives without significantly degrading the signal’s signal-to-noise ratio (SNR) . The amplified RF signal that is output by the LNA 408 is provided to a mixer 410. The mixer 410, in addition to receiving the amplifier RF signal from the LNA 408, also receives an oscillator signal LO from a local oscillator, and adjusts the frequency of the amplifier RF signal, e.g., from first frequency to a second frequency that is lower than the first frequency. More specifically, the mixer 410 can be a down-mixer (DN MIX) that frequency down-converts the amplified RF signal from a relatively high frequency to a baseband frequency, or an intermediate frequency (IF) that is offset from the baseband frequency.

In some embodiments, an attenuator circuit may be used in the RF path of receiver 404, such as between the antenna 310 and RF input 406 or on the receiver circuit 404 between the RF input 406 and the down-mixer 410. This may be used, for example, the receiver is for a short range wireless network that can experience relatively high RF input signals when the receiver and transmitter are in close proximity. In the particular embodiment shown in FIG. 4, an attenuator circuit Attn 433 is located between RF input 406 and LNA 408 and can be incorporated on-chip, on the same integrated circuit as the other elements of 404.

Still referring to FIG. 4, the frequency down-converted RF signal that is output from the mixer 410 is shown as being provided to a trans-impedance amplifier (TIA) 412. The TIA 412 acts as a current buffer to isolate a multi-feedback (MFB) filter 414 that is downstream of the TIA 412, from the mixer 410 that is upstream of the TIA 412. The MBF filter 414 low pass filters the frequency down-converted RF signal, to filter out high frequency signal components that are not of interest, such as HF noise. The filtered RF signal that is output from the MBF filter 414 is provided to a variable gain amplifier (VGA) 416, which is used to amplify the RF signal before it provided to an analog-to-digital converter (A/D) 418, which converts the RF signal from an analog signal to a digital signal. The digital signal output from the A/D 418 is then provided to a digital filter 420, which performs additional filtering to remove out of band signal components and attenuates quantization energy from the A/D 418. The filtered digital signal that is output by the digital filter 420 is then provided to further digital circuitry that is downstream from the digital filter 420. Such further digital circuity can include, for example, a digital signal processor (DSP) , but is not limited thereto. The same DSP, or a different DSP, can be used to implement the digital filter 420.

The local oscillator signal LO in FIG. 4 can be provided by a voltage controlled oscillator VCO system 431, which is frequently incorporated into a phase locked loop. The LO signal is provided to the mixer 410 for use in the down-conversion process. Although shown as outside of receiver 404, depending on the embodiment, the VCO system 431 can be formed on the same integrated circuit as one or more of the other elements in FIG. 4.

FIG. 5 illustrates details of one example of a transmitter 502, which can be the transmitter 202 included in the UE 110 (shown in FIG. 2) or the transmitter 302 included in the BS 170 (shown in FIG. 3) , but is not limited thereto. Referring to FIG. 5, the transmitter 502 is shown as including an output 518 at which is provided as a radio frequency (RF) signal, and thus, the output 518 can also be referred to as the RF output 518. The RF output 518 can be coupled to an antenna or a coupler, but is not limited thereto. The RF signal provided by the RF output 518 is provided from a power amplifier PA 514 though the bandpass or notch filter 516. The filter 516 can, for example, be a duplex/SAW filter and is used to remove unwanted frequency components above and below the desired RF frequency range from the amplified RF output signal generated by PA 514. The power amp PA 514 receives its input from a power pre-amplifier PPA 512, which initially receives the up-converted signal to be transmitted from the mixer 510.

Still referring to FIG. 5 the signal to be transmitted is received from the processor 208 of UE 110 of FIG. 2 or processor 308 of BS 170 of FIG. 3 at the digital to analog converter 506, with the digitized signal being filtered by low pass filter 508 to initially remove any high frequency noise before being up-converted at the mixer 510. The mixer 510, in addition to receiving the analog version of the signal, typically an intermediate frequency (IF) signal, from the low pass filter 508, also receives an oscillator signal LO from a local oscillator VCO 531, and adjusts the received IF signal, e.g., from first frequency to a second frequency that is higher than the first frequency. More specifically, the mixer 510 can be an up-mixer (UP MIX) that frequency up-converts the IF signal to an RF signal.

In some embodiments, an attenuator circuit ican be included in the RF path of transmitter 502, such as between the antenna 310 and RF output 518 or on the receiver circuit 502 between the RF output 518 and the up-mixer 510, if the receiver may need to attenuate the RF signal at some stage. In the particular embodiment shown in FIG. 5, an attenuator circuit Attn 533 is located between up-mixer 510 and PPA 512 and can be incorporated on-chip, on the same integrated circuit as the other elements of 502. Attenuator circuits, such as Attn 433 and Attn 533 of FIGS. 4 and 5, are discussed in more detail with respect to FIGS. 6-10.

More specifically, FIGS. 6-10 illustrate embodiments of signal attenuators that can be used with RF signals, such as those at millimeter wavelengths (e.g., 60 GHz, or, more generally the super-to extremely-high frequency ranges of 3-300GHz) . Specific embodiments use 90 degree hybrid couplers to create an on-chip signal attenuator for millimeter wavelength applications that can incorporate programmable, self-calibrating resistors to achieve a constant attenuation in presence of process and temperature variations.

The designs presented can be programmable across a wide range of attenuation levels, such as from 0dB to 12dB. Although there are different existing architectures that can realize similar ranges of attenuation, these architectures cannot easily maintain stable input and output impedances without having significant loss at millimeter wave frequencies. Not having predictable and stable input and output impedances results in impedance mismatches, power loss, in-band ripple, and signal reflection. The embodiments presented below can provide the required amounts of attenuation without changing the input and output impedances of attenuation circuits.

In addition to controlling the input and output impedances, it is very difficult to generate constant attenuation in the presence of temperature variations and process deviations. Having a constant attenuation from a transceiver or other applications of the attenuation circuit is desirable at any ambient temperature, regardless of the integrated circuit (IC) process deviation. The process variations when devices get down to range of tens of nanometers (e.g., a 28 nm CMOS process) can be significant and could affect the performance of the transceiver or other device using an attenuator if the signal level out of the attenuator circuit is unpredictable and has large variations. The embodiments presented here can provide the required amounts of attenuation while being insensitive to temperature and process variations.

The embodiments of FIGS. 6 and 7 illustrate an architecture of a balanced attenuator that uses of two passive 90° hybrid couplers for a single-ended design with two variable resistors in between. The embodiments of FIG. 9 illustrate an embodiment with four couplers for a differential input design. FIG. 8 illustrates embodiments of a calibration circuit that can be incorporated into these embodiments in order to eliminate the influence of process and temperature variations of the variable resistors (such as n-channel field effect transistors (NFETs) ) on the attenuation.

FIG. 6 illustrates a single-ended embodiment of an attenuation circuit 633, receiving an RF input RFin and providing an attenuated RF output RFout. The RF input RFin is received at a first input of a hybrid coupler 611, whose second input is connected to ground through a resistor 617. In this example, the hybrid coupler 611 is a 90° hybrid coupler that splits the input signal to provide a quadrature output of two intermediate RF signals with a 90° difference at its two outputs. The two intermediate RF signals are received at the two inputs of a second hybrid coupler 613 that combines the two intermediate RF signals to be in phase and provide the RF output RFout, where in this example the second hybrid coupler 613 will also be a 90° hybrid coupler. RFout is provided from a first of the outputs of the 90° hybrid coupler 613, whose second output is connected to ground through the resistor 617.

The two intermediate RF signals internal to the attenuator are each connected to ground though a respective

variable resistor

621 or 623. As discussed further with respect to FIG. 8, the

variable resistors

621 and 623 can implemented by multiple transistors connected between the corresponding intermediate signal line and ground, where an amount of attenuation can be varied by configuring the number of these transistors that are connected to the corresponding intermediate signal line.

The attenuator of FIG. 6 achieves the desired attenuation by using the 90°

hybrid couplers

611 and 613. The attenuator 633 can provide 0 dB to 12 dB attenuation, for example, without changing the input and output impedances of the structure by placing two

variable resistors

621 and 623 between two 90°

hybrid couplers

611 and 613. These on-

chip hybrid couplers

611 and 613 can be designed to operate at 60 GHz and similar frequencies, where their task is to isolate the

variable resistors

621 and 623 from the input port of hybrid coupler 611 and the output port of hybrid coupler 613. As a result, the network of attenuator 633 maintains stable input and output impedances and can provide the desired attenuation (e.g., 0 dB to 12 dB) without affecting the input and output impedances of the network.

The embodiment for an attenuator circuit 733 of FIG. 7 adds a resistor calibration circuit 725 to the embodiment of FIG. 6. As in FIG. 6, a first 90° hybrid coupler 711 has a first input connected to receive RFin and a second input connected to ground through a resistor 715. The intermediate RF signals internal to the attenuator from the outputs of the first hybrid coupler 711 have a phase difference of 90° and are received from the internal lines carrying them at the inputs of the second 90° hybrid coupler 713. At the second 90° hybrid coupler 713, the attenuated internal signals are combined to be in phase and provided at a first output of the second 90° hybrid coupler 713. The second output of the second 90° hybrid coupler 713 is connected to ground through resistor 717.

Variable resistors

721 and 723 are connected between corresponding ones of the internal RF signals lines and ground.

The

variable resistors

721 and 723 can each be implemented by using multiple switchable NFET or other transistors connected in parallel to ground. Switching the transistors on and off would result in a variable resistance. The transistors adding to the resistance of the

variable resistors

721 and 723 can be controlled by a variable gate voltage Vgate from a control circuit, here the resistor calibration circuit 725. The resistor calibration circuit 725 provides the gate voltage Vgate that can account for temperature variations and process deviations, resulting in a fixed resistance independent of variations in temperature and process. FIG. 8 illustrates an embodiment for the resistor calibration circuit 725 and the variable resistances of 621/721 and 623/723.

FIG. 8 illustrates an embodiment where a variable resistor 821 is made up of multiple “sub-resistors” , with detail shown for the one represented at front as 821-a. The other sub-resistors (821-b, 821-c, …) can similarly formed and the number of such sub-resistors 821-i can vary depending on the embodiment and the range of attenuation levels desired. As shown for sub-resistor 821-a, a transistor 843-i is connected between the corresponding internal RF signal line and ground. The amount of attenuation can be configured by using a switch SWi 841-i to selectively connect the gate of transistor 843-i either to ground, in which case the sub-resistor does not contribute to the total resistance of 821, or to Vgate, in which case it will contribute. By trimming the resistance of resistor 821 based on how the switches SWi 841-i are connected, the resistor 821 can configured for a given amount of attenuation. The transistors 843-i are of the same type, such as the NFETs illustrated FIG. 8, or a different type, but should be of the same type as each other and as transistor 837, as discussed further below. Depending on the embodiment, the transistors 843-i can all be sized the same or sized differently. For example, if transistor 843-i is sized to give a resistance of Ri for sub-resistor 821-i, these could be sized such that Rb=2Ra, Rc=2Rb and so on, in a binary digit sort of arrangement. In other embodiments, all of the transistors 843-i can be formed to be the same, as this will provide for the transistors to have more processing uniformity.

The Vgate voltage is generated by the resistor calibration circuit 825. In the shown embodiment, a difference amplifier 835 has an output connected to the control gate of a transistor 833. The transistor 833 is connected through a current source 831 to a high voltage level for the integrated circuit and connected to ground through the transistor 837. A first input (+ input) of the difference amplifier 835 is connected to receive a reference voltage Vref, such as can be provided by a band gap circuit. The second input (-input) of difference amplifier 835 is connected to receive feedback from a node between transistor 833 and transistor 837. Current source 831 provides a reference current Iref.

The transistor 837 is located between the feedback node for the difference amplifier 835 and ground. The transistor 837 is formed to be of the same type as the transistors 843-i. In the embodiment of FIG. 8, these are shown as NFETs, but other device types can be used. The transistor 837 is also formed to be sized the same as the transistors 843-i, or, if the transistors 843-i are sized differently, they should be formed to be in a determined size ratio relative to transistor 837 so that the variable resistance value can be accurately trimmed. By having the transistor 837 of the same type and sized the same as the transistors 843-i, these devices will behave similar with respect to process and temperature variations.

By providing a gate voltage Vgate that varies over temperature variations and process deviations, when the transistor 837 is on the resistor calibration circuit 825 will calibrate the transistor 837 to maintain a fixed resistance. This fixed resistance results in a fixed attenuation by the resistor 821 independent of variations in temperature and process. The resistor calibration circuit 825 generates the required gate voltage Vgate depending on the operating temperature and processing. The calibration circuit loop generates the appropriate gate voltage Vgate by forcing a fixed reference voltage across a replica transistor 837 of the resistor 821 transistors 843-i, forcing a fixed reference current Iref through transistor 837. The gate voltage of transistor 837 is set so that its resistance is R = Vref/Iref, where Vref and Iref can vary as long as the ratio is maintained. This gate voltage Vgate is then applied to the transistors 843-i (for those whose gates are not set to ground) of variable resistor 821.

FIG. 9 illustrates an embodiment for a differential input attenuator design, having the inputs RFin+ and RFin-and generating the differential outputs RFout+ and RFout-. The + attenuation path and –attenuation path each can use a leg formed similarly to the single-ended embodiment of FIG. 6, with a shared resistor calibration circuit 925 for the shared variable resistors of both legs.

Considering FIG. 9 in more detail, a first leg includes a first 90° hybrid coupler 911 configured to receive the RFin+ signal at a first input and having its second input connected through a resistor 915 to the second input of the first 90° hybrid coupler 941 of the second leg, rather than ground as for the corresponding element of FIG. 7. The first 90° hybrid coupler 911 generates first and second internal RF+ waveforms that are provided over corresponding internal signal lines to the inputs of the second 90° hybrid coupler 913. The second 90° hybrid coupler 913 combines the two internal signals to be in phase to provide the RFout+ signal at a first output of second 90° hybrid coupler 913. The second output of the second 90° hybrid coupler 913 is connected through resistor 917 second output of the second 90° hybrid coupler 943 of the second leg, rather than ground as for the corresponding element of FIG. 7. The first and second internal RF+ waveforms are attenuated by corresponding

variable resistors

921 and 923, that can be implemented as described with respect to resistor 821 of FIG. 8. Rather than the

variable resistors

921 and 923 being connected to ground on the other end, as in the corresponding elements of FIG. 7, they are each connected between the corresponding internal lines of the two legs.

In the similarly arranged second leg, a first 90° hybrid coupler 941 is configured to receive the RFin-signal at a first input and has its second input connected through resistor 915 to the corresponding input of the first leg. The first 90° hybrid coupler 941 generates first and second internal RF-waveforms that are provided over corresponding internal signal lines to the inputs of the second 90° hybrid coupler 943. The second 90° hybrid coupler 943 combines the two internal signals to be in phase to provide the RFout-signal at a first output of second 90° hybrid coupler 943, whose second output is connected through resistor 917 to the corresponding output of the upper leg. The first and second internal RF-waveforms are attenuated by corresponding

variable resistors

921 and 923 that are connected between the corresponding internal lines of the two legs.

The

variable resistors

921 and 923 are connected to a common resistor calibration circuit 925 to receive the same Vgate level. The resistor calibration circuit 925 can use an embodiment such as the resistor calibration circuit 825 of FIG. 8. The general operation of the differential embodiment of FIG. 9 can be as described with respect to FIGS. 6-8 for the single-ended embodiments, but duplicated for the two legs of the differential input.

FIG. 10 is a high-level flow diagram that is used to summarize methods for operating of a self-calibrating balanced attenuator. The flow of FIG. 10 will be described with respect to the embodiments illustrated in FIGS. 7 and 8.

Starting at 1001, an input waveform RFin is received at the first 90° hybrid coupler 711, where it is split into the first and second intermediate waveforms at 1003. For the first 90° hybrid coupler 711 of FIG. 7, the two intermediate RF signals will be quadrature signals 90° out of phase. At 1005, the first and second intermediate waveforms are recombined to be in phase and form the attenuated RF output by the second 90° hybrid coupler 713 at 1005.

In between the first 90° hybrid coupler 711 and the second 90° hybrid coupler 713, at 1007 the first intermediate waveform is attenuated by the variable resistor 721 connected between the internal line of attenuator 733 carrying the first intermediate waveform and ground. At 1009, the second intermediate waveform is attenuated by the variable resistor 723 connected between the internal line of attenuator 733 carrying the second intermediate waveform and ground. The amount of attenuation from the

variable resistors

721 and 723 can have been previously configured by trimming the individual sub-resistors to set the gates of their respective transistors either to ground or to receive Vgate, as described above with respect to FIG. 8.

During the attenuating of the input waveform at 1001-1009, at 1011 the value of the first variable resistor 721 and the second variable resistor 723 can be set by the resistor calibration circuit 725 at 1001 according to the reference value of R=Vref/Iref, as described above with respect to FIG. 8.

The embodiments described above allow for the described attenuators to provide constant attenuation independently of process variations and operating temperature. The utilization of on-chip hybrid couplers provides stable and predictable input and output impedances of the attenuator at millimeter wavelength frequencies (e.g., 60 GHz) . By incorporating a resistor calibration circuit, the system can achieve temperature and process independent performance. In addition to wireless communication devices such as cellular telephones, the embodiments described above can also be applied to applications such as virtual-reality headsets and short distance wireless networks

It is understood that the present subject matter may be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this subject matter will be thorough and complete and will fully convey the disclosure to those skilled in the art. Indeed, the subject matter is intended to cover alternatives, modifications and equivalents of these embodiments, which are included within the scope and spirit of the subject matter as defined by the appended claims. Furthermore, in the following detailed description of the present subject matter, numerous specific details are set forth in order to provide a thorough understanding of the present subject matter. However, it will be clear to those of ordinary skill in the art that the present subject matter may be practiced without such specific details.

Aspects of the present disclosure are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatuses (systems) and computer program products according to embodiments of the disclosure. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable instruction execution apparatus, create a mechanism for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks.

The description of the present disclosure has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the disclosure in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the disclosure. The aspects of the disclosure herein were chosen and described in order to best explain the principles of the disclosure and the practical application, and to enable others of ordinary skill in the art to understand the disclosure with various modifications as are suited to the particular use contemplated.

The disclosure has been described in conjunction with various embodiments. However, other variations and modifications to the disclosed embodiments can be understood and effected from a study of the drawings, the disclosure, and the appended claims, and such variations and modifications are to be interpreted as being encompassed by the appended claims. In the claims, the word “comprising” does not exclude other elements or steps, and the indefinite article “a” or “an” does not exclude a plurality.

For purposes of this document, it should be noted that the dimensions of the various features depicted in the figures may not necessarily be drawn to scale.

For purposes of this document, reference in the specification to “an embodiment, ” “one embodiment, ” “some embodiments, ” or “another embodiment” may be used to describe different embodiments or the same embodiment.

For purposes of this document, a connection may be a direct connection or an indirect connection (e.g., via one or more other parts) . In some cases, when an element is referred to as being connected or coupled to another element, the element may be directly connected to the other element or indirectly connected to the other element via intervening elements. When an element is referred to as being directly connected to another element, then there are no intervening elements between the element and the other element. Two devices are “in communication” if they are directly or indirectly connected so that they can communicate electronic signals between them.

For purposes of this document, the term “based on” may be read as “based at least in part on. ”

For purposes of this document, without additional context, use of numerical terms such as a “first” object, a “second” object, and a “third” object may not imply an ordering of objects, but may instead be used for identification purposes to identify different objects.

The foregoing detailed description has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the subject matter claimed herein to the precise form (s) disclosed. Many modifications and variations are possible in light of the above teachings. The described embodiments were chosen in order to best explain the principles of the disclosed technology and its practical application to thereby enable others skilled in the art to best utilize the technology in various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope be defined by the claims appended hereto.

Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.

Claims

A radio frequency (RF) integrated circuit, comprising:

an attenuator, comprising:

a first variable resistor configured to provide a settable amount of attenuation for a first internal signal;

a second variable resistor configured to provide a settable amount of attenuation for a second internal signal;

a first 90 degree hybrid coupler configured to receive an RF input signal at a first input port and generating the first internal signal and the second internal signal, wherein the first 90 degree hybrid coupler isolates the first variable resistor and the second variable resistor from the first input port; and

a second 90 degree hybrid coupler configured to receive the first internal signal at the first input port and the second internal signal at a second input port and outputting an RF output signal from a combination of the first internal signal and the second internal signal at a first output port, wherein the second 90 degree hybrid coupler isolates the first variable resistor and the second variable resistor from the first output port.
The RF integrated circuit of claim 1, the attenuator further comprising:

a control circuit configured to control a value of the resistance of the first variable resistor and the second variable resistor to provide constant attenuation across process and temperature variations.
The RF integrated circuit of any of claims 1-2, wherein the first variable resistor and the second variable resistor are configurable to provide from 0dB to 12dB attenuation for an RF input signal in the millimeter range.
The RF integrated circuit of any of any of claims 1-3, wherein the first variable resistor is connected between a first internal transmission line, through which the second 90 degree hybrid coupler is configured to receive the first internal signal, and ground,

the second variable resistor is connected between a second internal transmission line, through which the second 90 degree hybrid coupler is configured to receive the second internal signal, and ground, and

each of the first variable resistor and the second variable resistor comprise one or more transistors having a gate configured to receive a control voltage from the control circuit.
The RF integrated circuit of any of claims 1-4, wherein the control circuit is configured to receive a reference voltage and a reference current and to generate the control voltage in response to the reference voltage and the reference current.
The RF integrated circuit of any of claims 1-5, wherein the control circuit comprises:

a current source configured to provide the reference current;

a first transistor connected between the current source and ground;

a second transistor through which the first transistor is connected to ground, wherein a control gate of the second transistor is connected between current source and first transistor, the control voltage corresponding to a voltage level on the control gate of the second transistor; and

a difference amplifier having a first input connected to the reference voltage, a second input connected between the first transistor and the second transistor, and having an output connected to a gate of the first transistor.
The RF integrated circuit of any of claims 1-6, wherein the one or more transistors of the first variable resistor and second variable resistor are formed to be sized the same as the second transistor of the control circuit.
The RF integrated circuit of any of any of claims 1-7, further comprising:

a band gap circuit configured to provide the reference voltage.
The RF integrated circuit of any of any of claims 1-8, wherein:

the first variable resistor comprises a plurality of transistors connected in parallel between the first internal transmission line and ground, each having a gate selectively connectable to receive the control voltage; and

the second variable resistor comprises a plurality of transistors connected in parallel between the second internal transmission line and ground, each having a gate selectively connectable to receive the control voltage.
The RF integrated circuit of any of claims 1-9, wherein the attenuator is part of a receiver circuit.
The RF integrated circuit of any of claims 1-10, wherein the attenuator is part of a transmitter circuit.
A programmable attenuator, comprising:

a first leg comprising:

a first hybrid coupler having a first input connected to receive a first input waveform and generate therefrom a first intermediate waveform and a second intermediate waveform having a phase difference relative to the first intermediate waveform;

a second hybrid coupler configured to receive the first intermediate waveform and the second intermediate waveform, the second hybrid coupler configured to generate at a first output a first output waveform combining the first intermediate waveform in phase with the second intermediate waveform;

a first variable resistor connected between ground and a line through which the first intermediate waveform is supplied from the first hybrid coupler to the second hybrid coupler; and

a second variable resistor connected between ground and a line through which the second intermediate waveform is supplied from the first hybrid coupler to the second hybrid coupler; and

a resistor calibration circuit configured to set a resistance value for the first variable resistor and a resistance value for the second variable resistor to provide constant attenuation across process and temperature variations.
The programmable attenuator of claim 12, wherein:

the first variable resistor comprises a plurality of first resistances selectively connectable in parallel between ground and the line through which the first intermediate waveform is supplied from the first hybrid coupler to the second hybrid coupler; and

the second variable resistor comprises a plurality of second resistances selectively connectable in parallel between ground and the line through which the first intermediate waveform is supplied from the first hybrid coupler to the second hybrid coupler.
The programmable attenuator of any of claims 12-13, wherein each of the first resistances and the second resistances comprise a transistor having a control gate selectively connectable to receive a control gate voltage from the resistor calibration circuit.
The programmable attenuator of any of claims 12-14, wherein the resistor calibration circuit comprises:

a current source configured to provide a reference current;

a first transistor connected between the current source and ground;

a second transistor through which the first transistor is connected to ground, wherein a control gate of the second transistor is connected between current source and first transistor, the control gate voltage corresponding to a voltage level on the control gate of the second transistor; and

a difference amplifier having a first input connected to a reference voltage, a second input connected between the first transistor and the second transistor, and having an output connected to a gate of the first transistor.
The programmable attenuator of any of claims 12-15, wherein the programmable attenuator is configured to receive a radio frequency (RF) first input waveform and the first variable resistor and the second variable resistor are configurable to provide from 0dB to 12dB attenuation for the RF input waveform.
The programmable attenuator of any of claims 12-16, wherein the RF first input waveform is in the millimeter range.
The programmable attenuator of any of claims 12-17, wherein the first hybrid coupler and the second hybrid coupler are each 90 degree hybrid couplers.
The programmable attenuator of any of claims 12-18, wherein the first leg further includes:

a first fixed value resistance through which a second input of the first hybrid coupler is connected to ground; and

a second fixed value resistance through which a second output of the second hybrid coupler is connected to ground.
The programmable attenuator of any of claims 12-19, wherein the first input waveform is a first waveform of a differential input waveform, the programmable attenuator further comprising:

a second leg comprising:

a third hybrid coupler having a first input connected to receive a second waveform of a differential input waveform and generate therefrom a third intermediate waveform and a fourth intermediate waveform having a phase difference relative to the third intermediate waveform;

a fourth hybrid coupler configured to receive the third intermediate waveform and the fourth intermediate waveform, the fourth hybrid coupler configured to generate at a first output a second output waveform combining the third intermediate waveform in phase with the fourth intermediate waveform;

a third variable resistor connected between ground and a line through which the third intermediate waveform is supplied from the third hybrid coupler to the fourth hybrid coupler; and

a fourth variable resistor connected between ground and a line through which the fourth intermediate waveform is supplied from the third hybrid coupler to the fourth hybrid coupler,

wherein the resistor calibration circuit is further configured to set a resistance value for the third variable resistor and the fourth variable resistor to provide constant attenuation across process and temperature variations.
A method, comprising:

receiving an input waveform;

splitting the input waveform into a first intermediate waveform and a second intermediate waveform, the second intermediate wave having a phase difference relative to the first intermediate waveform;

recombining the first intermediate waveform and the second intermediate waveform, including removing the phase difference, to generate an output waveform;

attenuating the first intermediate waveform by a first resistor connected to ground;

attenuating the second intermediate waveform by a second resistor connected to ground; and

setting a value of the first resistor and a value of the second resistor according to a reference value.
The method of claim 21, further comprising:

generating by a calibration circuit of the reference value to set the value of the first resistor and the value of the second resistor to provide constant attenuation across process and temperature variations.
The method of any of claims 21-22, further comprising:

configuring the first resistor and the second resistor to provide an attenuation in a range of from 0dB to 12dB attenuation.
The method of any of claims 21-23, wherein the phase difference is 90 degrees.
The method of any of claims 21-24, wherein the input waveform is a radio frequency (RF) signal.
The method of any of claims 21-25, wherein the RF signal is in the millimeter range.
The method of any of claims 21-26, wherein the first resistor and the second resistor each comprise a number of one or more transistors connected in parallel and setting the value of the first resistor and the second resistor comprises generating a control gate voltage and applying the control gate voltage to a control gate of each of the transistors of the first resistor and the second resistor.
The method of any of claims 21-27, further comprising:

prior to generating the output waveform, configuring the number of transistors connected in parallel in the first resistor and the second resistor.
The method of any of claims 21-28, w herein setting the value of the first resistor and the value of the second resistor is performed prior to receiving the input waveform.
The method of any of claims 21-29, wherein setting the value of the first resistor and the value of the second resistor is performed as part of a trimming process based on an amplitude of the output waveform.