WO2020103132A1 - 一种像素电路、驱动方法及显示面板 - Google Patents

一种像素电路、驱动方法及显示面板

Info

Publication number
WO2020103132A1
WO2020103132A1 PCT/CN2018/117196 CN2018117196W WO2020103132A1 WO 2020103132 A1 WO2020103132 A1 WO 2020103132A1 CN 2018117196 W CN2018117196 W CN 2018117196W WO 2020103132 A1 WO2020103132 A1 WO 2020103132A1
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
module
electrode
driving
pixel circuit
Prior art date
Application number
PCT/CN2018/117196
Other languages
English (en)
French (fr)
Inventor
吴焕达
张祖强
Original Assignee
深圳市柔宇科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市柔宇科技有限公司 filed Critical 深圳市柔宇科技有限公司
Priority to CN201880096037.5A priority Critical patent/CN112703551A/zh
Priority to PCT/CN2018/117196 priority patent/WO2020103132A1/zh
Publication of WO2020103132A1 publication Critical patent/WO2020103132A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix

Definitions

  • the present invention relates to the field of driving display panels, and more particularly, to a pixel circuit, a driving method, and a display panel.
  • the pixel circuit in the AMOLED display can be composed of a 4T2C structure, that is, the traditional pixel circuit can be composed of four TFTs (thin film transistors), two capacitors, and a light-emitting diode.
  • the conventional 4T2C structure has a limited effect of compensating for the threshold voltage drift of the driving transistor T4, and the uniformity of the display screen brightness of the entire display panel is poor.
  • the technical problem to be solved by the present invention is to provide a pixel circuit, a driving method and a display panel which can improve the threshold voltage drift compensation of the driving transistor and improve the uniformity of the display bright bottom in view of the above-mentioned defects of the prior art.
  • the technical solution adopted by the present invention to solve its technical problem is to provide a pixel circuit including an input module, a compensation module, a driving module, and a light emitting module;
  • the first end of the input module is connected to the input signal, and the second end of the input module is connected to the first end of the drive module;
  • the first end of the light-emitting module is connected to the high-level input terminal, the second end of the light-emitting module is connected to the second end of the drive module; the third end of the drive module is connected to the first end of the compensation module , The fourth end of the drive module is connected to the low-level input terminal; the second end of the compensation module is connected to the low-level input terminal;
  • the input module is used to input a reference voltage according to the second scan signal and a data voltage according to the first scan signal; the compensation module is used to compensate the drive module when it is turned on; the drive module is used to turn on A driving signal is output at all times to drive the light emitting module to emit light; wherein, the input signal includes the reference voltage and the data voltage.
  • the present invention also provides a display panel including the pixel circuit described above.
  • the invention also provides a pixel circuit, including a first node, a second node, a compensation capacitor connected to the first node, a fifth transistor, and a driving transistor;
  • the gate of the driving transistor is connected to the first node, the drain of the driving transistor is connected to the second electrode of the light-emitting module through the fifth transistor, and the first electrode of the light-emitting module is connected to the high-level input terminal;
  • the source of the driving transistor is used to output the driving current to the low-level input terminal;
  • the voltage of the second node in the second stage is the data voltage Vdata
  • the voltage in the third stage is VSS
  • VSS is the low level received by the low-level input terminal Voltage
  • the voltage of the first node in the third stage is Vdata + Vth, where Vth is the threshold voltage of the driving transistor;
  • the pixel circuit uses a non-coupling compensation method to perform voltage compensation on the driving module, which can effectively improve the driving threshold voltage drift compensation and improve the uniformity of the display panel display brightness.
  • the pixel circuit has a simple structure and a small occupied area.
  • Figure 1 is a schematic diagram of the traditional 4T2C circuit
  • FIG. 2 is a circuit diagram of a first embodiment of a pixel circuit provided by the present invention.
  • FIG. 3 is a timing diagram of the pixel circuit of FIG. 2 of the present invention.
  • FIG. 4 is a circuit diagram of a second embodiment of a pixel circuit provided by the present invention.
  • FIG. 5 is a schematic flowchart of a driving method of a pixel circuit provided by the present invention.
  • FIG. 2 is a circuit diagram of a first embodiment of a pixel circuit provided by the present invention.
  • the pixel circuit can be applied to a display panel, and specifically can be disposed in a light emitting area of the display panel.
  • the display panel includes but is not limited to an AMOLED display panel, a TFT-LCD display panel, an LED display panel, and the like.
  • the pixel circuit includes an input module 10, a compensation module 30, a driving module 20, and a light emitting module 50.
  • the first end of the input module 10 is connected to the input signal, the second end of the input module 10 is connected to the first end of the drive module 20; the first end of the light emitting module 50 is connected to the high level input terminal (ELVDD), the second end of the light emitting module 50 Is connected to the second end of the drive module 20; the third end of the drive module 20 is connected to the first end of the compensation module 30, and the fourth end of the drive module 20 is connected to the low-level input terminal (ELVSS); the second end of the compensation module 30 Connect the low level input (ELVSS).
  • the input module 10 is used to input a reference voltage (Vref) according to the second scan signal (Scan2) and a data voltage (Vdata) according to the first scan signal (Scan1); the compensation module 30 is used to input the drive module 20 when it is turned on Compensation is performed; the driving module 20 is used to output a driving signal when turned on to drive the light emitting module 50 to emit light.
  • the input signal includes a reference voltage (Vref) and a data voltage (Vdata), and the reference voltage (Vref) is greater than the data voltage (Vdata).
  • the high-level input terminal (ELVDD) is used to receive a high-level input voltage (VDD), and the low-level input terminal (ELVSS) is used to receive a low-level input voltage (VSS).
  • the pixel circuit may further include a switch module 40 for conducting according to the fourth scan signal (Scan4), so that the driving module 20 and the light-emitting module 50 form a light-emitting circuit, and the light-emitting module 50 is controlled to emit light.
  • Scan4 fourth scan signal
  • the turning on or off of the compensation module 30 is controlled by the third scan signal (Scan3).
  • the first scan signal (Scan1), the second scan signal (Scan2), the third scan signal (Scan3), and the fourth scan signal (Scan4) are timing control signals of the pixel circuit, and these scan signals can be It is provided by other circuits inside the display panel, and can also be provided by the IC outside the display panel. The invention is not specifically limited.
  • the input module 10 includes: a second transistor T2 and a third transistor T3.
  • the first electrode of the second transistor T2 is connected to the second electrode of the driving transistor T1, the second electrode of the second transistor T2 is connected to the input signal, and the third electrode of the second transistor T2 is connected to the first scan signal (Scan1); the third transistor T3 Is connected to the first electrode of the driving transistor T1, the second electrode of the third transistor T3 is connected to the second electrode of the second transistor T2, and the third electrode of the third transistor T3 is connected to the second scan signal (Scan2); the second The first electrode of the transistor T2 and the first electrode of the third transistor T3 form the second end of the input module 10, and the second electrode of the second transistor T2 and the second electrode of the third transistor T3 are connected to form the input The first end of the module 10.
  • the driving module 20 includes a driving transistor T1.
  • the first electrode of the driving transistor T1 as the second end of the driving module 20 is connected to the second electrode of the fifth transistor T5, and the second electrode of the driving transistor T1 as the fourth end of the driving module 20 is connected to the first electrode of the sixth transistor T6.
  • the third electrode of the driving transistor T1 as the third end of the driving module 20 is connected to the first end of the compensation module 30 (that is, as shown in FIG. 2, the third electrode of the driving transistor T1 is connected to the first end of the compensation capacitor).
  • the first electrode and the second electrode of the driving transistor T1 are independently connected to the second end of the input module 10, wherein the first electrode and the second electrode of the driving transistor T1 form the first end of the driving module 20. That is, as shown in FIG. 2, the first electrode of the driving transistor T1 is connected to the first electrode of the third transistor T3, and the second electrode of the driving transistor T1 is connected to the first electrode of the second transistor T2 and the first electrode of the sixth transistor T6.
  • the driving transistor T1 is an N-type MOS transistor, the first electrode of the N-type driving transistor T1 is its drain, the second electrode of the N-type driving transistor T1 is its source, and the first electrode of the N-type driving transistor T1 The three electrodes are its gate.
  • the switch module 40 includes a fifth transistor T5 and a sixth transistor T6.
  • the first electrode of the fifth transistor T5 is connected to the second end of the light emitting module 50, the second electrode of the fifth transistor T5 is connected to the second end of the driving module 20 (ie, the first electrode of the driving transistor T1), and the fifth electrode of the fifth transistor T5
  • the three electrodes are connected to the fourth scan signal (Scan4); the first electrode of the sixth transistor T6 is connected to the fourth end of the drive module 20 (ie, the second electrode of the drive transistor T1), and the second electrode of the sixth transistor T6 is connected to the low level At the input terminal (ELVSS), the third electrode of the sixth transistor T6 is connected to the fourth scan signal (Scan4).
  • the compensation module 30 includes a compensation capacitor and a fourth transistor T4.
  • the first end of the compensation capacitor is connected to the first electrode of the fourth transistor T4, and the second end of the compensation capacitor is connected to the low-level input terminal (ELVSS); the second electrode of the fourth transistor T4 is connected to the second end of the driving module 20 (ie The first electrode of the driving transistor T1), the first electrode of the fourth transistor T4 and the first end of the compensation capacitor are connected as the first end of the compensation module 30 to the third end of the driving module 20 (ie the first end of the driving transistor T1) Three electrodes).
  • the second end of the compensation capacitor is the second end of the compensation module 30.
  • the light emitting module 50 may be a light emitting diode (OLED).
  • OLED light emitting diode
  • the driving transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are all N-type MOS transistors.
  • the timing control of the pixel circuit is shown in FIG. 3.
  • the driving transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are all P-type MOS transistors.
  • the driving transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are all P-type MOS transistors
  • the timing control potential of the pixel circuit is as shown in FIG. 3 'S potential just reversed.
  • the driving transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may be an N-type MOS tube and a P-type MOS tube, That is, in the driving transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6, there are N-type MOS transistors and P-type MOS transistors.
  • the pixel circuit includes three stages: a first stage, a second stage, and a third stage.
  • the first stage is an initialization stage
  • the second stage is a threshold voltage (Vth) compensation stage of the driving transistor T1
  • the third stage is a light-emitting stage of the light-emitting module 50.
  • the third transistor T3 and the fourth transistor T4 are turned on, the fifth transistor T5 and the sixth transistor T6 are turned off; the reference voltage (Vref) passes through the third transistor T3 and the fourth The transistor T4 charges the compensation capacitor, and the voltage of the third electrode of the driving transistor T1 is the reference voltage (Vref).
  • the second transistor T2, the fourth transistor T4 and the driving transistor T1 are turned on, the third transistor T3, the fifth transistor T5 and the sixth transistor T6 are turned off; the data voltage (Vdata) is input to the driving through the second transistor T2
  • the second electrode of the transistor T1 makes the voltage of the second electrode of the driving transistor T1 the data voltage (Vdata); the compensation capacitor is discharged through the fourth transistor T4 and the driving transistor T1, and the discharge current is output to the external circuit through the second transistor T2 .
  • the external circuit here may be another circuit inside the display panel, or an external IC of the display panel.
  • the second transistor T2, the third transistor T3, and the fourth transistor T4 are turned off, the fifth transistor T5, the sixth transistor T6, and the driving transistor T1 are turned on; the driving current passes through the light emitting module 50, the fifth transistor T5, and the driving The transistor T1 and the sixth transistor T6 input a low-level input terminal (ELVSS).
  • EVSS low-level input terminal
  • the driving transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are all N-type MOS transistors.
  • both the first scan signal (Scan1) and the fourth scan signal (Scan4) are low, and the second scan signal (Scan2) and third scan signal (Scan3) are high
  • the third transistor T3 and the fourth transistor T4 are turned on, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the driving transistor T1 are all turned off; the reference voltage (Vref) is from the third transistor T3, the fourth The transistor T4 is input to the compensation capacitor C1.
  • the voltage of the third electrode (gate) of the driving transistor T1 is the reference voltage (Vref), and the initialization of the driving transistor T1 is completed.
  • both the first scan signal (Scan1) and the third scan signal (Scan3) are high, and the second scan signal (Scan2) and fourth scan signal (Scan4) are both low
  • the second transistor T2 and the fourth transistor T4 are turned on, and the third transistor T3, the fifth transistor T5, and the sixth transistor T6 are turned off; at this time, the data voltage (Vdata) is input to the driving transistor T1 through the second transistor T2
  • the compensation capacitor is in a discharged state, and its discharge current is output to an external circuit through the fourth transistor T4, the drain to the source of the driving transistor T1, and then through the second transistor T2 until the gate voltage of the driving transistor T1 is equal to The voltage difference of the source voltage is equal to its threshold voltage (Vth), the driving transistor T1 is turned off, and the compensation capacitor stops discharging.
  • Vth threshold voltage
  • the driving transistor T1 is turned off, and the compensation capacitor stops discharging.
  • the gate voltage of the driving transistor T1 Vg Vdata + Vth to complete the threshold voltage of the driving transistor T1 ( Vth) compensation.
  • the first scan signal (Scan1), the second scan signal (Scan2), and the third scan signal (Scan3) are all low level
  • the fourth scan signal (Scan4) is high level
  • the second transistor T2, the third transistor T3, and the fourth transistor T4 are all turned off
  • the fifth transistor T5 and the sixth transistor T6 are turned on
  • the driving current flowing through the light emitting diode is only affected by the data voltage (Vdata) and the low-level input voltage (VSS), and has no relationship with the threshold voltage (Vth) of the driving transistor T1, which effectively solves the driving
  • Vdata data voltage
  • VSS low-level input voltage
  • Vth threshold voltage
  • the pixel circuit of this embodiment also includes an input module 10, a driving module 20, a switching module 40, and a compensation module 30.
  • the driving module 20, the switching module 40, and the compensation module 30 are all the same as the first embodiment, and the second electrode of the third transistor T3 and the second electrode of the second transistor T2 in the input module 10 are separated and are independently connected
  • the present invention also provides a display panel including the pixel circuit of the above embodiment.
  • the display panel includes but is not limited to an AMOLED display panel, a TFT-LCD display panel, an LED display panel, and the like.
  • the present invention also provides a pixel circuit including a first node, a second node, a compensation capacitor connected to the first node, a fifth transistor T5, and a driving transistor T1.
  • the gate of the driving transistor T1 is connected to the first node, the drain of the driving transistor T1 is connected to the second electrode of the light emitting module 50 through the fifth transistor T5, and the first electrode of the light emitting module 50 is connected to the high level input terminal (ELVDD);
  • the source of the transistor T1 is used to output the drive current to the low-level input terminal (ELVSS).
  • the voltage of the second node in the second stage is the data voltage (Vdata) Vdata
  • the voltage in the third stage is VSS
  • VSS is the low level received by the low level input terminal (ELVSS) Voltage
  • the voltage of the first node in the third stage is Vdata + Vth, where Vth is the threshold voltage of the driving transistor T1.
  • the first node voltage is a reference voltage (Vref), and the initialization of the driving transistor T1 is completed by inputting the reference voltage (Vref).
  • the invention also provides a driving method of a pixel circuit.
  • the driving method of the pixel circuit can be applied to the aforementioned pixel circuit.
  • the driving method of the pixel circuit includes the following steps:
  • Step S501 In the first stage, the input module 10 is turned on according to the second scan signal (Scan2) and receives the input reference voltage (Vref) to complete the initialization of the drive module 20.
  • Scan2 the second scan signal
  • Vref the input reference voltage
  • the first scan signal (Scan1) and the fourth scan signal (Scan4) are both low level, and the second scan signal (Scan2) and the third scan signal (Scan3) Both are high level, at this time, the third transistor T3 in the input module 10 and the fourth transistor T4 in the compensation module 30 are both turned on, the second transistor T2 in the input module 10, and the fifth transistor in the switch module 40 T5 and the sixth transistor T6 and the driving transistor T1 in the driving module 20 are all turned off.
  • the reference voltage (Vref) is input from the third transistor T3 and the fourth transistor T4 to the compensation capacitor C1.
  • the voltage of the third electrode (gate) of the driving transistor T1 is the reference voltage (Vref), and the driving transistor T1 is completed. initialization.
  • Step S502 In the second stage, the input module 10 inputs the data voltage (Vdata) according to the first scan signal (Scan1), and the compensation module 30 is turned on according to the third scan signal (Scan3) to perform compensation on the drive module 20.
  • Vdata data voltage
  • Scan1 first scan signal
  • Scan3 third scan signal
  • the first scan signal (Scan1) and the third scan signal (Scan3) are both high level
  • the second scan signal (Scan2) and the fourth scan signal (Scan4) are both low level
  • the second transistor T2 and The fourth transistor T4 is turned on, the third transistor T3, the fifth transistor T5, and the sixth transistor T6 are turned off; at this time, the data voltage (Vdata) is input to the second electrode (source) of the driving transistor T1 via the second transistor T2,
  • the voltage of the third electrode (gate) of the driving transistor T1 is the reference voltage (Vref), and the reference voltage (Vref) is greater than the data voltage ( Vdata), so the driving transistor T1 is turned on.
  • the compensation capacitor is in a discharged state, and its discharge current is output to an external circuit through the fourth transistor T4, the drain to the source of the driving transistor T1, and then through the second transistor T2 until the gate voltage of the driving transistor T1 is equal to The voltage difference of the source voltage is equal to its threshold voltage (Vth), the driving transistor T1 is turned off, and the compensation capacitor stops discharging.
  • Vth threshold voltage
  • the gate voltage of the driving transistor T1 Vg Vdata + Vth
  • the threshold voltage of the driving transistor T1 is completed ( Vth) compensation.
  • Step S503 In the third stage, the driving module 20 is turned on to form a driving loop, and a driving current flows through the light emitting module 50 to control the light emitting module 50 to emit light.
  • VSS low level input voltage

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of El Displays (AREA)

Abstract

一种像素电路、驱动方法及显示面板，该像素电路包括输入模块（10）、补偿模块（30）、驱动模块（20）、以及发光模块（50）；输入模块（10）的第一端连接输入信号，输入模块（10）的第二端连接驱动模块（20）的第一端；发光模块（50）的第一端连接高电平输入端（ELVDD），发光模块（50）的第二端连接驱动模块（20）的第二端；驱动模块（20）的第三端连接补偿模块（30）的第一端，驱动模块（20）的第四端连接低电平输入端（ELVSS）；补偿模块（30）的第二端连接低电平输入端（ELVSS）；输入模块（10）用于根据第二扫描信号（Scan2）输入参考电压（Vref）和根据第一扫描信号（Scan1）输入数据电压（Vdata）；补偿模块（30）用于在导通时对驱动模块（20）进行补偿；驱动模块（20）用于在导通时输出驱动信号，以驱动发光模块（50）发光；输入信号包括参考电压（Vref）和数据电压（Vdata）。该像素电路可以提高驱动的阈值电压漂移补偿以及亮度均匀性。

Description

一种像素电路、驱动方法及显示面板 技术领域
本发明涉及显示面板的驱动领域，更具体地说，涉及一种像素电路、驱动方法及显示面板。
 背景技术
AMOLED显示器中的像素电路可以采用4T2C的结构组成，即传统的像素电路可以由四个TFT（薄膜晶体管）、两个电容和一个发光二极管组成。
如图1所示，为传统的4T2C的电路原理图。其具体工作原理为：Rn（复位信号）为高电平、En（使能信号）为高电平时，晶体管T1和晶体管T3打开，晶体管T2和晶体管T4关闭，Int（输入信号）对N1节点进行复位。Gn（扫描信号）为高电平、Rn为低电平且En为高电平时，晶体管T2、晶体管T3和晶体管T4打开，晶体管T1关闭，Data（数据信号）对N2节点传输ref（参考）电位，N1节点电位为ref-Vth，其中，这里的Vth为晶体管T4的阈值电压。Gn为高电平、En为低电平时，晶体管T2和晶体管T4打开，晶体管T1和晶体管T3关闭，Data对N1节点传输data电位。En为高电平、Gn/Rn为低电平时，晶体管T3和晶体管T4打开，晶体管T1和晶体管T2关闭，VDD对N1节点充电，二极管发光。
但是，该传统的4T2C结构，对驱动晶体管T4的阈值电压漂移补偿效果有限，整个显示面板的显示画面亮度均匀性差。
 技术问题
本发明要解决的技术问题在于，针对现有技术的上述缺陷，提供一种可提高驱动晶体管的阈值电压漂移补偿，提升显示亮底均匀性的像素电路、驱动方法及显示面板。
 技术解决方案
本发明解决其技术问题所采用的技术方案是：提供一种像素电路，包括输入模块、补偿模块、驱动模块、以及发光模块；
所述输入模块的第一端连接输入信号，所述输入模块的第二端连接所述驱动模块的第一端；
所述发光模块的第一端连接高电平输入端，所述发光模块的第二端连接所述驱动模块的第二端；所述驱动模块的第三端连接所述补偿模块的第一端，所述驱动模块的第四端连接低电平输入端；所述补偿模块的第二端连接所述低电平输入端；
所述输入模块用于根据第二扫描信号输入参考电压和根据第一扫描信号输入数据电压；所述补偿模块用于在导通时对所述驱动模块进行补偿；所述驱动模块用于在导通时输出驱动信号，以驱动所述发光模块发光；其中，所述输入信号包括所述参考电压和所述数据电压。
本发明还提供一种显示面板，包括以上所述的像素电路。
本发明还提供一种像素电路，包括第一节点、第二节点、与所述第一节点连接的补偿电容、第五晶体管、以及驱动晶体管；
所述驱动晶体管的栅极与所述第一节点连接，所述驱动晶体管的漏极通过所述第五晶体管连接发光模块的第二电极，发光模块的第一电极连接高电平输入端；所述驱动晶体管的源极用于输出驱动电流至低电平输入端；
在所述像素电路的一个驱动周期内，所述第二节点在第二阶段的电压为数据电压Vdata，在第三阶段的电压为VSS，VSS为所述低电平输入端接收的低电平电压；
所述第一节点在第三阶段的电压为Vdata+Vth，其中，Vth为所述驱动晶体管的阈值电压；
所述驱动晶体管输出的驱动电流满足公式I=K(Vdata-VSS) 2，其中K为与输入电压无关的参数。
有益效果
本发明的有益效果：该像素电路采用非耦合补偿的方式对驱动模块进行电压补偿，可以有效提高驱动的阈值电压漂移补偿，提高了显示面板显示亮度的均匀性。另外，该像素电路结构简单，占用面积小。
 附图说明
下面将结合附图及实施例对本发明作进一步说明，附图中：
图1是传统的4T2C的电路原理图；
图2是本发明提供的像素电路第一实施例的电路图；
图3是本发明图2的像素电路的时序图；
图4是本发明提供的像素电路第二实施例的电路图；
图5是本发明提供的像素电路的驱动方法的流程示意图。
 本发明的最佳实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
图2是本发明提供的一种像素电路第一实施例的电路图，该像素电路可以应用于显示面板，具体可以设置在显示面板的发光区域。其中，显示面板包括但不限于AMOLED显示面板、TFT-LCD显示面板、LED显示面板等。
如图2所示，该像素电路包括输入模块10、补偿模块30、驱动模块20、以及发光模块50。
输入模块10的第一端连接输入信号，输入模块10的第二端连接驱动模块20的第一端；发光模块50的第一端连接高电平输入端（ELVDD），发光模块50的第二端连接驱动模块20的第二端；驱动模块20的第三端连接补偿模块30的第一端，驱动模块20的第四端连接低电平输入端（ELVSS）；补偿模块30的第二端连接低电平输入端（ELVSS）。
其中，输入模块10用于根据第二扫描信号（Scan2）输入参考电压（Vref）和根据第一扫描信号（Scan1）输入数据电压（Vdata）；补偿模块30用于在导通时对驱动模块20进行补偿；驱动模块20用于在导通时输出驱动信号，以驱动发光模块50发光。在本实施例中，输入信号包括参考电压（Vref）和数据电压（Vdata），且参考电压（Vref）大于数据电压（Vdata）。高电平输入端（ELVDD）用于接收高电平输入电压（VDD），低电平输入端（ELVSS）用于接收低电平输入电压（VSS）。
进一步地，该像素电路还可以包括开关模块40，该开关模块40用于根据第四扫描信号（Scan4）导通，以使驱动模块20和发光模块50形成发光回路，控制发光模块50发光。
其中，补偿模块30的导通或截止由第三扫描信号（Scan3）控制。
这里需要说明的是，第一扫描信号（Scan1）、第二扫描信号（Scan2）、第三扫描信号（Scan3）以及第四扫描信号（Scan4）为该像素电路的时序控制信号，这些扫描信号可以由显示面板内部的其他电路产生提供，也可以由显示面板外部的IC提供。本发明不作具体限定。
如图2所示，本实施例中，输入模块10包括：第二晶体管T2和第三晶体管T3。
第二晶体管T2的第一电极连接驱动晶体管T1的第二电极，第二晶体管T2的第二电极连接输入信号，第二晶体管T2的第三电极连接第一扫描信号（Scan1）；第三晶体管T3的第一电极连接驱动晶体管T1的第一电极，第三晶体管T3的第二电极连接第二晶体管T2的第二电极，第三晶体管T3的第三电极连接第二扫描信号（Scan2）；第二晶体管T2的第一电极和第三晶体管T3的第一电极形成输入模块10的第二端，第二晶体管T2的第二电极和第三晶体管T3的第二电极连接短接后的连接端形成输入模块10的第一端。
本实施例中，驱动模块20包括驱动晶体管T1。
驱动晶体管T1的第一电极作为驱动模块20的第二端连接第五晶体管T5的第二电极，驱动晶体管T1的第二电极作为驱动模块20的第四端连接第六晶体管T6的第一电极，驱动晶体管T1的第三电极作为驱动模块20的第三端连接补偿模块30的第一端（即如图2所示，驱动晶体管T1的第三电极连接补偿电容的第一端）。
其中，驱动晶体管T1的第一电极和第二电极分别独立连接至输入模块10的第二端，其中，驱动晶体管T1的第一电极和第二电极形成驱动模块20的第一端。即如图2所示，驱动晶体管T1的第一电极连接第三晶体管T3的第一电极，驱动晶体管T1的第二电极连接第二晶体管T2的第一电极和第六晶体管T6的第一电极。
进一步地，驱动晶体管T1为N型MOS管，N型的驱动晶体管T1的第一电极为其漏极，N型的驱动晶体管T1的第二电极为其源极，N型的驱动晶体管T1的第三电极为其栅极。
本实施例中，开关模块40包括第五晶体管T5和第六晶体管T6。
第五晶体管T5的第一电极连接发光模块50的第二端，第五晶体管T5的第二电极连接驱动模块20的第二端（即驱动晶体管T1的第一电极），第五晶体管T5的第三电极连接第四扫描信号（Scan4）；第六晶体管T6的第一电极连接驱动模块20的第四端（即驱动晶体管T1的第二电极），第六晶体管T6的第二电极连接低电平输入端（ELVSS），第六晶体管T6的第三电极连接第四扫描信号（Scan4）。
本实施例中，补偿模块30包括补偿电容和第四晶体管T4。
补偿电容的第一端连接第四晶体管T4的第一电极，补偿电容的第二端连接低电平输入端（ELVSS）；第四晶体管T4的第二电极连接驱动模块20的第二端（即驱动晶体管T1的第一电极），第四晶体管T4的第一电极和补偿电容的第一端的连接端点作为补偿模块30的第一端连接驱动模块20的第三端（即驱动晶体管T1的第三电极）。这里，补偿电容的第二端为补偿模块30的第二端。
本实施例中，发光模块50可以为发光二极管（OLED）。
可选的，在本实施例中，驱动晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5以及第六晶体管T6均为N型MOS管。此时，该像素电路的时序控制如图3所示。当然，可以理解地，在其他一些实施例中，驱动晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5以及第六晶体管T6均为P型MOS管。当驱动晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5以及第六晶体管T6均为P型MOS管时，该像素电路的时序控制的电位与图3所示的电位刚好反转。或者，在其他一些实施例中，驱动晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5以及第六晶体管T6可以为N型MOS管和P型MOS管交叉，即在驱动晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5以及第六晶体管T6中有N型MOS管也有P型MOS管。
进一步地，本实施例中，该像素电路包括第一阶段、第二阶段和第三阶段三个阶段。第一阶段为初始化阶段，第二阶段为驱动晶体管T1的阈值电压（Vth）补偿阶段，第三阶段为发光模块50发光阶段。
可选的，本实施例中，在第一阶段，第三晶体管T3和第四晶体管T4导通，第五晶体管T5和第六晶体管T6截止；参考电压（Vref）经第三晶体管T3和第四晶体管T4给补偿电容充电，驱动晶体管T1的第三电极的电压为参考电压（Vref）。
在第二阶段，第二晶体管T2、第四晶体管T4和驱动晶体管T1导通，第三晶体管T3、第五晶体管T5和第六晶体管T6截止；数据电压（Vdata）经第二晶体管T2输入至驱动晶体管T1的第二电极，使驱动晶体管T1的第二电极电压为数据电压（Vdata）； 补偿电容经第四晶体管T4和驱动晶体管T1进行放电，且通过第二晶体管T2将放电电流输出至外部电路。这里的外部电路可以为显示面板内部的其他电路，或者是显示面板的外部IC。
在第三阶段，第二晶体管T2、第三晶体管T3和第四晶体管T4截止，第五晶体管T5、第六晶体管T6和驱动晶体管T1导通；驱动电流经发光模块50、第五晶体管T5、驱动晶体管T1和第六晶体管T6输入低电平输入端（ELVSS）。
下面结合图3，对本实施例的像素电路的工作原理进行说明。
在该实施例中，驱动晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6均N型MOS管。
如图2所示：
在第一阶段（初始化阶段），第一扫描信号（Scan1）和第四扫描信号（Scan4）均为低电平，第二扫描信号（Scan2）和第三扫描信号（Scan3）均为高电平，此时，第三晶体管T3和第四晶体管T4导通，第二晶体管T2、第五晶体管T5、第六晶体管T6以及驱动晶体管T1均截止；参考电压（Vref）从第三晶体管T3、第四晶体管T4输入给补偿电容C1，待充电结束，驱动晶体管T1的第三电极（栅极）电压为参考电压（Vref），完成对驱动晶体管T1的初始化。
在第二阶段（补偿阶段），第一扫描信号（Scan1）和第三扫描信号（Scan3）均为高电平，第二扫描信号（Scan2）和第四扫描信号（Scan4）均为低电平，此时，第二晶体管T2和第四晶体管T4导通，第三晶体管T3、第五晶体管T5和第六晶体管T6截止；此时，数据电压（Vdata）经第二晶体管T2输入到驱动晶体管T1的第二电极（源极），驱动晶体管T1的源极电压等于数据电压（Vdata）（即Vs=Vdata），同时驱动晶体管T1的第三电极（栅极）电压为参考电压（Vref），而参考电压（Vref）大于数据电压（Vdata），所以驱动晶体管T1导通。进一步地，此时补偿电容处于放电状态，其放电电流经由第四晶体管T4、驱动晶体管T1的漏极到源极、再通过第二晶体管T2输出到外部电路，直到驱动晶体管T1的栅极电压与源极电压的压差等于其阈值电压（Vth），驱动晶体管T1关断，补偿电容停止放电，此时，驱动晶体管T1的栅极电压Vg=Vdata+Vth，完成对驱动晶体管T1的阈值电压（Vth）补偿。
在第三阶段（发光显示阶段），第一扫描信号（Scan1）、第二扫描信号（Scan2）、第三扫描信号（Scan3）均为低电平，第四扫描信号（Scan4）为高电平；此时，第二晶体管T2、第三晶体管T3、第四晶体管T4均截止，第五晶体管T5和第六晶体管T6导通，由于第六晶体管T6导通，所以驱动晶体管T1的源极电压被下拉到低电平输入电压（VSS）（即Vs=VSS），因此，驱动晶体管T1也导通，且驱动晶体管T1工作于饱和状态，由晶体管的特性可知，流过发光二极管的驱动电流满足：
I=K（Vgs-Vth） 2
= K（（Vdata+Vth-VSS）-Vth） 2
=K（Vdata -VSS） 2。
由此可以看出，流过发光二极管的驱动电流只受数据电压（Vdata）和低电平输入电压（VSS）的影响，与驱动晶体管T1的阈值电压（Vth）没有关系，有效地解决了驱动晶体管T1的阈值电压（Vth）漂移补偿受限的问题，提升了显示画面的均匀性。
图4为本发明提供的一种像素电路第二实施例的电路图，该实施例的像素电路同样包括输入模块10、驱动模块20、开关模块40和补偿模块30。其中，驱动模块20、开关模块40和补偿模块30均与第一实施例相同，而输入模块10中的第三晶体管T3的第二电极与第二晶体管T2的第二电极分开，且分别独立连接外部电路，其中，第三晶体管T3的第二电极接收参考电压（Vref），第二晶体管T2的第二电极接收数据电压（Vdata）。
同样地，该实施例的像素电路的工作原理与第一实施例的工作原理相同，在此不再赘述。
本发明还提供了一种显示面板，该显示面板包括以上实施例的像素电路。该显示面板包括但不限于AMOLED显示面板、TFT-LCD显示面板、LED显示面板等。
本发明还提供了一种像素电路，该像素电路包括第一节点、第二节点、与第一节点连接的补偿电容、第五晶体管T5、以及驱动晶体管T1。
驱动晶体管T1的栅极与第一节点连接，驱动晶体管T1的漏极通过第五晶体管T5连接发光模块50的第二电极，发光模块50的第一电极连接高电平输入端（ELVDD）；驱动晶体管T1的源极用于输出驱动电流至低电平输入端（ELVSS）。
在像素电路的一个驱动周期内，第二节点在第二阶段的电压为数据电压（Vdata）Vdata，在第三阶段的电压为VSS，VSS为低电平输入端（ELVSS）接收的低电平电压；第一节点在第三阶段的电压为Vdata+Vth，其中，Vth为驱动晶体管T1的阈值电压。
驱动晶体管T1输出的驱动电流满足公式I=K(Vdata-VSS) 2，其中K为与输入电压无关的参数。
进一步地，在第一阶段，第一节点电压为参考电压（Vref），通过输入该参考电压（Vref）完成对驱动晶体管T1的初始化。
本发明还提供了一种像素电路的驱动方法，该像素电路的驱动方法可应用于前述的像素电路。
如图5所示，该像素电路的驱动方法包括以下步骤：
步骤S501、在第一阶段，输入模块10根据第二扫描信号（Scan2）导通并接收输入参考电压（Vref），完成对驱动模块20的初始化。
具体的，如图2所示，在第一阶段，第一扫描信号（Scan1）和第四扫描信号（Scan4）均为低电平，第二扫描信号（Scan2）和第三扫描信号（Scan3）均为高电平，此时，输入模块10中的第三晶体管T3和补偿模块30中的第四晶体管T4均导通，输入模块10中的第二晶体管T2、开关模块40中的第五晶体管T5和第六晶体管T6以及驱动模块20中的驱动晶体管T1均截止。参考电压（Vref）从第三晶体管T3、第四晶体管T4输入给补偿电容C1，待充电结束，驱动晶体管T1的第三电极（栅极）电压为参考电压（Vref），完成对驱动晶体管T1的初始化。
步骤S502、在第二阶段，输入模块10根据第一扫描信号（Scan1）输入数据电压（Vdata），并由补偿模块30根据第三扫描信号（Scan3）导通执行对驱动模块20的补偿。
第一扫描信号（Scan1）和第三扫描信号（Scan3）均为高电平，第二扫描信号（Scan2）和第四扫描信号（Scan4）均为低电平，此时，第二晶体管T2和第四晶体管T4导通，第三晶体管T3、第五晶体管T5和第六晶体管T6截止；此时，数据电压（Vdata）经第二晶体管T2输入到驱动晶体管T1的第二电极（源极），驱动晶体管T1的源极电压等于数据电压（Vdata）（即Vs=Vdata），同时驱动晶体管T1的第三电极（栅极）电压为参考电压（Vref），而参考电压（Vref）大于数据电压（Vdata），所以驱动晶体管T1导通。进一步地，此时补偿电容处于放电状态，其放电电流经由第四晶体管T4、驱动晶体管T1的漏极到源极、再通过第二晶体管T2输出到外部电路，直到驱动晶体管T1的栅极电压与源极电压的压差等于其阈值电压（Vth），驱动晶体管T1关断，补偿电容停止放电，此时，驱动晶体管T1的栅极电压Vg=Vdata+Vth，完成对驱动晶体管T1的阈值电压（Vth）补偿。
步骤S503、在第三阶段，驱动模块20导通以形成驱动回路，使驱动电流流过发光模块50控制发光模块50发光。
第一扫描信号（Scan1）、第二扫描信号（Scan2）、第三扫描信号（Scan3）均为低电平，第四扫描信号（Scan4）为高电平；此时，第二晶体管T2、第三晶体管T3、第四晶体管T4均截止，第五晶体管T5和第六晶体管T6导通，由于第六晶体管T6导通，所以驱动晶体管T1的源极电压被下拉到低电平输入电压（VSS）（即Vs=VSS），因此，驱动晶体管T1也导通，驱动电流依次流过发光模块50、第五晶体管T5、驱动晶体管T1和第六晶体管T6，发光模块50由驱动电流的控制发光。
以上实施例只为说明本发明的技术构思及特点，其目的在于让熟悉此项技术的人士能够了解本发明的内容并据此实施，并不能限制本发明的保护范围。凡跟本发明权利要求范围所做的均等变化与修饰，均应属于本发明权利要求的涵盖范围。
应当理解的是，对本领域普通技术人员来说，可以根据上述说明加以改进或变换，而所有这些改进和变换都应属于本发明所附权利要求的保护范围。

Claims (16)

  1. 一种像素电路，其特征在于，包括输入模块、补偿模块、驱动模块、以及发光模块；
    所述输入模块的第一端连接输入信号，所述输入模块的第二端连接所述驱动模块的第一端；
    所述发光模块的第一端连接高电平输入端，所述发光模块的第二端连接所述驱动模块的第二端；所述驱动模块的第三端连接所述补偿模块的第一端，所述驱动模块的第四端连接低电平输入端；所述补偿模块的第二端连接所述低电平输入端；
    所述输入模块用于根据第二扫描信号输入参考电压和根据第一扫描信号输入数据电压；所述补偿模块用于在导通时对所述驱动模块进行补偿；所述驱动模块用于在导通时输出驱动信号，以驱动所述发光模块发光；其中，所述输入信号包括所述参考电压和所述数据电压。
  2. 根据权利要求1所述的像素电路，其特征在于，还包括开关模块；
    所述开关模块用于根据第四扫描信号导通，以使所述驱动模块和所述发光模块形成发光回路，控制所述发光模块发光。
  3. 根据权利要求2所述的像素电路，其特征在于，所述开关模块包括第五晶体管和第六晶体管；
    所述第五晶体管的第一电极连接所述发光模块的第二端，所述第五晶体管的第二电极连接所述驱动模块的第二端，所述第五晶体管的第三电极连接所述第四扫描信号；
    所述第六晶体管的第一电极连接所述驱动模块的第四端，所述第六晶体管的第二电极连接所述低电平输入端，所述第六晶体管的第三电极连接所述第四扫描信号。
  4. 根据权利要求3所述的像素电路，其特征在于，所述驱动模块包括驱动晶体管；
    所述驱动晶体管的第一电极作为所述驱动模块的第二端连接所述第五晶体管的第二电极，所述驱动晶体管的第二电极作为所述驱动模块的第四端连接所述第六晶体管的第一电极，所述驱动晶体管的第三电极作为所述驱动模块的第三端连接所述补偿模块的第一端；
    所述驱动晶体管的第一电极和第二电极分别独立连接至所述输入模块的第二端，其中，所述驱动晶体管的第一电极和第二电极形成所述驱动模块的第一端。
  5. 根据权利要求4所述的像素电路，其特征在于，所述输入模块包括第二晶体管和第三晶体管；
    所述第二晶体管的第一电极连接所述驱动晶体管的第二电极，所述第二晶体管的第二电极连接所述输入信号，所述第二晶体管的第三电极连接所述第一扫描信号；
    所述第三晶体管的第一电极连接所述驱动晶体管的第一电极，所述第三晶体管的第二电极连接所述第二晶体管的第二电极，所述第三晶体管的第三电极连接所述第二扫描信号；
    所述第二晶体管的第一电极和所述第三晶体管的第一电极形成所述输入模块的第二端，所述第二晶体管的第二电极和所述第三晶体管的第二电极连接短接后的连接端形成所述输入模块的第一端。
  6. 根据权利要求4所述的像素电路，其特征在于，所述输入模块包括第二晶体管和第三晶体管；
    所述第二晶体管的第一电极连接所述驱动晶体管的第二电极，所述第二晶体管的第二电极连接所述数据电压，所述第二晶体管的第三电极连接所述第一扫描信号；
    所述第三晶体管的第一电极连接所述驱动晶体管的第一电极，所述第三晶体管的第二电极连接所述参考电压，所述第三晶体管的第三电极连接所述第二扫描信号；
    所述第二晶体管的第一电极和所述第三晶体管的第一电极形成所述输入模块的第二端，所述第二晶体管的第二电极和所述第三晶体管的第二电极形成所述输入模块的第一端。
  7. 根据权利要求5或6所述的像素电路，其特征在于，所述补偿模块包括补偿电容和第四晶体管；
    所述补偿电容的第一端连接所述第四晶体管的第一电极，所述补偿电容的第二端连接所述低电平输入端；所述第四晶体管的第二电极连接所述驱动模块的第二端，所述第四晶体管的第一电极和所述补偿电容的第一端的连接端点作为所述补偿模块的第一端连接所述驱动模块的第三端；
    所述补偿电容的第二端为所述补偿模块的第二端。
  8. 根据权利要求7所述的像素电路，其特征在于，所述驱动晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管均为N型MOS管；
    或者，所述驱动晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管均为P型MOS管。
  9. 根据权利要求7所述的像素电路，其特征在于，在第一阶段，所述第三晶体管和所述第四晶体管导通，所述第五晶体管和所述第六晶体管截止；
    所述参考电压经所述第三晶体管和所述第四晶体管给所述补偿电容充电，所述驱动晶体管的第三电极的电压为所述参考电压。
  10. 根据权利要求9所述的像素电路，其特征在于，在第二阶段，所述第二晶体管、所述第四晶体管和所述驱动晶体管导通，所述第三晶体管、所述第五晶体管和所述第六晶体管截止；
    所述数据电压经所述第二晶体管输入至所述驱动晶体管的第二电极，使所述驱动晶体管的第二电极电压为所述数据电压；
    所述补偿电容经所述第四晶体管和所述驱动晶体管进行放电，且通过所述第二晶体管将放电电流输出至外部电路。
  11. 根据权利要求10所述的像素电路，其特征在于，在第三阶段，所述第二晶体管、所述第三晶体管和所述第四晶体管截止，所述第五晶体管、所述第六晶体管和所述驱动晶体管导通；
    驱动电流经所述发光模块、所述第五晶体管、所述驱动晶体管和所述第六晶体管输入所述低电平输入端。
  12. 根据权利要求11所述的像素电路，其特征在于，所述第一阶段、所述第二阶段和所述第三阶段为所述像素电路的一个驱动周期。
  13. 根据权利要求1所述的像素电路，其特征在于，所述参考电压大于所述数据电压。
  14. 一种像素电路，其特征在于，包括第一节点、第二节点、与所述第一节点连接的补偿电容、第五晶体管、以及驱动晶体管；
    所述驱动晶体管的栅极与所述第一节点连接，所述驱动晶体管的漏极通过所述第五晶体管连接发光模块的第二电极，发光模块的第一电极连接高电平输入端；所述驱动晶体管的源极用于输出驱动电流至低电平输入端；
    在所述像素电路的一个驱动周期内，所述第二节点在第二阶段的电压为数据电压Vdata，在第三阶段的电压为VSS，VSS为所述低电平输入端接收的低电平电压；
    所述第一节点在第三阶段的电压为Vdata+Vth，其中，Vth为所述驱动晶体管的阈值电压；
    所述驱动晶体管输出的驱动电流满足公式I=K(Vdata-VSS) 2，其中K为与输入电压无关的参数。
  15. 一种像素电路的驱动方法，应用于如权利要求1-13任一项所述的像素电路，其特征在于，包括：
    在第一阶段，输入模块根据第二扫描信号导通并接收输入参考电压，完成对驱动模块的初始化；
    在第二阶段，输入模块根据第一扫描信号输入数据电压，并由补偿模块根据第三扫描信号导通执行对驱动模块的补偿；
    在第三阶段，驱动模块导通以形成驱动回路，使驱动电流流过发光模块控制发光模块发光。
  16. 一种显示面板，其特征在于，包括权利要求1-14任一项所述的像素电路。
     
     
     
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