WO2020103038A1 - 薄膜晶体管阵列基板的缺陷检测方法 - Google Patents

薄膜晶体管阵列基板的缺陷检测方法

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Publication number
WO2020103038A1
WO2020103038A1 PCT/CN2018/116729 CN2018116729W WO2020103038A1 WO 2020103038 A1 WO2020103038 A1 WO 2020103038A1 CN 2018116729 W CN2018116729 W CN 2018116729W WO 2020103038 A1 WO2020103038 A1 WO 2020103038A1
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WIPO (PCT)
Prior art keywords
thin film
film transistor
transistor array
layer
array substrate
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Ceased
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PCT/CN2018/116729
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English (en)
French (fr)
Inventor
倪奎
林茂仲
陈羿恺
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Shenzhen Royole Technologies Co Ltd
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Shenzhen Royole Technologies Co Ltd
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Application filed by Shenzhen Royole Technologies Co Ltd filed Critical Shenzhen Royole Technologies Co Ltd
Priority to CN201880095931.0A priority Critical patent/CN112912996A/zh
Priority to PCT/CN2018/116729 priority patent/WO2020103038A1/zh
Publication of WO2020103038A1 publication Critical patent/WO2020103038A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
    • G01N21/84—Systems specially adapted for particular applications
    • G01N21/88—Investigating the presence of flaws or contamination
    • G01N21/91—Investigating the presence of flaws or contamination using penetration of dyes, e.g. fluorescent ink
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells

Definitions

  • the present application relates to the field of display technology, and in particular to a defect detection method for a thin film transistor array substrate.
  • TFT Thin-Film Transistor
  • the present application provides a defect detection method for detecting a thin film transistor array substrate with high efficiency and low quality safety risk.
  • the present application provides a defect detection method for a thin film transistor array substrate, including the following steps:
  • the thin film transistor array substrate to be tested includes a base, and a thin film transistor array layer disposed on the base;
  • the sensing signal it is determined whether the thin film transistor array layer has defects.
  • Embodiments of the present application provide a defect detection method for a thin film transistor array substrate by providing a thin film transistor array substrate to be detected, the thin film transistor array substrate to be detected includes a substrate, and a thin film transistor array layer disposed on the substrate Forming a film layer containing a tracer on the side of the thin film transistor array layer facing away from the substrate; removing the film layer covering the exposed surface of the thin film transistor array layer; irradiating the source with a radiation source The side of the thin film transistor array layer facing away from the substrate, and a sensing signal is obtained through a photoelectric sensor; and according to the sensing signal, it is determined whether the thin film transistor array layer is defective, because the tracer can penetrate into the thin film transistor array layer Locate the defect, so when the radiation source illuminates the thin film transistor array layer, the tracer will emit visible light and the light signal is collected by the light sensor, so that the internal and / or external defects of the thin film transistor array layer can be detected, which improves The detection is efficient and the quality and safety risks
  • FIG. 1 is a flowchart of a method for detecting a defect of a thin film transistor array substrate provided by an embodiment of the present application.
  • FIG. 2 is a schematic flowchart of defect detection of a thin film transistor array substrate provided by an embodiment of the present application.
  • FIG. 1 is a flowchart of a defect detection method of a thin film transistor array substrate provided by an embodiment of the present application.
  • FIG. 2 is a diagram of a thin film transistor array substrate provided by an embodiment of the present application. Schematic diagram of defect detection process.
  • the defect detection method of the thin film transistor array substrate includes the following steps:
  • the thin film transistor array substrate 100 to be inspected includes a base 10, and a TFT driving circuit 20, a flat layer 30, an anode layer 40, a pixel defining layer 50 and a thin film transistor array layer 60 sequentially disposed on the base 10 .
  • the base 10 is a flexible substrate.
  • the substrate 10 is made of transparent material.
  • the substrate 10 includes, but is not limited to, polyimide (PI), colorless transparent polyimide (Colorless Polyimide; CPI), polyethylene terephthalate (PET), polyimide Polyamide (PA), polycarbonate (PC), polyethersulfone (PES), polyethylene naphthalate (PEN), polymethylmethacrylate; PMMA), cycloolefin copolymer (COC), cycloolefin polymer (Cyclo-olefin polymer; COP).
  • PI polyimide
  • CPI colorless transparent polyimide
  • PET polyethylene terephthalate
  • PA polyimide Polyamide
  • PC polycarbonate
  • PES polyethersulfone
  • PEN polyethylene naphthalate
  • PMMA cycloolefin copolymer
  • COCyclo-olefin polymer Cyclo-olefin polymer
  • the TFT drive circuit 20 and the substrate 10 are stacked.
  • the TFT driving circuit 20 is electrically connected to the electrodes of the thin film transistor array substrate 100 and the light emitting device.
  • the TFT driving circuit 20 is, for example, but not limited to a low temperature polycrystalline silicon thin film transistor (Low Temperature Poly-Si Thin Film Transistor; LTP-Si) TFT drive circuit, an amorphous silicon thin film transistor ( ⁇ -Si Thin Film Transistor; ⁇ -Si TFT ) Drive circuit, Oxide thin film transistor (Oxide Thin-Film Transistor; Oxide-TFT) drive circuit.
  • the flat layer 30 has two openings 301 on the side facing away from the TFT driving circuit 20.
  • the anode layer 40 is correspondingly disposed in the opening 301 of the flat layer 30 and is in electrical contact with the pixel defining layer 50.
  • the pixel defining layer 50 is used to define the plurality of pixel regions.
  • the number of pixel defining layers 50 includes a plurality.
  • Each pixel defining layer 50 is disposed on the side of the anode layer 40 facing the thin film transistor array layer 60, and the orthographic projection of each pixel defining layer 50 on the substrate 10 is within the anode layer 40.
  • the thin film transistor array layer 60 covers the flat layer 30 and the pixel defining layer 50.
  • the side of the thin film transistor array layer 60 facing away from the substrate 10 has an exposed surface 601.
  • a film layer containing a tracer is formed on a side of the thin film transistor array layer facing away from the substrate.
  • the film layer 70 and the thin film transistor array layer 60 are stacked.
  • a film layer 70 containing a tracer is formed on the side of the thin film transistor array layer 60 facing away from the substrate 10, specifically including:
  • a surface active substance is added to the coating liquid to promote the tracer to penetrate into the defects of the thin film transistor array layer 60.
  • the surface-active substance is selected from volatile materials to avoid the problem of optical signal interference when the tracer is subsequently irradiated with the radiation source.
  • the volatile material includes, but is not limited to, one of benzene, toluene, and n-hexane, or a combination thereof.
  • a film layer containing a tracer is formed on the side of the thin film transistor array layer facing away from the substrate, specifically including:
  • the vapor deposition gas is formed on the thin film transistor array layer 60 by vapor deposition to cover the exposed surface of the thin film transistor array layer 60 with a film layer 70 containing the tracer.
  • the thin film transistor array layer 60 is prone to defects during the manufacturing process.
  • the thin film transistor array layer 60 forms a slit 61 penetrating the exposed surface 601 or the residual particles 62 on the exposed surface 601 of the thin film transistor array layer 60.
  • the tracer can penetrate into the gap 61 of the thin film transistor array layer 60 and remain on the particles 62 or remain on The boundary between the particles 62 and the exposed surface 601 of the thin film transistor array layer 60.
  • the tracer is selected from substances with lower tension.
  • the tension of the tracer is less than 20Mn / m to ensure that the tracer can penetrate into the gap 61, remain on the particles 62, or remain on the exposed surface 601 of the particles 62 and the thin film transistor array layer 60 Junction.
  • the tracer is selected from substances with a low adsorption coefficient.
  • the tracer is selected from substances that can react with the radiation source 1 described below.
  • the tracer is a scintillator.
  • the scintillator includes one of inorganic scintillator, organic scintillator, or a combination thereof.
  • Inorganic scintillators are, for example, but not limited to, thallium activated sodium iodide (NaI (Tl)), cesium iodide (CsI), sodium activated cesium iodide (CsI (Na)), thallium activated cesium iodide ( CsI (Tl)), Europium activated lithium fluoride (LiF (Eu)), Europium activated calcium fluoride (CaF 2 (Eu)), cadmium fluoride (CdF 2 ), barium fluoride (BaF 2 ), fluorine Cerium oxide (CeF 3 ), bismuth germanate ((Bi 3 Ge 4 O 12 ); BGO), zinc tungstate (ZnWO 4 ; ZWO), cadmium tungstate ((CdWO) 4 ; CWO), lead tungstate (PbWO 4 ; PWO), cerium-doped gadolinium silicate ((Gd 2 SiO 2
  • the removal of the film layer covering the exposed surface 601 of the thin film transistor array layer 60 specifically includes:
  • the cleaning agent is used to remove the film layer 70 covering the exposed surface 601 of the thin film transistor array layer 60 according to preset parameter conditions.
  • the cleaning reagent is selected from ethanol. It is understandable that in other embodiments, other solvents capable of dissolving the tracer are suitable for the present application.
  • the preset parameter conditions include at least one of cleaning time, cleaning strength, cleaning direction, and cleaning method.
  • the cleaning reagent is cleaned by spraying.
  • the spraying direction of the cleaning reagent forms an angle with the normal of the exposed surface 601 of the thin film transistor array layer 60.
  • the included angle is greater than 0 degrees and less than 45 degrees, so that the cleaning agent removes the film layer 70 covering the exposed surface 601 of the thin film transistor array layer 60, and remains in the gap 61, the particles 62, or It is a tracer at the boundary between the particles 62 and the exposed surface 601 of the thin film transistor array layer 60.
  • the determination of the preset parameter conditions specifically includes the following steps:
  • the standard thin film transistor array substrate refers to a thin film transistor array substrate without defects.
  • Standard parameter conditions include, but are not limited to standard cleaning time, standard cleaning intensity and standard cleaning direction.
  • the standard parameter conditions are applicable to the preset parameter conditions in the embodiments of the present application.
  • a radiation source is used to illuminate the side of the thin film transistor array layer far away from the substrate, and a sensing signal is obtained through a photoelectric sensor.
  • the radiation source 1 is selected from energy that can excite the tracer to react, such as heat, pressure, light, electron bombardment, and the like.
  • the radiation source 1 in order to avoid damage to the thin film transistor array substrate 100 irradiated by the radiation source 1, the radiation source 1 is selected from ultraviolet light. In some embodiments, the radiation source 1 may also be X-ray, oxygen plasma, or the like.
  • the photoelectric sensor 2 is a charge-coupled device (Charge-coupled Device; CCD).
  • the tracer will produce visible light (such as fluorescence) under the irradiation of the radiation source 1.
  • the tracer is a light wavelength conversion substance that converts the radiation source 1 into visible light.
  • the photoelectric sensor 2 is used to collect the light signal generated by the tracer and convert the light signal into a charge signal.
  • judging whether the thin film transistor array layer has defects according to the sensing signal specifically includes:
  • the thin film transistor array layer has a defect.
  • the detection method further includes: determining the position of the defect of the thin film transistor array layer,
  • Determining the location of the defects of the thin film transistor array layer specifically including:
  • a position where the difference in light intensity is greater than a preset comparison threshold is determined as a defect position of the thin film transistor array layer.
  • Embodiments of the present application provide a defect detection method for a thin film transistor array substrate.
  • the thin film transistor array substrate to be detected includes a substrate, and a thin film transistor array layer disposed on the substrate Forming a film layer containing a tracer on the side of the thin film transistor array layer facing away from the substrate; removing the film layer covering the exposed surface of the thin film transistor array layer; irradiating the source with a radiation source
  • the thin film transistor array layer is away from the substrate, and the sensing signal is obtained through the photo sensor; and according to the sensing signal, it is determined whether the thin film transistor array layer is defective, because the tracer can penetrate into the thin film transistor array layer positioning Defects, so when the radiation source illuminates the thin film transistor array layer, the tracer emits visible light and the light signal is collected by the light sensor, so that the internal and / or external defects of the thin film transistor array layer can be detected, thereby improving detection Effective, and lower quality and safety risks.
  • the position where the light intensity difference is greater than the preset comparison threshold can be determined as a defect of the thin film transistor array layer
  • the position of the thin film transistor array layer by detecting the position of the tracer to accurately locate the defect position of the thin film transistor array layer.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • General Health & Medical Sciences (AREA)
  • Biochemistry (AREA)
  • Analytical Chemistry (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Immunology (AREA)
  • Pathology (AREA)
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  • Optics & Photonics (AREA)
  • Thin Film Transistor (AREA)

Abstract

本申请提供了一种薄膜晶体管阵列基板的缺陷检测方法，包括如下步骤：提供待检测的薄膜晶体管阵列基板，所述待检测的薄膜晶体管阵列基板包括基底、设置在所述基底上的薄膜晶体管阵列层(S101)；在所述薄膜晶体管阵列层背朝所述基底的侧面形成包含有示踪物的膜层(S103)；去除覆盖在所述薄膜晶体管阵列层的裸露面上的所述膜层(S105)；采用辐射源照射所述薄膜晶体管阵列层背朝所述基底的一侧，并通过光电传感器获取感测信号(S107)；以及根据所述感测信号，判断薄膜晶体管阵列层是否存在缺陷(S109)。本申请薄膜晶体管阵列基板的缺陷检测方法，不仅提高了检测有效率，且较低了质量安全风险。

Description

薄膜晶体管阵列基板的缺陷检测方法 技术领域
本申请涉及显示技术领域，尤其涉及一种薄膜晶体管阵列基板的缺陷检测方法。
背景技术
目前，薄膜晶体管阵列基板(Thin-Film Transistor；TFT)封装后，一般是基于二维的平面自动光学检查。然而，这种检测方法不易检测到薄膜晶体管阵列基板的内部缺陷(例如裂缝)，不仅检测有效率低，且造成薄膜晶体管阵列基板的质量安全存在风险。
发明内容
鉴于现有技术中存在的上述问题，本申请提供一种检测有效率较高、且质量安全风险较低的薄膜晶体管阵列基板的缺陷检测方法。
第一方面，本申请提供一种薄膜晶体管阵列基板的缺陷检测方法，包括如下步骤：
提供待检测的薄膜晶体管阵列基板，所述待检测的薄膜晶体管阵列基板包括基底、设置在所述基底上的薄膜晶体管阵列层；
在所述薄膜晶体管阵列层背朝所述基底的侧面形成包含有示踪物的膜层；
去除覆盖在所述薄膜晶体管阵列层的裸露面上的所述膜层；
采用辐射源照射所述薄膜晶体管阵列层背朝所述基底的一侧，并通过光电传感器获取感测信号；以及
根据所述感测信号，判断薄膜晶体管阵列层是否存在缺陷。
本申请实施例提供了一种薄膜晶体管阵列基板的缺陷检测方法，通过提供待检测的薄膜晶体管阵列基板，所述待检测的薄膜晶体管阵列基板包括基底、 设置在所述基底上的薄膜晶体管阵列层；在所述薄膜晶体管阵列层背朝所述基底的侧面形成包含有示踪物的膜层；去除覆盖在所述薄膜晶体管阵列层的裸露面上的所述膜层；采用辐射源照射所述薄膜晶体管阵列层背朝所述基底的一侧，并通过光电传感器获取感测信号；以及根据所述感测信号，判断薄膜晶体管阵列层是否存在缺陷，由于示踪物可渗入至薄膜晶体管阵列层定位缺陷处，因此辐射源照射薄膜晶体管阵列层时，示踪物会发出可见光并由光线传感器采集光信号，从而薄膜晶体管阵列层的内部和/或外部的缺陷均可以被检测到，进而提高了检测有效率，以及较低了质量安全风险。
附图说明
为了更清楚地说明本申请实施方式或现有技术中的技术方案，下面将对实施方式或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施方式，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例提供的薄膜晶体管阵列基板的缺陷检测方法的流程框图。
图2是本申请一实施例提供的薄膜晶体管阵列基板的缺陷检测的流程示意图。
具体实施方式
下面将结合本申请实施方式中的附图，对本申请实施方式中的技术方案进行清楚、完整地描述，显然，所描述的实施方式仅仅是本申请一部分实施方式，而不是全部的实施方式。基于本申请中的实施方式，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施方式，都属于本申请保护的范围。
请一并参阅图1和图2，图1所示为本申请实施方式提供的薄膜晶体管阵列基板的缺陷检测方法的流程框图，图2所示为本申请一实施例提供的薄膜晶体 管阵列基板的缺陷检测的流程示意图。薄膜晶体管阵列基板的缺陷检测方法，其包括如下步骤：
S101，提供待检测的薄膜晶体管阵列基板。
如图2所示，待检测的薄膜晶体管阵列基板100包括基底10、及依序设置在基底10上的TFT驱动电路20、平坦层30、阳极层40、像素界定层50及薄膜晶体管阵列层60。
在本实施例中，基底10为柔性衬底。基底10由透明材料制成。基底10包含有，但不局限于聚酰亚胺(Polyimide；PI)、无色透明聚酰亚胺(Colorless Polyimide；CPI)、聚对苯二甲酸乙二醇酯(polyethylene terephthalate；PET)、聚酰胺(polyamide；PA)、聚碳酸酯(polycarbonate；PC)、聚苯醚砜(polyethersulfone；PES)、聚萘二甲酸乙二醇酯(polyethylene naphthalate；PEN)、聚甲基丙烯酸甲酯(polymethylmethacrylate；PMMA)、环烯烃共聚物(cycloolefin copolymer；COC)、环烯烃聚合物(Cyclo-olefin polymer；COP)中的一种。
TFT驱动电路20与基底10层叠设置。TFT驱动电路20电气连通于薄膜晶体管阵列基板100的电极及发光器件。TFT驱动电路20例如是，但不局限于低温多晶硅薄膜晶体管(Low Temperature Poly-Si Thin Film Transistor；LTP-Si TFT)驱动电路、非晶硅薄膜晶体管(α-Si Thin Film Transistor；α-Si TFT)驱动电路、氧化物薄膜晶体管(Oxide Thin-Film Transistor；Oxide-TFT)驱动电路。平坦层30背朝TFT驱动电路20的侧面开设有两开口301。阳极层40对应设置于平坦层30的开口301内，且与像素界定层50电性接触。像素界定层50用于界定所述多个像素区域。在本实施例中，像素界定层50的数量包括多个。每一像素界定层50设置在阳极层40面朝薄膜晶体管阵列层60的侧面上，且每一像素界定层50在基底10上的正投影位于阳极层40内。薄膜晶体管阵列层60覆盖平坦层30及像素界定层50。薄膜晶体管阵列层60背朝基底10的一侧具有裸露面601。
S103，在所述薄膜晶体管阵列层背朝所述基底的侧面上形成包含有示踪物的膜层。
在本实施例中，膜层70与薄膜晶体管阵列层60层叠设置。
在一实施例中，在所述薄膜晶体管阵列层60背朝所述基底10的侧面形成包含有示踪物的膜层70，具体包括：
配置包含有所述示踪物的涂布液；
将所述涂布液涂覆或喷涂在所述薄膜晶体管阵列层60背朝所述基底10的侧面上，并固化，以在所述薄膜晶体管阵列层60的裸露面上覆盖一层包含有所述示踪物的膜层70。
其中，为了降低涂布液的张力，涂布液中还加入有表面活性物质，以促使示踪物能够渗入至薄膜晶体管阵列层60的缺陷内。表面活性物质选自挥发性材料，以避免在后续采用辐射源照射示踪物时而产生光信号干扰的问题。所述挥发性材料包括，但不局限于苯、甲苯、正己烷中的一者或它们之间的组合。
在另一实施例中，在所述薄膜晶体管阵列层背朝所述基底的侧面形成包含有示踪物的膜层，具体包括：
制备包含有所述示踪物的蒸镀气体；
将所述蒸镀气体通过蒸镀方式形成在所述薄膜晶体管阵列层60上，以在所述薄膜晶体管阵列层60的裸露面上覆盖一层包含有所述示踪物的膜层70。
可以理解的，薄膜晶体管阵列层60在制作过程中容易产生缺陷，例如，薄膜晶体管阵列层60形成贯穿裸露面601的缝隙61，或是薄膜晶体管阵列层60的裸露面601上的残留颗粒62。当包含有示踪物的膜层70形成在薄膜晶体管阵列层60的裸露面601上时，示踪物能够渗入至薄膜晶体管阵列层60的缝隙61内，残留在颗粒62上，或是残留在颗粒62与薄膜晶体管阵列层60的裸露面601的交界处。
可选的，示踪物选自具有较低的张力的物质。在本实施例中，示踪物的张力小于20Mn/m，以确保示踪物能够渗入至缝隙61内，残留在颗粒62上，或是残留在颗粒62与薄膜晶体管阵列层60的裸露面601的交界处。此外，为了方便后续去除覆盖在薄膜晶体管阵列层60的裸露面601上的膜层70，示踪物选自吸附 系数较低的物质。
可以理解的，示踪物选自能与下述辐射源1发生反应的物质。在本实施例中，示踪物为闪烁剂。闪烁剂包括无机闪烁剂、有机闪烁剂中的一者或它们之间的组合。无机闪烁剂例如是，但不局限于铊激活的碘化钠(NaI(Tl))、碘化铯(CsI)、钠激活的碘化铯(CsI(Na))、铊激活的碘化铯(CsI(Tl))、铕激活的氟化锂(LiF(Eu))、铕激活的氟化钙(CaF 2(Eu))、氟化镉(CdF 2)、氟化钡(BaF 2)、氟化铈(CeF 3)、锗酸铋((Bi 3Ge 4O 12)；BGO)、钨酸锌(ZnWO 4；ZWO)、钨酸镉((CdWO) 4；CWO)、钨酸铅(PbWO 4；PWO)、铈掺杂的硅酸钆((Gd 2SiO 2O 5:Ce)；GSO:Ce)、铈掺杂的铝酸镧((LaAlO 3:Ce)；LAP:Ce)、掺铈的铝酸钇((YAlO 3:Ce)；YAP:Ce)、铈掺杂的硅酸镥((Lu 2Si 2O 5:Ce)；LSO:Ce)中的一种或它们之间的组合。有机闪烁剂例如是，但不局限于蒽、茋、萘中的一者或它们之间的组合。
S105，去除覆盖在所述薄膜晶体管阵列层的裸露面上的所述膜层。
去除覆盖在所述薄膜晶体管阵列层60的裸露面601上的所述膜层，具体包括：
采用清洗试剂按预设参数条件清除覆盖在薄膜晶体管阵列层60的裸露面601上的膜层70。
具体的，在本实施例中，清洗试剂选自乙醇。可以理解的，在其他实施例中，其他能够溶解示踪物的溶剂均适用于本申请。所述预设参数条件包括清洗时间、清洗力度、清洗方向、清洗方式中至少一者。
在本实施例中，清洗试剂采用喷晒方式清洗。可选的，清洗试剂的喷晒方向与薄膜晶体管阵列层60的裸露面601的法线形成夹角。所述夹角大于0度且小于45度，以便清洗试剂清除覆盖在所述薄膜晶体管阵列层60的裸露面601上的所述膜层70，并保留残留在缝隙61内、颗粒62上，或是颗粒62与薄膜晶体管阵列层60的裸露面601的交界处的示踪物。
进一步的，在一可选实施例中，预设参数条件的确定，具体包括如下步骤：
获取标准薄膜晶体管阵列基板；
在标准薄膜晶体管阵列基板的薄膜晶体管阵列层的裸露面上形成包含有示踪物的标准膜层；
去除覆盖在薄膜晶体管阵列层的裸露面上的标准膜层；
获取清除标准膜层的标准参数条件。
其中，标准薄膜晶体管阵列基板是指不存在缺陷的薄膜晶体管阵列基板。标准参数条件包括，但不局限于标准清洗时间、标准清洗力度及标准清洗方向。标准参数条件适用于本申请实施例中的预设参数条件。
S107，采用辐射源照射所述薄膜晶体管阵列层远朝所述基底的侧面，并通过光电传感器获取感测信号。
可以理解的，辐射源1选自可激发示踪物发生反应的能量，例如热、压力、光照、电子轰击等。在本实施例中，为了避免辐射源1照射薄膜晶体管阵列基板100的损坏，辐射源1选自紫外光。在一些实施例中，辐射源1还可以为X射线、氧等离子体等。光电传感器2为电荷耦合元件(Charge-coupled Device；CCD)。示踪物在辐射源1的照射下会产生可见光(例如荧光)。在本实施例中，示踪物为将辐射源1转换成可见光的光波长转换物质。光电传感器2用于采集示踪物产生的光信号，并将所述光信号转换成电荷信号。
S109，根据所述感测信号，判断薄膜晶体管阵列层是否存在缺陷。
具体的，根据所述感测信号，判断薄膜晶体管阵列层是否存在缺陷，具体包括：
获取标准薄膜晶体管阵列基板对应的标准光强度值分布数据；
对所述感测信号进行光强度分析，得到所述感测信号的光强度值分布数据；
获取所述光强度值分布数据与所述标准光强度值分布数据中对应位置处的光强度差值；
当所述光强度值大于预设的比较阈值时，确定所述薄膜晶体管阵列层存在缺陷。
进一步的，所述检测方法还包括：确定所述薄膜晶体管阵列层的缺陷的位置，
确定所述薄膜晶体管阵列层的缺陷的位置，具体包括：
将光强度差值大于预设的比较阈值的位置确定为所述薄膜晶体管阵列层的缺陷位置。
本申请实施例提供了一种薄膜晶体管阵列基板的缺陷检测方法，通过提供待检测的薄膜晶体管阵列基板，所述待检测的薄膜晶体管阵列基板包括基底、设置在所述基底上的薄膜晶体管阵列层；在所述薄膜晶体管阵列层背朝所述基底的侧面形成包含有示踪物的膜层；去除覆盖在所述薄膜晶体管阵列层的裸露面上的所述膜层；采用辐射源照射所述薄膜晶体管阵列层远离所述基底的一侧，并通过光电传感器获取感测信号；以及根据所述感测信号，判断薄膜晶体管阵列层是否存在缺陷，由于示踪物可渗入至薄膜晶体管阵列层定位缺陷处，因此辐射源照射薄膜晶体管阵列层时，示踪物会发出可见光并由光线传感器采集光信号，从而薄膜晶体管阵列层的内部和/或外部的缺陷均可以被检测到，进而提高了检测有效率，以及较低了质量安全风险。进一步的，通过获取光强度值分布数据与标准光强度值分布数据中对应位置处的光强度差值，从而能够将光强度差值大于预设的比较阈值的位置确定为薄膜晶体管阵列层的缺陷位置，进而通过检测示踪物的位置来精准定位薄膜晶体管阵列层的缺陷位置，以便后续对薄膜晶体管阵列层的缺陷进行修复。
以上对本申请实施例进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的一般技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上上述，本说明书内容不应理解为对本申请的限制。

Claims (19)

  1. 一种薄膜晶体管阵列基板的缺陷检测方法，其特征在于，包括如下步骤：
    提供待检测的薄膜晶体管阵列基板，所述待检测的薄膜晶体管阵列基板包括基底、设置在所述基底上的薄膜晶体管阵列层；
    在所述薄膜晶体管阵列层背朝所述基底的侧面形成包含有示踪物的膜层；
    去除覆盖在所述薄膜晶体管阵列层的裸露面上的所述膜层；
    采用辐射源照射所述薄膜晶体管阵列层背朝所述基底的一侧，并通过光电传感器获取感测信号；以及
    根据所述感测信号，判断薄膜晶体管阵列层是否存在缺陷。
  2. 如权利要求1所述的薄膜晶体管阵列基板的缺陷检测方法，其特征在于，所述膜层与所述薄膜晶体管阵列层层叠设置。
  3. 如权利要求1所述的薄膜晶体管阵列基板的缺陷检测方法，其特征在于，在所述薄膜晶体管阵列层背朝所述基底的侧面形成包含有示踪物的膜层，具体包括：
    配置包含有所述示踪物的涂布液；
    将所述涂布液涂覆或喷涂在所述薄膜晶体管阵列层的裸露面上，并固化，以在所述薄膜晶体管阵列层的裸露面上覆盖一层包含有所述示踪物的膜层。
  4. 如权利要求3所述的薄膜晶体管阵列基板的缺陷检测方法，其特征在于，所述涂布液中还加入有表面活性物质，所述表面活性物质为挥发性材料。
  5. 如权利要求4所述的薄膜晶体管阵列基板的缺陷检测方法，其特征在于，所述挥发性材料包括苯、甲苯、正己烷中的一者或它们之间的组合。
  6. 如权利要求1所述的薄膜晶体管阵列基板的缺陷检测方法，其特征在于，在所述薄膜晶体管阵列层背朝所述基底的侧面形成包含有示踪物的膜层，具体包括：
    制备包含有所述示踪物的蒸镀气体；
    将所述蒸镀气体通过蒸镀方式形成在所述薄膜晶体管阵列层的裸露面上，以在所述薄膜晶体管阵列层的裸露面上覆盖一层包含有所述示踪物的膜层。
  7. 如权利要求1所述的薄膜晶体管阵列基板的缺陷检测方法，其特征在于，所述示踪物为将所述辐射源转换成可见光的光波长转换物质，所述光电传感器用于采集所述示踪物产生的光信号，及将所述光信号转换成电荷信号。
  8. 如权利要求1所述的薄膜晶体管阵列基板的缺陷检测方法，其特征在于，所述示踪物为闪烁剂，所述闪烁剂包括无机闪烁剂、有机闪烁剂中的一者或它们之间的组合。
  9. 如权利要求8所述的薄膜晶体管阵列基板的缺陷检测方法，其特征在于，所述无机闪烁剂包括铊激活的碘化钠、碘化铯、钠激活的碘化铯、铊激活的碘化铯、铕激活的氟化锂、铕激活的氟化钙、氟化镉、氟化钡、氟化铈、锗酸铋、钨酸锌、钨酸镉、钨酸铅、铈掺杂的硅酸钆、铈掺杂的铝酸镧、掺铈的铝酸钇、铈掺杂的硅酸镥中的一者或它们之间的组合；所述有机闪烁剂包括蒽、茋、萘中的一者或它们之间的组合。
  10. 如权利要求1所述的薄膜晶体管阵列基板的缺陷检测方法，其特征在于，所述示踪物的张力小于20Mn/m。
  11. 如权利要求1所述的薄膜晶体管阵列基板的缺陷检测方法，其特征在于，去除覆盖在所述薄膜晶体管阵列层的裸露面上的所述膜层，具体包括：
    采用清洗试剂按预设参数条件清除覆盖在所述薄膜晶体管阵列层的裸露面上的所述膜层。
  12. 如权利要求11所述的薄膜晶体管阵列基板的缺陷检测方法，其特征在于，所述清洗试剂为乙醇。
  13. 如权利要求12所述的薄膜晶体管阵列基板的缺陷检测方法，其特征在于，所述预设参数条件包括清洗时间、清洗力度、清洗方向、清洗方式中至少一者。
  14. 如权利要求1所述的薄膜晶体管阵列基板的缺陷检测方法，其特征在于，所述辐射源包括紫外光。
  15. 如权利要求1所述的薄膜晶体管阵列基板的缺陷检测方法，其特征在于，根据所述感测信号，判断薄膜晶体管阵列层是否存在缺陷，具体包括：
    获取标准薄膜晶体管阵列基板对应的标准光强度值分布数据；
    对所述感测信号进行光强度分析，得到所述感测信号的光强度值分布数据；
    获取所述光强度值分布数据与所述标准光强度值分布数据中对应位置处的光强度差值；
    当所述光强度值大于预设的比较阈值时，确定所述薄膜晶体管阵列层存在缺陷。
  16. 如权利要求15所述的薄膜晶体管阵列基板的缺陷检测方法，其特征在于，其特征在于，所述检测方法还包括：确定所述薄膜晶体管阵列层的缺陷的位置，
    确定所述薄膜晶体管阵列层的缺陷的位置，具体包括：
    将光强度差值大于预设的比较阈值的位置确定为所述薄膜晶体管阵列层的缺陷位置。
  17. 如权利要求16所述的薄膜晶体管阵列基板的缺陷检测方法，其特征在于，所述薄膜晶体管阵列层的缺陷包括残留在所述薄膜晶体管阵列层的裸露面的颗粒和/或所述薄膜晶体管阵列层形成贯穿所述裸露面的缝隙。
  18. 如权利要求17所述的薄膜晶体管阵列基板的缺陷检测方法，其特征在于，在所述薄膜晶体管阵列层背朝所述基底的侧面形成包含有示踪物的膜层，具体包括：
    在所述薄膜晶体管阵列层背朝所述基底的侧面形成包含有示踪物的膜层，以使所述示踪物渗入所述缝隙内，残留在所述颗粒上，或是残留在所述颗粒与所述薄膜晶体管阵列层的裸露面的交界处。
  19. 如权利要求1所述的薄膜晶体管阵列基板的缺陷检测方法，其特征在于，所述基底为柔性衬底。
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