WO2020099578A1

WO2020099578A1 - Semiconductor chip having an inner contact element and two outer contact elements, and semiconductor component

Info

Publication number: WO2020099578A1
Application number: PCT/EP2019/081361
Authority: WO
Inventors: Christian Eichinger; Korbinian Perzlmaier
Original assignee: Osram Opto Semiconductors Gmbh
Priority date: 2018-11-16
Filing date: 2019-11-14
Publication date: 2020-05-22
Also published as: DE102018128896A1

Abstract

Embodiments of the invention relate to a semiconductor chip (10, 11, 12, 13) comprising an inner contact element (128) and two outer contact elements (129). The inner contact element (128) and the two outer contact elements (129) are arranged on a second main surface (108) of the semiconductor chip (10, 11, 12, 13). One of the outer contact elements (129) is arranged on each of the opposite sides of the inner contact element (128). For example, the inner contact element (128) is designed as a first contact element that is electrically connected to a first semiconductor layer (100), and the two outer contact elements (129) are designed as second contact elements (117) that are electrically connected to a second semiconductor layer (110). Alternatively, the two outer contact elements (129) are designed as first contact elements (115) that are electrically connected to a first semiconductor layer (100), and the inner contact element (128) is designed as a second contact element (117) and is electrically connected to a second semiconductor layer (110).

Description

SEMICONDUCTOR CHIP WITH AN INNER CONTACT ELEMENT AND TWO EXTERNAL CONTACT ELEMENTS AND SEMICONDUCTOR COMPONENT

BACKGROUND

This patent application claims the priority of German patent application DE 10 2018 128 896.4, the disclosure content of which is hereby incorporated by reference.

Optoelectronic semiconductor chips such as LEDs ("Light Emitting Diodes") can be connected to form larger functional units. For example, several optoelectronic semiconductor chips, each with different color characteristics, e.g. Red, green, and blue (RGB) can be combined. Such RGB units can be used, for example, in a matrix connection in display devices or video screens.

In general, possibilities are sought to improve the electrical contacting of the semiconductor chips in semiconductor chip arrangements.

The present invention has for its object to provide an improved semiconductor chip and an improved semiconductor device.

The task is solved by the subject matter of the independent claims. Further refinements are the subject of the dependent claims.

SUMMARY

According to embodiments, a semiconductor chip comprises an inner contact element and two outer contact elements. The inner Contact element and the two outer contact elements are arranged on a second main surface of the semiconductor chip. One of the outer contact elements is arranged on opposite sides of the inner contact element. For example, the inner contact element is designed as a first contact element which is electrically connected to a first semiconductor layer, and the two outer contact elements are each designed as second contact elements which are electrically connected to a second semiconductor layer. Alternatively, the two outer contact elements are each designed as first contact elements that are electrically connected to a first semiconductor layer, and the inner contact element is designed as a second contact element that is electrically connected to a second semiconductor layer.

According to embodiments, the first and the second semiconductor layer are part of a layer stack, and the second semiconductor layer is arranged on a side of the semiconductor layer stack facing away from the second main surface.

For example, the two outer contact elements are electrically connected to one another via a conductive layer within the semiconductor chip. According to embodiments, the two outer contact elements can be electrically connected to one another via a first current spreading layer.

A part of the second semiconductor layer cannot be covered with the first semiconductor layer. As a result, part of a first main surface of the second semiconductor layer can be exposed.

The semiconductor chip may further have a contact structure on the exposed part of the first main surface, wherein the outer contact elements are electrically connected to one another via the contact structure.

For example, the semiconductor chip can be an optoelectronic semiconductor chip, in particular an LED chip or a sensor chip. According to further embodiments, however, the semiconductor chip can also be an electromechanical, a driver or a logic semiconductor chip.

According to embodiments, a semiconductor component comprises a multiplicity of semiconductor chips as described above and a printed circuit board on which the semiconductor chips are arranged. The semiconductor component can furthermore have a multiplicity of first connection regions and second connection regions, the first connection regions being suitable for connecting the inner contact elements of two adjacent semiconductor chips to one another.

The second connection regions can be suitable for connecting the outer contact elements of two adjacent semiconductor chips to one another.

For example, the semiconductor chips can be arranged in rows and columns. The first connection areas can be executed in lines that intersect the columns.

For example, the second connection areas can each be arranged in columns.

According to embodiments, the semiconductor chips can each be LED chips and comprise a first plurality of LED chips of a first color, a second plurality of LED chips of a second color and a third plurality of LED chips of a third color. BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings serve to understand exemplary embodiments of the invention. The drawings illustrate exemplary embodiments and, together with the description, serve to explain them. Further exemplary embodiments and numerous of the intended advantages result directly from the following detailed description. The elements and structures shown in the drawings are not necessarily drawn to scale with respect to one another. The same reference numerals refer to the same or corresponding elements and structures.

FIG. 1A shows a perspective view of an optoelectronic semiconductor chip according to embodiments.

FIGS. 1B and IC each show views of a second main surface of the semiconductor chip according to embodiments.

FIG. 2A shows a schematic cross-sectional view of an optoelectronic semiconductor chip.

FIG. 2B shows a further cross-sectional view of the optoelectronic semiconductor chip in accordance with embodiments.

FIG. 2C shows a further cross-sectional view of the optoelectronic semiconductor chip.

FIG. 3 shows a vertical cross-sectional view of an optoelectronic semiconductor chip in accordance with further embodiments.

FIG. 4A shows a schematic view of a printed circuit board. FIG. 4B shows a schematic view of a semiconductor component in accordance with embodiments.

DETAILED DESCRIPTION

In the following detailed description, reference is made to the accompanying drawings, which form a part of the disclosure and in which specific exemplary embodiments are shown for purposes of illustration. In this context, a directional terminology such as "top", "bottom", "front", "back", "over", "on", "in front", "behind", "front", "back" and so on the orientation of the fi gures just described related. Since the components of the exemplary embodiments can be positioned in different orientations, the directional terminology is only used for explanation and is in no way restrictive.

The description of the exemplary embodiments is not restrictive, since other exemplary embodiments also exist and structural or logical changes can be made without deviating from the range defined by the claims. In particular, elements of exemplary embodiments described below can be combined with elements of other exemplary embodiments described, unless the context provides otherwise.

The terms “lateral” and “horizontal”, as used in this description, are intended to describe an orientation or alignment that runs essentially parallel to a first surface of a substrate or semiconductor body. This can be, for example, the surface of a wafer or a chip (die). The horizontal direction can lie, for example, in a plane perpendicular to a growth direction when layers are grown.

The term "vertical", as used in this description, is intended to describe an orientation which is essentially perpendicular to the first surface of a substrate or semiconductor body. The vertical direction can, for example, correspond to a growth direction when layers are grown.

The terms "wafer" or "semiconductor substrate" used in the following description may include any semiconductor-based structure that has a semiconductor surface. Wafers and structures are to be understood to include doped and undoped semiconductors, epitaxial semiconductor layers, optionally supported by a base, and other semiconductor structures. For example, a layer of a first semiconductor material can be grown on a growth substrate made of a second semiconductor material or of an insulating material, for example on a sapphire substrate. Other examples of materials for growth substrates include glass, silicon dioxide, quartz or a ceramic.

Depending on the intended use, the semiconductor can be based on a direct or an indirect semiconductor material. Examples of games for semiconductor materials which are particularly suitable for generating electromagnetic radiation include, in particular, nitride semiconductor compounds, by means of which, for example, ultra violet, blue or longer-wave light can be generated, such as, for example, GaN, InGaN, A1N, AlGaN, AlGalnN, Al-GalnBN, phosphide semiconductor compounds , which can be used to generate green or long-wave light, for example, such as GaAsP, AlGalnP, GaP, AlGaP, and further semiconductor materials such as GaAs, AlGaAs, InGaAs, AlInGaAs, SiC, ZnSe, ZnO, Ga ₂ Ct, diamond, hexagonal BN and combinations of the materials mentioned. The stoichiometric ratio of the compound semiconductor materials can vary. Other examples of semiconductor materials can include silicon, silicon germanium and germanium. In the context of the present description, the term “semiconductor” also includes organic semiconductor materials.

The term “substrate” generally encompasses insulating, conductive or semiconductor substrates.

Insofar as the terms "have", "contain", "comprise", "have" and the like are used here, they are open terms which indicate the presence of the said elements or features, the presence of further elements or features but do not rule out. The undefined articles and the certain articles include both the plural and the singular, unless the context clearly indicates otherwise.

In the context of this description, the term "electrically connected" means a low-resistance electrical connection between the connected elements. The electrically connected elements do not necessarily have to be connected directly to one another. Further elements can be arranged between electrically connected elements.

The term “electrically connected” also includes tunnel contacts between the connected elements. According to further embodiments, the term “electrically connected” can also include metal-semiconductor contacts, for example Schottky contacts or contacts between a transparent conductive oxide, for example as indium tin oxide or indium zinc oxide, and include a semiconductor material.

Embodiments are described below with reference to an optoelectronic semiconductor chip, in particular an LED. However, the features described can be applied to all types of semiconductor chips and optoelectronic semiconductor chips, for example sensors, in which, for example, contacts are arranged adjacent to a main surface of the semiconductor chip. For example, such sensors can be suitable for detecting incoming electromagnetic radiation.

FIG. 1A shows a perspective view of an optoelectronic semiconductor chip 10 according to embodiments. The optoelectronic semiconductor chip 10 shown in FIG. 1A can, for example, be cuboid or in any other shape. Electromagnetic radiation generated in the optoelectronic semiconductor chip 10 is output, for example, via a first main surface 107 of the optoelectronic semiconductor chip. Furthermore, generated electromagnetic radiation 16 can also be output via side surfaces of the optoelectronic semiconductor chip. The optoelectronic semiconductor chip 10 has an inner contact element 128 and two outer contact elements 129. The inner contact element 128 and the two outer contact elements 129 are arranged on a second main surface 108 of the semiconductor chip 10. The two outer contact elements 129 are electrically connected to one another. For example, the two outer contact elements can be electrically connected to one another via a conductive layer within the semiconductor chip. In example, such a conductive layer can be isolated from the outside. One of the outer contact elements 129 is arranged on opposite sides of the inner contact element 128. As will be explained in more detail below, the inner contact element 128 can be embodied as a first contact element that is electrically connected to a first semiconductor layer (not shown in FIG. 1A). In this case, the two outer contact elements 129 are designed as second contact elements and are electrically connected to a second semiconductor layer (not shown in FIG. 1A). Alternatively, the two outer contact elements 129 can each be designed as first contact elements and can be electrically connected to a first semiconductor layer (not shown in FIG. 1A). Furthermore, the inner contact element 128 is designed as a second contact element and is electrically connected to a second semiconductor layer (not shown in FIG. 1A).

FIG. 1B shows a plan view of the second main surface 108 of the optoelectronic semiconductor chip 10. As shown in FIG. 1B, the two outer contact elements 129 are each arranged on opposite sides of the inner contact element 128. The two outer contact elements 129 can be electrically connected to one another via a conductive layer within the semiconductor chip. The conductive layer can also be a semiconductor layer. For example, the conductive layer via which the two outer contact elements 129 are electrically connected to one another cannot be exposed in a region of the second main surface 108. According to embodiments, an insulating layer can be arranged over this conductive layer. As a result, as will be explained below with reference to FIGS. 4A and 4B, when the inner contact element 128 is electrically contacted, the outer contact elements 129 are not short-circuited with the inner contact element 128. For example FIG. 1B shows the case in which the outer contact elements 129 each represent first contact elements 115 which are electrically connected to a first semiconductor layer. The first semiconductor layer is arranged on a side of the semiconductor layer stack facing the second main surface 108. In this case, the inner contact element 128 can be a second contact element 117. According to further embodiments, the inner contact element 128 can also be a first contact element, and the two outer contact elements 129 are each second contact elements.

FIG. IC illustrates a case in which the two outer contact elements 129 are electrically connected to one another via a conductive structure 118. For example, the outer contact elements 129 can each be second contact elements 117, which are electrically connected to a second semiconductor layer. The second semiconductor layer is arranged on a side of the semiconductor layer stack facing away from the second main surface 108. As will be explained in more detail with reference to FIGS. 2A and 2B, the second contact elements 117 can be electrically connected to one another via the contact structure 118. The contact structure 118 can be designed such that it is not exposed on the second main surface 108 of the semiconductor chip 10. For example, there may be a space between the contact structure 118 and the second main surface 108 of the semiconductor chip 10. As a result, as will be explained below with reference to FIGS. 4A and 4B, when the inner contact element 115 is electrically contacted, the outer contact elements 117 are not short-circuited with the inner contact element 115. According to further embodiments, in the structure shown in FIG. IC, the outer contact elements 129 can also be first contact elements 115, and the inner contact element 128 is a second contact element 117. The shape of the inner and outer contact elements can be arbitrary. For example, the contact elements can be rectangular, square or with a round or oval cross section. The shape and size of the contact elements can each be different.

FIG. 2A shows a cross-sectional view of the semiconductor chip between I and I 'shown in FIG. 1B or IC. The cross-sectional view shown cuts the optoelectronic semiconductor chip in the region of a first contact element 115, as will be explained below. It is irrelevant for the structure of the first contact element 115 whether the first contact element is an inner or an outer contact element. The optoelectronic semiconductor component shown in FIG. 2A has a layer stack of a first semiconductor layer 100 of a first conductivity type, for example p-type, and a second semiconductor layer 110 of a second conductivity type, for example n-type. An active zone 105 can be arranged between the semiconductor layers 100, 110.

The active zone 105 can have, for example, a pn junction, a double heterostructure, a single quantum well structure (SQW, single quantum well) or a multiple quantum well structure (MQW, multi quantum well) for generating radiation. The term "quantum well structure" has no significance with regard to the dimensionality of the quantization. It therefore includes, among other things, quantum wells, quantum wires and quantum dots as well as any combination of these layers.

A first current spreading layer 123 may be formed in electrical contact with the first semiconductor layer 100. The first current spreading layer 123 may have one or more layers. For example, the first current spreading layer 123 can contain a silver layer, which can be encapsulated by suitable layers. The first contact element 115 is electrically connected to the first semiconductor layer 100 via the first current spreading layer 123. According to embodiments, a first passivation layer 120 can be arranged between the first current expansion layer 123 and the first contact element 115. According to further embodiments, this first passivation layer 120 can also be dispensed with. The second semiconductor layer 110 is arranged on the side of the optoelectronic semiconductor chip facing away from the second main surface 108. A second main surface of the second semiconductor layer 111 can be roughened, for example, in order to increase the coupling-out efficiency of the electromagnetic radiation generated.

The first semiconductor layer 100 can be structured so that a mesa 103 is formed. For example, a horizontal part 113, 114 of the second semiconductor layer can thereby be exposed, ie not covered with the first semiconductor layer 100. For example, the exposed part 113, 114 of the second semiconductor layer is arranged on the edge of the semiconductor chip. For example, a contact structure 118 can be arranged on the exposed part 113, 114 of the first main surface. If the two outer contact elements 129, as shown in FIG. 1B, each represent first contact elements 115, for example the first contact elements 115 can be electrically connected to one another via the first current expansion layer 123. A surface of the contact structure 118 may be arranged at a height that is smaller than a height of the second main surface 108 of the semiconductor chip. The term “second main surface” denotes an outermost horizontal boundary surface of the Semiconductor chips 10. For example, the second main surface 108 of the semiconductor chip 10 can be brought into contact with a printed circuit board (not shown in FIG. 2A) when the semiconductor component is formed. The contact structure 118 can be spaced from the circuit board when the semiconductor chip is brought into contact with the circuit board.

FIG. 2B shows a cross-sectional view of the semiconductor chip between II and II 'shown in FIGS. 1B and IC. The cross-sectional view shown in FIG. 2B cuts the semiconductor chip in the region of a second contact element 117. The second contact element 117 is electrically connected to the second semiconductor layer 110, which is arranged on a side of the semiconductor layer stack facing away from the second main surface 108. It is irrelevant whether the second contact element 117 is an inner or an outer contact telement. As has been explained with reference to FIG. 2A, for example the first semiconductor layer 100 can be structured to form a mesa, so that a first and a second horizontal part 113, 114 of the second semiconductor layer 110 are exposed. For example, the exposed part 113, 114 of the second semiconductor layer is arranged at the edge of the semiconductor chip. According to embodiments, electrical contact between the second contact element 117 and the second semiconductor layer 110 can only take place via exposed parts 113, 114 which are arranged on the edge of the semiconductor chip. For example, there are no contacts between the second contact elements 117 and the second semiconductor layer in a central part of the semiconductor chip. A passivation layer 120 can be arranged over the first current expansion layer 123 and over exposed parts of the first semiconductor layer 100 in order to electrically isolate the first semiconductor layer 100 from the second contact element 117. The second contact element 117 can be arranged in direct contact with the second semiconductor layer 110 and can be electrically connected to the latter. According to further embodiments, further conductive layers can be arranged between the second semiconductor layer 110 and the second contact element 117. A contact structure 118 can be arranged in areas outside of the second contact element 117 above the exposed part 113, 114 of the second semiconductor layer 110. In accordance with embodiments, the contact structure 118 and the second contact element 117 can be produced from the same conductive material. According to further embodiments, the second contact element 117 and the contact structure 118 can each be constructed from different materials. According to the embodiments of FIG. 1B, the second contact element 117 forms the inner contact element 128. According to the embodiments that are shown in FIG. IC, two second contact elements 117 each form the outer contact elements 129. In this case, the two outer contact elements 117 can over the contact structure 118 may be electrically connected to one another. According to further embodiments, however, they can also be electrically connected to one another via any other suitable conductive layer of the semiconductor chip.

FIG. 2C shows a schematic cross-sectional view of the optoelectronic semiconductor chip between III and III ', as shown in FIG. 1B. According to embodiments, the two outer contact elements 129 are each first contact elements 115, which are electrically connected to the first semiconductor layer 100. For example, the two outer contact elements 129 are electrically connected to one another via the first current spreading layer 123. The further components of the semiconductor chip illustrated in FIG. 2C have already been explained with reference to FIGS. 2A and 2B. For example The first current spreading layer 123 can contain silver, as a result of which the first current spreading layer 123 has a high conductivity and thus current carrying capacity. The current carrying capacity can be increased by suitably adjusting the layer thickness of the first current spreading layer.

FIG. 3 shows a cross-sectional view of an optoelectronic semiconductor chip in which the two outer contact elements 129 are each second contact elements 117. However, it goes without saying that further changes can be made, so that the structure shown in FIG. 3 is applicable to the case where the two outer contact elements 129 are first contact elements 115.

The optoelectronic semiconductor chip shown in FIG. 3 has a first semiconductor layer 100 of a first conductivity type, for example p-type, and a second semiconductor layer 110 of a second conductivity type, for example n-type. The first and second semiconductor layers 100, 110 form a semiconductor layer stack. An active zone 105 can be arranged between the first and second semiconductor layers 100, 110. Electromagnetic radiation emitted by the optoelectronic semiconductor chip can be output, for example, via the second main surface 111 of the second semiconductor layer. The second main surface 111 of the second semiconductor layer 110 can be roughened in order to generate the coupling-out efficiency of the generated electromagnetic radiation.

A first current spreading layer 123 may be arranged in contact with the first semiconductor layer 100. The first current expansion layer 123 can, for example, contain silver or consist of silver and be encapsulated by a suitable passivation layer 120. According to further However, the first current spreading layer 123 can also be realized in different ways. In a departure from the embodiments shown in FIGS. 2A to 2C, a second contact structure 122 is provided here which makes electrical contact with the second semiconductor layer 110. For example, the second contact structure 122 can be arranged in an opening 124 formed in the first semiconductor layer 100 and thus extend through the first semiconductor layer 100. The second contact structure 122 can be electrically insulated from the first semiconductor layer 100 via an insulating material, for example part of a first passivation layer 120. The second contact structure 122 can be electrically connected to a second current expansion layer 125. The second current spreading layer 125 can be arranged on a side of the first semiconductor layer 100 facing away from the second semiconductor layer 110. The first current spreading layer 123 can be arranged between the first semiconductor layer 100 and the second current spreading layer 125. A part of the second current expansion layer 125 can extend laterally along the semiconductor layer stack and thus form a type of carrier structure of the optoelectronic semiconductor chip 10.

According to embodiments, the optoelectronic semiconductor chip 10 can be electrically contacted directly adjacent to the second current spreading layer 125 and thus form a chip size package. According to further embodiments, the first and the second contact elements 115, 117 can each be designed as contact columns, as shown in FIG. 3. For example, a potting compound 130 can be arranged between the contact columns and thus contribute to stabilizing the optoelectronic semiconductor chip. As illustrated in FIG. 3, the second contact elements 117 are each in contact with the second current spreading layer 125 arranged. The first contact element 115 is electrically connected to the first current expansion layer 123 via a first opening 121, which is formed in particular in the second current expansion layer 125. A first contact area 116 can be electrically connected to the first contact element 115. Second contact areas 119 can each be electrically connected to the second contact elements 117.

As illustrated in FIG. 3, the inner and the two outer contact elements are arranged on one side of the second main surface 108 of the semiconductor chip. The second main surface 108 of the semiconductor chip 10 is the light emitting surface of the semiconductor chip 10 opposite lying. The semiconductor chip described accordingly represents a flip-chip component. According to embodiments, the semiconductor chip can comprise a multiplicity of second contact structures 122, which in each case connect the second semiconductor layer 110 to the second current expansion layer 125.

As has been described with reference to FIGS. 2A to 2C and FIG. 3, the two outer contact elements 129 can be electrically connected to one another via a conductive layer within the semiconductor chip 10 according to embodiments. For example, this conductive layer can be insulated from the outside. According to embodiments, the conductive layer can be formed such that it does not come into contact with a printed circuit board when the second main surface of the semiconductor chip is brought into contact with the printed circuit board. According to further embodiments, the outer contact elements 129 can be electrically connected via a contact structure. This contact structure can be arranged, for example, on an exposed part of a first main surface of the second semiconductor layer. As a result, the contact structure is not on the second main surface of the Semiconductor chips in front but is spaced from the second main surface. According to further embodiments, a corresponding contact structure can be buried in the semiconductor chip. As a result, electrical connection of the outer and inner contacts 129, 128 of the semiconductor chips, respectively, can be realized by connection regions which are arranged in a single plane, as will be described below.

A semiconductor device 20 comprises a plurality of semiconductor chips 10 as described above and a circuit board 200 on which the semiconductor chips 10 are arranged. FIG. 4A illustrates an example of a printed circuit board 200. The printed circuit board 200 shown in FIG. 4A can be constructed from any base material, such as, for example, ceramic, glass or other insulating materials. Conductive layers or foils can be arranged above the printed circuit board and suitably structured. The circuit board 200 has a plurality of first connection areas 205 and a large number of second connection areas 210.

For example, the first connection regions 205 can be arranged such that they each connect the inner contact elements 128 of adjacent semiconductor chips to one another. Furthermore, the second contact regions 210 can each connect the outer contact elements 129 of two adjacent optoelectronic semiconductor chips to one another. For example, the first contact areas 205 can be formed in a line-like manner. The second contact regions 210 can each be designed as broken lines. The length of the broken lines is dimensioned such that they are suitable for connecting the outer contact elements 129 of two adjacent semiconductor chips to one another. The first and two th contact areas can be structured, for example be made of a conductive layer. For example, the conductive layer can be a copper layer or another conductive layer, for example a metallic layer.

FIG. 4B shows an example of an arrangement of different optoelectronic semiconductor chips 11, 12, 13, which can be applied to the printed circuit board 200. For example, a large number of similar or identical optoelectronic semiconductor chips can be applied to the printed circuit board 200 and form the optoelectronic component. According to further embodiments, the plurality of semiconductor chips can be a first plurality of semiconductor chips 11 of a first color, for example blue, a second plurality of semiconductor chips 12 of a second color, for example green, and a third plurality of optoelectronic semiconductor chips 13 of a third color, for example red , contain. For example, the semiconductor chips can be arranged in rows and columns, where in each case the semiconductor chips of one color are arranged in such a way that they can be electrically connected to one another by adjacent second contact regions 210. For example, the semiconductor chips of one color can each be arranged in columns, so that they are each electrically connected to one another via the second contact regions 210. For example, the outer contact elements 129 of two adjacent semiconductor chips can be electrically connected to one another via the second connection areas 210. In this way, a large number of optoelectronic semiconductor chips in a column are connected in series. Furthermore, the inner contact elements 128 of semiconductor chips in a row can be electrically connected to one another via the first connection regions 205. According to further embodiments, the semiconductor component 20 can further comprise a driver, for example with a first driver element 206, by means of which a predetermined voltage is applied to the rows or the first th connection areas 205 can be created. The driver can further comprise a second driver element 211, by means of which a predetermined voltage can be applied to the columns or the second connection regions 210, respectively.

For example, a total of more than 50 or more than 100 optoelectronic semiconductor chips can be arranged and electrically connected in a simple manner in this way. For example, the optoelectronic semiconductor component can have approximately more than 15 x 30, for example 18 x 32 optoelectronic semiconductor chips. For example, a typical size of a chip can be approximately 50 μm. However, the size can also be smaller, for example up to 10 μm.

Due to the special design of the optoelectronic semiconductor chips with two outer and one inner contact element, it is possible to connect these optoelectronic semiconductor chips of the type with one another, so that the current can be passed through the two terminal regions 210. As has been described, part of the electrical connection of the outer contact elements 129 and thus the second connection regions is effected via a conductive or semiconductor layer within the optoelectronic semiconductor chip. This special wiring scheme within the chip, through which two outer contact elements 129 are electrically connected to one another and are each arranged on opposite sides of an inner contact element 128, allows simple interconnection of a multiplicity of optoelectronic semiconductor chips in an optoelectronic semiconductor component. Correspondingly, a connection of different LEDs can be easily implemented without the need to provide lines which could cause shading of the component or which are expensive to manufacture. As has been described, the wiring device of the individual semiconductor chips 10, 11, 12, 13 are effected by conductor tracks or connection regions 205, 210, which are arranged in a single plane. Accordingly, it is not necessary to provide insulation between different wiring levels.

The semiconductor component described here can be, for example, a semiconductor component with a multiplicity of semiconductor chips which are arranged in a matrix and interconnected with one another. Examples include display devices, video screens, sensors, and others. The semiconductor chips can be optoelectronic semiconductor chips which are suitable for emitting or receiving electromagnetic radiation. According to further embodiments, the optoelectronic semiconductor chips can also be electromechanical semiconductor chips, logic or driver chips.

Although specific embodiments have been illustrated and described herein, those skilled in the art will recognize that the specific embodiments shown and described may be replaced by a variety of alternative and / or equivalent configurations without departing from the scope of the invention. The application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, the invention is limited only by the claims and their equivalents. REFERENCE SIGN LIST

10 semiconductor chip

11 first semiconductor chip

12 second semiconductor chip

13 third semiconductor chip

1 6 emitted electromagnetic radiation

20 semiconductor device

100 first semiconductor layer

101 first main surface of the first semiconductor layer

1 03 mesa

1 05 active zone

1 07 first main surface of the semiconductor chip

1 0 8 second main surface of the semiconductor chip

110 second semiconductor layer

111 second main surface of the second semiconductor layer

1 13 first exposed part of the second semiconductor layer

1 14 second exposed part of the second semiconductor layer

1 15 first contact element

1 1 6 first contact area

1 17 second contact element

1 1 8 Contact structure

1 1 9 second contact area

120 first passivation layer

121 first opening

122 second contact structure

123 first current spreading layer

124 opening

125 second current spreading layer

127 insulating layer

12 8 inner contact element

12 9 outer contact element 130 potting compound

200 pcb

205 first connection area

206 first driver element 210 second connection area

211 second driver element

Claims

PATENT CLAIMS

1. Semiconductor chip (10, 11, 12, 13) with

a semiconductor layer stack comprising a first and a second semiconductor layer (100, 110),

an inner contact element (128), and

two outer contact elements (129),

wherein the inner contact element (128) and the two outer contact elements (129) on a second main surface (108) of the semiconductor chip (10, 11, 12, 13) are arranged and one of the outer contact elements (129) on opposite sides the inner contact element (128) is arranged, and

the two outer contact elements (129) are each designed as first contact elements (115) which are electrically connected to the first semiconductor layer (100) and the inner contact element (128) is designed as a second contact element (117) which is connected to the second semiconductor layer (110) is electrically connected, wherein

the second semiconductor layer (110) is arranged on a side of the semiconductor layer stack facing away from the second main surface (108).

2. The semiconductor chip (10, 11, 12, 13) according to claim 1, wherein the two outer contact elements (129) are electrically connected to one another via a first current spreading layer (123).

The semiconductor chip (10, 11, 12, 13) according to claim 1 or 2, wherein a part of the second semiconductor layer (110) is not covered with the first semiconductor layer (100), whereby a part (113, 114) of a first main surface the second semiconductor layer (110) is exposed.

4. Semiconductor chip (10, 11, 12, 13) with

an inner contact element (128), and

two outer contact elements (129),

the inner contact element (128) is designed as a first contact element (115) which is electrically connected to the first semiconductor layer (100) and the two outer contact elements (129) are each designed as second contact elements (117) which are connected to the second semiconductor layer (110) are electrically connected, the second semiconductor layer (110) being arranged on a side of the semiconductor layer stack facing away from the second main surface (108),

a part of the second semiconductor layer (110) is not covered with the first semiconductor layer (100), whereby a

Part (113, 114) of a first main surface of the second semiconductor layer (110) is exposed,

further with a contact structure (118) on the exposed part (113, 114) of the first main surface, the outer contact elements (129) being electrically connected to one another via the contact structure (118).

5. The semiconductor chip (10, 11, 12, 13) according to one of the preceding claims, wherein the semiconductor chip (10, 11, 12, 13) is an optoelectronic semiconductor chip (10, 11, 12, 13).

6. The semiconductor chip (10, 11, 12, 13) according to claim 5, wherein the semiconductor chip (10, 11, 12, 13) is a light-emitting diode chip.

7. The semiconductor chip (10, 11, 12, 13) according to claim 5, wherein the semiconductor chip (10, 11, 12, 13) is a sensor chip.

8. Semiconductor component (20) with a plurality of semiconductor chips (10, 11, 12, 13) according to one of the preceding claims and a circuit board (200) on which the semiconductor chips (10, 11, 12, 13) are arranged .

9. Semiconductor component (20) with a plurality of semiconductor chips (10, 11, 12, 13) and a printed circuit board (200) on which the semiconductor chips (10, 11, 12, 13) are arranged, the semiconductor chips in each case

an inner contact element (128), and

have two outer contact elements (129),

wherein the inner contact element (128) and the two outer contact elements (129) are arranged on a second main surface (108) of the semiconductor chip (10, 11, 12, 13) and one of the outer contact elements (129) on opposite sides in each case the inner contact element (128) is arranged, and

a) the inner contact element (128) is designed as a first contact element (115) which is electrically connected to a first semiconductor layer (100) and the two outer contact elements (129) are each designed as second contact elements (117), which are electrically connected to a second semiconductor layer (110), or

b) the two outer contact elements (129) are each designed as first contact elements (115), which are electrically connected to a first semiconductor layer (100) and the inner contact element (128) is designed as a second contact element (117), which has a second Semiconductor layer (110) is electrically connected, and the printed circuit board (200) furthermore has a plurality of first connection regions (205) and second connection regions (210), the first connection regions (205) being suitable for connecting the inner contact elements (128) of two adjacent semiconductor chips (10, 11, 12, 13) to connect with each other.

10. The semiconductor component (20) according to claim 9, in which the second connection regions (210) are suitable for the outer contact elements (129) of two adjacent semiconductor chips (10,

11, 12, 13) to connect with each other.

11. The semiconductor component (20) according to claim 9 or 10, wherein the semiconductor chips (10, 11, 12, 13) are arranged in rows and columns and the first connection regions (205) in lines which intersect the columns are executed.

12. The semiconductor component (20) according to claim 11, wherein the second connection regions (210) are each arranged in columns.

13. The semiconductor component (20) according to any one of claims 9 to 12, wherein the semiconductor chips (10, 11, 12, 13) are each LED chips and a first plurality of LED chips (11) of a first color, a second A plurality of LED chips (12) of a second color and a third plurality of LED chips (13) of a third color.

14. The semiconductor component (20) according to any one of claims 9 to 13, wherein the first and the second semiconductor layer (100, 110) are part of a layer stack, and the second semiconductor layer (110) on a surface facing away from the second main surface (108) Side of the semiconductor layer stack is arranged.

15. The semiconductor component (20) according to one of claims 9 to 14, in which the two outer contact elements (129) are electrically connected to one another via a conductive layer (123) within the semiconductor chip (10, 11, 12, 13).

16. The semiconductor component (20) according to one of claims 9 to 15, in which the two outer contact elements (129) are electrically connected to one another via a first current spreading layer (123).

17. The semiconductor device (20) according to claim 14, wherein a part of the second semiconductor layer (110) is not covered with the first semiconductor layer (100), whereby a part (113, 114) of a first main surface of the second semiconductor layer (110) is exposed is.

18. The semiconductor device (20) according to claim 17, further comprising a contact structure (118) on the exposed part (113, 114) of the first main surface, the outer contact elements (129) being electrically connected to one another via the contact structure (118).

19. The semiconductor component (20) according to any one of claims 9 to 18, wherein the semiconductor chip (10, 11, 12, 13) is an optoelectronic semiconductor chip (10, 11, 12, 13).

20. The semiconductor device (20) according to claim 19, wherein the

Semiconductor chip (10, 11, 12, 13) is a light-emitting diode chip.

21. The semiconductor device (20) according to claim 19, wherein the

Semiconductor chip (10, 11, 12, 13) is a sensor chip.