WO2020095544A1 - Dispositif d'imagerie et appareil électronique - Google Patents

Dispositif d'imagerie et appareil électronique Download PDF

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Publication number
WO2020095544A1
WO2020095544A1 PCT/JP2019/036339 JP2019036339W WO2020095544A1 WO 2020095544 A1 WO2020095544 A1 WO 2020095544A1 JP 2019036339 W JP2019036339 W JP 2019036339W WO 2020095544 A1 WO2020095544 A1 WO 2020095544A1
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Prior art keywords
pixel
switch transistor
pixel portion
transistor
addition
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PCT/JP2019/036339
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English (en)
Japanese (ja)
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ルォンフォン 朝倉
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ソニーセミコンダクタソリューションズ株式会社
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Priority to JP2020556650A priority Critical patent/JP7362651B2/ja
Priority to US17/281,423 priority patent/US11405568B2/en
Publication of WO2020095544A1 publication Critical patent/WO2020095544A1/fr
Priority to US17/732,925 priority patent/US20220272287A1/en
Priority to JP2023170486A priority patent/JP2023171452A/ja

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/50—Control of the SSIS exposure
    • H04N25/57—Control of the dynamic range
    • H04N25/59—Control of the dynamic range by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14641—Electronic components shared by two or more pixel-elements, e.g. one amplifier shared by two pixel elements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/40—Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled
    • H04N25/46—Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled by combining or binning pixels
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
    • H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
    • H04N25/771—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/78—Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14634—Assemblies, i.e. Hybrid structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1464—Back illuminated imager structures

Definitions

  • the present disclosure relates to an imaging device and an electronic device.
  • a still image mode in which pixel signals are read out at the full angle of view of all pixels of the image pickup device, and a moving image in which pixel signals are read out at a smaller angle of view such as HD (High Definition) / 4K It is required to support both modes.
  • Additive reading is desirable.
  • addition reading methods there is an FD addition method that performs addition between floating diffusion FDs (Floating Diffusions) of pixels (see, for example, Patent Document 1).
  • Patent Document 1 The conventional technique described in Patent Document 1 is configured to selectively connect FD nodes of two pixels via a switch for switching conversion efficiency (efficiency of converting charges into voltage). .. Therefore, in this conventional technique, when the switch is in the non-conducting state, the parasitic capacitance of the wiring for short-circuiting the FD nodes of the two pixels does not attach to the FD node as an extra capacitance, so that in the still image mode. The conversion efficiency does not decrease. However, in the related art, there is a problem that addition reading by FD addition can be performed only in a state of low conversion efficiency.
  • an object of the present disclosure to provide an image pickup apparatus capable of performing addition reading by FD addition even in a state other than the state of low conversion efficiency, and an electronic apparatus having the image pickup apparatus.
  • An imaging device of the present disclosure for achieving the above object is A first pixel unit having a floating diffusion for converting charges transferred from the light receiving unit into a voltage, and selectively performing pixel addition for adding pixel signals by electrically connecting the floating diffusions between pixels; With 2 pixel parts, The first pixel portion is connected between a first switch transistor whose one source / drain electrode is connected to the floating diffusion and between the other source / drain electrode of the first switch transistor and the power supply node. Has a reset transistor, The second pixel portion has a second switch transistor in which one source / drain electrode is connected to the floating diffusion, and a second switch transistor in which one source / drain electrode is connected to the other source / drain electrode of the second switch transistor.
  • the electronic device of the present disclosure for achieving the above object includes the image pickup apparatus having the above configuration.
  • FIG. 1 is a block diagram showing an outline of a basic configuration of a CMOS image sensor which is an example of the image pickup apparatus of the present disclosure.
  • FIG. 2 is a circuit diagram showing an example of a circuit configuration of a pixel.
  • FIG. 3 is a block diagram showing an example of the configuration of a column parallel analog-digital conversion unit mounted on the CMOS image sensor.
  • FIG. 4 is a plan view showing an outline of a flat type chip structure.
  • FIG. 5 is an exploded perspective view showing an outline of a laminated chip structure.
  • FIG. 6 is an explanatory view of the outline of the addition read of the logic addition method.
  • FIG. 7 is an explanatory view of the outline of the addition reading of the AD (analog-digital) addition method.
  • FIG. 8 is an explanatory diagram of an outline of addition reading in the SF (source follower) addition method.
  • FIG. 9 is an explanatory diagram of an outline of addition reading in the FD (floating diffusion) addition method.
  • FIG. 10 is a diagram for comparing and describing the power consumption of the logic addition method, the AD addition method, the SF addition method, and the FD addition method, and the linearity of the signal after addition.
  • FIG. 11 is a diagram for explaining the linearity problem of the SF addition method.
  • FIG. 12 is a diagram for explaining the deterioration of the number of circuit noise electrons in the input conversion of the FD addition method.
  • FIG. 13 is a circuit diagram illustrating the circuit configuration of the pixel circuit according to the first embodiment.
  • FIG. 14 is a timing chart for explaining the operation in the case of high conversion efficiency in the still image mode without pixel addition.
  • FIG. 15 is a timing chart for explaining the operation in the case of medium conversion efficiency in the still image mode without pixel addition.
  • FIG. 16 is a timing chart for explaining the operation in the case of low conversion efficiency in the still image mode without pixel addition.
  • FIG. 17A is a timing chart for explaining the operation in the case of addition reading with medium conversion efficiency
  • FIG. 17B is a timing chart for explaining the operation in the case of addition reading with low conversion efficiency.
  • FIG. 18 is a plan view showing the layout of the pixel circuit according to the first embodiment.
  • FIG. 19 is a sectional view taken along the line XX of FIG. FIG.
  • FIG. 20 is a circuit diagram illustrating the circuit configuration of the pixel circuit according to the second embodiment.
  • FIG. 21 is a diagram illustrating pixel addition in the Bayer pixel array.
  • FIG. 22 is a timing chart for explaining the operation in the case of high conversion efficiency in the still image mode without pixel addition.
  • FIG. 23 is a timing chart for explaining the operation in the case of medium conversion efficiency in the still image mode without pixel addition.
  • FIG. 24 is a timing chart for explaining the operation in the case of low conversion efficiency in the still image mode without pixel addition.
  • FIG. 25A is a timing chart for explaining the operation in the case of addition reading of the pixels 1 and 3 with medium conversion efficiency
  • FIG. 25B is the timing chart for the case of addition reading of pixels 2 and 4 with medium conversion efficiency.
  • FIG. 6 is a timing chart for explaining the operation.
  • 26A is a timing chart for explaining the operation in the case of addition reading of the pixels 1 and 3 with low conversion efficiency
  • FIG. 26B is the timing chart for the case of addition reading of pixels 2 and 4 with low conversion efficiency.
  • 6 is a timing chart for explaining the operation.
  • FIG. 27 is a plan view showing the layout of the pixel circuit according to the second embodiment. 28 is a cross-sectional view taken along the line YY of FIG.
  • FIG. 29 is a diagram illustrating an application example of the technology according to the present disclosure.
  • FIG. 30 is a block diagram showing an outline of the configuration of an imaging system which is an example of the electronic device of the present disclosure.
  • Example 1 (example in which each of the first and second pixel portions is composed of a single pixel) 3-2.
  • Example 2 an example in which the first and second pixel portions each include a plurality of pixels, and the FD is shared between the plurality of pixels) 4.
  • Application example 6. Electronic device of the present disclosure (example of imaging device) 7. Configurations that the present disclosure can take
  • the first switch transistor and the second switch transistor in the first pixel section and the second pixel section when pixel addition is not performed Can be configured to realize high conversion efficiency with respect to the conversion efficiency of the floating diffusion when each of them is in the non-conducting state.
  • the first pixel portion and the second pixel portion when no pixel addition is performed, when the first switch transistor, the second switch transistor, and the third switch transistor are all in a conductive state, floating diffusion With regard to the conversion efficiency of, it is possible to adopt a configuration that realizes low conversion efficiency.
  • both the first switch transistor and the second switch transistor are conductive.
  • the pixel addition can be performed, and the conversion efficiency of the floating diffusion can be configured to realize the medium conversion efficiency.
  • the third switch transistor when the third switch transistor is in the conductive state, a low conversion efficiency can be realized with respect to the conversion efficiency of the floating diffusion.
  • the capacitive element is configured to be divided and arranged in each pixel of the first pixel portion and the second pixel portion. be able to. Further, the capacitance element can be configured to be realized by the coupling capacitance between the metal wirings.
  • the first pixel portion and the second pixel portion each include a plurality of pixels, and the floating diffusion is shared between the plurality of pixels. Can be configured. Further, in the first pixel portion and the second pixel portion, pixel addition can be performed between pixels of the same color.
  • the first pixel section and the second pixel section of the first pixel section constituent element and the second pixel section constituent element can secure a symmetry with respect to the center line between the pixel section and the pixel section.
  • the first pixel portion and the second pixel portion are formed more than the central portions of the first pixel portion and the second pixel portion. It can be configured to be arranged at a position close to the center line between them.
  • the first pixel portion and the second pixel portion can be configured to have a backside illumination pixel structure.
  • CMOS Complementary Metal Oxide Semiconductor
  • CMOS image sensor which is a type of an XY addressing type imaging device, will be described as an example of the imaging device.
  • the CMOS image sensor is an image sensor manufactured by applying a CMOS process or partially using it.
  • FIG. 1 is a block diagram showing an outline of a basic configuration of a CMOS image sensor which is an example of the image pickup apparatus of the present disclosure.
  • the CMOS image sensor 1 has a configuration including a pixel array section 11 and a peripheral circuit section of the pixel array section 11.
  • the pixel array unit 11 includes pixels 2 including light receiving units (photoelectric conversion units) arranged two-dimensionally in the row direction and the column direction, that is, in a matrix.
  • the row direction means the arrangement direction of the pixels 2 in the pixel row (so-called horizontal direction)
  • the column direction means the arrangement direction of the pixels 2 in the pixel column (so-called vertical direction).
  • the pixel 2 performs photoelectric conversion to generate and accumulate photocharges according to the amount of received light.
  • the peripheral circuit section of the pixel array section 11 includes, for example, a row selection section 12, a constant current source section 13, an analog-digital conversion section 14, a horizontal transfer scanning section 15, a signal processing section 16, a timing control section 17, and the like. Has been done.
  • pixel control lines 31 1 to 31 m are arranged along the row direction for each pixel row with respect to the matrix-shaped pixel array. Is wired.
  • vertical signal lines 32 1 to 32 n (hereinafter, may be collectively referred to as “vertical signal line 32”) are arranged along the column direction for each pixel column.
  • the pixel control line 31 transmits a drive signal for driving when reading a signal from the pixel 2.
  • the pixel control line 31 is illustrated as one wiring, but the number is not limited to one.
  • One end of the pixel control line 31 is connected to the output end corresponding to each row of the row selection unit 12.
  • the control unit 17 will be described.
  • the row selection unit 12 is configured by a shift register, an address decoder, and the like, and controls the scanning of the pixel row and the address of the pixel row when selecting each pixel 2 of the pixel array unit 11.
  • the row selection section 12 generally has two scanning systems, a read scanning system and a sweep scanning system.
  • the read scanning system sequentially selects and scans the pixels 2 of the pixel array unit 11 in units of rows in order to read pixel signals from the pixels 2.
  • the pixel signal read from the pixel 2 is an analog signal.
  • the sweep-out scanning system performs sweep-out scanning with respect to the read-out row in which read-out scanning is performed by the read-out scanning system, prior to the read-out scanning by the shutter speed time.
  • the electronic shutter operation refers to an operation of discarding the photocharges of the photoelectric conversion unit and newly starting the exposure (starting the accumulation of the photocharges).
  • the constant current source unit 13 includes a plurality of current sources I each composed of, for example, a MOS transistor, connected to each of the vertical signal lines 32 1 to 32 n for each pixel column, and selectively scanned by the row selection unit 12. A bias current is supplied to each pixel 2 in the pixel row through each of the vertical signal lines 32 1 to 32 n .
  • the analog-digital conversion unit 14 is formed of a set of a plurality of analog-digital converters provided corresponding to the pixel columns of the pixel array unit 11, for example, provided for each pixel column.
  • the analog-digital conversion unit 14 is a column parallel type analog-digital conversion unit that converts an analog pixel signal output through each of the vertical signal lines 32 1 to 32 n for each pixel column into an N-bit digital signal. is there.
  • analog-digital converter in the column parallel analog-digital converter 14 for example, a single slope type analog-digital converter which is an example of a reference signal comparison type analog-digital converter can be used.
  • analog-digital converter is not limited to a single slope type analog-digital converter, but a successive approximation type analog-digital converter, a delta-sigma modulation type ( ⁇ modulation type) analog-digital converter, etc. Can be used.
  • the horizontal transfer scanning unit 15 is composed of a shift register, an address decoder, and the like, and controls the scanning of the pixel column and the address of the pixel column when reading the signal of each pixel 2 of the pixel array unit 11. Under the control of the horizontal transfer scanning unit 15, the pixel signal converted into a digital signal by the analog-digital conversion unit 14 is read out to the horizontal transfer line 18 having a 2N-bit width in pixel column units.
  • the signal processing unit 16 performs predetermined signal processing on the digital pixel signal supplied through the horizontal transfer line 18 to generate two-dimensional image data. For example, the signal processing unit 16 corrects vertical line defects and point defects, or clamps signals, and performs digital signal processing such as parallel-serial conversion, compression, encoding, addition, averaging, and intermittent operation. Or The signal processing unit 16 outputs the generated image data as an output signal of the CMOS image sensor 1 to a device in the subsequent stage.
  • the timing control unit 17 generates various timing signals, clock signals, control signals, and the like, and based on these generated signals, the row selection unit 12, the constant current source unit 13, the analog-digital conversion unit 14, the horizontal Drive control of the transfer scanning unit 15, the signal processing unit 16 and the like is performed.
  • FIG. 2 is a circuit diagram showing an example of the circuit configuration of the pixel 2.
  • the pixel 2 has, for example, a photodiode 21 as a photoelectric conversion unit that is a light receiving unit.
  • the pixel 2 has a pixel configuration including a transfer transistor 22, a reset transistor 23, an amplification transistor 24, and a selection transistor 25 in addition to the photodiode 21.
  • the four transistors of the transfer transistor 22, the reset transistor 23, the amplification transistor 24, and the selection transistor 25, for example, N-channel MOS type field effect transistors (FETs) are used.
  • FETs field effect transistors
  • the pixel 2 By configuring the pixel 2 with only N-channel transistors, it is possible to optimize the area efficiency and the process reduction viewpoint.
  • the combination of the conductivity types of the four transistors 22 to 25 illustrated here is merely an example, and the present invention is not limited to these combinations.
  • a plurality of control lines are wired commonly to each pixel 2 in the same pixel row.
  • the plurality of control lines are connected to the output terminals of the row selection unit 12 corresponding to each pixel row in pixel row units.
  • the row selection unit 12 appropriately outputs the transfer signal TRG, the reset signal RST, and the selection signal SEL to the plurality of control lines.
  • the photodiode 21 has an anode electrode connected to a low-potential-side power source (eg, ground), and photoelectrically converts the received light into a photocharge (here, photoelectron) having a charge amount corresponding to the light amount thereof. Accumulates electric charge.
  • the cathode electrode of the photodiode 21 is electrically connected to the gate electrode of the amplification transistor 24 via the transfer transistor 22.
  • the region where the gate electrode of the amplification transistor 24 is electrically connected is a floating diffusion (floating diffusion region / impurity diffusion region) FD.
  • the floating diffusion FD is a charge-voltage converter that converts charges into a voltage.
  • a transfer signal TRG that activates a high level (for example, V DD level) is applied to the gate electrode of the transfer transistor 22 from the row selection unit 12.
  • the transfer transistor 22 becomes conductive in response to the transfer signal TRG, and thus photoelectrically converts in the photodiode 21 and transfers the photocharges accumulated in the photodiode 21 to the floating diffusion FD.
  • the reset transistor 23 is connected between the node of the high-potential-side power supply voltage V DD and the floating diffusion FD.
  • a reset signal RST that activates a high level is applied to the gate electrode of the reset transistor 23 from the row selection unit 12.
  • the reset transistor 23 becomes conductive in response to the reset signal RST, and resets the floating diffusion FD by discarding the charge of the floating diffusion FD to the node of the voltage V DD .
  • the gate electrode is connected to the floating diffusion FD and the drain electrode is connected to the node of the high potential side power supply voltage V DD .
  • the amplification transistor 24 serves as an input unit of a source follower that reads out a signal obtained by photoelectric conversion in the photodiode 21. That is, the source electrode of the amplification transistor 24 is connected to the vertical signal line 32 via the selection transistor 25.
  • the amplification transistor 24 and the current source I connected to one end of the vertical signal line 32 form a source follower that converts the voltage of the floating diffusion FD into the potential of the vertical signal line 32.
  • the drain electrode of the selection transistor 25 is connected to the source electrode of the amplification transistor 24, and the source electrode is connected to the vertical signal line 32.
  • a selection signal SEL that activates the high level is applied to the gate electrode of the selection transistor 25 from the row selection unit 12.
  • the selection transistor 25 is rendered conductive in response to the selection signal SEL, and thereby transfers the signal output from the amplification transistor 24 to the vertical signal line 32 with the pixel 2 in the selected state.
  • the selection transistor 25 may have a circuit configuration connected between the node of the high-potential-side power supply voltage V DD and the drain electrode of the amplification transistor 24. Further, in this example, as the pixel circuit of the pixel 2, the 4Tr configuration including the transfer transistor 22, the reset transistor 23, the amplification transistor 24, and the selection transistor 25, that is, four transistors (Tr) has been described as an example. , But is not limited to this.
  • the selection transistor 25 may be omitted, and the amplification transistor 24 may have a 3Tr configuration in which the function of the selection transistor 25 is provided. If necessary, the number of transistors may be increased to 5Tr or more. ..
  • FIG. 3 is a block diagram showing an example of the configuration of the column parallel analog-digital conversion unit 14.
  • the analog-digital converter 14 in the CMOS image sensor 1 of the present disclosure is composed of a set of a plurality of single slope type analog-digital converters provided corresponding to the vertical signal lines 32 1 to 32 n .
  • the single-slope analog-digital converter 140 in the n-th column will be described as an example.
  • the single-slope analog-digital converter 140 has a circuit configuration including a comparator 141, a counter circuit 142, and a latch circuit 143.
  • the single-slope analog-to-digital converter 140 uses a so-called RAMP waveform (slope waveform) reference signal whose voltage value changes linearly with the passage of time.
  • the reference signal having the ramp waveform is generated by the reference signal generation unit 19.
  • the reference signal generation unit 19 can be configured using, for example, a DAC (digital-analog conversion) circuit.
  • the comparator 141 uses the analog pixel signal read from the pixel 2 as a comparison input and the ramp waveform reference signal generated by the reference signal generation unit 19 as a reference input, and compares the two signals. Then, for example, when the reference signal is larger than the pixel signal, the output of the comparator 141 is in the first state (for example, high level), and when the reference signal is less than or equal to the pixel signal, the output is in the second state ( For example, low level). Accordingly, the comparator 141 outputs a pulse signal having a pulse width corresponding to the signal level of the pixel signal, specifically, the magnitude of the signal level, as a comparison result.
  • the clock signal CLK is given to the counter circuit 142 from the timing control unit 17 at the same timing as the timing of starting the supply of the reference signal to the comparator 141. Then, the counter circuit 142 measures the pulse width period of the output pulse of the comparator 141, that is, the period from the start of the comparison operation to the end of the comparison operation by performing the counting operation in synchronization with the clock signal CLK. ..
  • the count result (count value) of the counter circuit 142 becomes a digital value obtained by digitizing an analog pixel signal.
  • the latch circuit 143 holds (latches) the digital value that is the count result of the counter circuit 142. Further, the latch circuit 143 is an example of noise removal processing by calculating the difference between the D-phase count value corresponding to the signal level pixel signal and the P-phase count value corresponding to the reset level pixel signal. , CDS (Correlated Double Sampling). Then, under the drive of the horizontal transfer scanning unit 15, the latched digital value is output to the horizontal transfer line 18.
  • the reference signal of the linearly changing analog value generated by the reference signal generation unit 19 and the pixel A digital value is obtained from time information until the magnitude relationship with the analog pixel signal output from 2 changes.
  • the analog-to-digital conversion unit 14 in which the analog-to-digital converter 140 is arranged in a one-to-one relationship with the pixel column is illustrated, but the analog-to-digital conversion is performed in units of a plurality of pixel columns. It is also possible to use the analog-digital conversion unit 14 in which the converter 140 is arranged.
  • Chip structure Examples of the chip (semiconductor integrated circuit) structure of the CMOS image sensor 1 having the above configuration include a flat chip structure and a laminated chip structure.
  • the flat type chip structure and the laminated type chip structure will be specifically described below.
  • FIG. 4 is a plan view showing an outline of a flat type chip structure of the CMOS image sensor 1.
  • a flat chip structure that is, a flat structure, has a circuit around the pixel array unit 11 on the same semiconductor substrate 41 as the pixel array unit 11 in which the pixels 2 are arranged in a matrix. It has a structure in which parts are formed. Specifically, on the same semiconductor substrate 41 as the pixel array unit 11, the row selection unit 12, the constant current source unit 13, the analog-digital conversion unit 14, the horizontal transfer scanning unit 15, the signal processing unit 16, and the timing control. The part 17 and the like are formed.
  • FIG. 5 is an exploded perspective view schematically showing a layered chip structure of the CMOS image sensor 1.
  • a laminated chip structure a so-called laminated structure, is a structure in which at least two semiconductor substrates of a first semiconductor substrate 42 and a second semiconductor substrate (so-called logic chip) 43 are laminated.
  • the first semiconductor substrate 42 is a so-called pixel chip
  • the second semiconductor substrate 43 is a so-called logic chip.
  • the pixel array section 11 is formed on the first semiconductor substrate 42 of the first layer.
  • the circuit parts such as the row selection part 12, the constant current source part 13, the analog-digital conversion part 14, the horizontal transfer scanning part 15, the signal processing part 16 and the timing control part 17 are the second semiconductor of the second layer. It is formed on the substrate 43.
  • the first semiconductor substrate 42 of the first layer and the second semiconductor substrate 43 of the second layer are electrically connected to each other through a connecting portion 44 such as a bump, a via (VIA), or a Cu—Cu connection.
  • the size (area) of the first semiconductor substrate 42 is sufficient to form the pixel array section 11, and thus the size (area) of the first semiconductor substrate 42 of the first layer is required. ), And eventually, the size of the entire chip can be reduced. Further, a process suitable for manufacturing the pixel 2 can be applied to the first semiconductor substrate 42 of the first layer, and a process suitable for manufacturing a circuit portion can be applied to the second semiconductor substrate 43 of the second layer. In manufacturing the image sensor 1, there is also an advantage that the process can be optimized. In particular, when manufacturing a circuit portion, it is possible to apply an advanced process.
  • the laminated structure of the two-layer structure in which the first semiconductor substrate 42 and the second semiconductor substrate 43 are laminated is illustrated, but the laminated structure is not limited to the two-layer structure, and three or more layers are included. It can also be a structure of. In the case of a laminated structure of three layers or more, circuit parts such as the row selection part 12, the constant current source part 13, the analog-digital conversion part 14, the horizontal transfer scanning part 15, the signal processing part 16, and the timing control part 17 Can be formed dispersedly on the second and subsequent semiconductor substrates.
  • the addition read method includes a logic addition method in which addition is performed in the subsequent stage of the analog-digital conversion unit 14, an AD (analog-digital) addition method in which addition is performed in the analog-digital conversion unit 14, and addition on the vertical signal line 32.
  • FIG. 6 is an explanatory diagram showing an outline of addition reading in the logic addition method.
  • the output terminals of the vertical signal lines 32 1 and 32 2 are connected to the input terminals of the analog-digital converters (ADC) 140 1 and 140 2 .
  • ADC analog-digital converters
  • the pixel signal of the pixel 1 is supplied to the analog-digital converter 140 1 through the vertical signal line 32 1 and converted into a digital signal.
  • the pixel signal of the pixel 2 is supplied to the analog-digital converter 140 2 through the vertical signal line 32 2 and converted into a digital signal.
  • the analog - the digital converter 140 1, 140 2 of the subsequent logic circuit 30, an analog - addition processing for each pixel signal of the digital converter 140 1, 140 2 pixels 1 and 2 are converted into digital signals by the row Be seen.
  • FIG. 7 is an explanatory diagram showing an outline of the addition reading of the AD addition method.
  • the output terminals of the vertical signal lines 32 1 and 32 2 are connected to the respective ends of the switches SW 1 and SW 2 .
  • Sample-and-hold capacitors SH 1 and SH 2 are connected between the other ends of the switches SW 1 and SW 2 and the ground.
  • a switch SW 3 is connected between the other ends of the switches SW 1 and SW 2 .
  • the pixel signals of the pixels 1 and 2 read out through the vertical signal lines 32 1 and 32 2 are sampled and held in the sample and hold capacitors SH 1 and SH 2 , and then supplied to the analog-digital converter 140 1 .
  • the analog-to-digital converter 140 1 adds and the analog-to-digital conversion processing is performed.
  • FIG. 8 is an explanatory diagram showing an outline of addition reading in the SF addition method.
  • the amplification transistor 24 of each pixel and the current source I connected to one end of the vertical signal line 32 (32 1 to 32 n ) form a source follower. Then, each pixel signal of the pixels 1 and 2 is read out to the same vertical signal line 32 1 , and the addition processing is performed in the source follower.
  • FIG. 9 is an explanatory diagram showing an outline of addition reading in the FD addition method.
  • a switch transistor 26 that selectively connects the FD nodes is connected between the floating diffusions FD of the pixels 1 and 2. Then, by making the switch transistor 26 conductive, addition processing is performed on the pixel signals of the pixels 1 and 2 between the floating diffusions FD of the pixels 1 and 2.
  • the numerical values shown in FIG. 10 are relative values of the current consumption of the current source I connected to one end of the vertical signal line 32 and the analog-digital converter 140.
  • each pixel signal of the pixels 1 and 2 is read through the two vertical signal lines 32 1 and 32 2 , and in the case of the logic addition method, two analog-digital converters 140 1 , 140 2 is used to perform addition processing. Therefore, the SF addition method and the FD addition method in which the pixel signals of the pixels 1 and 2 are read through one vertical signal line 32 1 have lower power consumption than the logic addition method and the AD addition method.
  • the SF addition method has a problem in the linearity of the signal after addition.
  • the linearity problem of this SF addition method will be described with reference to FIG.
  • the signal V o after addition can follow the average value of the pixel signals V 1 and V 2 .
  • the signal V o after addition is clipped to the higher potential of the pixel signals V 1 and V 2 , and ideally the pixel It becomes impossible to follow the average value of the signals V 1 and V 2 .
  • the FD addition method is the best as the addition reading method among the logic addition method, the AD addition method, the SF addition method, and the FD addition method.
  • the wirings L 1 and L 2 for selectively connecting the FD nodes (FD 1 -FD 2 ) of two pixels and the switch transistor 26 are simply connected. If provided, an extra parasitic capacitance will be attached to the FD node.
  • the extra parasitic capacitance attached to the FD node is the parasitic capacitances c 11 and c 12 of the wirings L 1 and L 2 , the coupling capacitances c 21 and c 22 between the gate electrode of the switch transistor 26 and the drain / source region, and the drain. / Diffusion capacitances c 31 , c 32, etc. of the source region.
  • the conversion efficiency is the efficiency of converting charges into voltage in the floating diffusion FD. This conversion efficiency is determined by the capacitance of the floating diffusion FD (including the parasitic capacitance).
  • the FD nodes of two pixels are selectively connected via a switch for switching the conversion efficiency, and when the switch is in a non-conducting state.
  • the parasitic capacitance of the wiring for short-circuiting the FD nodes of two pixels does not attach to the FD node as an extra capacitance. Therefore, in the related art, although the conversion efficiency does not decrease in the still image mode, pixel addition by FD addition can be performed only in the low conversion efficiency state.
  • a read mode without pixel addition by FD addition (still image mode).
  • the read mode with pixel addition moving image mode
  • the conversion efficiency can be switched in a plurality of stages. Specifically, the conversion efficiency of the read mode without pixel addition can be switched in three stages of low / medium / high. As a result, the degree of freedom in optimal setting of the noise characteristic / maximum charge amount Q s increases according to the ISO sensitivity.
  • Example 1 is a basic form of a pixel circuit according to an embodiment that performs pixel addition by FD addition, and is an example in which each of the first and second pixel portions is composed of a single pixel.
  • FIG. 13 shows the circuit configuration of the pixel circuit according to the first embodiment.
  • pixel addition is selectively performed between the first pixel unit 20A and the second pixel unit 20B that are vertically adjacent to each other in a certain pixel column.
  • the first pixel section 20A is composed of a single pixel 1
  • the second pixel section 20B is composed of a single pixel 2.
  • Each of the pixel 1 and the pixel 2 has a photodiode 21, which is an example of a light receiving portion, a transfer transistor 22, a floating diffusion FD (FD 1 / FD 2 ), an amplification transistor 24, and a selection transistor 25.
  • the pixel 1 has a first switch transistor 26 1 , a reset transistor 23, and a capacitive element C 1 in addition to the above circuit elements.
  • the first one of the source / drain electrode of the switching transistor 26 1 is connected to the floating diffusion FD 1.
  • the reset transistor 23 is connected between the other source / drain electrode of the first switch transistor 26 1 and the power supply node of the power supply voltage V DD .
  • a common connection node between the other source / drain electrode of the first switch transistor 26 1 and one source / drain electrode of the reset transistor 23 is defined as a node FD s .
  • the pixel 2 has a second switch transistor 26 2 , a third switch transistor 27, and a capacitive element C 2 in addition to the above circuit elements.
  • the second one of the source / drain electrode of the switch transistor 26 2 is connected to the floating diffusion FD 2.
  • One source / drain electrode of the third switch transistor 27 is connected to the other source / drain electrode of the second switch transistor 26 2 .
  • a common connection node between the other source / drain electrode of the second switch transistor 26 2 and one source / drain electrode of the third switch transistor 27 is a node FD s .
  • the capacitive elements C 1 and C 2 are divided and arranged in a pixel 1 and a pixel 2.
  • the capacitive element C 1 arranged in the pixel 1 has one end connected to the other source / drain electrode of the third switch transistor 27 via the line L b and the other end serving as a reference potential node. It is connected to the GND node.
  • a common connection node between one end of the capacitive element C 1 and the wiring L b is a node FD b .
  • the capacitive element C 2 arranged in the pixel 2 has one end connected to the other source / drain electrode of the third switch transistor 27 and the other end connected to the GND node.
  • a common connection node between one end of the capacitive element C 2 and the other source / drain electrode of the third switch transistor 27 is a node FD b .
  • the wiring L is provided between the node FD s which is a connection node of the other source / drain electrode of the second switch transistor 26 1 and the other source / drain electrode of the second switch transistor 26 2. It is electrically connected by s . Further, the node FD b, which is a connection node at one end of each of the capacitive elements C 1 and C 2 , is electrically connected by the wiring L b .
  • the conversion efficiency in the read mode (still image mode) without pixel addition can be switched between low / middle / high in three stages.
  • the first switch transistor 26 1 and the second switch transistor 26 2 are turned off.
  • the conversion efficiencies of the floating diffusions FD 1 and FD 2 are determined by the capacitances of the FD 1 node and the FD 2 node, resulting in high conversion efficiency.
  • the first switch transistor 26 1, the second switch transistor 26 2, and the third switch transistor 27 are both turned on.
  • the capacitance element C 1 is included in the capacitances of the FD 1 node and the FD 2 node.
  • C 2 and the parasitic capacitance of the line L b connecting the node FD b are both turned on.
  • the conversion efficiency of the readout mode (video mode) with pixel addition can be switched between low and medium.
  • both the first switch transistor 26 1 and the second switch transistor 26 2 are in the conductive state, so that the conversion efficiency is the respective capacitances of the FD 1 node and the FD 2 node, ,
  • the second switch transistors 26 1 and 26 2 have their respective gate capacitances and the parasitic capacitance of the wiring L s determined, resulting in medium conversion efficiency.
  • the conversion efficiency is FD 1 node and FD 2 node.
  • the gate capacitances of the first and second switch transistors 26 1 and 26 2 , the parasitic capacitance of the wiring L s , and the parasitic capacitance of the wiring L b resulting in low conversion efficiency.
  • FIG. 14 is a timing chart for explaining the operation in the case of high conversion efficiency in the still image mode without pixel addition.
  • the horizontal synchronization signal XHS, the reset signal RST, the first switch signal FDL 1 , the second switch signal FDL 2 , the third switch signal FDG, and the transfer signals TRG 1 and TRG 2 are shown. The timing relationship is shown. The same applies to each timing chart described later.
  • the reset signal RST and the first switch signal FDL 1 transit from the low level to the high level at the time t 11 to reset the reset transistor 23 and the first switch transistor. 26 1 becomes conductive. As a result, the floating diffusion FD 1 of the pixel 1 is reset. In this case, the level of the second switch signal FDL 2 does not matter.
  • the first switch signal FDL 1 makes a transition from a high level to a low level
  • the transfer signal TRG 1 makes a transition from a low level to a high level, whereby the transfer transistor of the pixel 1 22 becomes conductive and the pixel signal is read out from the pixel 1.
  • the reset signal RST at time t 15 transitions from high to low.
  • the reset signal RST and the second switch signal FDL 2 make a transition from the low level to the high level at time t 11 to thereby reset the reset transistor 23 and the second switch transistor. 26 2 becomes conductive. As a result, the floating diffusion FD 2 of the pixel 2 is reset. In this case, the level of the first switch signal FDL 1 is irrelevant.
  • the second switch signal FDL 2 makes a transition from a high level to a low level
  • the transfer signal TRG 2 makes a transition from a low level to a high level, whereby the transfer transistor of the pixel 2 22 becomes conductive, and the pixel signal is read out from the pixel 2.
  • the transfer signal TRG 2 changes from the high level to the low level
  • the reset signal RST changes from the high level to the low level.
  • FIG. 15 is a timing chart for explaining the operation in the case of medium conversion efficiency in the still image mode without pixel addition.
  • the transfer signal TRG 1 transits from the low level to the high level at the time t 23 , whereby the transfer transistor 22 of the pixel 1 becomes conductive. Then, the pixel signal is read out from the pixel 1. Then, the transfer signal TRG 1 at time t 24 is after the transition from the high level to the low level at time t 25 the first switch signal FDL 1 and a second switch signal FDL 2 transitions from high to low.
  • Readout of Pixel 2 In reading out the pixel signal of the pixel 2, resetting is performed by transitioning the reset signal RST, the first switch signal FDL 1 and the second switch signal FDL 2 from low level to high level at time t 21.
  • the transistor 23, the first switch transistor 26 1 and the second switch transistor 26 2 are turned on. As a result, the floating diffusion FD 1 of the pixel 1 and the floating diffusion FD 2 of the pixel 2 are reset.
  • the transfer signal TRG 2 transits from the low level to the high level at the time t 23 , whereby the transfer transistor 22 of the pixel 2 becomes conductive. Then, the pixel signal is read out from the pixel 2. Then, the transfer signal TRG 2 at time t 24 is after the transition from the high level to the low level at time t 25 the first switch signal FDL 1 and a second switch signal FDL 2 transitions from high to low.
  • FIG. 16 is a timing chart for explaining the operation in the case of low conversion efficiency in the still image mode without pixel addition.
  • the reset signal RST, the first switch signal FDL 1 , the second switch signal FDL 2 , and the third switch signal FDG are changed from the low level at time t 31.
  • the transition to the high level brings the reset transistor 23, the first switch transistor 26 1 , the second switch transistor 26 2 , and the third switch transistor 27 into the conductive state.
  • the floating diffusion FD 1 of the pixel 1 and the floating diffusion FD 2 of the pixel 2 are reset, and the capacitive elements C 1 and C 2 are connected to the node FD s .
  • the transfer signal TRG 1 transits from the low level to the high level at the time t 33 , whereby the transfer transistor 22 of the pixel 1 becomes conductive. Then, the pixel signal is read out from the pixel 1.
  • the transfer signal TRG 1 at time t 34 transitions from high to low
  • the first switch signal FDL 1 at time t 35, the second switch signal FDL 2, and the third switch signal FDG Transition from high level to low level.
  • the reset signal RST, the first switch signal FDL 1 , the second switch signal FDL 2 , and the third switch signal FDG are changed from the low level at time t 31.
  • the transition to the high level brings the reset transistor 23, the first switch transistor 26 1 , the second switch transistor 26 2 , and the third switch transistor 27 into the conductive state.
  • the floating diffusion FD 1 of the pixel 1 and the floating diffusion FD 2 of the pixel 2 are reset, and the capacitive elements C 1 and C 2 are connected to the node FD s .
  • the transfer signal TRG 2 transits from the low level to the high level at the time t 33 , so that the transfer transistor 22 of the pixel 2 becomes conductive. Then, the pixel signal is read out from the pixel 2.
  • the transfer signal TRG 2 at time t 34 transitions from high to low
  • the first switch signal FDL 1 at time t 35, the second switch signal FDL 2, and the third switch signal FDG Transition from high level to low level.
  • FIG. 17A is a timing chart for explaining the operation in the case of additive read at medium conversion efficiency.
  • the reset signal RST, the first switch signal FDL 1, and the second switch signal FDL 2 transit from the low level to the high level, so that the reset transistor 23, the first switch transistor 26 1, and the second switch signal 26 1 .
  • the switch transistor 26 2 becomes conductive.
  • the floating diffusion FD 1 of the pixel 1 and the floating diffusion FD 2 of the pixel 2 are reset.
  • both the transfer signal TRG 1 of the pixel 1 and the transfer signal TRG 2 of the pixel 2 transit from the low level to the high level at the time t 43.
  • both the transfer transistors 22 of the pixel 1 and the pixel 2 become conductive.
  • addition reading of pixel signals is performed between the pixel 1 and the pixel 2.
  • FIG. 17B is a timing chart for explaining the operation in the case of additive readout with low conversion efficiency.
  • the reset signal RST, the first switch signal FDL 1 , the second switch signal FDL 2 , and the third switch signal FDG transit from the low level to the high level.
  • the switch transistor 26 1 , the second switch transistor 26 2 , and the third switch transistor 27 are turned on.
  • the floating diffusion FD 1 of the pixel 1 and the floating diffusion FD 2 of the pixel 2 are reset, and the capacitive elements C 1 and C 2 are connected to the node FD s .
  • both the transfer signal TRG 1 of the pixel 1 and the transfer signal TRG 2 of the pixel 2 transit from the low level to the high level at the time t 43.
  • both the transfer transistors 22 of the pixel 1 and the pixel 2 become conductive.
  • addition reading of pixel signals is performed between the pixel 1 and the pixel 2.
  • FIG. 18 A layout diagram (plan view) of the pixel circuit according to the first embodiment is shown in FIG. 18, and a sectional view taken along the line XX of FIG. 18 is shown in FIG. In FIG. 18, the gate electrodes of the respective transistors are illustrated by hatching for easy understanding.
  • the floating diffusion FD 1 and the floating diffusion FD 2 are arranged closer to the center line O than the central portions of the pixels 1 and 2.
  • the floating diffusion FD 1 and the floating diffusion FD 2 have a close positional relationship.
  • the wiring L s of each node FD b of the pixel 1 and the pixel 2 can be short, and the parasitic capacitance of the wiring L s can be reduced, so that the medium conversion efficiency at the time of pixel addition can be increased. it can.
  • the capacitive element C 1 of the pixel 1 and the capacitive element C 2 of the pixel 2 which determine the low conversion efficiency can be configured as one capacitive element common to the pixel 1 and the pixel 2. However, it is preferable to divide and arrange the pixel 1 and the pixel 2 because the symmetry of the pixel layout can be improved and the uniformity of the pixel characteristics can be ensured.
  • the capacitive element C 1 of the pixel 1 and the capacitive element C 2 of the pixel 2 can be realized by the coupling capacitance between the metal wiring M 11 and the metal wiring M 12 .
  • the implementation is not limited to the coupling capacitance between the metal wirings M 11 and M 12 , and may be implemented by a capacitive element using an oxide film, for example.
  • the pixel structure of the first pixel section 20A and the second pixel section 20B when the substrate surface on the side where the wiring layer is arranged is the front surface (front surface), the light emitted from the back surface side on the opposite side is used.
  • a back-illuminated pixel structure for capturing light can be used, or a front-illuminated pixel structure for capturing light emitted from the front surface can be used.
  • the metal wirings M 11 and M 12 forming the capacitive element C 1 and the capacitive element C 2 should be prevented from protruding into the region of the photodiode 21 (PD 1 , PD 2 ). It is important to place When the metal wirings M 11 and M 12 protrude into the area of the photodiode 21, the opening area of the photodiode 21 is reduced.
  • the arrangement of the metal wirings M 11 and M 12 is of the front-illuminated type.
  • the metal wirings M 11 and M 12 forming the capacitive elements C 1 and C 2 can be arranged so as to be widened to the region of the photodiode 21 and thus larger. Capacitance elements C 1 and C 2 having a capacitance value can be realized.
  • the second embodiment is an example in which the first and second pixel portions each include a plurality of pixels, and the floating diffusion FD is shared between the plurality of pixels.
  • the circuit configuration of the pixel circuit according to the second embodiment is shown in FIG.
  • a circuit configuration in which the first and second pixel units 20A and 20B each include two pixels and the floating diffusion FD is shared between the photodiodes (PD) 21 of the two pixels is illustrated.
  • the reset transistor 23 / the third switch transistor 27, the amplification transistor 24, the selection transistor 25, and the first photodiode 21 (PD 1 / PD 2 ) are provided in each photodiode 21 (PD 1 / PD 2 ).
  • Switch transistor 26 1 / second switch transistor 26 2 of the above is exclusively allocated. Therefore, the opening area of the pixel becomes small.
  • the floating diffusion FD and the subsequent circuit elements are provided between the photodiodes (PD 11 , PD 12 / PD 21 , PD 2 ) of the two pixels.
  • the circuit elements after the floating diffusion FD are the reset transistor 23, the amplification transistor 24, the selection transistor 25, and the first switch transistor 26 1 in the first pixel section 20A, and the circuit elements in the second pixel section 20B are The third switch transistor 27, the amplification transistor 24, the selection transistor 25, and the second switch transistor 26 2 .
  • the technology of the pixel circuit according to the first embodiment can be applied to the pixel circuit according to the second embodiment with FD sharing.
  • the conversion efficiency of the read mode (still image mode) without pixel addition can be switched to three stages of low / middle / high, and the pixel addition can be performed.
  • the existing moving image mode it is possible to perform addition reading with medium conversion efficiency and addition reading with low conversion efficiency.
  • two vertical pixels form a group sharing the floating diffusion FD (a group of pixels surrounded by a broken line in the figure). Specifically, the red pixel R and the green pixel Gb, and the green pixel Gr and the blue pixel B are set to share the floating diffusion FD.
  • the charges photoelectrically converted by the photodiode (PD) 21 of each pixel in the set are read, but in the moving image mode, pixel signals are added between adjacent two pixels of the same color in the vertical direction. Specifically, the pixel R 1 and the pixel R 2 , the pixel Gb 1 and the pixel Gb 2 , the pixel Gr 1 and the pixel Gr 2 , and the pixel B 1 and the pixel B 2 are added.
  • FIG. 20 A unit circuit for pixel addition of the same color is shown in FIG.
  • the pixel 1 including the photodiode PD 11 is the pixel R 1
  • the pixel 2 including the photodiode PD 12 is the pixel Gb 1
  • the pixel 3 including the photodiode PD 21 is the pixel R 2
  • the pixel 4 including the diode PD 22 corresponds to the pixel Gb 2 .
  • the circuit operation in the still image mode without pixel addition and the moving image mode with pixel addition in the pixel circuit according to the second embodiment will be described.
  • the two pixels of the first pixel unit 20A are the pixels 1 and 2
  • the two pixels of the second pixel unit 20B are the pixels 3 and 4.
  • FIG. 22 is a timing chart for explaining the operation in the case of high conversion efficiency in the still image mode without pixel addition.
  • the horizontal synchronization signal XHS, the reset signal RST, the first switch signal FDL 1 , the second switch signal FDL 2 , the third switch signal FDG, and the transfer signals TRG 11 , TRG 12 The timing relationship between TRG 21 and TRG 22 is shown. The same applies to each timing chart described later.
  • the reset signal RST and the first switch signal FDL 1 transit from the low level to the high level at time t 51 , so that the reset transistor 23 and the first switch transistor 26 1 It becomes conductive. As a result, the pixel-shared floating diffusion FD 1 of the first pixel unit 20A is reset. In this case, the level of the second switch signal FDL 2 does not matter.
  • the first switch signal FDL 1 transits from the high level to the low level
  • the transfer signal TRG 11 transits from the low level to the high level, whereby the transfer transistor of the pixel 1 is transferred. 22 becomes conductive, and the charges photoelectrically converted by the photodiode PD 11 are read out.
  • the reset signal RST at time t 55 transitions from high to low.
  • the second switch signal FDL 2 transits from the high level to the low level
  • the transfer signal TRG 12 transits from the low level to the high level, whereby the transfer transistor of the pixel 2 is transferred. 22 becomes conductive, and the charges photoelectrically converted by the photodiode PD 12 are read out.
  • the reset signal RST at time t 55 transitions from high to low.
  • the second switch signal FDL 2 transits from the high level to the low level
  • the transfer signal TRG 21 transits from the low level to the high level, whereby the transfer transistor of the pixel 2 is transferred. 22 becomes conductive, and the charges photoelectrically converted by the photodiode PD 21 are read out.
  • the reset signal RST at time t 55 transitions from high to low.
  • the reset signal RST and the second switch signal FDL 1 transit from the low level to the high level at time t 51 , whereby the reset transistor 23 and the second switch transistor 26 2 are changed. It becomes conductive. As a result, the pixel-shared floating diffusion FD 2 of the second pixel unit 20B is reset. In this case, the level of the first switch signal FDL 1 is irrelevant.
  • the second switch signal FDL 2 transits from the high level to the low level
  • the transfer signal TRG 22 transits from the low level to the high level, whereby the transfer transistor of the pixel 2 is transferred. 22 becomes conductive, and the charges photoelectrically converted by the photodiode PD 22 are read out.
  • the reset signal RST at time t 55 transitions from high to low.
  • FIG. 23 is a timing chart for explaining the operation in the case of high conversion efficiency in the still image mode without pixel addition.
  • the reset transistor RST, the reset signal RST, the first switch signal FDL 1 and the second switch signal FDL 2 transit from the low level to the high level at time t 51 ,
  • the first switch transistor 26 1 and the second switch transistor 26 2 are turned on.
  • the floating diffusion FD 1 pixel shared first pixel unit 20A, and, the reset floating diffusion FD 2 of pixel sharing of the second pixel unit 20B is performed.
  • the transfer transistor 22 of the pixel 1 is conductive state Then, the charges photoelectrically converted by the photodiode PD 11 are read out.
  • the reset signal RST at time t 55 transitions from high to low.
  • the transfer transistor 22 of the pixel 2 is conductive state Therefore, the charges photoelectrically converted by the photodiode PD 12 are read out.
  • the reset signal RST at time t 55 transitions from high to low.
  • the reset transistor RST, the first switch signal FDL 1 and the second switch signal FDL 2 transit from the low level to the high level at the time t 51 , and thus the reset transistor 23,
  • the first switch transistor 26 1 and the second switch transistor 26 2 are turned on.
  • the floating diffusion FD 1 pixel shared first pixel unit 20A, and, the reset floating diffusion FD 2 of pixel sharing of the second pixel unit 20B is performed.
  • the transfer transistor 22 of the pixel 2 is conductive state Then, the charges photoelectrically converted by the photodiode PD 21 are read out.
  • the reset signal RST at time t 55 transitions from high to low.
  • the reset transistor RST, the first switch signal FDL 1 and the second switch signal FDL 2 transit from the low level to the high level at the time t 51 , so that the reset transistor 23, The first switch transistor 26 1 and the second switch transistor 26 2 are turned on.
  • the floating diffusion FD 1 pixel shared first pixel unit 20A, and, the reset floating diffusion FD 2 of pixel sharing of the second pixel unit 20B is performed.
  • the transfer transistor 22 of the pixel 2 is conductive state Then, the charges photoelectrically converted by the photodiode PD 22 are read out.
  • the reset signal RST at time t 55 transitions from high to low.
  • FIG. 24 is a timing chart for explaining the operation in the case of low conversion efficiency in the still image mode without pixel addition.
  • the reset signal RST, the first switch signal FDL 1 , the second switch signal FDL 2 , and the third switch signal FDG change from low level to high level.
  • the reset transistor 23, the first switch transistor 26 1 , the second switch transistor 26 2 , and the third switch transistor 27 become conductive.
  • the floating diffusion FD 1 pixel shared first pixel unit 20A, and, the reset floating diffusion FD 2 of pixel sharing of the second pixel unit 20B is performed. Furthermore, the node FD s is connected to the capacitive element C 11 of the pixel 1, the capacitive element C 12 of the pixel 2, the capacitive element C 21 of the pixel 3, and the capacitive element C 22 of the pixel 4.
  • the transfer transistor 22 of the pixel 1 is conductive state Then, the charges photoelectrically converted by the photodiode PD 11 are read out.
  • the reset signal RST at time t 55 transitions from high to low.
  • the reset signal RST, the first switch signal FDL 1 , the second switch signal FDL 2 , and the third switch signal FDG are changed from the low level to the high level at time t 51.
  • the reset transistor 23, the first switch transistor 26 1 , the second switch transistor 26 2 , and the third switch transistor 27 become conductive.
  • the floating diffusion FD 1 pixel shared first pixel unit 20A, and, the reset floating diffusion FD 2 of pixel sharing of the second pixel unit 20B is performed. Furthermore, the node FD s is connected to the capacitive element C 11 of the pixel 1, the capacitive element C 12 of the pixel 2, the capacitive element C 21 of the pixel 3, and the capacitive element C 22 of the pixel 4.
  • the transfer transistor 22 of the pixel 2 is conductive state Therefore, the charges photoelectrically converted by the photodiode PD 12 are read out.
  • the reset signal RST at time t 55 transitions from high to low.
  • the reset signal RST at time t 51, the first switch signal FDL 1, the second switch signal FDL 2, and the third switch signal FDG is a high level from a low level
  • the reset transistor 23, the first switch transistor 26 1 , the second switch transistor 26 2 , and the third switch transistor 27 become conductive.
  • the floating diffusion FD 1 pixel shared first pixel unit 20A, and, the reset floating diffusion FD 2 of pixel sharing of the second pixel unit 20B is performed. Furthermore, the node FD s is connected to the capacitive element C 11 of the pixel 1, the capacitive element C 12 of the pixel 2, the capacitive element C 21 of the pixel 3, and the capacitive element C 22 of the pixel 4.
  • the transfer transistor 22 of the pixel 2 is conductive state Then, the charges photoelectrically converted by the photodiode PD 21 are read out.
  • the reset signal RST at time t 55 transitions from high to low.
  • the reset signal RST, the first switch signal FDL 1 , the second switch signal FDL 2 , and the third switch signal FDG change from low level to high level.
  • the reset transistor 23, the first switch transistor 26 1 , the second switch transistor 26 2 , and the third switch transistor 27 become conductive.
  • the floating diffusion FD 1 pixel shared first pixel unit 20A, and, the reset floating diffusion FD 2 of pixel sharing of the second pixel unit 20B is performed. Furthermore, the node FD s is connected to the capacitive element C 11 of the pixel 1, the capacitive element C 12 of the pixel 2, the capacitive element C 21 of the pixel 3, and the capacitive element C 22 of the pixel 4.
  • the transfer transistor 22 of the pixel 2 is conductive state Then, the charges photoelectrically converted by the photodiode PD 22 are read out.
  • the reset signal RST at time t 55 transitions from high to low.
  • the floating diffusions FD 1 and FD of pixel sharing are shared.
  • conversion efficiency of 2 high / medium / low will be switched in three stages.
  • the addition reading of the pixels 1 and 3 is the addition reading of the respective charges of the photodiode PD 11 and the photodiode PD 21
  • the addition reading of the pixels 2 and 4 is the photodiode PD 12.
  • the additional reading of each charge of the photodiode PD 22 is the photodiode PD 22 .
  • FIG. 25A is a timing chart for explaining the operation in the case of additive readout of pixel 1 and pixel 3 at medium conversion efficiency.
  • the reset signal RST, the first switch signal FDL 1, and the second switch signal FDL 2 transit from the low level to the high level, so that the reset transistor 23, the first switch transistor 26 1, and the second switch signal 26 1 .
  • the switch transistor 26 2 becomes conductive.
  • the floating diffusion FD 1 pixel shared first pixel unit 20A, and, the reset floating diffusion FD 2 of pixel sharing of the second pixel unit 20B is performed.
  • the transfer signals TRG 11 and TRG 21 transition from the high level to the low level, and then at time t 65 , the first switch signal FDL 1 and the second switch signal FDL 2 change from the high level to the low level. Transition.
  • FIG. 25B is a timing chart for explaining the operation in the case of additive readout of pixel 2 and pixel 4 at medium conversion efficiency.
  • the reset signal RST, the first switch signal FDL 1, and the second switch signal FDL 2 transit from the low level to the high level, so that the reset transistor 23, the first switch transistor 26 1, and the second switch signal 26 1 .
  • the switch transistor 26 2 becomes conductive.
  • the floating diffusion FD 1 pixel shared first pixel unit 20A, and, the reset floating diffusion FD 2 of pixel sharing of the second pixel unit 20B is performed.
  • the transfer signals TRG 11 and TRG 21 transit from the high level to the low level, and at time t 65 , the first switch signal FDL 1 and the second switch signal FDL 2 change from the high level to the low level. Transition.
  • FIG. 26A is a timing chart for explaining the operation in the case of additive readout of pixel 1 and pixel 3 at low conversion efficiency.
  • the reset signal RST, the first switch signal FDL 1 , the second switch signal FDL 2 , and the third switch signal FDG transit from the low level to the high level, so that the reset transistor 23, the first The switch transistor 26 1 , the second switch transistor 26 2 , and the third switch transistor 27 are turned on.
  • the floating diffusion FD 1 pixel shared first pixel unit 20A, and, the reset floating diffusion FD 2 of pixel sharing of the second pixel unit 20B is performed.
  • the node FD s is connected to the capacitive element C 11 of the pixel 1, the capacitive element C 12 of the pixel 2, the capacitive element C 21 of the pixel 3, and the capacitive element C 22 of the pixel 4.
  • the transfer signal TRG 21 of the transfer signal TRG 11 and pixel 3 of the pixel 1 at time t 63 transitions both from the low level to the high level
  • both the transfer transistor 22 of the pixel 1 and the transfer transistor 22 of the pixel 3 become conductive.
  • addition reading of pixel signals is performed between the photodiode PD 11 of the pixel 1 and the photodiode PD 21 of the pixel 3, that is, between the pixels R 1 and R 2 of the same color.
  • the transfer signals TRG 11 and TRG 21 transition from the high level to the low level, and then at time t 65 , the first switch signal FDL 1 and the second switch signal FDL 2 change from the high level to the low level. Transition.
  • FIG. 26B is a timing chart for explaining the operation in the case of additive readout of pixel 2 and pixel 4 with low conversion efficiency.
  • the reset signal RST, the first switch signal FDL 1 , the second switch signal FDL 2 , and the third switch signal FDG transit from the low level to the high level, so that the reset transistor 23, the first The switch transistor 26 1 , the second switch transistor 26 2 , and the third switch transistor 27 are turned on.
  • the floating diffusion FD 1 pixel shared first pixel unit 20A, and, the reset floating diffusion FD 2 of pixel sharing of the second pixel unit 20B is performed.
  • the node FD s is connected to the capacitive element C 11 of the pixel 1, the capacitive element C 12 of the pixel 2, the capacitive element C 21 of the pixel 3, and the capacitive element C 22 of the pixel 4.
  • the transfer signal TRG 22 of the pixel 2 transfer signal TRG 12 and the pixel 4 at time t 63 transitions both from the low level to the high level
  • both the transfer transistor 22 of the pixel 2 and the transfer transistor 22 of the pixel 4 become conductive.
  • pixel signal addition reading is performed between the photodiode PD 12 of the pixel 2 and the photodiode PD 22 of the pixel 4, that is, between the pixels Gb 1 and Gb 2 of the same color.
  • the first switch signal FDL 1 and the second switch signal FDL 2 change from the high level to the low level at time t 65 . Transition.
  • the floating diffusions FD 1 and FD 2 of pixel sharing are shared. Regarding the conversion efficiency of, the two-stage switching of medium / low will be performed.
  • FIG. 27 shows a layout diagram (plan view) of the pixel circuit according to the second embodiment
  • FIG. 28 is a sectional view taken along the line YY of FIG. 27.
  • the gate electrodes of the respective transistors are illustrated by hatching for easy understanding.
  • the constituent elements of the pixel 1 and the pixel 2 which are the first pixel section 20A and the constituent elements of the pixel 3 and the pixel 4 which are the second pixel section 20B are the same as those of the first pixel section 20A and the second pixel section 20B.
  • the pixel layout ensures symmetry with respect to the center line O between the and.
  • the first pixel section 20A and the second pixel It can be configured as one capacitive element common to the section 20B.
  • the metal wiring M 11 and the metal wiring M 11 are provided. It can be realized by the coupling capacity with M 12 .
  • the implementation is not limited to the coupling capacitance between the metal wirings M 11 and M 12 , and may be implemented by a capacitive element using an oxide film, for example.
  • the surface irradiation type is used. It is preferable to use a back-illuminated pixel structure which does not have the limitation as in the case of the pixel structure of.
  • the metal wirings M 11 and M 12 that form the capacitive elements C 11 , C 12 , C 21 , and C 22 can be arranged so as to be extended to the region of the photodiode 21, so that the capacitive elements having a larger capacitance value can be arranged.
  • C 11 , C 12 , C 21 , and C 22 can be realized.
  • the technique according to the present disclosure is limited to the application to the CMOS image sensor. Not a thing. That is, the technique according to the present disclosure can be applied to all XY addressing type image pickup devices in which pixels 2 are two-dimensionally arranged in a matrix.
  • the imaging device according to the present embodiment described above can be used in various devices that sense light such as visible light, infrared light, ultraviolet light, and X-rays, as shown in FIG. 29, for example. Specific examples of various devices are listed below.
  • -A device that captures images used for viewing, such as a digital camera or a portable device with a camera function.
  • a digital camera or a portable device with a camera function for safe driving such as automatic stop, and recognition of the driver's condition.
  • Devices used for traffic such as in-vehicle sensors that take images of the rear, surroundings, and inside the vehicle, surveillance cameras that monitor running vehicles and roads, ranging sensors that measure the distance between vehicles, etc.
  • Devices used for home appliances such as TVs, refrigerators, and air conditioners in order to take images and operate the devices according to the gestures-Endoscopes, devices that perform blood vessel imaging by receiving infrared light, etc.
  • Security devices such as security surveillance cameras and person authentication cameras
  • Skin measuring devices for skin and scalp Beauty such as microscope
  • Such action camera or wearable cameras provided by equipment and sports applications such as for the use, such as a camera for monitoring a sports state of the apparatus, groves and crops that are provided for use in, is provided for use in agricultural equipment
  • the technology according to the present disclosure can be applied to various products. More specifically, it can be applied to an imaging system such as a digital still camera or a video camera, a mobile terminal device having an imaging function such as a mobile phone, or an electronic device such as a copying machine using the imaging device as an image reading unit. it can.
  • an imaging system such as a digital still camera or a video camera
  • a mobile terminal device having an imaging function such as a mobile phone
  • an electronic device such as a copying machine using the imaging device as an image reading unit.
  • FIG. 30 is a block diagram showing a configuration of an imaging system which is an example of an electronic device.
  • the imaging system 100 includes an imaging optical system 101 including a lens group, an imaging unit 102, a DSP (Digital Signal Processor) circuit 103, a frame memory 104, a display device 105, and a recording device 106.
  • the DSP circuit 103, the frame memory 104, the display device 105, the recording device 106, the operation system 107, and the power supply system 108 are connected to each other via a bus line 109.
  • the imaging optical system 101 captures incident light (image light) from a subject and forms an image on the imaging surface of the imaging unit 102.
  • the image capturing unit 102 converts the light amount of the incident light imaged on the image capturing surface by the optical system 101 into an electric signal for each pixel and outputs the electric signal as a pixel signal.
  • the DSP circuit 103 performs general camera signal processing, such as white balance processing, demosaic processing, and gamma correction processing.
  • the frame memory 104 is used to appropriately store data in the process of signal processing in the DSP circuit 103.
  • the display device 105 includes a panel-type display device such as a liquid crystal display device and an organic EL (electroluminescence) display device, and displays a moving image or a still image captured by the image capturing unit 102.
  • the recording device 106 records the moving image or the still image captured by the image capturing unit 102 on a recording medium such as a portable semiconductor memory, an optical disc, or an HDD (Hard Disk Drive).
  • the operation system 107 issues operation commands for various functions of the imaging system 100 under the operation of the user.
  • the power supply system 108 appropriately supplies various power supplies serving as operating power supplies of the DSP circuit 103, the frame memory 104, the display device 105, the recording device 106, and the operation system 107 to these supply targets.
  • the imaging device according to the above-described embodiment can be used as the imaging unit 102. Then, by using the image pickup device as the image pickup unit 102, addition reading by FD addition can be performed even in a state other than the state of low conversion efficiency.
  • Imaging device ⁇ [A-1] A first addition that has a floating diffusion that converts the charge transferred from the light receiving unit into a voltage, and that electrically connects the floating diffusions between pixels to selectively perform pixel addition for adding pixel signals
  • a second pixel portion The first pixel portion is connected between a first switch transistor whose one source / drain electrode is connected to the floating diffusion and between the other source / drain electrode of the first switch transistor and the power supply node.
  • the second pixel portion has a second switch transistor in which one source / drain electrode is connected to the floating diffusion, and a second switch transistor in which one source / drain electrode is connected to the other source / drain electrode of the second switch transistor.
  • the first pixel section or the second pixel section has a high conversion efficiency of the floating diffusion when the first switch transistor or the second switch transistor is in the non-conducting state in the case of no pixel addition. Achieve conversion efficiency, The imaging device according to the above [A-1].
  • [A-3] Regarding the conversion efficiency of the floating diffusion, the first pixel portion and the second pixel portion, in the case where the pixel addition is not performed, when the first switch transistor and the second switch transistor are both non-conductive.
  • Achieve medium conversion efficiency The imaging device according to the above [A-1].
  • [A-6] The first pixel portion and the second pixel portion perform pixel addition when the first switch transistor, the second switch transistor, and the third switch transistor are all in a conductive state, and Achieving low conversion efficiency with regard to conversion efficiency of floating diffusion, The imaging device according to the above [A-1].
  • [A-7] The capacitive element is divided and arranged in each pixel of the first pixel portion and the second pixel portion, The imaging device according to any one of [A-1] to [A-6].
  • [A-8] The capacitive element is realized by a coupling capacitance between metal wires, The imaging device according to [A-7].
  • the first pixel portion and the second pixel portion each include a plurality of pixels, Share floating diffusion between multiple pixels, The imaging device according to any one of [A-1] to [A-8].
  • the first pixel portion and the second pixel portion perform pixel addition between pixels of the same color, The imaging device according to [A-9].
  • the constituent element of the first pixel portion and the constituent element of the second pixel portion are pixels in which symmetry is ensured with respect to a center line between the first pixel portion and the second pixel portion. Has become a layout, The imaging device according to any one of [A-1] to [A-10].
  • the floating diffusions of the first pixel portion and the second pixel portion have a first pixel portion and a second pixel portion more than the central portions of the first pixel portion and the second pixel portion. It is located near the center line between the The imaging device according to the above [A-11].
  • the first pixel portion and the second pixel portion have a backside illumination pixel structure, The imaging device according to any one of [A-1] to [A-12].
  • a floating diffusion that converts charges transferred from the light receiving unit into a voltage is provided, and pixel addition that selectively adds pixel signals by electrically connecting the floating diffusions between pixels is performed first.
  • a second pixel portion The first pixel portion is connected between a first switch transistor whose one source / drain electrode is connected to the floating diffusion and between the other source / drain electrode of the first switch transistor and the power supply node.
  • Has a reset transistor The second pixel portion has a second switch transistor in which one source / drain electrode is connected to the floating diffusion, and a second switch transistor in which one source / drain electrode is connected to the other source / drain electrode of the second switch transistor.
  • the first pixel section or the second pixel section has a high conversion efficiency of the floating diffusion when the first switch transistor or the second switch transistor is in the non-conducting state in the case of no pixel addition. Achieve conversion efficiency, The electronic device according to the above [B-1].
  • the first pixel portion and the second pixel portion include a first switch transistor, a second switch transistor, and a third switch in the case without pixel addition and in the case without pixel addition.
  • the transistors are both conductive, a low conversion efficiency is realized with respect to the conversion efficiency of the floating diffusion, The electronic device according to the above [B-1].
  • [B-5] The first pixel portion and the second pixel portion perform pixel addition when the first switch transistor and the second switch transistor are both in a conductive state, and perform medium conversion with respect to conversion efficiency of floating diffusion. To achieve efficiency, The electronic device according to the above [B-1].
  • [B-6] The first pixel portion and the second pixel portion perform pixel addition when the first switch transistor, the second switch transistor, and the third switch transistor are all in a conductive state, and Achieving low conversion efficiency with regard to conversion efficiency of floating diffusion, The electronic device according to the above [B-1].
  • [B-7] The capacitive element is divided and arranged in each pixel of the first pixel portion and the second pixel portion, The electronic device according to any one of [B-1] to [B-6].
  • the capacitive element is realized by a coupling capacitance between metal wirings, The electronic device according to [B-7].
  • the first pixel portion and the second pixel portion each include a plurality of pixels, Share floating diffusion between multiple pixels, The electronic device according to any one of [B-1] to [B-8].
  • the first pixel portion and the second pixel portion perform pixel addition between pixels of the same color.
  • the constituent element of the first pixel portion and the constituent element of the second pixel portion are pixels for which symmetry is ensured with respect to the center line between the first pixel portion and the second pixel portion. Has become a layout, The electronic device according to any one of [B-1] to [B-10].
  • the floating diffusions in the first pixel portion and the second pixel portion are more likely to occur in the first pixel portion and the second pixel portion than in the central portions of the first pixel portion and the second pixel portion. It is located near the center line between the The electronic device according to [B-11].
  • the first pixel portion and the second pixel portion have a backside illumination pixel structure, The electronic device according to any one of [B-1] to [B-12].
  • Pixel drive line 32 ( 32 1 to 32 n ) ... Vertical signal line, C 1 , C 2 , C 11 , C 12 , C 21 , C 22 ... Capacitance element, FD (FD 1 , FD 2 ) ... Floating diffusion

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  • Multimedia (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Geophysics And Detection Of Objects (AREA)
  • Measuring Pulse, Heart Rate, Blood Pressure Or Blood Flow (AREA)
  • Measuring Fluid Pressure (AREA)

Abstract

La présente invention comporte des première et seconde parties de pixel pour effectuer une addition FD. La première partie de pixel comprend un premier transistor de commutation ayant une électrode de source/drain connectée à un FD et un transistor de réinitialisation connecté entre un nœud d'alimentation électrique et l'autre électrode de source/drain du premier transistor de commutation. La seconde partie de pixel comprend un deuxième transistor de commutation ayant une électrode de source/drain connectée au FD, un troisième transistor de commutation ayant une électrode de source/drain connectée à l'autre électrode de source/drain du second transistor de commutation, et un élément de capacité connecté entre l'autre électrode de source/drain du troisième transistor de commutation et un nœud de potentiel électrique de référence. En outre, les autres électrodes source/drain respectives du premier transistor de commutation et du deuxième transistor de commutation sont électriquement connectées l'une à l'autre.
PCT/JP2019/036339 2018-11-07 2019-09-17 Dispositif d'imagerie et appareil électronique WO2020095544A1 (fr)

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JP2020556650A JP7362651B2 (ja) 2018-11-07 2019-09-17 撮像装置及び電子機器
US17/281,423 US11405568B2 (en) 2018-11-07 2019-09-17 Imaging apparatus and electronic device
US17/732,925 US20220272287A1 (en) 2018-11-07 2022-04-29 Imaging apparatus and electronic device
JP2023170486A JP2023171452A (ja) 2018-11-07 2023-09-29 光検出装置

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JPWO2020095544A1 (ja) 2021-09-30
US11405568B2 (en) 2022-08-02
JP2023171452A (ja) 2023-12-01
US20220272287A1 (en) 2022-08-25
TW202147827A (zh) 2021-12-16
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TWI822641B (zh) 2023-11-11
TW202335279A (zh) 2023-09-01

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