WO2020093268A1 - 低压差线性稳压电路、电子设备 - Google Patents

低压差线性稳压电路、电子设备 Download PDF

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Publication number
WO2020093268A1
WO2020093268A1 PCT/CN2018/114364 CN2018114364W WO2020093268A1 WO 2020093268 A1 WO2020093268 A1 WO 2020093268A1 CN 2018114364 W CN2018114364 W CN 2018114364W WO 2020093268 A1 WO2020093268 A1 WO 2020093268A1
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voltage
pmos
tube
nmos tube
drain
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PCT/CN2018/114364
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English (en)
French (fr)
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谢宜政
吴嘉训
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北京比特大陆科技有限公司
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Priority to PCT/CN2018/114364 priority Critical patent/WO2020093268A1/zh
Publication of WO2020093268A1 publication Critical patent/WO2020093268A1/zh

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/563—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices including two stages of regulation at least one of which is output level responsive, e.g. coarse and fine regulation

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  • the present application relates to the technical field of power supply for integrated circuits, in particular, to a low-dropout linear voltage regulator circuit and electronic equipment.
  • LDOs Low dropout linear regulators
  • the capacitance-free LDO has less large capacitance in parallel at the output end in the circuit structure, and it is easier to integrate into the SoC system, but accordingly has disadvantages in stability and transient response characteristics.
  • FIG. 1 is a schematic circuit diagram of a capacitance-less low-dropout linear regulator 100 in the prior art.
  • the low-dropout linear regulator includes an error amplifying circuit 110 and an output circuit 120.
  • the error amplifying circuit 110 uses several PMOS transistors MP1-MP4 and NMOS transistors MN1-MN4 to form a cascode amplifier structure, in which The gates of the NMOS transistors MN1 and MN2 constitute an input terminal of the error amplifying circuit 110, respectively receive the feedback voltage of the reference voltage VREF and the output voltage LDO_OUT, and control the power in the output circuit 120 according to the comparison result of the feedback voltage of the reference voltage VREF and the output voltage LDO_OUT The gate voltage VG of the transistor MPS, thereby adjusting the power transistor MPS to stabilize the output voltage LDO_OUT.
  • a capacitor C1 is connected across the output terminal and the gate of the power transistor MPS in the output circuit 120 as a Miller compensation capacitor.
  • the capacitor C1 usually needs to be very large, which will reduce the overall response speed of the circuit; when the output is loaded and the load current increases, the output voltage LDO_OUT will produce a large drop voltage (DROPVoltage) ; If the adjustment is made to make the response speed of the feedback loop faster, it will cause the feedback loop to become unstable and form an oscillation.
  • FIG. 2 is a circuit schematic diagram of a capacitance-less low-dropout linear regulator 200 improved on the basis of FIG. 1.
  • the low-dropout linear regulator adds a parallel integration circuit 230 between the output terminal and the gate of the power transistor MPS.
  • the integration circuit 230 is used to detect the output voltage LDO_OUT After the change, the gate voltage VG of the power transistor MPS is changed, thereby speeding up the loop response, but this additional integration circuit needs to add additional resistance and capacitance area, and it must be configured with a larger bias current to achieve, not Conducive to chip integration, and the stability of the overall circuit will also have problems.
  • Embodiments of the present disclosure provide a low-dropout linear voltage regulator circuit to solve the problems of poor stability, slow response speed, and unfavorable chip integration in the prior art.
  • an embodiment of the present disclosure provides a low-dropout linear voltage regulator circuit, including an error amplifying circuit and an output circuit;
  • the error amplifying circuit includes a first cascode circuit and a second cascode circuit, wherein the first cascode circuit includes a first PMOS transistor and a second PMOS transistor connected by a common gate. The connection between the drain of the first PMOS tube and the source of the second PMOS tube forms a first voltage feedback point; the second cascode circuit includes a first NMOS tube and a second NMOS tube connected by a common gate The connection between the drain of the first NMOS tube and the source of the second NMOS tube constitutes a second voltage feedback point;
  • the output circuit includes a power transistor, a first feedback capacitor, and a second feedback capacitor, wherein the gate of the power transistor is connected to the drains of the second PMOS tube and the second NMOS tube, and the drain of the power transistor
  • the pole provides an output voltage
  • the first feedback capacitor is connected across the first voltage feedback point and the output voltage
  • the second feedback capacitor is connected across the second voltage feedback point and the output voltage between.
  • the power transistor includes a PMOS transistor, the source of which is connected to the power supply voltage, the drain is connected to one end of the resistor, and the other end of the resistor is grounded.
  • the first cascode circuit further includes a third PMOS transistor and a fourth PMOS transistor connected by a common gate
  • the second cascode circuit further includes a third cascode connected An NMOS tube and a fourth NMOS tube, wherein the drain of the third PMOS tube is connected to the source of the fourth PMOS tube, and the drain of the third NMOS tube is connected to the source of the fourth NMOS tube, The drains of the fourth PMOS tube and the fourth NMOS tube are connected.
  • the error amplifying circuit further includes a fifth NMOS tube and a sixth NMOS tube connected in common, the gate of the fifth NMOS tube inputs a reference voltage, and the gate of the sixth NMOS tube Input the output voltage, the sources of the fifth NMOS tube and the sixth NMOS tube are connected to one end of a current source, and the other end of the current source is grounded.
  • the first cascode circuit further includes a fifth PMOS tube and a sixth PMOS tube connected with a common gate, and a drain of the fifth PMOS tube and a source phase of the sixth PMOS tube Connected, the drain of the sixth PMOS tube is short-circuited with the gate, and is connected to the drain of the sixth NMOS tube.
  • the first cascode circuit further includes a seventh PMOS tube and an eighth PMOS tube connected with a common gate, and a drain of the seventh PMOS tube and a source phase of the eighth PMOS tube Connected, the drain of the eighth PMOS tube is short-circuited with the gate, and is connected to the drain of the fifth NMOS tube.
  • the sixth PMOS tube is connected to the common gate of the second PMOS tube
  • the eighth PMOS tube is connected to the common gate of the fourth PMOS tube
  • the fourth NMOS tube is connected to the second NMOS tube Gate connection.
  • the sources of the first PMOS tube, the third PMOS tube, the fifth PMOS tube, and the seventh PMOS tube are connected to a power supply voltage, and the sources of the first NMOS tube and the third NMOS tube are grounded.
  • an embodiment of the present disclosure provides an electronic device, including the low-dropout linear voltage regulator circuit according to any one of the implementation manners in the first aspect.
  • the first and second PMOS transistors connected by the cascode are arranged in the first cascode circuit, and the cascode is arranged in the second cascode circuit
  • the first and second NMOS transistors connected to each other, the connection between the drain of the first PMOS transistor and the source of the second PMOS transistor is used as a first voltage feedback point, and the drain of the first NMOS transistor and the second
  • the connection of the source of the NMOS tube is used as the second voltage feedback point, and the voltage feedback from the output voltage end of the LDO to the first voltage feedback point and the second voltage feedback point is realized by using the first feedback capacitor and the second feedback capacitor respectively .
  • the embodiment of the present disclosure makes the loop of the capacitance-free low-dropout linear regulator more stable through dual-loop Miller compensation, has a faster response speed and a smaller drop voltage, and can obtain higher Bandwidth, and the area of the capacitor used will be smaller, which is conducive to chip integration.
  • FIG. 1 is a circuit schematic diagram of a capacitance-less low-dropout linear regulator 100 in the prior art
  • FIG. 2 is a circuit schematic diagram of a capacitance-less low-dropout linear regulator 200 improved on the basis of FIG. 1;
  • FIG. 3 is a schematic circuit diagram of a capacitance-less low-dropout linear regulator 300 according to an embodiment of the present disclosure
  • FIG. 4 is a schematic comparison diagram of the circuit simulation results of the embodiment of the present disclosure and the prior art.
  • FIG. 3 is a circuit diagram of a capacitance-less low-dropout linear regulator 300 according to an embodiment of the present disclosure. As shown in FIG. 3, the capacitance-less low-dropout linear regulator 300 of the embodiment of the present disclosure includes an error amplifying circuit 310 and an output circuit 320.
  • the error amplifier circuit 310 includes a first cascode circuit 311 and a second cascode circuit 312.
  • the first cascode circuit 311 includes at least PMOS transistors MP4 and MP14 connected to the common gate, the drain of the PMOS transistor MP4 is connected to the source of MP14, and the connection point constitutes a first voltage feedback point VFBP;
  • the second cascode circuit 312 at least includes NMOS transistors MN4 and MN14 connected by a common gate, the drain of the NMOS transistor MN4 is connected to the source of MN14, and the connection point constitutes a second voltage feedback point VFBN.
  • the output circuit 320 includes a power transistor MPS, a feedback capacitor CFBP and a CFBN, wherein the gate of the power transistor MPS is connected to the drains of the PMOS tube MP14 and the NMOS tube MN14, and the drain of the power transistor MPS provides the output voltage LDO_OUT
  • the feedback capacitor CFBP is connected between the first voltage feedback point VFBP and the output voltage LDO_OUT
  • the feedback capacitor CFBN is connected between the second voltage feedback point VFBN and the output voltage LDO_OUT.
  • the feedback loop design of the capacitance-free low-dropout linear regulator in the prior art shown in FIGS. 1 and 2 has poor stability, slow response speed, or requires additional resistance and capacitance area and large The bias current is not conducive to chip integration.
  • the embodiments of the present disclosure improve the structure of the cascode circuit in the error amplifying circuit by configuring the first and second PMOS transistors connected to the common gate in the first cascode circuit,
  • the gate circuit is configured with first and second NMOS transistors connected in common, and the connection between the drain of the first PMOS transistor and the source of the second PMOS transistor is used as a first voltage feedback point, and the The connection between the drain and the source of the second NMOS tube is used as the second voltage feedback point, and the output voltage end of the LDO is realized to the first voltage feedback point and the second voltage by using the first feedback capacitor and the second feedback capacitor, respectively Voltage feedback at the feedback point.
  • the feedback capacitor CFBP will immediately feed a downward voltage to the first voltage feedback point VFBP, forcing the PMOS transistor MP14 to turn off (OFF), and the feedback capacitor CFBN will The second voltage feedback point VFBN feeds a downward voltage, so that the current of the NMOS tube MN14 accelerates to the source direction, resulting in the gate voltage VG of the power transistor MPS connected to the drain of the NMOS tube MN14 can be lowered faster, thereby making The power transistor MPS reacts faster to compensate the current lost by the output voltage LDO_OUT due to pumping.
  • the feedback capacitor CFBP immediately feeds an upward voltage to the first voltage feedback point VFBP, forcing the PMOS tube MP14 to increase the current in the ON direction.
  • the feedback capacitor CFBN will feed an upward voltage to the second voltage feedback point VFBN, making the NMOS tube MN14 tend to turn off (OFF) direction, reducing the current flow to the source direction, resulting in the power transistor connected to the drain of the NMOS tube MN14
  • the gate voltage VG of the MPS can go up faster, so that the power transistor MPS tends to turn off (OFF) faster, allowing the output voltage LDO_OUT to quickly return to the lock voltage.
  • this embodiment uses dual-loop Miller compensation to make the loop of the capacitance-free low-dropout linear regulator more stable, with faster response speed and smaller drop voltage, and can obtain higher Bandwidth, and the area of the capacitor used will be smaller, which is conducive to chip integration.
  • the power transistor MPS in the output circuit 320 may be a PMOS transistor whose source is connected to the power supply voltage, and whose drain is connected to one end of the resistor R1, and the other end of the resistor R1 is grounded.
  • the first cascode circuit 311 further includes PMOS transistors MP1 and MP11 connected with a common gate
  • the second cascode circuit 312 further includes NMOS transistors MN3 and MN13 connected with a common gate.
  • the drain of the PMOS tube MP1 is connected to the source of MP11
  • the drain of the NMOS tube MN3 is connected to the source of MN13
  • the PMOS tube MP11 is connected to the drain of the NMOS tube MN13.
  • the error amplifying circuit further includes NMOS transistors MN1 and MN2 connected in common source, MN1 and MN2 as input pair transistors, wherein the gate of MN1 inputs the reference voltage VREF, and the gate of MN2 inputs the output Voltage LDO_OUT.
  • the sources of MN1 and MN2 are connected to one end of a current source IB, and the other end of the current source is grounded.
  • the first cascode circuit 311 further includes PMOS transistors MP3 and MP13 connected with a common gate, the drain of MP3 is connected to the source of MP13, and the drain of MP13 is shorted to the gate. And connected to the drain of the NMOS tube MN2.
  • the first cascode circuit 311 further includes PMOS transistors MP2 and MP12 connected to a common gate, the drain of MP2 is connected to the source of MP12, and the drain of MP12 is short-circuited to the gate. And connected to the drain of the NMOS tube MN1.
  • the PMOS transistors MP13 and MP14 are connected to the common gate
  • the PMOS transistors MP11 and MP12 are connected to the common gate
  • the NMOS transistors MN13 and MN14 are connected to the common gate.
  • the sources of the PMOS transistors MP1-MP4 are connected to a power supply voltage, and the sources of the NMOS transistors MN3 and MN4 are grounded.
  • FIG. 4 is a schematic comparison diagram of the circuit simulation results of the embodiment of the present disclosure and the prior art.
  • the drop voltages of the low-dropout linear regulators shown in FIGS. 1 and 2 in the prior art are 350 mv and 200 mv, respectively, while the low-dropout linear stability of the embodiments of the present disclosure is stable.
  • the drop voltage of the compressor is less than 80mv, and the response recovery speed is faster.

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Abstract

本公开实施例提供一种低压差线性稳压电路、电子设备，该低压差线性稳压电路包括误差放大电路和输出电路；所述误差放大电路包括第一共源共栅电路、第二共源共栅电路，其中第一共源共栅电路包括第一电压反馈点，第二共源共栅电路包括第二电压反馈点；输出电路包括第一反馈电容和第二反馈电容，第一反馈电容跨接于第一电压反馈点和输出电路的输出电压之间，第二反馈电容跨接于第二电压反馈点和输出电路的输出电压之间。本公开实施例通过双回路的密勒补偿，使得回路更加稳定，具有更快的响应速度和较小的跌落电压，能够获得更高的带宽，并且使用的电容面积会更小，有利于芯片集成。

Description

低压差线性稳压电路、电子设备 技术领域
本申请涉及集成电路的供电技术领域，具体而言，涉及一种低压差线性稳压电路、电子设备。
背景技术
低压差线性稳压器(LDO)作为线性稳压电源的一种，具有体积小、噪声小、较高的电源抑制比以及外围电路简单等优点，普遍应用于集成电路中。同传统的LDO相比，无电容型LDO在电路结构上少了输出端并联的大电容，更容易集成于SoC系统中，但是相应地在稳定性和瞬态响应特性方面存在缺点。
图1是现有技术中一种无电容型低压差线性稳压器100的电路示意图。如图1所示，该低压差线性稳压器包括误差放大电路110和输出电路120，误差放大电路110采用若干个PMOS晶体管MP1-MP4以及NMOS晶体管MN1-MN4组成共源共栅放大器结构，其中NMOS晶体管MN1和MN2的栅极构成误差放大电路110的输入端，分别接收参考电压VREF和输出电压LDO_OUT的反馈电压，根据参考电压VREF和输出电压LDO_OUT的反馈电压的比较结果控制输出电路120中功率晶体管MPS的栅极电压VG，从而调节功率晶体管MPS以稳定输出电压LDO_OUT。该低压差线性稳压器中，输出电路120中功率晶体管MPS的输出端和栅极之间跨接一电容C1，作为密勒补偿电容。为了使得反馈回路稳定，该电容C1通常需要非常大,这样就会降低电路整体的响应速度；当输出抽载，负载电流增大时，会造成输出电压LDO_OUT产生较大的跌落电压(DROP Voltage)；如果调整以使得反馈回路的响应速度加快，则会造成反馈回路不稳定，形成震荡。
图2是在图1基础上改进的一种无电容型低压差线性稳压器200的电路示意图。如图2所示，在图1基础上，该低压差线性稳压器在功率晶体管MPS的输出端和栅极之间增加一并联的积分电路230，该积分电路230用于侦测输出电压LDO_OUT的变化后，改变功率晶体管MPS的栅极电压VG，进而 加速回路响应，但是这种额外增加的积分电路需要增加额外的电阻和电容面积，且要配置较大的偏置电流才能得以实现，不利于芯片集成，并且电路整体的稳定性也会存在问题。
发明内容
本公开实施例提供一种低压差线性稳压电路，以解决现有技术中低压差线性稳压器在稳定性差、响应速度慢、不利于芯片集成的问题。
第一方面，本公开实施例提出一种低压差线性稳压电路，包括误差放大电路和输出电路；
所述误差放大电路包括第一共源共栅电路、第二共源共栅电路，其中，所述第一共源共栅电路包括共栅极连接的第一PMOS管和第二PMOS管，所述第一PMOS管的漏极和第二PMOS管的源极相连接处构成第一电压反馈点；所述第二共源共栅电路包括共栅极连接的第一NMOS管和第二NMOS管，所述第一NMOS管的漏极和第二NMOS管的源极相连接处构成第二电压反馈点；
所述输出电路包括功率晶体管、第一反馈电容和第二反馈电容，其中，所述功率晶体管的栅极连接至所述第二PMOS管和第二NMOS管的漏极，所述功率晶体管的漏极提供输出电压，所述第一反馈电容跨接于所述第一电压反馈点和所述输出电压之间，所述第二反馈电容跨接于所述第二电压反馈点和所述输出电压之间。
在一些实施方式中，所述功率晶体管包括PMOS晶体管，其源极连接电源电压，漏极连接电阻的一端，该电阻的另一端接地。
在一些实施方式中，所述第一共源共栅电路还包括共栅极连接的第三PMOS管和第四PMOS管，所述第二共源共栅电路还包括共栅极连接的第三NMOS管和第四NMOS管，其中，所述第三PMOS管的漏极和第四PMOS管的源极相连接，所述第三NMOS管的漏极和第四NMOS管的源极相连接，所述第四PMOS管和第四NMOS管的漏极相连接。
在一些实施方式中，所述误差放大电路还包括共源极连接的第五NMOS管和第六NMOS管，所述第五NMOS管的栅极输入参考电压，所述第六NMOS管的栅极输入所述输出电压，所述第五NMOS管和第六NMOS管的 源极连接至电流源的一端，该电流源的另一端接地。
在一些实施方式中，所述第一共源共栅电路还包括共栅极连接的第五PMOS管和第六PMOS管，所述第五PMOS管的漏极和第六PMOS管的源极相连接，所述第六PMOS管的漏极与栅极短接，并连接至所述第六NMOS管的漏极。
在一些实施方式中，所述第一共源共栅电路还包括共栅极连接的第七PMOS管和第八PMOS管，所述第七PMOS管的漏极和第八PMOS管的源极相连接，所述第八PMOS管的漏极与栅极短接，并连接至所述第五NMOS管的漏极。
在一些实施方式中，所述第六PMOS管与第二PMOS管共栅极连接，所述第八PMOS管与第四PMOS管共栅极连接，所述第四NMOS管与第二NMOS管共栅极连接。
在一些实施方式中，所述第一PMOS管、第三PMOS管、第五PMOS管、第七PMOS管的源极连接电源电压，所述第一NMOS管、第三NMOS管的源极接地。
第二方面，本公开实施例提出一种电子设备，包括如第一方面任一实施方式所述的低压差线性稳压电路。
本公开实施例通过改进误差放大电路中共源共栅电路的结构，在第一共源共栅电路配置共栅极连接的第一和第二PMOS管，在第二共源共栅电路配置共栅极连接的第一和第二NMOS管，将该第一PMOS管的漏极和第二PMOS管的源极的连接处作为第一电压反馈点，将该第一NMOS管的漏极和第二NMOS管的源极的连接处作为第二电压反馈点，并分别利用第一反馈电容和第二反馈电容实现LDO的输出电压端到所述第一电压反馈点和第二电压反馈点的电压反馈。相比现有技术，本公开实施例通过双回路的密勒补偿，使得无电容型低压差线性稳压器的回路更加稳定，具有更快的响应速度和较小的跌落电压，能够获得更高的带宽，并且使用的电容面积会更小，有利于芯片集成。
附图说明
为了更清楚地说明本公开实施例或现有技术中的技术方案，下面将对实 施例或现有技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本公开的一些实施例，对于本领域普通技术人员来说，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1是现有技术中一种无电容型低压差线性稳压器100的电路示意图；
图2是在图1基础上改进的一种无电容型低压差线性稳压器200的电路示意图；
图3是根据本公开一实施方式的无电容型低压差线性稳压器300的电路示意图；
图4是本公开实施例与现有技术的电路仿真结果的对比示意图。
具体实施方式
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本公开中，应理解，诸如“包括”或“具有”等的术语旨在指示本说明书中所公开的特征、数字、步骤、行为、部件、部分或其组合的存在，并且不欲排除一个或多个其他特征、数字、步骤、行为、部件、部分或其组合存在或被添加的可能性。
图3是根据本公开一实施方式的无电容型低压差线性稳压器300的电路示意图。如图3所示，本公开实施例的无电容型低压差线性稳压器300包括误差放大电路310和输出电路320。
该误差放大电路310包括第一共源共栅电路311、第二共源共栅电路312。其中，该第一共源共栅电路311至少包括共栅极连接的PMOS管MP4和MP14，该PMOS管MP4的漏极和MP14的源极相连接，相连接处构成第一电压反馈点VFBP；该第二共源共栅电路312至少包括共栅极连接的NMOS管MN4和MN14，该NMOS管MN4的漏极和MN14的源极相连接，相连接处构成第二电压反馈点VFBN。
该输出电路320包括功率晶体管MPS、反馈电容CFBP和CFBN，其中， 该功率晶体管MPS的栅极连接至所述PMOS管MP14和NMOS管MN14的漏极，该功率晶体管MPS的漏极提供输出电压LDO_OUT，该反馈电容CFBP跨接于所述第一电压反馈点VFBP和所述输出电压LDO_OUT之间，该反馈电容CFBN跨接于所述第二电压反馈点VFBN和所述输出电压LDO_OUT之间。
之前提及，如图1和图2所示的现有技术中的无电容型低压差线性稳压器的反馈回路设计存在稳定性差、响应速度慢，或者需要额外的电阻和电容面积以及较大的偏置电流，不利于芯片集成。
考虑到上述缺陷，本公开实施例通过改进误差放大电路中共源共栅电路的结构，在第一共源共栅电路配置共栅极连接的第一和第二PMOS管，在第二共源共栅电路配置共栅极连接的第一和第二NMOS管，将该第一PMOS管的漏极和第二PMOS管的源极的连接处作为第一电压反馈点，将该第一NMOS管的漏极和第二NMOS管的源极的连接处作为第二电压反馈点，并分别利用第一反馈电容和第二反馈电容实现LDO的输出电压端到所述第一电压反馈点和第二电压反馈点的电压反馈。
这种具有双回路的反馈回路的工作原理说明如下：
一方面，当输出电压LDO_OUT被抽取电流时，反馈电容CFBP会马上向所述第一电压反馈点VFBP反馈向下电压，迫使PMOS管MP14趋向关断(OFF)方向，同时反馈电容CFBN则会向第二电压反馈点VFBN反馈向下电压，使得NMOS管MN14的电流加速向源极方向流动，导致连接至NMOS管MN14的漏极的功率晶体管MPS的栅极电压VG能够更快向下，从而使得功率晶体管MPS更快反应补偿输出电压LDO_OUT因为抽载失去的电流。
另一方面，当输出电压LDO_OUT不再被抽取电流而产生电压上升时，反馈电容CFBP会马上向所述第一电压反馈点VFBP反馈向上电压，迫使PMOS管MP14趋向导通(ON)方向增加电流，同时反馈电容CFBN则会向第二电压反馈点VFBN反馈向上电压，使得NMOS管MN14趋向关断(OFF)方向，降低电流向源极方向流动，导致连接至NMOS管MN14的漏极的功率晶体管MPS的栅极电压VG能够更快向上，从而使得功率晶体管MPS更快趋向关断(OFF)方向，让输出电压LDO_OUT快速向下恢复至锁定电压。
本实施方式相比现有技术，通过双回路的密勒补偿，使得无电容型低压 差线性稳压器的回路更加稳定，具有更快的响应速度和较小的跌落电压，能够获得更高的带宽，并且使用的电容面积会更小，有利于芯片集成。
在一些实施方式中，输出电路320中的功率晶体管MPS可以是PMOS晶体管，其源极连接电源电压，漏极连接电阻R1的一端，该电阻R1的另一端接地。
在一些实施方式中，该第一共源共栅电路311还包括共栅极连接的PMOS管MP1和MP11，该第二共源共栅电路312还包括共栅极连接的NMOS管MN3和MN13，其中，该PMOS管MP1的漏极和MP11的源极相连接，该NMOS管MN3的漏极和MN13的源极相连接，该PMOS管MP11和该NMOS管MN13的漏极相连接。
在一些实施方式中，该误差放大电路还包括共源极连接的NMOS管MN1和MN2，MN1和MN2作为输入对管，其中，MN1的栅极输入参考电压VREF，MN2的栅极输入所述输出电压LDO_OUT。MN1和MN2的源极连接至电流源IB的一端，该电流源的另一端接地。
在一些实施方式中，该第一共源共栅电路311还包括共栅极连接的PMOS管MP3和MP13，MP3的漏极和MP13的源极相连接，MP13的漏极与栅极短接，并连接至NMOS管MN2的漏极。
在一些实施方式中，该第一共源共栅电路311还包括共栅极连接的PMOS管MP2和MP12，MP2的漏极和MP12的源极相连接，MP12的漏极与栅极短接，并连接至NMOS管MN1的漏极。
在一些实施方式中，该PMOS管MP13与MP14共栅极连接，该PMOS管MP11与MP12共栅极连接，该NMOS管MN13与MN14共栅极连接。
在一些实施方式中，该PMOS管MP1-MP4的源极连接电源电压，该NMOS管MN3和MN4的源极接地。
图4是本公开实施例与现有技术的电路仿真结果的对比示意图。如图4所示，在同样的抽载电流下，现有技术中图1和图2所示低压差线性稳压器的跌落电压分别为350mv和200mv，而本公开实施例的低压差线性稳压器的跌落电压小于80mv，并且响应回复速度更快。
最后应说明的是：以上各实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述各实施例对本公开进行了详细的说明，本领域的普通 技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (9)

  1. 一种低压差线性稳压电路，其特征在于，包括误差放大电路和输出电路；
    所述误差放大电路包括第一共源共栅电路、第二共源共栅电路，其中，所述第一共源共栅电路包括共栅极连接的第一PMOS管和第二PMOS管，所述第一PMOS管的漏极和第二PMOS管的源极相连接处构成第一电压反馈点；所述第二共源共栅电路包括共栅极连接的第一NMOS管和第二NMOS管，所述第一NMOS管的漏极和第二NMOS管的源极相连接处构成第二电压反馈点；
    所述输出电路包括功率晶体管、第一反馈电容和第二反馈电容，其中，所述功率晶体管的栅极连接至所述第二PMOS管和第二NMOS管的漏极，所述功率晶体管的漏极提供输出电压，所述第一反馈电容跨接于所述第一电压反馈点和所述输出电压之间，所述第二反馈电容跨接于所述第二电压反馈点和所述输出电压之间。
  2. 根据权利要求1所述的低压差线性稳压电路，其特征在于，所述功率晶体管包括PMOS晶体管，其源极连接电源电压，漏极连接电阻的一端，该电阻的另一端接地。
  3. 根据权利要求2所述的低压差线性稳压电路，其特征在于，所述第一共源共栅电路还包括共栅极连接的第三PMOS管和第四PMOS管，所述第二共源共栅电路还包括共栅极连接的第三NMOS管和第四NMOS管，其中，所述第三PMOS管的漏极和第四PMOS管的源极相连接，所述第三NMOS管的漏极和第四NMOS管的源极相连接，所述第四PMOS管和第四NMOS管的漏极相连接。
  4. 根据权利要求3所述的低压差线性稳压电路，其特征在于，所述误差放大电路还包括共源极连接的第五NMOS管和第六NMOS管，所述第五NMOS管的栅极输入参考电压，所述第六NMOS管的栅极输入所述输出电压，所述第五NMOS管和第六NMOS管的源极连接至电流源的一端，该电流源的另一端接地。
  5. 根据权利要求4所述的低压差线性稳压电路，其特征在于，所述第一共源共栅电路还包括共栅极连接的第五PMOS管和第六PMOS管，所述第五 PMOS管的漏极和第六PMOS管的源极相连接，所述第六PMOS管的漏极与栅极短接，并连接至所述第六NMOS管的漏极。
  6. 根据权利要求5所述的低压差线性稳压电路，其特征在于，所述第一共源共栅电路还包括共栅极连接的第七PMOS管和第八PMOS管，所述第七PMOS管的漏极和第八PMOS管的源极相连接，所述第八PMOS管的漏极与栅极短接，并连接至所述第五NMOS管的漏极。
  7. 根据权利要求6所述的低压差线性稳压电路，其特征在于，所述第六PMOS管与第二PMOS管共栅极连接，所述第八PMOS管与第四PMOS管共栅极连接，所述第四NMOS管与第二NMOS管共栅极连接。
  8. 根据权利要求7所述的低压差线性稳压电路，其特征在于，所述第一PMOS管、第三PMOS管、第五PMOS管、第七PMOS管的源极连接电源电压，所述第一NMOS管、第三NMOS管的源极接地。
  9. 一种电子设备，其特征在于，包括如权利要求1-8任一项所述的低压差线性稳压电路。
PCT/CN2018/114364 2018-11-07 2018-11-07 低压差线性稳压电路、电子设备 WO2020093268A1 (zh)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102279612A (zh) * 2011-05-11 2011-12-14 电子科技大学 一种低压差线性稳压器
JP2014090306A (ja) * 2012-10-30 2014-05-15 Asahi Kasei Electronics Co Ltd 演算増幅器
CN106708151A (zh) * 2016-12-26 2017-05-24 上海迦美信芯通讯技术有限公司 一种低功耗低压差线性稳压器系统

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102279612A (zh) * 2011-05-11 2011-12-14 电子科技大学 一种低压差线性稳压器
JP2014090306A (ja) * 2012-10-30 2014-05-15 Asahi Kasei Electronics Co Ltd 演算増幅器
CN106708151A (zh) * 2016-12-26 2017-05-24 上海迦美信芯通讯技术有限公司 一种低功耗低压差线性稳压器系统

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