WO2020088005A1 - 一种基于忆阻器阵列潜流路径的内嵌快速加法器装置及计算方法 - Google Patents

一种基于忆阻器阵列潜流路径的内嵌快速加法器装置及计算方法 Download PDF

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WO2020088005A1
WO2020088005A1 PCT/CN2019/097848 CN2019097848W WO2020088005A1 WO 2020088005 A1 WO2020088005 A1 WO 2020088005A1 CN 2019097848 W CN2019097848 W CN 2019097848W WO 2020088005 A1 WO2020088005 A1 WO 2020088005A1
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carry
memristor
mapping
calculation
adder
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景乃锋
李桃中
李彤
王琴
蒋剑飞
贺光辉
毛志刚
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Shanghai Jiao Tong University
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/5052—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination using carry completion detection, either over all stages or at sample stages only

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  • the invention belongs to the field of nonvolatile memory based on new materials and relates to memory calculation technology.
  • Boolean logic The method based on Boolean logic is the simplest and most intuitive, that is, it is spliced by the basic logic organization supported by the circuit according to the logic expression of addition.
  • Typical implementations include IMPLY circuits and MAGIC circuits.
  • the disadvantage of this calculation method is also obvious, that is, the calculation efficiency is low.
  • For the 1-bit full adder using IMPLY circuit and MAGIC circuit to achieve 29 and 12 steps, respectively, contemporary computing systems are usually 32-bit wide. Without considering the carry movement, only the calculation part requires 928 and 384 steps, considering the write speed of memristors is usually slow, such a large computational overhead is unacceptable.
  • look-up table (LUT) is to imitate the design idea of FPGA, use the programmable characteristic of memristor, calculate the result of a certain specific logic function by means of IMPLY or MAGIC in advance, and store it in the memristor array. Because these pre-calculations are done offline, this method has a high computational efficiency, and one calculation is equivalent to only one read operation. For example, if the lookup table stores a 1-bit full adder, 32 steps are required to complete the 32-bit adder calculation, and if a 2-bit adder result is stored, only 16 steps are required to complete the 32-bit calculation.
  • this method is not a real memory calculation, they are just using the memristor storage array as a programmable arithmetic unit, and once the storage array is configured as this type of arithmetic unit, there is no way to use it as data
  • the memory stores the operands and operation results. And this way and it consumes hardware resources, only the lookup table of the 1-bit full adder needs to occupy 8 ⁇ 14 array space, and as the bit width increases, the consumed array area increases nonlinearly.
  • the method based on the programmable logic array is based on the characteristics that any digital logic can be expressed as a product-of-sum or a sum-of-product form, and is customized using a memristor array
  • the minimum item (maximum item) plane In this plane, the structure of the minimum item (maximum item) is fixed.
  • different digital logics can be implemented by activating different rows or columns to achieve The purpose of programming.
  • the shortcomings of this implementation are consistent with the lookup table-based approach, that is, it is not really a memory calculation, and consumes a lot of hardware resources of the memristor array.
  • Memristor memory is used as an alternative to memory calculation to solve the memory wall problem.
  • the present invention proposes an implementation scheme of an adder to improve the efficiency of memory calculation of the memristive memory.
  • Figure 1 shows the principle diagram of carrying calculation based on memristor. Note that the memristor represents the logic value through the resistance value, the low resistance state (LRS) represents logic 1, and the high resistance state (HRS) represents logic. 0.
  • Figure 1 (b) shows a schematic diagram of 4-bit carry calculation based on memristor, where the calculation of the carry of each bit is based on the above three cases. Since the states of R_G, R_D, and R_P can be obtained in advance by means of logical calculation, the circuit can quickly complete the carry calculation according to the submerged flow path of the corresponding bit.
  • the logic calculation here can be implemented using existing memristor operation technology, such as IMPLY or MAGIC.
  • R_P forms a carry chain of carry propagation through series connection.
  • the series connection method is not perfectly compatible with the array structure, so it is necessary to customize the carry propagation path on the basis of the array structure.
  • the adder implementation based on memristive array is mainly reflected in the following three points:
  • Carry underflow path mapping pre-calculate the status of R_G, R_D and R_P, used to determine the way of carrying calculations for different bits;
  • This patent mainly proposes an adder design based on a memristor storage array.
  • the design is tested using HSPICE, a new non-volatile memory simulation tool NVSim, which reflects the technical effects of this patent from three aspects: computing performance, area overhead and power consumption overhead. :
  • Area overhead The area overhead is evaluated from two aspects. On the one hand, the number of array elements that need to be occupied by the intermediate data generated during the addition calculation. This part of the unit needs to be reserved for buffering intermediate data during the addition operation and cannot be used for other The storage of data, that is, the greater the proportion of this part of the unit, the lower the utilization rate of the array, and the greater the overhead of the addition operation. Also taking the 32-bit adder as an example, IMPLY and MAGIC require an additional 2 and 352 units, respectively, and this design requires an additional 64 units. For IMPLY design, the array overhead is increased by 31 times, and for MAGIC design, the array overhead is reduced. 4.5 times; on the other hand is the overhead of the carry chain and the control circuit relative to the traditional memristive memory, this part of the overhead is about 12.4%;
  • Power consumption overhead The additional power consumption overhead is also caused by the control circuit and the introduced carry chain. Compared with the power consumption of the peripheral circuit during the storage operation, the power consumption overhead of these two parts accounts for about 19.5%.
  • FIG. 1 is a schematic diagram of a system framework according to an embodiment of the present invention (a) 1-bit (b) 4-bit;
  • FIG. 2 is a schematic diagram of a carry potential path mapping according to an embodiment of the present invention (a) voltage division read operation (b) current sensing read operation;
  • FIG. 3 is a schematic diagram of a carry chain of a carry propagation path according to an embodiment of the present invention (a) based on ReRAM (b) based on CMOS.
  • the addition implementation based on the memristor storage array mainly includes three points: carry-underflow path mapping, construct serial carry chain and sum calculation. The embodiment is specifically explained below.
  • Figure 1 shows the principle diagram of adding operation based on memristor.
  • the main work completed by carrying underflow path mapping is to map the schematic to the real array structure. Since R_G of different bits are independent of each other, they can be mapped to the same row of the array and the mapping calculation is performed at the same time.
  • R_D the mapping method is the same as R_G, and it can be mapped to another row of the array.
  • R_D mapping is not necessary because the voltage-divided read operations usually need to be
  • the load resistance is connected to the bottom of the array to sense the resistance state of the selected cell during the reading process.
  • the load resistance plays the same role as R_D, so the mapping step of R_D can be omitted, further reducing the Calculate delay and mapping overhead.
  • R_P cannot be directly mapped into the array structure, and a serial carry chain needs to be constructed to realize the function of R_P.
  • carry out the calculation by applying the operation voltage to the row where R_G is located.
  • the array uses a voltage-divided read operation, just turn off the rest of the array; if the array uses other types of read operations, such as current sensing, you need to ground the row where R_D is located and turn off the rest of the array.
  • Figure 2 shows the schematic diagrams of these two different mapping methods respectively.
  • the low resistance state of the memristor should also reach the order of kilo-ohms, so even if the memorization on the carry path
  • the resistors are in a low-impedance state, and the current may still be gradually weakened in the propagation process due to the excessive resistance of the path, and the calculation of the subsequent carry cannot be completed.
  • the present invention uses a traditional MOS tube to complete the construction of the carry chain, as shown in FIG. 3b.
  • the present invention will use the line buffer to temporarily store the control signal of the carry propagation path And use this signal to directly control the turning on and off of the transistors in the carry chain.
  • the present invention does not directly connect the transistor to the adjacent bit line, but connects its lower bit end to the corresponding sensitive amplifier output, using the strong power of the sensitive amplifier
  • the driving ability drives the spread of carry. In this way, no matter how long the carry chain is, the carry propagation will not be affected by the lack of driving force, because the carry propagation of any bit is directly driven by the sensitive amplifier of the previous bit, so that the process of carry propagation is independent
  • the length of the carry chain The serial carry chain constructed in this way can quickly obtain the carry of each bit after the carry calculation is activated.

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Abstract

本发明是一种基于忆阻阵列潜流路径的加法器装置，相比于现阶段通过逻辑迭代进行加法计算的忆阻器加法器而言，本发明的特点在于：1分离加法运算的串并行部分，即串行进位和并行求和；2针对串行进位，构造相应的潜流路径并定制化其中的进位传播潜流路径，利用电流传播模拟进位行为，从而极大加快进位计算；3得到各比特位的进位后，利用现阶段忆阻器逻辑计算方式及交叉阵列并行结构特点同时完成所有比特位的求和计算。

Description

一种基于忆阻器阵列潜流路径的内嵌快速加法器装置及计算方法 技术领域
本发明属于基于新型材料的非易失存储器领域，涉及内存计算技术。
背景技术
现阶段针对基于忆阻器存储阵列进行加法计算的方法主要有三种。分别是基于布尔逻辑的方式，基于查找表的方式(LUT)以及基于可编程逻辑阵列的方式(PLA)。
基于布尔逻辑的方式最为简单直观，即根据加法的逻辑表达式通过电路支持的基本逻辑组织拼接而成，典型的实现包括IMPLY电路，MAGIC电路等。然而这种运算方式的缺点也很明显，即计算效率低下。对于1-bit全加器而言，利用IMPLY电路和MAGIC电路实现分别需要29和12步操作，当代计算系统通常为32位宽，在不考虑进位搬移的前提下，仅计算部分就需要928和384步，考虑到忆阻器的写速度通常较慢，如此大的计算开销是难以接受的。
基于查找表(LUT)的方式是仿照FPGA的设计思想，利用忆阻器可编程特性，提前通过IMPLY或MAGIC等手段计算得到某种特定逻辑功能的结果并存入忆阻阵列中。由于这些预计算都是在线下完成的，因此这种方法的运算效率较高，一次计算仅相当于一次读操作。例如，若查找表存储的是1-bit全加器，则完成32-bit加法计算需要32步，若存储的是2-bit加法器结果，则仅需要16步完成32-bit计算。然而这种方式并不是真正意义上的内存计算，它们仅仅是将忆阻器存储阵列作为一种可编程的运算单元，并且一旦存储阵列被配置成这种类型的运算单元，就没办法作为数据存储器去存储操作数和运算结果。并且这种方式及其耗费硬件资源，仅1-bit全加器的查找表就需要占据8×14的阵列空间，且随着位宽增加，消耗的阵列面积呈非线性增长。
基于可编程逻辑阵列(PLA)的方式是根据任意数字逻辑均可表示为和之积(product-of-sum)或积之和(sum-of-product)形式的特点，利用忆阻器阵列定制最小项(最大项)平面，在这个平面中，最小项(最大项)的构造是固定的，然 而在形成这些基本项后，可以通过激活不同行或列来实现不同的数字逻辑，从而达到可编程的目的。这种实现方式的缺点和基于查找表的方式是一致的，即并非真正意义上的内存计算，并且相当耗费忆阻器阵列的硬件资源。
发明内容
忆阻存储器作为内存计算的备选方案，用于解决存储器墙问题。本发明针对忆阻存储阵列的结构，提出一种加法器的实现方案，以提高忆阻存储器内存计算的效率。
1-bit全加器的逻辑表达式可表示为以下两式：
Figure PCTCN2019097848-appb-000001
C_o＝AB+AC_i+BC_i
对于多比特加法器，如果按照逻辑迭代的方式一步一步进行计算，则运算效率低下，从而丧失了内存计算技术由于降低数据搬移开销带来的优势。但如果可以以一种高效的方式得到所有位的进位，则可以利用阵列结构并行的特点一次性求得所有位的和。依据这种思想，图1给出了基于忆阻器实现进位计算的原理图，注意忆阻器通过阻值表示逻辑值，低阻态(LRS)表示逻辑1，高阻态(HRS)表示逻辑0。其中图1(a)显示了进位产生的三条潜流路径：1)进位产生路径，R_G＝A·B，意味着当两个加数都为1时，该路径为低阻态，电源通过该路径对电容充电并最终形成进位；2)进位取消路径，R_D＝A -·B -，意味着当两个加数都为0时，该路径为低阻态，电容通过该路径放电并最终不形成进位；3)进位传播路径，
Figure PCTCN2019097848-appb-000002
意味着当两个加数互斥时，该路径为低阻态，上一位的进位通过该路径传播给当前位。图1(b)显示了基于忆阻器4-bit进位计算的示意图，其中每一位的进位的计算都出于上述三种情况。由于R_G，R_D和R_P的状态可以通过逻辑计算的方式预先得到，因此电路可以根据相应位的潜流路径快速完成进位计算。此处的逻辑计算可以采用现有的忆阻器运算技术实现，如IMPLY或MAGIC实现。然而不同于R_G和R_D并联结构，R_P是通过串联方式形成了进位传播的进位链，串联方式与阵列结构无法完美兼容，因此需要在阵列结构的基础上定制进位传播路径。不难看出当进位从最低位沿着R_P的进位链传播到最高位时，整个进位计算的延时是最长的。虽然电路依然受制于进位串行传播的本质，然而相较于逻辑迭代的方式，进位计算的速度得到极大幅度的提升，原因在于本发明利用的是模拟电流传播并充电的方式完成进位的 传播过程，而逻辑迭代的方式则按照时钟周期并根据逻辑表达式一步一步计算得到每一位的进位，并且每一步的进位计算都需要写操作，而写操作对于忆阻器件而言普遍较慢，因此这种进位计算的方式速度很慢。在得到所有位的进位后，根据求和逻辑表达式计算出最终的结果，在这一步计算中，位与位之间是相互独立的，因此不同位的求和运算可以在阵列结构下并行进行。
综上，基于忆阻阵列的加法器实现主要体现在以下三点：
进位潜流路径映射：预先计算R_G，R_D和R_P的状态，用于确定不同位的进位计算途径；
构造串行进位链：由于阵列结构无法形成进位传播路径，因此需要定制一条由R_P控制的进位传播路径，以应对上述介绍的进位计算的第三种情况；
求和计算：各比特位进位计算完成后，通过相应的逻辑实现并行完成所有位的求和计算。
本专利主要提出一种基于忆阻器存储阵列的加法器设计，利用HSPICE，新型非易失存储器仿真工具NVSim对本设计进行测试，从计算性能，面积开销和功耗开销三方面体现本专利技术效果：
计算性能：虽然进位传播的延时依然与操作数位宽有关，但由于本发明是通过模拟的方式，利用电流在构造好的路径上流动传播以形成进位，从而使进位计算所消耗的时钟周期与操作数位宽呈亚线性关系。例如对于32-bit加法器，IMPLY和MAGIC的实现方式分别需要928和384个时钟周期，但采用本发明仅需要消耗13个时钟周期，计算性能相应提高了约70和28倍；
面积开销：面积开销从两个方面进行评定，一方面是加法计算过程中产生的中间数据需要额外占据的阵列单元数目，这部分单元在加法操作中需要预留出来缓存中间数据而无法用于其它数据的存储，即这部分单元占据的比例越大，阵列的利用率就越低，加法操作的开销就越大。同样以32-bit加法器为例，IMPLY和MAGIC分别额外需要2和352个单元，而本设计额外需要64个单元，对于IMPLY设计，阵列开销增大了31倍，对于MAGIC设计，阵列开销降低了4.5倍；另一方面是进位链以及控制电路相对于传统忆阻存储器的开销，这部分开销大约为12.4％；
功耗开销：额外的功耗开销同样由控制电路和引入的进位链导致，相对于存储操作时外围电路的功耗，这两部分的功耗开销约占19.5％。
附图说明
通过阅读参照以下附图对非限制性实施例所作的详细描述，本发明的其它特征、目的和优点将会变得更明显：
图1为本发明实施例的系统框架示意图(a)1-bit(b)4-bit；
图2为本发明实施例的进位潜流路径映射示意图(a)分压式读操作(b)电流感应式读操作；
图3为本发明实施例的进位传播潜流路径进位链示意图(a)基于ReRAM(b)基于CMOS。
具体实施方式
基于忆阻器存储阵列的加法实现主要包括三点：进位潜流路径映射，构造串行进位链和求和计算。以下具体阐述实施方案。
进位潜流路径映射：图1给出了基于忆阻器实现加法操作的原理图，进位潜流路径映射完成的主要工作就是将该原理图映射到真正的阵列结构中。由于不同比特位的R_G是相互独立的，因此它们可以被映射至阵列的同一行并且同时进行映射计算。对于R_D而言，其映射方式与R_G相同，将其映射至阵列的另一行即可，然而对于采用分压式读操作的存储阵列，无需进行R_D映射，原因在于分压式读操作通常需要在阵列底部连接负载电阻，用以在读过程中感应区分选中单元的阻值状态，而在进位计算中，该负载电阻起到了与R_D同样的作用，因此可以省去R_D的映射步骤，进一步减小了计算延迟及映射开销。R_P无法直接映射到阵列结构中，需要构造串行进位链实现R_P的功能。当映射工作全部完成后，通过对R_G所在行施加运算电压以激活进位计算。此外，如果阵列采用的是分压式读操作，则关闭阵列其余行即可；如果阵列采用的是其它类型的读操作，如电流感应式，则需要将R_D所在行接地并关闭阵列其余行。图2分别给出了这两种不同映射方式的示意图。
构造串行进位链：构造串行进位链的目的是为无法直接映射到阵列结构中的R_P定制一条电流传输路径，从而实现进位的串行传播。然而在电路实现中发现，如果直接采用忆阻器构造进位传播路径(图3a)，则存在两个问题，一是无法并行的对串行连接的忆阻器进行编程，这导致映射过程与操作数位宽相关，极大降低了加法器运算效率；二是进位计算过程中电流驱动力不足，一般来说，忆阻器的低阻状态也要达到千欧量级，因此即使进位路径上的忆阻器都处于低阻态，电流可能还是会由于路径阻值过大而在传播过程中逐渐减弱而无法完成对后续位进位的计算。为解决这两个问题，本发明使用传 统MOS管完成进位链的搭建，如图3b所示。首先为解决串行映射的问题，本发明将利用行缓存临时存储进位传播路径的控制信号
Figure PCTCN2019097848-appb-000003
并用此信号直接控制进位链上晶体管的开启与关断，由于这些控制信号是由每条位线独立的计算出来，因此整个计算过程可以并行进行，此外还省去了写入忆阻器的时间；其次为解决进位传播过程中电流驱动力不足的问题，本发明并未将晶体管直接连接于相邻位线上，而将其低位比特端连接到对应的敏感放大器输出上，利用敏感放大器的强驱动能力驱使进位的传播。采用这种方式后，无论进位链多长，进位传播都不会受驱动力不足的影响，因为任意比特位的进位传播都由上一比特位的敏感放大器直接驱动，从而使进位传播的过程独立于进位链的长度。以这种方式构造的串行进位链，可以在进位计算激活后快速得到各个比特位的进位。
求和计算：在进位计算完成后可以得到所有位对应的进位值，此时所有比特位的求和计算都是独立的，因此可以根据其逻辑表达式并行执行完成最终运算。
在上述介绍的基于忆阻阵列实现的加法器方案中，所有涉及逻辑计算的步骤，本发明都采用现有基于忆阻器逻辑运算的技术，如IMPLY，MAGIC等。这说明本加法器设计是独立于具体的逻辑运算技术的，只要该逻辑运算可以在阵列结构下执行并且能实现本发明所要求的一些特定的逻辑功能，就可以利用不同的逻辑运算方式完成进位路径的映射以及最终的求和运算。

Claims (8)

  1. 一种基于忆阻器存储阵列的加法器设计，其特征是，包括：
    进位路径映射；
    串行进位链的构造；
    求和计算。
  2. 根据权利要求1所述的基于忆阻器存储阵列的加法器设计，其特征是，进位路径映射，包括：
    针对R_G映射，在忆阻器存储阵列上完成并行映射；
    针对R_D映射，在忆阻器存储阵列上完成并行映射。
  3. 根据权利要求1所述的基于忆阻器存储阵列的加法器设计，其特征是，串行进位链的构造，包括：
    由MOS管构成进位传播路径；
    利用阵列行缓存并行计算并存储进位链控制信号；
    借助敏感放大器提高电流驱动力。
  4. 根据权利要求1所述的基于忆阻器存储阵列的加法器设计，其特征是，求和计算，包括：
    利用进位计算的结果并行完成所有比特位的求和运算。
  5. 根据权利要求2所述的基于忆阻器存储阵列的加法器设计，其特征是，针对R_G映射，在忆阻器存储阵列上完成并行映射，包括：
    启动进位计算时，在R_G所在行施加运算电压。
  6. 根据权利要求2所述的基于忆阻器存储阵列的加法器设计，其特征是，针对R_D映射，在忆阻器存储阵列上完成并行映射，包括：
    针对分压式读操作，无需进行R_D映射；
    针对其它方式读操作，启动进位计算时，将R_D所在行接地。
  7. 根据权利要求3所述的基于忆阻器存储阵列的加法器设计，其特征是，利用阵列行缓存并行计算并存储进位链控制信号，包括：
    利用行缓存临时存储进位传播路径的控制信号R_P＝A⊕B，并用此信号直接控制进位链上晶体管的开启与关断。
  8. 根据权利要求3所述的基于忆阻器存储阵列的加法器设计，其特征是，借助敏感 放大器提高电流驱动力，包括：
    将晶体管靠近低比特位的一端接于敏感放大器的输出上，高比特位一端接于下一比特位对应的位线上。
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