WO2020080621A1 - Structure de film, élément et élément à plusieurs niveaux - Google Patents

Structure de film, élément et élément à plusieurs niveaux Download PDF

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Publication number
WO2020080621A1
WO2020080621A1 PCT/KR2019/003242 KR2019003242W WO2020080621A1 WO 2020080621 A1 WO2020080621 A1 WO 2020080621A1 KR 2019003242 W KR2019003242 W KR 2019003242W WO 2020080621 A1 WO2020080621 A1 WO 2020080621A1
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Prior art keywords
active
monolayer
active monolayer
gate voltage
layer
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PCT/KR2019/003242
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English (en)
Korean (ko)
Inventor
성명모
김홍범
정진원
박진선
Original Assignee
한양대학교 산학협력단
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Priority claimed from KR1020190021029A external-priority patent/KR102250011B1/ko
Application filed by 한양대학교 산학협력단 filed Critical 한양대학교 산학협력단
Priority to EP19873247.1A priority Critical patent/EP3869567A4/fr
Priority to JP2021521212A priority patent/JP7207784B2/ja
Priority to US17/285,633 priority patent/US11985835B2/en
Publication of WO2020080621A1 publication Critical patent/WO2020080621A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/737—Hetero-junction transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present invention relates to film structures and devices, and more particularly, to film structures, devices and multilevel devices comprising a quantized active monolayer.
  • the present inventors try to solve the problems of the prior art through creative film structures, devices, and multilevel devices that can be applied to future-oriented devices.
  • One technical problem to be solved by the present invention is to provide a film structure and a device in which current flow is limited.
  • Another technical problem to be solved by the present invention is to provide a film structure and a device including a quantized active monolayer.
  • Another technical problem to be solved by the present invention is to provide a film structure and a device including an active monolayer quantized in 1-axis or 3-axis.
  • Another technical problem to be solved by the present invention is to provide a film structure and a device having a superlattice structure.
  • Another technical problem to be solved by the present invention is to provide a film structure and a device having a quantum well structure.
  • Another technical problem to be solved by the present invention is to provide a film structure and a device in which the current / gate voltage is below a predetermined slope above a threshold voltage.
  • Another technical problem to be solved by the present invention is to provide a film structure and a device that is easy to manufacture.
  • Another technical problem to be solved by the present invention is to provide a multi-level device.
  • Another technical problem to be solved by the present invention is to provide a multi-level device with a simple manufacturing process.
  • One technical problem to be solved by the present invention is to provide an ultra-thin multi-level device.
  • the technical problem to be solved by the present invention is not limited to the above.
  • the membrane structure according to an embodiment of the present invention includes at least one active monolayer having an energy level quantized in at least one axial direction and at least one layer alternately stacked with the active monolayer of the at least one layer. Although a barrier is included, current flows through the active monolayer, and current flow may be limited by the quantized energy level.
  • the active monolayer and the barrier may have a hybrid superlattice structure.
  • the active monolayer may have a two-dimensional layered structure.
  • the lamination of the monolayer and the barrier may provide a quantum well structure.
  • the active monolayer when the active monolayer is made of a metal single atom or a transition metal dichalcogenide (TMDC), the active monolayer may have an energy level quantized in a short axis direction.
  • TMDC transition metal dichalcogenide
  • the active monolayer when the active monolayer is made of a metal oxide, the active monolayer may have an energy level quantized in a 3-axis direction.
  • the flow of current may be limited by the quantized energy level.
  • the membrane structure according to an embodiment of the present invention includes at least one active monolayer having a two-dimensional layered structure; And at least one barrier layer alternately stacked with the active monolayer of the at least one layer, wherein the active monolayer and the barrier may have a hybrid superlattice structure.
  • the film structure according to an embodiment of the present invention includes an active monolayer of at least one layer of a quantum well structure, wherein the active monolayer has an energy level quantized in at least one axial direction, and the quantization is performed.
  • the flow of current flowing through the active monolayer may be limited by the energy level.
  • a device includes a gate electrode; A gate insulating film on one side of the gate electrode; At least one active monolayer provided on one side of the gate insulating layer; A barrier of at least one layer alternately stacked with the at least one layer of active monolayer; And a source electrode and a drain electrode through which current flows through the active monolayer when a gate voltage is applied to the gate electrode.
  • the active monolayer may have a quantized energy level in at least one axial direction.
  • the quantized energy level may limit the amount of current flowing through the active monolayer when the gate voltage is greater than or equal to a turn on voltage.
  • a current change between the source and drain electrodes with respect to the voltage applied to the gate electrode may be equal to or less than a predetermined slope.
  • the active monolayer when the active monolayer includes at least one of a metal single atom and TMDC, the active monolayer may have an energy level quantized in a short axis direction.
  • the active monolayer may have an energy level quantized in a 3-axis direction.
  • the active monolayer may include a plurality of crystalline regions and an amorphous region surrounding the crystalline regions.
  • the active monolayer may have an energy level quantized in a 3-axis direction.
  • the barrier may be stacked between the active monolayer and the source and drain electrodes.
  • the active monolayer may have a structure sandwiched between the barriers.
  • the active monolayer has a predetermined thickness, and the predetermined thickness may be nano-sized.
  • a device includes a gate electrode, a gate insulating layer on one side of the gate electrode, and at least one active monolayer provided on one side of the gate insulating layer, but applied to the gate electrode Even if the gate voltage to be increased, an increase in current flowing through the active monolayer may be limited.
  • a multi-level device is formed on one side of a gate electrode, the gate electrode, and a first active layer including a first TMDC (Transition Metal Dichalcogenide), and one side of the first active layer. It may include a second active layer including a second TMDC, source and drain electrodes provided on one side of the second active layer, and a barrier layer separating the first active layer and the second active layer.
  • TMDC Transition Metal Dichalcogenide
  • the multi-level device is formed on one side of a gate electrode and the gate electrode, and includes a first active layer including a first metal single atom and a first active layer on one side, and a second A second active layer including a metal unit, a source and drain electrode provided on one side of the second active layer, and a barrier layer separating the first active layer and the second active layer may be included.
  • the number of active layers activated among the first and second active layers may be controlled according to a gate voltage applied to the gate electrode.
  • the first active layer, the barrier layer, the second active layer, and the source and drain electrodes may be sequentially stacked.
  • the source electrode and the drain electrode may be in electrical contact only with the second active layer.
  • the source electrode and the drain electrode may be electrically non-contact with the first active layer.
  • the first gate voltage range, the second gate voltage range, and the third gate voltage range applied to the gate electrode are divided into the first, second, and second gate voltages in increasing order.
  • the third gate voltage range may be provided.
  • the first active layer when a gate voltage in the first gate voltage range is applied to the gate electrode, only the first active layer is activated, and a gate voltage in the third gate voltage range is applied to the gate electrode.
  • the first and second active layers may be activated.
  • the first active layer may be in a saturation state within the second gate voltage range.
  • the second active layer at the gate electrode by a current flowing through the first active layer can be shielded.
  • the first and second active layers may include a TMDC monolayer.
  • a multi-level device manufacturing method includes depositing a first active layer including a first TMDC, depositing a barrier layer on one side of the first active layer and one side of the barrier layer It may include the step of depositing a second active layer comprising a second TMDC.
  • At least one active layer deposition step of depositing the first active layer and the second active layer includes depositing the TMDC monolayer, and depositing the TMDC monolayer.
  • the first chalcogen deposition step of dosing and purging the chalcogen source gas by closing the outlet of the chamber, by providing a metal precursor source gas comprising a transition metal precursor, thereby increasing the pressure in the chamber, Metal precursor source gas pressurized dosing to adsorb a transition metal precursor to the substrate, after the metal precursor source gas pressurized dosing, first main purging to purge, after the first main purging to react
  • a reaction gas dosing step of providing gas, a second main purging step of purging after the reaction gas dosing step, and the chalcogenide Dosing the gas and may include a first deposition step Kogen knife 2 purging.
  • a method of manufacturing a multilevel device includes depositing a first active layer including a first metal single atom, depositing a barrier layer on one side of the first active layer, and the barrier layer one It may include the step of depositing a second active layer including a second metal single element on the side.
  • At least one active layer deposition step of depositing the first active layer and the second active layer by closing the outlet of the chamber, by providing a metal precursor source gas containing a metal precursor , Source gas pressurized dosing to increase the pressure in the chamber to adsorb the metal precursor to the substrate, after the source gas pressurized dosing, the first main purging step to purge, the first main After the purging step, a reaction gas dosing step for providing a reaction gas and a second main purging step for purging after the reaction gas dosing step may be included.
  • the membrane structure according to an embodiment of the present invention includes at least one active monolayer having an energy level quantized in at least one axial direction and at least one layer alternately stacked with the active monolayer of the at least one layer. It may include a barrier (barrier).
  • the stacking of the monolayer and the barrier can provide a quantum well structure, and since the active monolayer has an energy level quantized in at least one axial direction, swing of the gate voltage Nevertheless, the flow of current can be limited.
  • the active monolayer has a two-dimensional layered structure, and since it has a hybrid superlattice structure, stability may be improved.
  • the manufacturing process of the membrane structure according to an embodiment of the present invention can be performed in a low temperature process, thereby providing excellent process stability.
  • a hybrid superlattice structure can be easily provided by a manufacturing process of a membrane structure according to an embodiment of the present invention.
  • the multi-level device according to an embodiment of the present invention may provide multi-level conductivity.
  • the multi-level device according to an embodiment of the present invention may provide a simple manufacturing method.
  • the multilevel device according to an embodiment of the present invention may provide easy control of the thickness of the active layer.
  • the multi-level device according to an embodiment of the present invention may provide ultra-thin properties.
  • FIG. 1 to 3 are views for explaining a device according to a first embodiment of the present invention.
  • FIGS 4 and 5 are diagrams for explaining the active monolayer according to the first embodiment of the present invention in detail.
  • 6 to 9 are views for explaining a method of manufacturing a device according to a first embodiment of the present invention.
  • 10 to 12 are views for explaining the operating characteristics of the device according to the first embodiment of the present invention.
  • FIG. 13 and 14 are views for explaining a device according to a second embodiment of the present invention.
  • 15 to 17 are diagrams for explaining the operating characteristics of the device according to the second embodiment of the present invention.
  • FIGS. 18 and 19 are diagrams for describing a device according to a third embodiment of the present invention.
  • 20 to 22 are views for explaining the operating characteristics of the device according to the third embodiment of the present invention.
  • FIG. 23 is a view for explaining a multi-level device according to a first embodiment of the present invention.
  • 24 is a view for explaining a method of manufacturing a multi-level device according to a first embodiment of the present invention.
  • 25 is a view for explaining the characteristics of a multi-level device according to a first embodiment of the present invention.
  • 26 shows a multi-level device according to a second embodiment of the present invention.
  • FIG. 27 is a flowchart illustrating a method of manufacturing a multi-level device according to a second embodiment of the present invention.
  • FIG. 28 is a view for explaining the characteristics of a multi-level device according to a second embodiment of the present invention.
  • 29 is a result of measuring the surface coverage according to the pressure dosing step.
  • FIG. 33 shows a WS2 thin film manufactured according to an embodiment of the present invention.
  • a component when referred to as being on another component, it means that it may be formed directly on another component, or a third component may be interposed between them.
  • a third component may be interposed between them.
  • the thickness of the films and regions are exaggerated for effective description of the technical content.
  • first, second, and third are used to describe various components, but these components should not be limited by these terms. These terms are only used to distinguish one component from another component. Therefore, what is referred to as the first component in one embodiment may be referred to as the second component in another embodiment.
  • first component in one embodiment
  • second component in another embodiment
  • Each embodiment described and illustrated herein also includes its complementary embodiment. Also, in this specification, 'and / or' is used to mean including at least one of the components listed before and after.
  • the film according to an embodiment of the present invention has at least one layer of an active monolayer having an energy level quantized in at least one axial direction and at least one layer of the barrier layer alternately stacked with the at least one layer of active monolayer ( barrier) ;, the current flows in the active monolayer, and the current flow may be limited by the quantized energy level.
  • the active monolayer since the active monolayer has a quantized energy level in at least one axial direction, the amount of current flowing through the active monolayer may be limited.
  • the active monolayer may have an energy level quantized in a short axis direction.
  • the active monolayer may have an energy level quantized in the 3-axis direction. In this case, despite the field swing, the intensity of the current flowing through the active monolayer may be constant. That is, a current saturation state can be provided.
  • the current saturation characteristic can be understood as a unique effect according to an embodiment of the present invention.
  • a first embodiment using a metal oxide as an active monolayer will be described with reference to FIGS. 1 to 12.
  • FIG. 1 to 3 are views for explaining a device according to a first embodiment of the present invention.
  • the device 100a includes a substrate (not shown), a gate electrode 120, a first barrier 130, an active monolayer 140, and a second At least one of the barrier 150, the source electrode 160 and the drain electrode 162 may be included. It may be referred to as a membrane structure including at least one of an active monolayer and a barrier.
  • a membrane structure including at least one of an active monolayer and a barrier.
  • the substrate is not limited in its kind, and may be, for example, at least one of a silicon substrate, a glass substrate, and a flexible substrate.
  • the gate electrode 120 is configured to receive a gate voltage, and may be made of a conductive material, for example, a metallic material.
  • the gate insulating layer 125 is configured to perform the function of a dielectric layer, and may be formed of at least one of an insulating material, for example, a silicon-based insulating material or a metal oxide-based insulating material.
  • the thickness of the gate insulating layer 125 may be determined to correspond to the operating range of the applied gate voltage. For example, when the operating range of the gate voltage is low, the thickness of the insulating film 130 may be thin compared to the case where the operating range of the gate voltage is high.
  • At least one barrier among the first and second barriers 130 and 150 may include at least one of an organic material, an inorganic material, and an organic-inorganic complex.
  • the barrier may include at least one of 4MP (4-mercaptophenol) and Zn4MP (Zinc 4-mercaptophenol), and when the barrier is an organic-inorganic composite, the barrier has an Al linker 4MP or Al4MP.
  • first and second barriers 130 and 150 are Zn4MP.
  • the barrier may protect the active monolayer.
  • the second barrier 150 may inadvertently doped the active monolayer 140, or a precursor due to deposition of another layer. Infiltration into the active monolayer 140 may be minimized.
  • the active mono layer 140 may include a metal oxide, for example, ZnO.
  • the active monolayer 140 may have a two-dimensional layered structure. At this time, the two-dimensional layered structure of the active monolayer 140 may form a superlattice structure through a predetermined stacking.
  • the thickness of the active monolayer 140 may be within a range in which field effect transistor (FET) characteristics are exhibited.
  • FET field effect transistor
  • the active monolayer 140 when the active monolayer 140 includes zinc oxide, it may have a thickness of 1.5 nm or more. If the thickness of the zinc oxide is less than 1.5 nm, the zinc oxide may lose FET characteristics.
  • the thickness of the active monolayer may be 20 nm or less. If the thickness of the active monolayer is greater than 20 nm, an increase in operating voltage may be disadvantageous in terms of power consumption.
  • the gate insulating layer 125 needs to be thicker in order to withstand a large gate voltage, it cannot meet the trend of miniaturization of the device.
  • the active monolayer of at least one layer and the barrier of at least one layer may be alternately stacked.
  • a barrier may be provided on at least one side of the active monolayer. If barriers are provided on one side and the other side of the active monolayer, the active monolayer may have a structure sandwiched between the first and second barriers.
  • at least one surface of the active monolayer 140 may directly contact the barrier. That is, one surface of the active monolayer 140 may contact the first barrier 130 and the other surface may contact the second barrier 150.
  • the first barrier 130 and the second barrier 150 are located on both sides of the active monolayer 140, respectively.
  • each of the first barrier 130, the active monolayer 140, and the second barrier 150 may have a thickness of several nm.
  • the active monolayer and the barrier adjacent to the active monolayer may form a hybrid superlattice structure. Stability can be improved by the super lattice structure.
  • the barrier by forming an adjacent interface with the active monolayer, the active monolayer may have a quantum well structure (quantum well) through the barrier.
  • the active monolayer 140 includes a plurality of crystalline regions NC_R surrounded by an amorphous region (AM_R) and the amorphous region (AM_R). ) May include a layer. That is, the amorphous region AM_R and the crystalline region NC_R may be mixed in the active monolayer.
  • each of the crystalline regions NC_R may be formed of a nano size to have a quantum confinement effect.
  • the crystalline region NC_R may have a size of several nm, for example, about 3 nm, and an average distance between the crystalline regions may be about 2.5 nm.
  • the crystalline regions NC_R are spaced apart from each other by an average distance of about 2.5 nm, and the crystalline regions NC_R may be surrounded by the amorphous regions AM_R to have an isolated island shape.
  • the crystalline regions NC_R may be randomly distributed in two dimensions within the amorphous region AM_R. Accordingly, the crystalline region NC_R may provide a quantum confinement effect in a 3-axis direction. That is, the crystalline region NC_R may provide a quantum confinement effect not only in the thickness direction but also in the surface direction.
  • a current saturation region (Vs region in FIG. 12) may be generated by triaxial quantization of the active monolayer. 4 and 5 will be referred for a detailed description.
  • FIGS 4 and 5 are diagrams for explaining the active monolayer according to the first embodiment of the present invention in detail.
  • the amorphous region AM_R of the active monolayer 140 may have a number of localized states.
  • the crystalline region NC_R of the active monolayer 140 may have fewer discrete localized states than ubiquitous states caused by the amorphous region AM_R.
  • a specific energy state (AM_E) among ubiquitous energy states of the amorphous region (AM_R) and a specific energy state (NC_E) of ubiquitous energy states of the crystalline region (NC_R) are matched to each other by resonance energy matching ( resonant energy matching).
  • Hybridization by resonance energy matching may provide a quantized conduction state.
  • the quantized conductive state provides a conductive state, but may provide limited current transfer.
  • the quantized conductive state will be described in more detail with reference to FIG. 5.
  • DOS simulation results are calculated using a program called Vienna ab initio simulation (VASP), but the manufactured active monolayer is calculated using the PBE (Perdew-Burke-Ernzerhof) exchange-correlation functional and PAW (projector-augmented wave) pseudopotentials method. By doing, it can be obtained.
  • VASP Vienna ab initio simulation
  • the DOS of FIG. 5 shows the change in the number of electronic states according to the increase of the electronic energy.
  • the active monolayer 140 according to an embodiment of the present invention may have a valence band and a conduction band.
  • the consumer electronics zone may be divided into an extended state and a ubiquitous state, which are non-ubiquitous states by a mobility edge. Also, the conduction band can be divided into an extended state and a ubiquitous state by a mobility edge.
  • the active monolayer 140 provides the number of first electron states in a low level electron energy range (about 2.8 eV to 2.9 eV) in a conduction band
  • the number of second electron states in the high-level electron energy range (about 3.2 eV or more) higher than the low-level electron energy range in the conduction band may be provided.
  • the number curve of the first electron state in the low-level electron energy range and the number curve of the second electron state in the high-level electron energy range may be discontinuous.
  • the maximum electron energy value of the low level electron energy range (about 2.9 eV) may be smaller than the minimum electron energy value (about 3.2 eV) of the high level electron energy range.
  • the maximum value of the number of first electronic states in the low-level electronic energy range may be less than the minimum value of the number of second electronic states in the high-level electronic energy range.
  • the low level electron energy range and the high level electron energy range may be provided at a higher electron energy than a mobility edge in a conduction band (i.e. mobility edge quantization).
  • mobility edge quantization i.e. mobility edge quantization
  • the energy level of the ubiquitous state of the amorphous region AM_R of the active monolayer 140 is matched with the energy level of the ubiquitous state of the crystalline region, but is matched at a mobility edge or higher.
  • the active monolayer 140 may provide a conductive state in the low level electron energy range and the high level electron energy range.
  • the conduction state in the low-level electron energy range having the first number of electron states on the mobility edge may be defined as a quantized extended state.
  • a ubiquitous state ie, the number of electron states is 0
  • the crystalline region NC_R of the monolayer does not have an energy state between the low level electron energy range and the high level electron energy range. Accordingly, resonance energy is not matched between the crystalline region NC_R and the amorphous region AM_R between the low level electron energy range and the high level electron energy range.
  • the low-level electron energy range may be provided by resonance energy matching between the crystalline region NC_R and the amorphous region AM_R of the active monolayer 140.
  • the curve defined by the low-level electron energy range and the number of first electron states may have a very limited area. This may mean that very limited carriers may be present.
  • a current saturation state (Vs region in FIG. 12) may be provided.
  • the source and drain electrodes 160 and 162 may contact the uppermost barrier. In another aspect, the source and drain electrodes 160 and 162 may contact the second barrier 150 at the top, and may not contact the first barrier 130 and the active monolayer 140.
  • the device according to the first embodiment of the present invention has been described above from a structural point of view.
  • a method of manufacturing a device according to a first embodiment of the present invention will be described with reference to FIGS. 6 to 9.
  • 6 to 9 are views for explaining a method of manufacturing a device according to a first embodiment of the present invention.
  • a method of manufacturing a device includes preparing a substrate, a gate electrode, and a gate insulating layer (S110), forming a first barrier (S120), and forming an active monolayer (S130), a second barrier forming step (S140) and a source and drain electrode forming step (S150) may include at least one step. Each step will be described below.
  • Step S110 is a preliminary preparation step, and may include preparing a substrate, forming a gate electrode on the substrate, and forming a gate insulating film on the gate electrode.
  • a first barrier may be formed on the gate insulating layer.
  • the first barrier may be prepared through molecular layer growth (MLD).
  • MLD molecular layer growth
  • the molecular layer growth method may include a DEZ precursor providing step, a purging step, a 4MP precursor providing step, and a purging step.
  • the first barrier 130 can be deposited.
  • step S130 the active monolayer 140 may be deposited. Reference will be made to FIG. 7 to specifically describe step S130.
  • step S130 is a flowchart for explaining in detail step S130 according to an embodiment of the present invention.
  • an active monolayer manufacturing method includes a source gas pressurized dosing step (S210), a first main purging step (S220), a reactive gas dosing step (S230), and a second main It may include at least one of the purging step (S240).
  • S210 source gas pressurized dosing step
  • S220 first main purging step
  • S230 reactive gas dosing step
  • S240 second main It may include at least one of the purging step (S240).
  • the source gas may be prepared for the source gas pressurized dosing step (S210).
  • Source gas may be prepared in various ways depending on the type of film to be deposited. For example, when the film to be deposited is a metal oxide, a metal precursor source gas corresponding thereto may be prepared. For example, when the film to be deposited is zinc oxide (ZnO), the source gas may include diethyl zinc (DEZ).
  • ZnO zinc oxide
  • DEZ diethyl zinc
  • the source gas may be provided with the outlet of the chamber closed. Accordingly, the pressure in the chamber may rise as the source gas flows into the chamber. In other words, since the pressure in the chamber increases due to the supply of the source gas, the substrate may be adsorbed in the pressurized atmosphere. In addition, the pressure of the elevated chamber can be maintained for a predetermined time. Accordingly, the substrate adsorption efficiency can be improved.
  • step S210 may be greater than 0.03 Torr, preferably 0.1 Torr, or even 0.3 Torr or more.
  • the process temperature in step S210 may be 80 degrees to 250 degrees.
  • the process temperature may be 100 degrees to 150 degrees.
  • an inert gas may be used, and the inert gas may be, for example, argon (Ar) or nitrogen (N2) gas.
  • the inert gas may be, for example, argon (Ar) or nitrogen (N2) gas.
  • the reaction gas may be reduced to a film to be deposited by reacting with the source gas.
  • the reaction gas may consist of H2O.
  • a second main purging step (S240) may be further performed.
  • excess gas that has not been adsorbed on the surface of the substrate can be removed.
  • step S210 The steps S210 to S240 according to an embodiment of the present invention have been described above. Hereinafter, the pressure dosing in step S210 will be described in detail.
  • the source gas pressurized dosing step of step S210 may be performed in a pressurized atmosphere.
  • the source gas pressurized dosing step can be performed in an atmosphere of high pressure, which can be abbreviated as pressurization step.
  • step S210 For convenience of description, the source gas pressurized dosing step of step S210 is described above, but it is needless to say that pressurized dosing may also be performed in the step of dosing the reaction gas of step S230.
  • the pressure dosing step may be performed in a state in which the substrate is provided and the chamber is sealed. For example, by closing the outlet valve of the chamber, by supplying the metal precursor source gas into the chamber (sub-pressurized dosing step), it is possible to induce the chamber into high pressure and maintain the induced high pressure (sub-exposure step). By maintaining the high pressure for a predetermined time, it is possible to induce the metal precursor source gas to be adsorbed on the target surface in a high pressure atmosphere.
  • the pressure dosing step may include at least one of a sub pressure dosing step, a sub exposure step, and a sub purging step.
  • the sub-pressurizing dosing step may be understood as a step of providing a source gas in a state in which the outlet of the chamber is closed, thereby reaching a predetermined pressure in the chamber.
  • the sub-exposure step is a step of maintaining a predetermined pressure provided by the sub-pressurizing dosing step. To this end, both the inlet and outlet of the chamber can be closed. That is, the chamber can be closed.
  • the sub-purging step may be performed after the sub-exposing step, to remove the excess source gas.
  • the pressure of the sub-exposure step may be kept constant even if the number of sub-exposure steps increases, or otherwise, as shown in FIG. 9.
  • the Y axis in FIG. 17 shows the pressure
  • the X axis shows the process steps.
  • the process temperature of step S210 may be between 80 degrees and 250 degrees. More specifically, the process temperature may be between 100 degrees and 150 degrees.
  • each of the sub-steps of step S210 may be performed at the same temperature as each other, particularly at low temperatures.
  • the low temperature may mean 250 degrees or less.
  • the active monolayer 140 may be deposited by the above-described steps S210 to S240.
  • the thickness of the deposited film may be controlled according to the number of repetitions of steps S210 to S240. For example, when the deposited film is zinc oxide, steps S210 to S240 may be repeated so that the thickness of the film exceeds 1.5 nm. Further, when the deposited film is zinc oxide, steps S210 to S240 may be repeated so that the thickness of the film is 20 nm or less.
  • the active monolayers manufactured according to steps S210 to S240 may provide DOS simulation results as shown in FIG. 5 above. That is, the quantized conductive state, more specifically, at a higher energy than the mobility edge, may provide a quantized conductive state.
  • DOS simulation results use a program called Vienna ab initio simulation (VASP), but the prepared active monolayer is a PBE (Perdew-Burke-Ernzerhof) exchange-correlation functional and a projector-augmented wave (PAW) pseudopotentials method. By calculating as, it can be obtained.
  • VASP Vienna ab initio simulation
  • PBE Perdew-Burke-Ernzerhof exchange-correlation functional
  • PAW projector-augmented wave
  • Step S140 corresponds to step S120 described above, so a detailed description thereof will be omitted.
  • Source and drain electrodes 160 and 162 may be deposited on the second barrier 11500. That is, the source and drain electrodes 160 and 162 may contact the second barrier 150. In another aspect, the source electrode and the drain electrode (160, 162) may be in non-contact with the first barrier 130 and the active monolayer 140.
  • the device according to the first embodiment of the present invention may be manufactured by steps S110 to S150 described above.
  • the manufacturing method of the device according to the first embodiment of the present invention has been described above with reference to FIGS. 6 to 9.
  • the method of manufacturing a device according to an embodiment of the present invention has an advantage in that the process is performed at a low temperature as a whole and a hybrid superlattice structure can be easily manufactured.
  • 10 to 12 are views for explaining the operating characteristics of the device according to the first embodiment of the present invention.
  • the device according to the first embodiment of the present invention was manufactured.
  • Zn4MP was deposited on the first barrier 130 through step S120 of the above-described manufacturing method. More specifically, DEZ was provided at a pressure of 30 mTorr for 2 seconds, and 20 seconds was purged. Then, 4MP was provided at a pressure of 10 mTorr for 20 seconds and purged for 200 seconds. The process temperature was 120 degrees. Each step of step S120 was repeatedly performed 25 cycles to deposit a first barrier 130 having a thickness of 10 nm.
  • step S130 was performed according to the process illustrated in FIG. 10.
  • DEZ was prepared as a source gas and H 2 O was prepared as a reaction gas.
  • DEZ was provided in accordance with step S210 through sub-pressurized dosing steps. That is, in the first sub-pressurizing dosing step, DEZ was supplied while the outlet of the chamber was closed, and the chamber was maintained in a pressurized atmosphere at 1 Torr for 3 seconds and purged for 15 seconds. Subsequently, in the second sub-pressurizing dosing step, DEZ was supplied while the outlet of the chamber was closed, and the chamber was maintained in a pressurized atmosphere at 1 Torr for 3 seconds and purged again for 15 seconds.
  • step S210 was performed.
  • steps S220 and S230 were performed. Since step S230 corresponds to step S210, a detailed description will be omitted.
  • step S230 purging is performed through step S240. This step was defined as 1 cycle, and 15 cycles were performed.
  • the active monolayer 140 having a thickness of 3 nm could be deposited.
  • the deposition process of the active monolayer 140 was also 110 to 120 degrees.
  • step S130 the second barrier 150 is deposited again according to step S130, and the source and drain electrodes 160 and 162 are deposited according to step S140.
  • the device according to the first embodiment of the present invention was manufactured.
  • the first and second barriers 130 and 150 and the active monolayer 140 may have a quantum well structure. At this time, since the active monolayer 140 has a quantum confinement effect in the 3-axis direction, current movement may be limited.
  • the device 100a manufactured according to the first embodiment of the present invention has a turn-on voltage around 1V. That is, as a voltage of 1 V or more is applied to the gate electrode 120, a current flows between the source and drain electrodes 160 and 162. At this time, as the gate voltage applied to the gate electrode 120 increases, the current flowing between the source and drain electrodes 160 and 162 increases. However, when the gate voltage increases to 2 V or more, the current between the source and drain electrodes 160 and 162 is a constant current saturation region Vs despite the increase of the gate voltage. The current saturation region with constant current was clearly observed even on the linear scale and logarithmic scale. That is, the current between the source and drain electrodes is saturated despite the swing of the gate voltage.
  • the active monolayer 140 has a quantum confinement effect in the 3-axis direction. In other respects, it is interpreted that the active monolayer 140 is in DOS, because there may be very limited carriers in the low level electron energy range.
  • the active monolayer 140 includes ZnO, that is, a metal oxide.
  • the active monolayer 140 may be made of a material having a plurality of crystalline regions and an amorphous region surrounding the crystalline region, as well as a material having a limited (discontinuous) low level electron energy region on the mobility edge in DOS. Of course it can be made of.
  • the second embodiment of the present invention is different in that the active monolayer includes a metal single atom.
  • a second embodiment of the present invention will be mainly described with respect to differences, and descriptions of parts common to the first embodiment will be omitted.
  • FIG. 13 and 14 are views for explaining a device according to a second embodiment of the present invention.
  • the active monolayer 142 of the device 100b according to the second embodiment of the present invention may include a metal unit.
  • the metal single atom may be one of tungsten (W), molybdenum (Mo), and copper (Cu), but is not limited thereto.
  • the active mono layer 142 may also have a thickness of several nano sizes.
  • the thickness of the active monolayer 142 may also be within a range in which FET (Field Effect Transistor) characteristics appear. More specifically, the thickness of the active mono layer 142 may be 1.0 nm to 20 nm.
  • the active monolayer 142 according to the second embodiment may also have a quantum well structure and a hybrid superlattice structure.
  • the active monolayer 142 may have a state quantized in at least one axis, for example, in a short axis direction. Accordingly, it is possible to limit the current flow even above the turn-on voltage. More specifically, the current slope between the source and drain electrodes as the gate voltage increases may be 15.1 nA / V or less.
  • 15 is a view for explaining a method of manufacturing a device according to a second embodiment of the present invention.
  • the device according to the second embodiment was manufactured according to the manufacturing method of the device described with reference to FIGS. 6 to 9 above. Except for the active mono layer 142, the manufacturing process conditions of the device according to the first embodiment described with reference to FIG. The specific process of the active monolayer 142 according to the second embodiment is as illustrated in FIG. 15.
  • step S210 WF6 was prepared as a source gas.
  • the process temperature in step S210 was 120 degrees.
  • Step S210 was performed, but WF6 was provided by 5 sub-pressurizing dosing. That is, during the first sub-pressurizing dosing, WF6 was provided with the outlet of the chamber closed, thereby increasing the pressure of the chamber to 1.0 Torr. Thereafter, the inlet of the chamber was also closed for 30 seconds to infiltrate WF6 at a pressure of 1.0 Torr. Subsequently, it was sub-purged for 30 seconds. Subsequently, during the second sub-pressure dosing, WF6 was provided with the outlet of the chamber closed, and the pressure in the chamber was increased again to 1.0 Torr. Thereafter, the inlet of the chamber was also closed for 30 seconds to infiltrate WF6 at a pressure of 1.0 Torr. In the same manner, the fifth sub-pressurizing dosing step and the fifth sub-penetration step were performed.
  • step S220 The first main purging (process temperature 120 ° C) was performed according to step S220 for 30 seconds.
  • step S230 Si2H6 was prepared as a reaction gas.
  • the process temperature in step S230 was 120 degrees.
  • Step S230 was performed, but SiH6 was provided in 5 sub-pressurized dosing and sub-exposure steps. At this time, process variables such as pressure and time were the same as for WF6 dosing.
  • step S240 a second main purging (process temperature 120 ° C) was performed for 30 seconds.
  • the height of the tungsten layer was controlled by repeatedly performing steps S210 to S240. In this example, 3 cycles were repeated to produce a 1 nm thick tungsten metal monolayer. Thereby, an active monolayer could be deposited.
  • 16 and 17 are diagrams for explaining the operating characteristics of the device according to the second embodiment of the present invention.
  • the first and second barriers 130 and 150 and the active monolayer 142 may have a quantum well structure.
  • the active monolayer 140 has a quantum confinement effect in a uniaxial direction (for example, a thickness direction), current movement may be limited.
  • the device manufactured according to the second embodiment of the present invention has a turn-on voltage around -5V. That is, as a voltage of -5 V or more is applied to the gate electrode 120, a current flows between the source and drain electrodes 160 and 162. At this time, as the gate voltage applied to the gate electrode 120 increases, the current flowing between the source and drain electrodes 160 and 162 increases. However, when the gate voltage is increased to about 7 V or more, it can be seen that a region in which an increase in current between the source and drain electrodes 160 and 162 is limited despite the increase of the gate voltage. That is, it can be seen that despite the swing of the gate voltage, the current increase between the source and drain electrodes is extremely limited to 15.1 nA / V. This is interpreted because the active monolayer 142 has an energy level quantized in the short axis direction.
  • the devices according to the second embodiment of the present invention have been described above with reference to FIGS. 13 to 17.
  • a device according to a third embodiment of the present invention will be described with reference to FIGS. 18 to 22.
  • the third embodiment of the present invention is different in that the active monolayer includes a transition metal dichalcogenide (TMDC).
  • TMDC transition metal dichalcogenide
  • a third embodiment of the present invention will be mainly described with respect to differences, and descriptions of parts common to the first embodiment will be omitted.
  • FIGS. 18 and 19 are diagrams for describing a device according to a third embodiment of the present invention.
  • the active monolayer 146 of the device 100c according to the third embodiment of the present invention may include TMDC.
  • TMDC may be one of WS2 and MOS2, but is not limited thereto.
  • the active mono layer 146 may also have a thickness of several nano sizes.
  • the active mono layer 146 may also have a thickness of several nano sizes.
  • the thickness of the active monolayer 142 may also be within a range in which FET (Field Effect Transistor) characteristics appear. More specifically, the thickness of the active mono layer 142 may be 1.0 nm to 20 nm.
  • the active monolayer 146 may also have a quantum well structure and a hybrid superlattice structure.
  • the active monolayer 146 may have a state quantized in at least one axis, for example, in a short axis direction. Accordingly, it is possible to limit the current flow even above the turn-on voltage. More specifically, the slope of the current between the source and drain electrodes as the gate voltage increases may be -0.2 nA / V or less.
  • 20 is a view for explaining a method of manufacturing a device according to a third embodiment of the present invention.
  • the device according to the third embodiment was manufactured according to the manufacturing method of the device described with reference to FIGS. 6 to 9 above. Except for the active mono layer 146, the manufacturing process conditions of the device according to the first embodiment described with reference to FIG. The specific process of the active monolayer 146 according to the third embodiment is as illustrated in FIG. 15.
  • the chalcogenide source gas was heated to 100 degrees or more to provide for 30 seconds, and then purged for 30 seconds.
  • S sulfur
  • step S210 WF6 was prepared as a source gas.
  • the process temperature in step S210 was 120 degrees.
  • Step S210 was performed, but WF6 was provided by 5 sub-pressurizing dosing. That is, during the first sub-pressurizing dosing, WF6 was provided with the outlet of the chamber closed, thereby increasing the pressure of the chamber to 1.0 Torr. Thereafter, the inlet of the chamber was also closed for 30 seconds to infiltrate WF6 at a pressure of 1.0 Torr. Subsequently, it was sub-purged for 30 seconds. Subsequently, during the second sub-pressure dosing, WF6 was provided with the outlet of the chamber closed, and the pressure in the chamber was increased again to 1.0 Torr. Thereafter, the inlet of the chamber was also closed for 30 seconds to infiltrate WF6 at a pressure of 1.0 Torr. In the same manner, the fifth sub-pressurizing dosing step and the fifth sub-penetration step were performed.
  • step S220 The first main purging (process temperature 120 ° C) was performed according to step S220 for 30 seconds.
  • step S230 Si2H6 was prepared as a reaction gas.
  • the process temperature in step S230 was 120 degrees.
  • Step S230 was performed, but SiH6 was provided in 5 sub-pressurized dosing and sub-exposure steps. At this time, process variables such as pressure and time were the same as for WF6 dosing.
  • step S240 a second main purging (process temperature 120 ° C) was performed for 30 seconds.
  • steps S210 to S240 were performed once. That is, unlike the first and second embodiments, the cycle was not repeated.
  • the chalcogen source gas was heated to 100 degrees or more and provided for 30 seconds, followed by purging for 30 seconds.
  • the WS2 monolayer having a thickness of 1 nm could be deposited with the active monolayer 146.
  • 21 and 22 are diagrams for explaining the operating characteristics of the device according to the third embodiment of the present invention.
  • the first and second barriers 130 and 150 and the active monolayer 146 may have a quantum well structure. At this time, since the active monolayer 146 has a quantum confinement effect in a short axis direction (for example, a thickness direction), current movement may be limited.
  • the device manufactured according to the third embodiment of the present invention has a turn-on voltage around 0V. That is, as a voltage of about 0 V or more is applied to the gate electrode 120, a current flows between the source and drain electrodes 160 and 162. At this time, as the gate voltage applied to the gate electrode 120 increases, the current flowing between the source and drain electrodes 160 and 162 increases. However, when the gate voltage is increased to about -5 V or more, it can be seen that a region in which the current increase between the source and drain electrodes 160 and 162 is limited despite the increase of the gate voltage. That is, it can be seen that despite the swing of the gate voltage, the current increase between the source and drain electrodes is extremely limited to -0.2 nA / V. This is interpreted because the active monolayer 146 has an energy level quantized in the short axis direction.
  • the membrane structures and devices according to the first to third embodiments of the present invention have a superlattice structure and a quantum well structure and may have a quantized energy level in at least one axial direction. Accordingly, it is possible to provide a unique effect that the movement of the current is limited and saturated even in the gate voltage section above the turn-on voltage.
  • the transistor structures have been described with reference to the transistor structure, but the film structures according to the first to third embodiments of the present invention can be applied to three-terminal devices and two-terminal devices other than transistors Of course it can.
  • the membrane structures according to the embodiments may provide multilevel characteristics. More specifically, when the film structures according to the embodiments are stacked, a non-gating region due to current saturation may occur between each turn-on voltage of the film structures. That is, activation of the active monolayer of each membrane structure can be clearly distinguished. Accordingly, the film structure according to embodiments of the present invention can be utilized in a multilevel device. Hereinafter, a multi-level device according to embodiments of the present invention will be described.
  • the multi-level device may have a structure in which the first activiation layer, the barrier layer, and the second active layer are sequentially stacked.
  • the number of active layers activated among the first and second active layers may be controlled according to a gate voltage applied to the gate electrode of the multilevel device according to an embodiment.
  • Conductive activation of the first and second active layers may be controlled according to the magnitude of the gate voltage applied to the gate electrode.
  • the first gate voltage range, a second gate voltage range that is a region larger than the first gate voltage range, and a third gate voltage range that is a region larger than the second gate voltage range are described by dividing the case where the gate electrode is applied. I will do it.
  • the gate voltage is described based on absolute values without distinguishing between positive and negative.
  • the first gate voltage range may be understood as R1 of FIGS. 25 and 28, the second gate voltage range of R2 of FIGS. 25 and 28, and the third gate voltage range of R3 of FIGS. 25 and 28.
  • the smallest gate voltage of the first gate voltage range may be the first turn-on voltage.
  • the first active layer When the first turn-on voltage is applied to the gate electrode, the first active layer may be activated, that is, turned on. At this time, the second active layer may be inactive, that is, in a turn-off state. Thereafter, as the voltage increases within the first gate voltage range, the magnitude of the current flowing between the source and drain electrodes may increase. That is, the current ratio between the source and drain electrodes according to the increase of the gate voltage within the first gate voltage range may have a first slope.
  • the gate voltage in the second gate voltage range will be described later, and application of the gate voltage in the third gate voltage range will be described first.
  • the second active layer as well as the first active layer may be activated, that is, turned on. That is, the smallest gate voltage in the third gate voltage range may be the second turn-on voltage.
  • the magnitude of the current flowing between the source and drain electrodes may increase with a third slope. That is, the current ratio according to the increase of the gate voltage within the third gate voltage range may have a third slope.
  • both the first and second active layers are turned on, so a larger current flows between the source and drain electrodes when the gate voltage in the first gate voltage range is applied. You can.
  • the first active layer When a gate voltage in the second gate voltage range larger than the first gate voltage range and smaller than the third gate voltage range is applied to the gate electrode, only the first active layer may be activated, that is, in a turn-on state. At this time, even if the gate voltage increases within the second gate voltage range, the degree of current movement between the source / drain electrodes can be maintained. That is, when the gate voltage increases within the first gate voltage range, the amount of current flowing between the source and the drain electrode increases, for example, at a first slope, while the gate voltage within the second gate voltage range increases. When increasing, the amount of current flowing between the source and drain electrodes may be smaller than the first and third slopes.
  • the multi-level device may provide multi-level conductivity.
  • the first active layer when a gate voltage within the first gate voltage range is applied, the first active layer may be turned on. In this case, the field caused by the gate voltage does not reach the second active layer by the current flowing through the first active layer (electrons of the source electrode tunnel the second active layer and the barrier layer) and is shielded (shielding effect).
  • the barrier layer may maintain limited electron flow of the first active layer while delaying gating of the second active layer even if the gate voltage increases within the second gate voltage range.
  • the gate voltage When a gate voltage in the third gate voltage range is applied, the gate voltage reaches the second active layer due to field penetration. Accordingly, the second active layer can be turned on.
  • the first active layer in order for the gate voltage to reach the second active layer by field penetration, it may be desirable that the first active layer is a TMDC monolayer. If the first active layer is thicker, the amount of current flowing through the first active layer is increased. Accordingly, a shielding effect that prevents the first active layer from field penetration of the gate voltage into the second active layer is increased. In this case, an excessively large gate voltage is required to turn on the second active layer, which is disadvantageous in terms of power consumption. In addition, since the gate insulating film has to be made thicker in order to withstand a large gate voltage, it cannot meet the trend of miniaturization of transistors. On the other hand, when the first active layer is the TMDC monolayer, the second active layer may be turned on even within a typical gate voltage range, thereby meeting power consumption and miniaturization trends.
  • FIG. 23 is a view for explaining a multi-level device according to a first embodiment of the present invention.
  • the multi-level device 300a includes a substrate, a gate electrode 120, a gate insulating film 125, a first active layer 142a, a barrier layer 132,
  • the second active layer 142b may include a source electrode 160 and a drain electrode 162.
  • the first active layer 142a includes a metal monoatomic layer W
  • the second barrier layer 132 includes a first barrier layer ZnO and a second barrier layer 4MP.
  • the second active layer 142b may include a metal monoatomic layer W.
  • the multilevel device according to the first embodiment of the present invention may be based on the device according to the second embodiment of the present invention described above.
  • 24 is a view for explaining a method of manufacturing a multi-level device according to a first embodiment of the present invention.
  • a method of manufacturing a multilevel device includes forming a gate insulating layer on one side of a gate electrode and the gate electrode (S310), and a first side on the gate insulating layer.
  • each step will be described in detail.
  • a gate insulating layer may be formed on the substrate and on one side of the gate electrode and the gate electrode.
  • the gate electrode has a structure in which a gate voltage is applied, and may be made of any material having conductivity, for example, metal.
  • the gate insulating layer is configured to prevent leakage of the gate current applied to the gate electrode, and may be made of any material having insulating properties, for example, at least one of Al2O3, SiNx, and SiO2.
  • a first active layer including a first metal single atom may be deposited on one side of the gate insulating layer.
  • Step S320 corresponds to the process described with reference to Figure 15 above, so a detailed description thereof will be omitted.
  • the pressure dosing step described with reference to FIG. 7 may be applied.
  • the thickness of the first active layer may be, for example, more than 0.7 nm and less than 4 nm, preferably 1 nm or more and 2 nm or less.
  • a barrier layer may be deposited on the first active layer.
  • the barrier layer may be provided between the second active layer to be described later and the deposited first active layer.
  • a barrier layer for example, an organic molecular layer and / or an inorganic molecular layer may be formed through a molecular layer growth method.
  • step S330 may include a unit cycle consisting of dosing and purging the organic precursor.
  • An organic molecular layer may be formed by a unit cycle. That is, the number of layers of the deposited organic molecular layer can be controlled as the unit cycle is repeated.
  • the pressure range may be 0.001 to 1 Torr
  • the process temperature range may be 80 to 200 degrees
  • the temperature range of the organic precursor may be 25 to 100 degrees.
  • a barrier layer having a desired thickness may be deposited on the first active layer.
  • step S340 corresponds to step S320, a detailed description will be omitted.
  • the source and drain electrodes may be formed after step S340.
  • the device having the multilevel conductivity according to the first embodiment of the present invention may be manufactured by the above steps S310 to S350.
  • 25 is a view for explaining the characteristics of a multi-level device according to a first embodiment of the present invention.
  • a multilevel device according to a first embodiment of the present invention was manufactured.
  • the first active layer and the second active layer were prepared according to step S320 (process conditions in FIG. 15) described above.
  • the barrier layer formed between the first active layer and the second active layer includes a first barrier layer and a second barrier layer.
  • ZnO was formed as the first barrier layer.
  • ZnO was also pressurized dosing. That is, DEZ, a ZnO metal precursor source gas, was provided in five sub-pressurized dosing. That is, during the first sub-pressurizing dosing, DEZ was provided with the outlet of the chamber closed, thereby increasing the pressure in the chamber to 1.0 Torr.
  • the inlet of the chamber was also closed for 3 seconds to infiltrate DEZ at a pressure of 1.0 Torr. Subsequently, it was sub-purged for 30 seconds. Subsequently, during the second sub-pressurizing dosing, DEZ was provided with the outlet of the chamber closed, and the pressure in the chamber was increased again to 1.0 Torr. Thereafter, the inlet of the chamber was also closed for 3 seconds to infiltrate DEZ at a pressure of 1.0 Torr. In the same manner, the fifth sub-pressurizing dosing step and the fifth sub-penetration step were performed. Thereafter, the first main purging step was performed for 15 seconds.
  • H 2 O was provided in 5 sub-pressurized dosing and sub-exposure steps. At this time, process parameters such as pressure and time were the same as for DEZ dosing. Thereafter, a second main purging step was performed to prepare a first barrier layer.
  • a second barrier layer was formed on the first barrier layer.
  • 4MP was deposited as the second barrier layer.
  • 4MP was prepared as an organic precursor, and argon was prepared as a purging gas.
  • the pressure of the step of dosing the organic precursor was 200 mTorr, for 20 seconds, and the step of purging was continued for 60 seconds.
  • the pressure of each process was 100 degrees.
  • an organic barrier layer was deposited.
  • 4 to 7 volts may be understood as the second gate voltage range R2.
  • This is interpreted as the first active layer being saturated while the second active layer is still turned off in the gate voltage range of 4 to 7 volts.
  • the gate voltage range of 4 to 7 volts it is interpreted that the gate field reaching the second active layer is blocked by the barrier layer and the first active layer, so that the second active layer cannot be turned on. That is, a current saturation phenomenon may occur due to the quantized energy level in at least one axial direction of the active layer, and a second gate voltage range R2 may be generated by the current saturation phenomenon.
  • the gate voltage of 7 volts or more may be understood as the third gate voltage range R3. It is interpreted that at a voltage of 7 volts or more, the gate voltage passes through the first active layer and the barrier layer to reach the second active layer.
  • 26 shows a multi-level device according to a second embodiment of the present invention.
  • the multi-level device 300b includes a substrate, a gate electrode 120, a gate insulating film 125, a first active layer 144a, a barrier layer 134,
  • the second active layer 144b may include a source electrode 160 and a drain electrode 162.
  • the device according to the second embodiment may have a structure in which the first active layer 144a, the barrier layer 134, and the second active layer 144b are sequentially stacked based on the gate electrode 120. have.
  • the source and drain electrodes 160 and 162 may be in electrical contact with the second active layer 144b. In other words, the source and drain electrodes 160 and 162 may be in electrical contact with the first active layer 144a and the barrier layer 134.
  • the first active layer 144a includes WS2 TMDC
  • the second barrier layer 134 includes 4MP
  • the second active layer 144b includes WS2 TMDC. You can.
  • the multilevel device according to the second embodiment of the present invention may be based on the device according to the third embodiment of the present invention described above.
  • FIG. 27 is a flowchart illustrating a method of manufacturing a multi-level device according to a second embodiment of the present invention.
  • a method of manufacturing a multilevel device includes forming a gate insulating film on one side of a gate electrode and the gate electrode (S410), and a first on the gate insulating film side.
  • Steps S410 and S450 correspond to the manufacturing method of the multi-level device according to the first embodiment, so a detailed description thereof will be omitted.
  • Steps S420 and S440 correspond to what has been described with reference to FIG. 20, so a detailed description thereof will be omitted. Since step S430 corresponds to step S330 described with reference to FIG. 23, a detailed description will be omitted.
  • the multi-level conductivity characteristics according to the second embodiment of the present invention will be described. It was confirmed that the multilevel device manufactured according to the conditions described with reference to FIG. 27 has a multilevel conductivity on the I-V curve, as shown in FIG. 28.
  • -19 to -22 volts may be understood as the second gate voltage range R2.
  • This is interpreted as the first active layer being saturated while the second active layer is still turned off in the gate voltage range of -19 to -22 volts.
  • the gate voltage range of -19 to -22 volts it is interpreted that the gate field reaching the second active layer is blocked by the barrier layer and the first active layer, so that the second active layer cannot be turned on. That is, a current saturation phenomenon may occur due to the quantized energy level in at least one axial direction of the active layer, and a second gate voltage range R2 may be generated by the current saturation phenomenon.
  • a gate voltage of -22 volts or more may be understood as the third gate voltage range R3. It is interpreted that the gate voltage reaches the second active layer through the first active layer and the barrier layer at a voltage of -22 volts or more.
  • the multi-level device according to the second embodiment of the present invention has been described above.
  • 29 is a result of measuring the surface coverage while increasing the pressure of the chamber by the metal precursor source gas while performing the pressurized dosing step described with reference to FIG. 7 using tungsten hexafluoride gas as the source gas.
  • the surface coverages were 61%, 62.5%, 62,65%, 66.5%, respectively. , 69.5%, 91.5%, 96.5%, 97.5%, improved to 99%.
  • the dosing pressure of the source gas was 0.2 mTorr and low pressure
  • the surface coverage was low at about 70%.
  • the dosing pressure of the source gas was increased to 0.3 Torr or more, the surface coverage was found to be remarkably excellent at about 90%.
  • the minimum pressure of the source gas pressurized dosing step is preferably 0.3 Torr or more.
  • the pressure dosing step may be applied to a device according to one embodiment of the present invention and a multi-level device according to one embodiment of the present invention.
  • XPS analysis was performed on WS2 of the device according to the third embodiment and the multi-level device according to the second embodiment of the present invention.
  • the manufacturing process is the same as described with reference to FIG. 20.
  • the WS2 prepared according to an embodiment of the present invention was able to clearly identify the peak by S in addition to the peak by W (FIG. 30 (b), FIG. 31 (b). Through this, it can be confirmed that WS2 was deposited.
  • the intensity ratio (I 2LA / IA 1g ) was 2.4, and the frequency difference (cm ⁇ 1 ) of E 2g and A 1g was confirmed to be 62.5 (FIG. 32 (b)).
  • WS2 manufactured according to an embodiment of the present invention is a monolayer.
  • AFM analysis was performed on WS2 prepared according to an embodiment of the present invention.
  • the multilevel device manufactured according to the exemplary embodiment of the present invention had a TMDC active layer of a monolayer having high coverage.

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  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Thin Film Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

la présente invention concerne, selon un mode de réalisation, une structure de film comprenant : au moins une couche d'une monocouche active ayant un niveau d'énergie quantifié dans au moins une direction ; et au moins une couche d'une barrière stratifiée en alternance avec la ou les couches de la monocouche active, un courant circulant dans la monocouche active, et la circulation du courant pouvant être limitée par le niveau d'énergie quantifié.
PCT/KR2019/003242 2018-10-18 2019-03-20 Structure de film, élément et élément à plusieurs niveaux WO2020080621A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP19873247.1A EP3869567A4 (fr) 2018-10-18 2019-03-20 Structure de film, élément et élément à plusieurs niveaux
JP2021521212A JP7207784B2 (ja) 2018-10-18 2019-03-20 膜構造体、素子およびマルチレベル素子
US17/285,633 US11985835B2 (en) 2018-10-18 2019-03-20 Film structure, element, and multilevel element

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
KR10-2018-0124405 2018-10-18
KR20180124405 2018-10-18
KR10-2019-0021029 2019-02-22
KR1020190021029A KR102250011B1 (ko) 2018-10-18 2019-02-22 막 구조체, 소자 및 멀티레벨 소자

Publications (1)

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WO2020080621A1 true WO2020080621A1 (fr) 2020-04-23

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5221849A (en) * 1992-06-16 1993-06-22 Motorola, Inc. Semiconductor device with active quantum well gate
JPH06163901A (ja) * 1992-11-18 1994-06-10 Sharp Corp 薄膜トランジスタ
KR950010120A (ko) * 1993-09-17 1995-04-26 이헌조 인덱스 가이드형 전계효과 트랜지스터 제조방법
JP2017017279A (ja) * 2015-07-06 2017-01-19 三菱電機株式会社 半導体装置
KR101780219B1 (ko) * 2009-12-07 2017-09-21 인텔 코포레이션 양자 우물 기반 반도체 디바이스를 형성하는 방법

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JP2012114320A (ja) 2010-11-26 2012-06-14 Nippon Telegr & Teleph Corp <Ntt> 窒化物半導体電界効果トランジスタ
KR102537022B1 (ko) 2013-05-20 2023-05-30 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치
WO2017149413A1 (fr) 2016-03-04 2017-09-08 Semiconductor Energy Laboratory Co., Ltd. Dispositif à semi-conducteurs et son procédé de fabrication

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5221849A (en) * 1992-06-16 1993-06-22 Motorola, Inc. Semiconductor device with active quantum well gate
JPH06163901A (ja) * 1992-11-18 1994-06-10 Sharp Corp 薄膜トランジスタ
KR950010120A (ko) * 1993-09-17 1995-04-26 이헌조 인덱스 가이드형 전계효과 트랜지스터 제조방법
KR101780219B1 (ko) * 2009-12-07 2017-09-21 인텔 코포레이션 양자 우물 기반 반도체 디바이스를 형성하는 방법
JP2017017279A (ja) * 2015-07-06 2017-01-19 三菱電機株式会社 半導体装置

Non-Patent Citations (1)

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Title
See also references of EP3869567A4 *

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JP7207784B2 (ja) 2023-01-18

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