WO2020077724A1

WO2020077724A1 - Pixel drive circuit and display panel

Info

Publication number: WO2020077724A1
Application number: PCT/CN2018/116118
Authority: WO
Inventors: 李冀翔
Original assignee: 深圳市华星光电技术有限公司
Priority date: 2018-10-17
Filing date: 2018-11-19
Publication date: 2020-04-23
Also published as: CN109243391B; CN109243391A

Abstract

A pixel drive circuit comprises: a first transistor (T1), wherein a first end of the first transistor (T1) is connected to a data line (D), a second end of the first transistor (T1) is connected to a coupling node (A), a first end of a liquid crystal capacitor (CLC), a first end of a storage capacitor (Cs) and a first end of a first coupling capacitor (C1), and a control end of the first transistor (T1) is connected to a scan line (G) and a second end of the first coupling capacitor (C1); and a coupling suppression module (101) connected to the coupling node (A) and used to generate, under control of an inversion signal (M), a first voltage at the coupling node (A).

Description

Pixel driving circuit and display panel

Technical field

The present application relates to the field of display technology, in particular to a pixel driving circuit and a display panel.

Background technique

The liquid crystal display panel is widely used in various electronic display devices due to its power saving, low radiation, soft light and other characteristics. The liquid crystal display panel mainly includes a plurality of pixels distributed in an array, each pixel includes a liquid crystal capacitor, and liquid crystal molecules are arranged between the liquid crystal capacitors. By changing the voltage between the two electrodes of the liquid crystal capacitor, the arrangement state of the liquid crystal molecules can be changed, thereby changing the pixel Display brightness.

In the related art, the data line is connected to the source of the transistor, and the scan line is connected to the gate of the transistor. Under the control of the scan line, the data line sends data signals to each pixel of the pixel array row by row to The liquid crystal capacitor of the pixel is charged, thereby controlling the display state of each pixel.

However, when the transistor is switched from on to off, due to the capacitive coupling effect, the pixel voltage written into the data line will be changed after the transistor is turned off. First, it will deviate from the gray level that the original written voltage expects to express. Second, the voltage deviation of the symmetrical size of the positive and negative polarities written in the original data line is generated, and a DC residual effect is generated.

technical problem

The present application provides a pixel driving circuit and a display panel, which can suppress the influence of the capacitive coupling effect on the pixel voltage, thereby improving the display performance of the display panel.

Technical solution

This application provides a pixel driving circuit, including:

A first transistor, a first end of the first transistor is connected to a data line, a second end of the first transistor is coupled to a coupling node, a first end of a liquid crystal capacitor, a first end of a storage capacitor, and a first coupling capacitor The first end is connected, the control end of the first transistor is connected to the scan line and the second end of the first coupling capacitor, the second end of the liquid crystal capacitor and the second end of the storage capacitor are both connected to the common Electrode voltage, the first coupling capacitor generates a second voltage to the coupling node through a capacitive coupling effect;

A coupling suppression module, the coupling suppression module is connected to the coupling node, and accesses an inverse signal opposite to the polarity of the scan signal on the scan line, and is used to generate a A voltage to the coupling node; the first voltage and the second voltage have opposite polarities.

In the pixel driving circuit described in this application, the coupling suppression module includes a second transistor and a second coupling capacitor;

The first end, the second end of the second transistor, and the first end of the second coupling capacitor are all connected to the coupling node, and the control end of the second transistor is connected to the inverted signal and the first The second end of the two coupling capacitors is connected.

In the pixel driving circuit described in this application, the first transistor is an N-type transistor, and the second transistor is an N-type transistor.

In the pixel driving circuit described in this application, the aspect ratio of the first transistor and the aspect ratio of the second transistor may be adjusted so that the capacitance value of the first coupling capacitor is equal to the second The capacitance value of the coupling capacitor.

In the pixel driving circuit described in this application, the aspect ratio of the second transistor is smaller than the aspect ratio of the first transistor.

In the pixel driving circuit described in this application, the coupling suppression module includes a third transistor and a third coupling capacitor;

The first end of the third transistor is connected to the data line, the second end of the third transistor and the first end of the third coupling capacitor are both connected to the coupling node, and the The control terminal is connected to the inverted signal and the second terminal of the third coupling capacitor.

In the pixel driving circuit described in this application, the first transistor is an N-type transistor, and the third transistor is a P-type transistor.

In the pixel driving circuit described in this application, the aspect ratio of the third transistor is equal to the aspect ratio of the first transistor.

This application also provides a pixel driving circuit, including:

A first transistor, a first end of the first transistor is connected to a data line, a second end of the first transistor is coupled to a coupling node, a first end of a liquid crystal capacitor, a first end of a storage capacitor, and a first coupling capacitor The first end is connected, the control end of the first transistor is connected to the scan line and the second end of the first coupling capacitor, the second end of the liquid crystal capacitor and the second end of the storage capacitor are both connected to the common Electrode voltage

A coupling suppression module, the coupling suppression module is connected to the coupling node, and accesses an inverse signal opposite to the polarity of the scan signal on the scan line, and is used to generate a A voltage to the coupling node.

The present application also provides a display panel, which includes a pixel driving circuit, and the pixel driving circuit includes:

In the display panel described in this application, the coupling suppression module includes a second transistor and a second coupling capacitor;

In the display panel described in this application, the coupling suppression module includes a third transistor and a third coupling capacitor;

Beneficial effect

The beneficial effects of the present application are as follows: the pixel driving circuit provided by the present application is provided with a coupling suppression module which is connected to the coupling node and connected with an inverted signal opposite to the polarity of the scan signal on the scan line. It is used to generate the first voltage to the coupling node under the control of the inverted signal, so as to suppress the influence of the capacitive coupling effect on the pixel voltage, thereby improving the display performance of the display panel.

BRIEF DESCRIPTION

In order to more clearly explain the embodiments or the technical solutions in the prior art, the following will briefly introduce the drawings required in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only for applications For some embodiments, those of ordinary skill in the art can obtain other drawings based on these drawings without creative work.

1 is a schematic structural diagram of a pixel driving circuit provided by this application;

2 is a timing diagram of some signals in the pixel driving circuit provided by the present application;

3 is a first schematic circuit diagram of a pixel driving circuit provided by this application;

FIG. 4 is a second schematic circuit diagram of a pixel driving circuit provided by this application.

Embodiments of the invention

The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the drawings, in which the same or similar reference numerals indicate the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the drawings are exemplary, and are only used to explain the present application, and cannot be construed as limiting the present application.

In the description of the present application, the terms "first" and "second" are used only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise specifically limited.

The following disclosure provides many different embodiments or examples for implementing different structures of the present application. In order to simplify the disclosure of the present application, the components and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit this application. In addition, the present application may repeat reference numerals and / or reference letters in different examples. Such repetition is for simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or settings discussed.

Please refer to FIG. 1 and FIG. 2. FIG. 1 is a schematic structural diagram of a pixel driving circuit provided by the present application. FIG. 2 is a timing diagram of some signals in the pixel driving circuit provided by the present application. 1 and 2, the pixel driving circuit of the present application includes: a first transistor T1, a first end of the first transistor T1 is connected to the data line D, and a second end of the first transistor T1 is coupled to the coupling node A 1. The first end of the liquid crystal capacitor CLC, the first end of the storage capacitor Cs and the first end of the first coupling capacitor C1 are connected, the control end of the first transistor T1 is connected to the scanning line G and the second end of the first coupling capacitor C1 The second terminal of the liquid crystal capacitor CLC and the second terminal of the storage capacitor Cs are both connected to the common electrode voltage.

Specifically, during the period t1-t2, the scan signal on the scan line G is transmitted to the control terminal of the first transistor T1, so that the first transistor T1 is turned on, and at the same time, the data signal on the data line D passes through the first The transistor T1 writes the set pixel voltage; however, at time t2, the polarity of the scan signal G1 on the scan line G changes, and the first coupling capacitor C1 generates the second voltage V2 to the coupling node A through the capacitive coupling effect, that is, The scanning signal G1 on the scanning line G changes from high level to low level. Since the second end of the first coupling capacitor C1 is connected to the scanning line G, the first end of the first coupling capacitor C1 is connected to the coupling node A, When the scanning signal G1 on the scanning line G changes from high level to low level, under the capacitive coupling effect, the voltage on the coupling node A also changes accordingly, causing the pixel voltage to be written to deviate from the pixel voltage originally written to The desired gray scale.

Please continue to refer to FIG. 1. Based on this, the pixel driving circuit provided by the present application further includes: a coupling suppression module 101 connected to the coupling node A, and connected to a polarity of the scanning signal G1 on the scanning line G The opposite inverted signal M is used to generate the first voltage to the coupling node A under the control of the inverted signal M.

Wherein, the polarities of the first voltage and the second voltage V2 are opposite, that is, the pixel circuit of the present application generates a first voltage having a polarity opposite to the second voltage V2 at time t1, thereby suppressing the first coupling capacitor The effect of the coupling effect of C1 on the written set voltage.

Please refer to FIG. 1 and FIG. 3, which is a first schematic circuit diagram of a pixel driving circuit provided by the present application. 1, the coupling suppression module 101 in the pixel driving circuit of the present application includes: a second transistor T2 and a second coupling capacitor C2; the first end, the second end, and the second end of the second transistor T2 The first end of the coupling capacitor C2 is connected to the coupling node A, and the control end of the second transistor T2 is connected to the inverted signal M and the second end of the second coupling capacitor C2. The first transistor T1 is an N-type transistor, and the second transistor T2 is an N-type transistor.

Specifically, referring to FIGS. 1, 2, and 3, during the period t1-t2, the high level of the scan signal G1 on the scan line G is transmitted to the control terminal of the first transistor T1, so that the first transistor T1 is turned on At the same time, the data signal on the data line D is written to the set pixel voltage through the first transistor T1; since the polarity of the inverted signal M is opposite to the scan signal G1, that is, at time t1-t2, the The low level of the phase signal M is transmitted to the control terminal of the second transistor T2, and the second transistor T2 is turned off, so as not to affect the normal writing of the pixel voltage.

At time t2, the polarity of the scanning signal G1 on the scanning line G changes, and the first coupling capacitor C1 generates the second voltage V2 to the coupling node through the capacitive coupling effect, that is, the scanning signal G1 on the scanning line G changes from high level Low level, because the second end of the first coupling capacitor C1 is connected to the scan line G, the first end of the first coupling capacitor C1 is connected to the coupling node A, the scan signal G1 on the scan line G changes from high level When it is low, under the capacitive coupling effect, the voltage on the coupling node A also changes accordingly; at time t2, the polarity of the inverted signal M changes, and the second coupling capacitor C2 generates the first voltage to the coupling node through the capacitive coupling effect A, because the polarity of the inverted signal M and the scan signal G1 are opposite, that is, when the scan signal G1 changes from high level to low level, the inverted signal M changes from low level to high level, because the second The second end of the coupling capacitor C2 is connected to the inverted signal M, and the first end of the second coupling capacitor C2 is connected to the coupling node A. When the inverted signal M changes from low level to high level, under the capacitive coupling effect, The voltage on the coupling node A also changes accordingly. Among them, the polarities of the first voltage and the second voltage V2 are opposite, and the influence of the coupling effect of the first coupling capacitor C1 on the written set voltage can be suppressed.

Further, in this application, the aspect ratio of the first transistor T1 and the aspect ratio of the second transistor T2 can be adjusted so that the capacitance value of the first coupling capacitor C1 is equal to the capacitance value of the second coupling capacitor C2, thereby making The magnitude of the first voltage and the second voltage V2 are equal.

Preferably, the aspect ratio of the second transistor T2 is less than the aspect ratio of the first transistor T1. Since the injected charge of the first transistor T1 is not fully injected into the coupling node A, the aspect ratio of the second transistor T2 is less than The aspect ratio of the first transistor T1 is to cancel or reduce the effect of charge injection.

Please refer to FIGS. 1 and 4. FIG. 4 is a second schematic circuit diagram of a pixel driving circuit provided by the present application. 1, the coupling suppression module 101 in the pixel driving circuit of the present application includes: a third transistor T3 and a third coupling C3 capacitor; the first end of the third transistor T3 is connected to the data line D, the The second terminal of the third transistor T3 and the first terminal of the third coupling capacitor C3 are both connected to the coupling node A, and the control terminal of the third transistor T3 is connected to the inverted signal M and the second terminal of the third coupling capacitor C3. The first transistor T1 is an N-type transistor, and the third transistor T3 is a P-type transistor.

Specifically, please refer to FIG. 1, FIG. 2, and FIG. 4, during the period t1-t2, the high level of the scanning signal G1 on the scanning line G is transmitted to the control terminal of the first transistor T1, so that the first transistor T1 is turned on At the same time, the data signal on the data line D is written to the set pixel voltage through the first transistor T1; since the polarity of the inverted signal M is opposite to the scan signal G1, that is, at time t1-t2, the The low level of the phase signal M is transmitted to the control terminal of the third transistor T3, and the third transistor T3 is also turned on, which does not affect the normal writing of the pixel voltage.

At time t2, the polarity of the scan signal G1 on the scan line G changes, and the first coupling capacitor C1 generates the second voltage V2 to the coupling node A through the capacitive coupling effect, that is, the scan signal G1 on the scan line G changes from high level Becomes low level, because the second end of the first coupling capacitor C1 is connected to the scan line G, the first end of the first coupling capacitor C1 is connected to the coupling node A, the scan signal G1 on the scan line G is changed from high level When it becomes low level, the voltage on the coupling node A also changes accordingly under the capacitive coupling effect; at time t2, the polarity of the inverted signal M changes, and the third coupling capacitor C3 generates the first voltage to the coupling through the capacitive coupling effect At the node A, since the polarity of the inverted signal M and the scan signal G1 are opposite, that is, when the scan signal G1 changes from high level to low level, the inverted signal M changes from low level to high level. The second end of the three coupling capacitors C3 is connected to the inverted signal M, and the first end of the third coupling capacitor C3 is connected to the coupling node A. When the inverted signal M changes from low level to high level, under the capacitive coupling effect , The voltage on the coupling node A also changes accordingly. Among them, the polarities of the first voltage and the second voltage V2 are opposite, and the influence of the coupling effect of the first coupling capacitor C1 on the written set voltage can be suppressed.

Further, in this application, the aspect ratio of the first transistor T1 and the aspect ratio of the third transistor T3 can be adjusted so that the capacitance value of the first coupling capacitor C1 is equal to the capacitance value of the third coupling capacitor C3, thereby making the The magnitude of the first voltage and the second voltage V2 are equal. Preferably, the aspect ratio of the third transistor T3 is equal to the aspect ratio of the first transistor T1.

The present application also provides a display panel, which includes the pixel driving circuit described above. For details, reference may be made to the foregoing, and details are not described herein.

The pixel driving circuit and the display panel provided by the present application are provided with a coupling suppression module, which is connected to the coupling node and connected with an inverted signal opposite to the polarity of the scanning signal on the scanning line. The first voltage is generated to the coupling node under the control of the phase signal to suppress the influence of the capacitive coupling effect on the pixel voltage, thereby improving the display performance of the display panel.

In summary, although the present application has been disclosed as preferred embodiments above, the above preferred embodiments are not intended to limit the present application. Those of ordinary skill in the art can make various changes without departing from the spirit and scope of the present application Such changes and retouching, so the scope of protection of this application shall be subject to the scope defined by the claims.

Claims

A pixel driving circuit includes:

A first transistor, a first end of the first transistor is connected to a data line, a second end of the first transistor is coupled to a coupling node, a first end of a liquid crystal capacitor, a first end of a storage capacitor, and a first coupling capacitor The first end is connected, the control end of the first transistor is connected to the scan line and the second end of the first coupling capacitor, the second end of the liquid crystal capacitor and the second end of the storage capacitor are both connected to the common Electrode voltage, the first coupling capacitor generates a second voltage to the coupling node through a capacitive coupling effect;

A coupling suppression module, the coupling suppression module is connected to the coupling node, and accesses an inverse signal opposite to the polarity of the scan signal on the scan line, and is used to generate a A voltage to the coupling node; the first voltage and the second voltage have opposite polarities.
The pixel driving circuit according to claim 1, wherein the coupling suppression module includes a second transistor and a second coupling capacitor;

The first end, the second end of the second transistor, and the first end of the second coupling capacitor are all connected to the coupling node, and the control end of the second transistor is connected to the inverted signal and the first The second end of the two coupling capacitors is connected.
The pixel driving circuit according to claim 2, wherein the first transistor is an N-type transistor and the second transistor is an N-type transistor.
The pixel driving circuit according to claim 3, wherein the aspect ratio of the first transistor and the aspect ratio of the second transistor can be adjusted so that the capacitance value of the first coupling capacitor is equal to the The capacitance value of the second coupling capacitor.
The pixel driving circuit according to claim 4, wherein the aspect ratio of the second transistor is smaller than the aspect ratio of the first transistor.
The pixel driving circuit according to claim 1, wherein the coupling suppression module includes a third transistor and a third coupling capacitor;

The first end of the third transistor is connected to the data line, the second end of the third transistor and the first end of the third coupling capacitor are both connected to the coupling node, and the The control terminal is connected to the inverted signal and the second terminal of the third coupling capacitor.
The pixel driving circuit according to claim 6, wherein the first transistor is an N-type transistor and the third transistor is a P-type transistor.
The pixel driving circuit according to claim 7, wherein the aspect ratio of the third transistor is equal to the aspect ratio of the first transistor.
A pixel driving circuit includes:

A first transistor, a first end of the first transistor is connected to a data line, a second end of the first transistor is coupled to a coupling node, a first end of a liquid crystal capacitor, a first end of a storage capacitor, and a first coupling capacitor The first end is connected, the control end of the first transistor is connected to the scan line and the second end of the first coupling capacitor, the second end of the liquid crystal capacitor and the second end of the storage capacitor are both connected to the common Electrode voltage

A coupling suppression module, the coupling suppression module is connected to the coupling node, and accesses an inverse signal opposite to the polarity of the scan signal on the scan line, and is used to generate a A voltage to the coupling node.
The pixel driving circuit according to claim 9, wherein the coupling suppression module includes a second transistor and a second coupling capacitor;

The first end, the second end of the second transistor, and the first end of the second coupling capacitor are all connected to the coupling node, and the control end of the second transistor is connected to the inverted signal and the first The second end of the two coupling capacitors is connected.
The pixel driving circuit according to claim 10, wherein the first transistor is an N-type transistor and the second transistor is an N-type transistor.
The pixel driving circuit according to claim 11, wherein the aspect ratio of the first transistor and the aspect ratio of the second transistor can be adjusted so that the capacitance value of the first coupling capacitor is equal to the The capacitance value of the second coupling capacitor.
The pixel driving circuit according to claim 12, wherein the aspect ratio of the second transistor is smaller than the aspect ratio of the first transistor.
The pixel driving circuit according to claim 9, wherein the coupling suppression module includes a third transistor and a third coupling capacitor;

The first end of the third transistor is connected to the data line, the second end of the third transistor and the first end of the third coupling capacitor are both connected to the coupling node, and the The control terminal is connected to the inverted signal and the second terminal of the third coupling capacitor.
The pixel driving circuit according to claim 14, wherein the first transistor is an N-type transistor and the third transistor is a P-type transistor.
The pixel driving circuit according to claim 15, wherein the aspect ratio of the third transistor is equal to the aspect ratio of the first transistor.
A display panel includes a pixel drive circuit. The pixel drive circuit includes:

A first transistor, a first end of the first transistor is connected to a data line, a second end of the first transistor is coupled to a coupling node, a first end of a liquid crystal capacitor, a first end of a storage capacitor, and a first coupling capacitor The first end is connected, the control end of the first transistor is connected to the scan line and the second end of the first coupling capacitor, the second end of the liquid crystal capacitor and the second end of the storage capacitor are both connected to the common Electrode voltage

A coupling suppression module, the coupling suppression module is connected to the coupling node, and accesses an inverse signal opposite to the polarity of the scan signal on the scan line, and is used to generate a A voltage to the coupling node.
The display panel according to claim 17, wherein the coupling suppression module includes a second transistor and a second coupling capacitor;

The first end, the second end of the second transistor, and the first end of the second coupling capacitor are all connected to the coupling node, and the control end of the second transistor is connected to the inverted signal and the first The second end of the two coupling capacitors is connected.
The display panel according to claim 1, wherein the coupling suppression module includes a third transistor and a third coupling capacitor;

The first end of the third transistor is connected to the data line, the second end of the third transistor and the first end of the third coupling capacitor are both connected to the coupling node, and the The control terminal is connected to the inverted signal and the second terminal of the third coupling capacitor.