WO2020073335A1 - 串联电路、电路板及计算设备 - Google Patents

串联电路、电路板及计算设备 Download PDF

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Publication number
WO2020073335A1
WO2020073335A1 PCT/CN2018/110141 CN2018110141W WO2020073335A1 WO 2020073335 A1 WO2020073335 A1 WO 2020073335A1 CN 2018110141 W CN2018110141 W CN 2018110141W WO 2020073335 A1 WO2020073335 A1 WO 2020073335A1
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Prior art keywords
chip
voltage
chipset
output terminal
voltage input
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PCT/CN2018/110141
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English (en)
French (fr)
Inventor
程文杰
邹桐
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北京比特大陆科技有限公司
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Application filed by 北京比特大陆科技有限公司 filed Critical 北京比特大陆科技有限公司
Priority to CN201880045865.6A priority Critical patent/CN110869877B/zh
Priority to PCT/CN2018/110141 priority patent/WO2020073335A1/zh
Publication of WO2020073335A1 publication Critical patent/WO2020073335A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/266—Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof

Definitions

  • This application relates to the technical field of integrated circuits, for example, to a series circuit, a circuit board, and a computing device.
  • the prior art has begun to adopt the power supply method of chip series connection on the printed circuit board (PCB) That is, multiple groups of chips are connected in series with each other to form a multi-level series voltage domain between the power input terminal and the ground terminal.
  • This series power supply architecture can effectively reduce the overall power supply current of the circuit, improve the power conversion efficiency, and can reduce the cost of some circuit devices in the power conversion.
  • Embodiments of the present disclosure provide a series circuit, a circuit board, and a computing device, which are used to realize the series power supply of two main operating voltages of a chip in a circuit board, and reduce the cost of a circuit device.
  • a first aspect of an embodiment of the present disclosure provides a series circuit, including:
  • At least two chipsets serially connected between chips in each of the chipsets;
  • the first voltage input terminal of the first chip is connected to the first voltage output terminal of the second chip adjacent to the same chip group, and the second chip of the first chip
  • the voltage input terminal is connected to the second voltage output terminal of the third chip in another chipset, and the first voltage output terminal and the second voltage output terminal jointly power the first chip.
  • a second aspect of an embodiment of the present disclosure provides a series circuit, including:
  • At least one first chip set and at least one second chip set serially connected between chips in each first chip set and each second chip set;
  • the first voltage input terminal of the i-th chip in the first chip group is connected to the voltage output terminal of the i + 1th chip in the same chip group, the first chip group
  • the first voltage input terminal of the jth chip in the second chip group is connected to the voltage output terminal of the j + 1th chip in the same chip group, the second chip group
  • a third aspect of the embodiments of the present disclosure provides a circuit board, including: the series circuit provided in the first aspect or the second aspect.
  • a fourth aspect of an embodiment of the present disclosure provides a circuit board, including: the series circuit provided in the second aspect above.
  • each first chip set is arranged on the left or right side of each second chip set; or,
  • Each first chip set and each second chip set are arranged alternately.
  • a fifth aspect of the embodiments of the present disclosure provides a computing device, including the series circuit provided in the first aspect or the second aspect.
  • Fig. 1 is a schematic diagram showing a first embodiment of a series circuit according to an exemplary embodiment
  • Fig. 2 is a schematic diagram of a second embodiment of a series circuit according to an exemplary embodiment
  • Fig. 3 is a schematic diagram of a third embodiment of a series circuit according to an exemplary embodiment
  • Fig. 4 is a schematic diagram of a fourth embodiment of a series circuit according to an exemplary embodiment
  • Fig. 5 is a schematic diagram of Embodiment 5 of a series circuit according to an exemplary embodiment
  • Fig. 6 is a schematic diagram of Embodiment 6 of a series circuit according to an exemplary embodiment
  • Fig. 7 is a schematic diagram of Embodiment 7 of a series circuit according to an exemplary embodiment
  • Fig. 8 is a schematic diagram of Embodiment 8 of a series circuit according to an exemplary embodiment
  • Fig. 9 is a schematic diagram of Embodiment 9 of a series circuit according to an exemplary embodiment
  • Fig. 10 is a schematic diagram showing a tenth embodiment of a series circuit according to an exemplary embodiment
  • FIG. 11 is a schematic diagram of Embodiment 1 of a circuit board according to an exemplary embodiment
  • FIG. 12 is a schematic diagram of Embodiment 2 of a circuit board according to an exemplary embodiment
  • FIG. 13 is a schematic diagram of Embodiment 3 of a circuit board according to an exemplary embodiment
  • Embodiment 4 of a circuit board according to an exemplary embodiment
  • Embodiment 15 is a schematic diagram of Embodiment 1 of a computing device according to an exemplary embodiment
  • Fig. 16 is a schematic diagram of a second embodiment of a computing device according to an exemplary embodiment.
  • FIG. 1 is a schematic diagram of a first embodiment of a series circuit according to an exemplary embodiment, including: at least two chipsets, serially connected between chips in each of the chipsets;
  • the first voltage input terminal of the first chip is connected to the first voltage output terminal of the second chip adjacent to the same chip group, and the second chip of the first chip
  • the voltage input terminal is connected to the second voltage output terminal of the third chip in another chipset, and the first voltage output terminal and the second voltage output terminal jointly power the first chip.
  • the first voltage input terminal and the second voltage input terminal of the chip are both the main working voltage input terminals of the chip, such as the core voltage and memory voltage of the chip, Such as 0.5V and 0.75V respectively.
  • each chip may also include two auxiliary voltages, such as 0.8V and 1.8V, which are not limited in this embodiment.
  • the first chip may be any chip in any chip set
  • the third chip may be any chip in another chip set that meets the following conditions: the voltage output terminal of the third chip (that is, the second voltage output terminal) Is higher than or equal to the voltage required by the second voltage input terminal of the first chip.
  • the second voltage input terminal is connected to the voltage output terminal of the fourth chip in chipset 2
  • the fourth chip in chipset 1 ie The voltage output terminal of the second chip shown in FIG. 1
  • the voltage output terminal of the fourth chip in the chipset 2 that is, the third chip shown in FIG.
  • One chip provides two main operating voltages.
  • the connection situation of other chips is similar to that of the first chip, which is not shown in FIG. 1.
  • the broken line part of the second voltage input terminal of each chip in FIG. 1 that does not show a connection relationship means that the second voltage input terminal of the chip can be connected to the voltage output terminal of one or more chips in another chipset, as long
  • the voltage at the voltage output terminal of the chip in the other chipset may be greater than or equal to the standard input voltage at the second voltage input terminal of the chip. Therefore, it is not shown in FIG. 1 that it is specifically connected to the voltage output terminal of the other chip.
  • the second voltage input terminal of each chip is shown by a broken line.
  • all the chips in the series circuit can be ASIC (Application Specific Integrated Circuit) chips, which can improve the data processing efficiency of the series circuit.
  • ASIC Application Specific Integrated Circuit
  • the second voltage input terminal of the first chip may be connected to the voltage output terminal of any third chip in the chipset 2, as long as the voltage of the voltage output terminal of the third chip can meet the voltage of the second voltage input terminal of the first chip The voltage requirement is sufficient, and this embodiment is not limited.
  • the second voltage output terminal of the third chip may be the same as the second voltage output terminal of the first chip
  • the voltage input terminal is directly connected, if the voltage of the second voltage output terminal of the third chip is higher than the standard input voltage required by the second voltage input terminal of the first chip, it can be connected to the second voltage of the first chip after being stepped down by a series load device Input connection.
  • the voltage output terminal (ie, the second voltage output terminal) of the third chip can simultaneously supply power to multiple chips of the chipset where the first chip is located.
  • the voltage output terminal of the third chip may be simultaneously connected to the second voltage input terminals of other chips in the chip group where the first chip is located, for example, the voltage output terminal of the third chip in chip group 2 in FIG. 1 may also be passed
  • the load device is connected to the second voltage input terminal of the first chip in the chipset 1 (that is, the lowest-level chip grounded) and the second chip (the chip connected in series with the aforementioned first chip) to supply power to it. Actual demand settings.
  • the two voltage input terminals of the last chip (that is, the highest-level chip) of each chipset are powered by a power source, for example, connected to the mains power through a DC-DC circuit or an AC-DC circuit.
  • the first chip of each chipset is directly or indirectly connected to ground.
  • the series circuit may further include chip set 3, chip set 4, and the like, that is, the series circuit may include more than two chip sets.
  • the two voltage input terminals of each chip of each chip group may be jointly powered by the voltage output terminals of adjacent chips in the same chip group and the voltage output terminals of chips in other chip groups.
  • which chip of which other chipsets is specifically powered may be set according to actual requirements, and this embodiment is not limited.
  • the second voltage input terminal of the first chip is The second voltage output terminal of the third chip in another chipset is connected, so that the first voltage output terminal of the second chip and the second voltage output terminal of the third chip jointly supply power to the first chip.
  • the series power supply of the chip with operating voltage can reduce the overall power supply current of the integrated circuit, improve the power conversion efficiency, and reduce the cost of the circuit device.
  • Fig. 2 is a schematic diagram of a second embodiment of a series circuit according to an exemplary embodiment.
  • the series circuit includes two chipsets, chip set 1 includes 5 chips, and chip set 2 includes 4 Chips, taking the chip in each chip set in Figure 2 close to the ground as the first chip, in order from bottom to top, in chip set 1, taking the third chip as the first chip as an example, the fourth The chip is the second chip, the first voltage input terminal of the third chip is connected to the voltage output terminal (ie the first voltage output terminal) of the fourth chip, and the second voltage input terminal of the third chip is connected to the chipset 2 The voltage output terminal (ie the second voltage output terminal) of the fourth chip (ie the third chip) is connected.
  • the first chip may also be the first chip in the chipset 1, then the second chip is the second chip in the chipset 1, and the third chip is the second chip in the chipset 2.
  • the first chip may also be the second chip in chipset 1, then the second chip is the third chip in chipset 1, and the third chip is the third chip in chipset 2.
  • the first chip may also be the first chip, the second chip or the third chip in the chip set 2, and the third chip is the chip in the chip set 1, which is specifically similar to the above and will not be repeated here.
  • the number of chips in each chip set is only an exemplary description.
  • Chip set 1 may include m chips, and chip set 2 may include n chips. Both m and n are integers greater than or equal to 2.
  • the chipset 1 may include 11 chips
  • the chipset 2 may include 10 chips
  • the chipset 1 may include 12 chips
  • the chipset 2 may include 12 chips, and so on, which may be set according to actual needs.
  • the voltage output terminal of the first chip of the chipset 1 may be connected to ground, and the two voltage input terminals of the fifth chip of the chipset 1 are connected to the power supply.
  • the first chip of chipset 2 is connected to ground through a load device (such as a Schottky diode, resistor, diode, buck circuit, DC-DC circuit, clamp circuit, etc.).
  • the two voltage input terminals of the fourth chip of chipset 2 are connected to the power supply. If the power supply voltage is higher than the voltage required by the voltage input terminal of the chip, the voltage input terminal of the chip can be connected to the voltage input terminal of the chip after the voltage is reduced.
  • the step-down method is the prior art, and will not be described here.
  • the series circuit of this embodiment may include at least one chip set 1 and at least one chip set 2.
  • it may include two chipsets 1, one chipset 2, or one chipset 1, two chipsets 2, or three chipsets 1, three chipsets 2, etc., which can be set according to actual needs, This embodiment is not limited.
  • the output voltage of the second voltage output terminal of the third chip is equal to the standard input voltage of the second voltage input terminal of the first chip, therefore, the second voltage output terminal of the third chip can directly The voltage input is connected.
  • the cost of the circuit device can be further reduced.
  • FIG. 3 is a schematic diagram of Embodiment 3 of a series circuit according to an exemplary embodiment.
  • the series circuit includes two chipsets.
  • the first chip in the chip set 1 the second voltage
  • the input terminal is connected to the second voltage output terminal of the third chip through a step-down device, that is, when the output voltage of the second voltage output terminal of the third chip is higher than the standard input voltage of the second voltage input terminal, the The second voltage output terminal may be connected to the second voltage input terminal of the first chip through a voltage-reducing device, so that the voltage output to the second voltage input terminal is equal to the standard input voltage.
  • FIG. 3 only exemplarily shows the connection relationship of a part of the voltage-reducing devices. Specifically, which voltage-reducing devices need to be connected can be set according to actual requirements, and this embodiment is not limited.
  • FIG. 4 is a schematic diagram of Embodiment 4 of a series circuit according to an exemplary embodiment.
  • the series circuit includes two chipsets.
  • the third chip For the third chip in the chipset 2, the third chip ’s
  • the second voltage output terminal simultaneously supplies power to other chips in the chipset 1. Since the voltage of the second voltage output terminal of the third chip is equal to the voltage of the second voltage input terminal of the first chip, the voltage of the second voltage output terminal of the third chip must be It is higher than the voltage of the second voltage input terminal of the first chip and the second chip in the chipset 1, so it can be connected to the second voltage input terminal of the first chip and the second chip in the chipset 1 through the buck device .
  • the second voltage output terminal of the third chip simultaneously supplies power to other chips in the chipset where the first chip is located. That is, the second voltage output terminal of the third chip may be simultaneously connected to the second voltage input terminals of other chips in the chip group where the first chip is located.
  • FIG. 4 only the connection relationship of some of the chips is shown by way of example, and the power supply modes of other chips are similar to those shown, which are not shown in FIG. 4.
  • FIG. 5 is a schematic diagram of Embodiment 5 of a series circuit according to an exemplary embodiment.
  • the series circuit further includes a first voltage clamping circuit and a second voltage clamping circuit, and the first voltage clamping circuit and The second voltage clamping circuit is connected between the power supply and ground.
  • the first voltage clamping circuit includes at least one first output terminal, the first output terminals are respectively connected to the first voltage input terminals of some chips of the chipset where the first chip is located, and the second voltage The clamping circuit includes at least one second output terminal, and the second output terminals are respectively connected to the first voltage input terminals of some chips of the chipset where the third chip is located.
  • the voltage clamping method is: clamping once every two chips. In practical applications, it can also be clamped every multiple chips. Alternatively, the voltage of the first voltage input terminal of each chip is clamped to improve the safety of the chip and ensure the normal operation of the circuit board.
  • Each chip in addition to setting a voltage clamping circuit for a group of chips, and performing voltage clamping on the first voltage input terminal of each chip through multiple output terminals of the one voltage clamping circuit, Each chip is provided with a voltage clamping circuit to clamp the voltage of the first voltage input terminal of each chip, thereby ensuring that each chip can work at the target operating voltage, thereby improving the applicability of the series circuit and the safety of the chip.
  • the specific circuit of the voltage clamping circuit may be any circuit that can be implemented in the prior art, and details are not described in this embodiment.
  • FIG. 6 is a schematic diagram of Embodiment 6 of a series circuit according to an exemplary embodiment.
  • the transmission direction of the control signal of each chip in the series circuit is: from the chipset where the first chip is located
  • the k-th chip of the third chip is transferred to the k-th chip in the chip set of the third chip, and the k-th chip in the chip set of the third chip is transferred to the k-th chip of the chipset of the first chip +1 chips
  • k 1, 2,..., M
  • m is the number of chips in the chip group where the first chip is located, and the first chip in each chip group is a chip close to the ground.
  • the control signal may refer to a signal of the control chip such as a reset signal, a close signal, and an open signal. Of course, it may also be other signals, as long as it is a control signal sent to each chip through a controller or a control chip, etc., which is not limited in any way.
  • the control signal is a reset signal.
  • the first chip in the chipset 1 receives the reset signal, it can perform a reset action first, and then pass it to the first chip in the chipset 2, or it can be passed to the chipset 2 first.
  • the reset operation is performed, or reset and transfer can be performed at the same time. It can be set according to actual needs.
  • Fig. 7 is a schematic diagram of Embodiment 7 of a series circuit according to an exemplary embodiment. As shown in Fig. 7, the series circuit includes:
  • At least one first chip set and at least one second chip set serially connected between chips in each first chip set and each second chip set;
  • the first voltage input terminal of the i-th chip in the first chip group is connected to the voltage output terminal of the i + 1th chip in the same chip group, the first chip group
  • the first voltage input terminal of the jth chip in the second chip group is connected to the voltage output terminal of the j + 1th chip in the same chip group, the second chip group
  • the first voltage input terminal of the first chip and the voltage output of the second chip Is connected to the terminal, and the second voltage input terminal of the first chip is connected to the voltage output terminal of the second chip in the second chip group.
  • the first voltage input terminal of the ith chip in the first chipset is connected to the voltage output terminal of the i + 1th chip, and the second voltage input terminal of the ith chip is connected to the i + 1th chip in the second chipset
  • the voltage output of each chip is connected.
  • the first voltage input terminal of the first chip in the second chipset is connected to the voltage output terminal of the second chip, and the second voltage input terminal of the first chip is connected to the first chip group
  • the voltage output of the third chip is connected.
  • the first voltage input terminal of the jth chip in the second chipset is connected to the voltage output terminal of the j + 1th chip in the same chipset, and the second voltage of the jth chip in the second chipset
  • the input terminal is connected to the voltage output terminal of the j + 2th chip in at least one first chipset.
  • each first chipset may be connected in parallel, and each second chipset may be connected in parallel.
  • each first chip set and a second chip set may form a series circuit shown in FIG. 7.
  • multiple first chipsets may be paired with the same second chipset group at the same time, or each first chipset may be paired with a different second chipset group.
  • there are 4 first chipsets and 4 second chipsets which can be divided into 4 pairs of series circuits as shown in Figure 7.
  • there are 4 first chipsets and one second chipset then 4 first chipsets
  • Each end of the corresponding chip in the chip set is connected in parallel, that is, each first chip set is connected to the same second chip set into a series circuit as shown in FIG. 7.
  • the specifics can be set according to actual needs, and will not be repeated here.
  • each second chipset includes n chips.
  • the voltage output terminal of the first chip is connected to ground; the two voltage input terminals of the mth chip are connected to the power supply.
  • the voltage output terminal of the first chip is connected to the ground through the load device; the two voltage input terminals of the nth chip are connected to the power supply.
  • the second voltage input terminal of each chip from the nth chip to the m-1th chip is connected to the power supply.
  • the second voltage input terminal of the n-1th chip is connected to the power supply.
  • the second voltage input terminal of each chip from the mth chip to the n-1th chip is connected to the power supply.
  • connection with the power supply may include direct connection or connection through a series step-down device.
  • the step-down device can be a Schottky diode, a resistor, a buck circuit, a DC-DC circuit, a clamping circuit, etc., which can be set according to actual needs.
  • the specific step-down method is the prior art, and will not be repeated here.
  • the load device may be a Schottky diode, a resistor, and so on.
  • FIG. 8 is a schematic diagram of Embodiment 8 of a series circuit according to an exemplary embodiment.
  • the two main operating voltages required by each chip are: core voltage 0.5V, and The memory voltage is 0.75V.
  • the voltage output of the first chip in the first chip set on the left is grounded at 0V, the first voltage input of the first chip on the left requires 0.5V, the second voltage input requires 0.75V, and the first chip on the left
  • the voltage input requires 1V, the second voltage input requires 1.25V, the third chip on the left requires 1.5V and 1.75V, the fourth chip on the left 2V and 2.25V, and so on, the m chip on the left has two The voltage input requires (m / 2) V and (m / 2 + 0.25) V, respectively.
  • the first chip of the second chip set on the right can be connected to ground through a load device (Schottky diode, resistor, etc.), and the voltage output terminal of the first chip is positioned to 0.25V, then the first chip of the first chip
  • the voltage input requires 0.75V and the second voltage input requires 1V.
  • the first and second voltage inputs of the second chip on the right are 1.25V and 1.5V, and the third chip on the right is 1.75V and 2V.
  • the fourth chip on the right is 2.25V and 2.5V, and the nth chip on the right requires (0.5n + 0.25) V and (0.5n + 0.5) V.
  • the voltage output voltage of some chips on the right is exactly equal to the voltage of the second voltage input terminal of some chips on the left
  • the voltage output terminal of the left chip is exactly equal to the voltage of some chips on the right.
  • the voltage of the second voltage input terminal therefore, the power supply of the second voltage input terminal can be performed crosswise. In this way, the entire series circuit only needs to have two power inputs, one for 3V and one for 2.75V.
  • the voltage of 3V can come from the city power. After AC-DC conversion, it becomes 12V DC voltage, and then through DC-DC conversion, it becomes 3V voltage and 2.75V voltage.
  • the 2.75V voltage is directly connected to the first voltage input terminal of the fifth chip in the second chip group on the right and the second voltage input terminal of the fifth chip in the first chip group on the left, and passes through a buck device (such as SCHOTT Base diode, resistor, etc.) 2.5V is connected to the first voltage input terminal of the fifth chip in the first chip set on the left; the 3V voltage is directly connected to the second voltage input terminal of the fifth chip in the second chip set on the right.
  • a buck device such as SCHOTT Base diode, resistor, etc.
  • the voltage of the power input and the voltage of the voltage output terminal of the first chip of the second chipset can be set according to actual requirements.
  • the number of chips included in each chip set is different, which also results in different voltages input from the electric power supply, which can be set according to actual needs.
  • the series circuit shown in FIG. 8 includes 11 chips in the first chip set and 10 chips in the second chip set, the two voltage input terminals of the 11th chip in the first chip set require 6V respectively And 6.25V, the two voltage input terminals of the 10th chip in the second chipset require 5.75V and 6V, respectively. The details are not repeated here.
  • the main power supply path of the first chip set is the first voltage input terminal of each chip from top to bottom, and the main power supply path of the second chip set on the right is the first voltage input terminal of each chip from top to bottom.
  • a load circuit or voltage clamping circuit needs to be added, such as a Schottky diode, resistor, diode, op amp + MOS tube, etc. Wait, release excess current.
  • the voltage of the second voltage input terminal of each chip is provided by crossing the first chipset and the second chipset.
  • the whole circuit board only needs two voltages input from the external power supply, assisted by a buck device and a load device, namely The two main working voltage requirements of each chip in the circuit board can be realized, and the cost of circuit devices can be effectively reduced.
  • the series circuit may further include a first auxiliary power supply unit group and a second auxiliary power supply unit group, where the first auxiliary power supply unit group is responsible for providing two auxiliary operating voltages for each chip of the first chipset, the first The two auxiliary power supply unit groups are responsible for providing two auxiliary operating voltages for each chip of the second chipset.
  • each chip requires two auxiliary operating voltages of 0.8V and 1.8V, respectively.
  • the specific power supply mode of the auxiliary operating voltage may be the same as or similar to the power supply mode in the prior art, and details are not described herein again.
  • Fig. 9 is a schematic diagram of Embodiment 9 of a series circuit according to an exemplary embodiment.
  • the series circuit includes 2 first chip sets and 1 second chip set. Among them, the two first chipsets are connected in parallel.
  • Fig. 10 is a schematic diagram of a tenth embodiment of a series circuit according to an exemplary embodiment. As shown in Fig. 10, the series circuit includes one first chip set and two second chip sets. Among them, two second chipsets are connected in parallel.
  • the second voltage input terminals of the chips in the first chipset may be respectively connected to the voltage output terminals of the chips in different second chipsets.
  • the second voltage input terminal of the first chip in the first chipset is connected to the voltage output terminal of the second chip in a second chipset
  • the second voltage input terminal of the second chip in the first chipset Connect to the voltage output of the third chip in another second chipset.
  • more first chipsets and more second chipsets may also be included, and the specific connection manners are similar to those in FIG. 9 and FIG. 10, and are not repeated here.
  • FIG. 11 is a schematic diagram of Embodiment 1 of a circuit board according to an exemplary embodiment.
  • the circuit board includes: the series circuit provided in any of the foregoing embodiments. The specific connection relationship of the series circuit has been described in detail in the above embodiment, and will not be repeated in this embodiment.
  • the circuit board may also be provided with a signal interface to achieve interaction with other circuit boards, control boards, controllers, or other control devices.
  • a power interface and other circuits can also be provided on the circuit board, which will not be repeated here.
  • the circuit board may be a main board, a computing board, a board card, etc. in the computing device, which is not limited in any way.
  • FIG. 12 is a schematic diagram of Embodiment 2 of a circuit board according to an exemplary embodiment.
  • the series circuit in the circuit board includes at least one first chip set and at least one second chip set, to Including 3 first chipsets and 3 second chipsets as an example, each first chipset is arranged on the left side of each second chipset.
  • the specific connection relationship of the series circuit has been described in detail in the above embodiment, and will not be repeated in this embodiment.
  • the number of the first chipset and the second chipset may be the same or different, for example, may include 4 first chipsets and 5 second chipsets, or include 3 first chipsets and 2 second chipsets
  • the chipset, etc. are not limited in this embodiment.
  • the number of the first chip set and the second chip set is the same, the current balance is better.
  • FIG. 13 is a schematic diagram of Embodiment 3 of a circuit board according to an exemplary embodiment. As shown in FIG. 13, in the circuit board, each first chip group is arranged on the right side of each second chip group. The specific connection relationship of the series circuit has been described in detail in the above embodiment, and will not be repeated in this embodiment.
  • each first chip set may also be arranged on the upper side or the lower side of each second chip set.
  • each first chip group may also be arranged on the first side of the circuit board, and each second chip group may also be arranged on the second side of the circuit board, which is not limited in any way.
  • FIG. 14 is a schematic diagram of Embodiment 4 of a circuit board according to an exemplary embodiment. As shown in FIG. 14, in the circuit board, each first chip group and each second chip group are arranged alternately. The specific connection relationship of the series circuit has been described in detail in the above embodiment, and will not be repeated in this embodiment. It should be noted that the phase-to-phase arrangement here can be strictly a first chipset, a second chipset, another first chipset, and then a second chipset, and so on, or they can be irregular phase-to-phase For example, as shown in FIG.
  • the first chip set, the second chip set, the first chip set, the second chip set, and the second chip set may also be two first chip sets and two second chips Group, two first chipsets, two second chipsets, etc. That is, the chip sets can be arranged in an arbitrary arrangement on the circuit board according to actual needs.
  • the number of the first chip set and the second chip set may be set to be the same or different, and the number of chips connected in series in each chip set may also be set to be the same or different. limited.
  • FIG. 15 is a schematic diagram of Embodiment 1 of a computing device according to an exemplary embodiment. As shown in FIG. 15, the computing device includes the series circuit provided in any of the foregoing embodiments.
  • the computing device may generally be a corresponding computer, supercomputer, AI (Artificial Intelligence) processing device, server, etc., as long as it can implement data calculation and processing, no limitation is made on this.
  • AI Artificial Intelligence
  • FIG. 16 is a schematic diagram of Embodiment 2 of a computing device according to an exemplary embodiment. As shown in FIG. 16, the computing device includes the circuit board provided in any of the foregoing embodiments.
  • the computing device may include at least one circuit board.
  • each circuit board may be connected in parallel with each other.
  • the computing device may further include a corresponding control board, and a signal connection between the control board and each circuit board is used to deliver control signals to each chip on the circuit board.
  • each chip on the circuit board, each circuit board in the computing device, and the control board can be detachable modules, and when some of the components fail, they can be detached separately. Improves the practicality and maintainability of computing equipment and control boards.
  • a corresponding chute may be provided on the chassis of the computing device to place each circuit board or control board, which is not limited in any way.
  • first, second, etc. may be used in this application to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another.
  • the first element can be called the second element, and likewise, the second element can be called the first element, as long as all occurrences of the "first element” are consistently renamed and all occurrences of The “second component” can be renamed consistently.
  • the first element and the second element are both elements, but they may not be the same element.

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Abstract

一种串联电路、电路板及计算设备，该串联电路包括：至少两个芯片组，在每个所述芯片组中芯片之间串行连接；针对每个芯片组中的第一芯片，所述第一芯片的第一电压输入端与同芯片组中与其相邻的第二芯片的第一电压输出端连接，所述第一芯片的第二电压输入端与另一芯片组中的第三芯片的第二电压输出端连接，由所述第一电压输出端和所述第二电压输出端共同为所述第一芯片供电。该串联电路实现了具有两个主工作电压的芯片的串联供电，可以降低电路器件成本。

Description

串联电路、电路板及计算设备 技术领域
本申请涉及集成电路技术领域，例如涉及一种串联电路、电路板及计算设备。
背景技术
随着云计算和服务器级别的大规模计算持续快速发展，以及全球对环境保护和节能意识的提升，能源使用效率变成了在硬件计算体系里一个非常重要的指标。目前基于大规模集成电路的计算设备采用传统并联电源架构存在电流过大、能源使用效率低等显著缺点，并且增加了芯片电路设计的要求和生产设计的成本。随着半导体工艺的发展，芯片的工作电源电压越来越低，工作电流越来越大，为了最大化电源的转换效率，现有技术在印刷电路板(PCB)上开始采取芯片串联的供电方式，即多组芯片采用相互串联的方式，在电源输入端和接地端之间形成多级串联的电压域。这种串联供电架构可以有效地减小电路整体供电电流，提高电源转换效率，并且可以降低电源转换部分电路器件的成本。
但是，本公开的发明人发现，在计算机、服务器、显卡或其他集成计算阵列中，在基于CPU/GPU的计算架构下使用这种串联供电架构还存在一些难点。现有的计算架构下，有两个不同电压的主电压源都存在较大的电流，例如VDD和VDDQ，现有的串联供电架构无论是以VDD还是VDDQ作为电源主路径，都无法同时对两个电源路径进行串联供电。这是因为VDD和VDDQ存在固定的电压差，如果两个电压在某一级上电压可以协同，那就意味着在这一级的上一级或下一级两者的电压无法正好配合给芯片供电。因此，如何减少集成电路整体的供电电流，提升电源转换效率，降低电路器件成本，成为亟需解决的技术问题。
上述背景技术内容仅用于帮助理解本申请，而并不代表承认或认可所提及的任何内容属于相对于本申请的公知常识的一部分。
发明内容
本公开实施例提供一种串联电路、电路板及计算设备，用于实现电路板中芯片的两个主工作电压的串联供电，降低电路器件成本。
本公开实施例的第一方面提供了一种串联电路，包括：
至少两个芯片组，在每个所述芯片组中芯片之间串行连接；
针对每个芯片组中的第一芯片，所述第一芯片的第一电压输入端与同芯片组中与其相邻的第二芯片的第一电压输出端连接，所述第一芯片的第二电压输入端与另一芯片组中的第三芯片的第二电压输出端连接，由所述第一电压输出端和所述第二电压输出端共同为所述第一芯片供电。
本公开实施例的第二个方面提供一种串联电路，包括：
至少一个第一芯片组及至少一个第二芯片组，在每个第一芯片组及每个第二芯片组中芯片之间串行连接；
针对每个第一芯片组，所述第一芯片组中的第i个芯片的第一电压输入端与同芯片组中的第i+1个芯片的电压输出端连接，所述第一芯片组中的第i个芯片的第二电压输入端与至少一个第二芯片组中的第i+1个芯片的电压输出端连接，i＝1,2,…,m，m为第一芯片组中芯片的个数；
针对每个第二芯片组，所述第二芯片组中的第j个芯片的第一电压输入端与同芯片组中的第j+1个芯片的电压输出端连接，所述第二芯片组中的第j个芯片的第二电压输入端与至少一个第一芯片组中的第j+2个芯片的电压输出端连接，j＝1,2,…,n，n为第二芯片组中芯片的个数。
本公开实施例第三个方面提供了一种电路板，包括：上述第一个方面或第二个方面提供的串联电路。
本公开实施例第四个方面提供了一种电路板，包括：上述第二个方面提供的串联电路。
其中，各第一芯片组均排列在各第二芯片组的左侧或右侧；或者，
各第一芯片组与各第二芯片组相间排列。
本公开实施例的第五个方面提供了一种计算设备，包括上述第一个方面或第二个方面提供的串联电路。
附图说明
一个或多个实施例通过与之对应的附图进行示例性说明，这些示例性说明和附图并不构成对实施例的限定，附图中具有相同参考数字标号的元件表示为类似的元件，附图不构成比例限制，并且其中：
图1是根据一示例性实施例示出的一种串联电路实施例一的示意图；
图2是根据一示例性实施例示出的一种串联电路实施例二的示意图；
图3是根据一示例性实施例示出的一种串联电路实施例三的示意图；
图4是根据一示例性实施例示出的一种串联电路实施例四的示意图；
图5是根据一示例性实施例示出的一种串联电路实施例五的示意图；
图6是根据一示例性实施例示出的一种串联电路实施例六的示意图；
图7是根据一示例性实施例示出的一种串联电路实施例七的示意图；
图8是根据一示例性实施例示出的一种串联电路实施例八的示意图；
图9是根据一示例性实施例示出的一种串联电路实施例九的示意图；
图10是根据一示例性实施例示出的一种串联电路实施例十的示意图；
图11是根据一示例性实施例示出的一种电路板实施例一的示意图；
图12是根据一示例性实施例示出的一种电路板实施例二的示意图；
图13是根据一示例性实施例示出的一种电路板实施例三的示意图；
图14是根据一示例性实施例示出的一种电路板实施例四的示意图；
图15是根据一示例性实施例示出的一种计算设备实施例一的示意图；
图16是根据一示例性实施例示出的一种计算设备实施例二的示意图。
具体实施方式
为了能够更加详尽地了解本公开实施例的特点与技术内容，下面结合附图对本公开实施例的实现进行详细阐述，所附附图仅供参考说明之用，并非用来限定本公开实施例。在以下的技术描述中，为方便解释起见，通过多个细节以提供对所披露实施例的充分理解。然而，在没有这些细节的情况下，一个或多个实施例仍然可以实施。在其它情况下，为简化附图，熟知的结构和装置可以简化展示。
本公开实施例提供了一种串联电路，该串联电路可以设置在电路板中。参 见图1，图1是根据一示例性实施例示出的一种串联电路实施例一的示意图，包括：至少两个芯片组，在每个所述芯片组中芯片之间串行连接；
针对每个芯片组中的第一芯片，所述第一芯片的第一电压输入端与同芯片组中与其相邻的第二芯片的第一电压输出端连接，所述第一芯片的第二电压输入端与另一芯片组中的第三芯片的第二电压输出端连接，由所述第一电压输出端和所述第二电压输出端共同为所述第一芯片供电。
需要说明的是，本实施例中，芯片的第一电压输入端以及第二电压输入端均为芯片的主工作电压输入端，如可为芯片的Core(内核)电压以及Memory(存储)电压，如分别可为0.5V以及0.75V。除此之外，每一个芯片还可包括两个辅助电压，如0.8V以及1.8V，本实施例对此不作任何限定。
其中，第一芯片可以是任意一个芯片组中的任意一个芯片，第三芯片可以是另一芯片组中任意一个满足以下条件的芯片：第三芯片的电压输出端(即第二电压输出端)的电压高于或等于第一芯片的第二电压输入端需要的电压。以芯片组1中第3个芯片作为第一芯片为例，其第二电压输入端与芯片组2中的第4个芯片的电压输出端连接，由芯片组1中的第4个芯片(即图1中所示的第二芯片)的电压输出端和芯片组2中的第4个芯片(即图1中所示的第三芯片)的电压输出端共同为第一芯片供电，从而为第一芯片提供两个主工作电压。其他芯片的连接情况与第一芯片类似，图1中未示出。
关于图1中各芯片的第二电压输入端未示出连接关系的折线部分，是表示该芯片的第二电压输入端可以连接另一芯片组中的一个或多个芯片的电压输出端，只要另一芯片组中的芯片的电压输出端的电压大于或等于该芯片的第二电压输入端的标准输入电压即可，因而在图1中没有体现具体连接到另一芯片的电压输出端上，而仅用折线显示出了各芯片的第二电压输入端。
本实施例中，串联电路中的芯片均可为ASIC(Application Specific Integrated Circuit，应用专用集成电路)芯片，从而能够提升串联电路的数据处理效率。
本实施例中，第一芯片的第二电压输入端可以与芯片组2中任意第三芯片的电压输出端连接，只要第三芯片的电压输出端的电压能够满足第一芯片的第二电压输入端的电压需求即可，本实施例不做限定。
示例性的，若第三芯片的第二电压输出端电压与第一芯片的第二电压输入端需要的标准输入电压相等，则第三芯片的第二电压输出端可以与第一芯片的 第二电压输入端直接连接，若第三芯片的第二电压输出端电压高于第一芯片的第二电压输入端需要的标准输入电压，可以通过串联负载器件降压后与第一芯片的第二电压输入端连接。
在一些实施方式中，第三芯片的电压输出端(即第二电压输出端)可以同时为第一芯片所在芯片组的多个芯片供电。具体的，第三芯片的电压输出端可以同时与第一芯片所在芯片组中的其他芯片的第二电压输入端连接，比如图1中芯片组2中的第三芯片的电压输出端还可以通过负载器件与芯片组1中第1个芯片(即接地的最低级芯片)及第2个芯片(与前述第1个芯片串联的芯片)的第二电压输入端连接，为其供电，具体可以根据实际需求设置。
在一些实施方式中，每个芯片组的最后一个芯片(即最高级芯片)的两个电压输入端由电源供电，比如通过DC-DC电路、AC-DC电路与市电连接。每个芯片组的第1个芯片直接或间接与地连接。
在一些实施方式中，该串联电路还可以包括芯片组3、芯片组4等等，即该串联电路可以包括两个以上的芯片组。其中每个芯片组的每个芯片的两个电压输入端都可以是由同芯片组中相邻芯片的电压输出端和其他芯片组中的芯片的电压输出端共同供电。对于需要其他芯片组中芯片供电的情况，具体由哪个其他芯片组的哪个芯片供电可以根据实际需求设置，本实施例不做限定。
本实施例，通过将一芯片组中的第一芯片的第一电压输入端与同芯片组中与其相邻的第二芯片的第一电压输出端连接，第一芯片的第二电压输入端与另一芯片组中第三芯片的第二电压输出端连接，从而由第二芯片的第一电压输出端和第三芯片的第二电压输出端共同为第一芯片供电，实现了具有两个主工作电压的芯片的串联供电，可以减少集成电路整体的供电电流，提升电源转换效率，降低电路器件成本。
以下结合具体的实施例对上述实施例一的技术方案进行扩展和优化。
图2是根据一示例性实施例示出的一种串联电路实施例二的示意图，如图2所示，该串联电路包括两个芯片组，芯片组1包括了5个芯片，芯片组2包括4个芯片，以图2中每个芯片组中靠近地的芯片为第1个芯片，从下到上依次排序，在芯片组1中，以第3个芯片作为第一芯片为例，第4个芯片为第二芯片，第3个芯片的第一电压输入端与第4个芯片的电压输出端(即第一电压输出端)连接，第3个芯片的第二电压输入端与芯片组2中第4个芯片(即第三芯片) 的电压输出端(即第二电压输出端)连接。这里第一芯片还可以是芯片组1中的第1个芯片，则第二芯片为芯片组1中的第2个芯片，第三芯片为芯片组2中的第2个芯片。第一芯片还可以是芯片组1中第2个芯片，则第二芯片为芯片组1中的第3个芯片，第三芯片为芯片组2中的第3个芯片。第一芯片还可以是芯片组2中的第1个芯片、第2个芯片或第3个芯片等，则第三芯片为芯片组1中的芯片，具体与上述相似，在此不再赘述。这里每个芯片组中芯片的个数仅为示例性说明，芯片组1可以包括m个芯片，芯片组2可以包括n个芯片，m和n均为大于或等于2的整数。比如芯片组1可以包括11个芯片，芯片组2可以包括10个芯片，再比如芯片组1可以包括12个芯片，芯片组2包括12个芯片等等，具体可以根据实际需求进行设置。
在图2中，芯片组1的第1个芯片的电压输出端可以与地连接，芯片组1的第5个芯片的两个电压输入端与电源连接。芯片组2的第1个芯片通过负载器件(比如肖特基二极管、电阻、二极管、buck电路、DC-DC电路、钳制电路等)与地连接。芯片组2的第4个芯片的两个电压输入端与电源连接，若电源电压高于芯片的电压输入端需要的电压时，可以通过降压器件降压后与芯片的电压输入端连接，具体降压方式为现有技术，在此不再赘述。
在一些实施方式中，本实施例的串联电路可以包括至少一个上述芯片组1以及至少一个上述芯片组2。比如可以包括两个芯片组1、一个芯片组2，或者包括一个芯片组1、两个芯片组2，或者包括3个芯片组1、3个芯片组2等等，具体可以根据实际需求设置，本实施例不做限定。
在图2中，第三芯片的第二电压输出端的输出电压等于第一芯片的第二电压输入端的标准输入电压，因此，第三芯片的第二电压输出端可以直接与第一芯片的第二电压输入端连接。
本实施例，通过各芯片组之间，芯片一对一提供另一电压输入端的输入电压，可以进一步降低电路器件成本。
图3是根据一示例性实施例示出的一种串联电路实施例三的示意图，如图3所示，该串联电路包括两个芯片组，对于芯片组1中的第一芯片，其第二电压输入端通过降压器件与第三芯片的第二电压输出端连接，即，当第三芯片的第二电压输出端的输出电压高于所述第二电压输入端的标准输入电压时，第三芯片的第二电压输出端可以通过降压器件与第一芯片的第二电压输入端连接，以 使输出到所述第二电压输入端的电压等于所述标准输入电压。图3中仅示例性的示出了部分采用降压器件的连接关系，具体哪些需要连接降压器件可以根据实际需求设置，本实施例不做限定。
图4是根据一示例性实施例示出的一种串联电路实施例四的示意图，如图4所示，该串联电路包括两个芯片组，对于芯片组2中的第三芯片，第三芯片的第二电压输出端同时为芯片组1中的其他芯片供电，由于第三芯片的第二电压输出端与第一芯片的第二电压输入端电压相等，第三芯片的第二电压输出端的电压必然高于芯片组1中第1个芯片及第2个芯片的第二电压输入端的电压，因此可以通过降压器件与芯片组1中第1个芯片及第2个芯片的第二电压输入端连接。即第三芯片的第二电压输出端同时为所述第一芯片所在芯片组中的其他芯片供电。也即第三芯片的第二电压输出端可以同时与第一芯片所在芯片组中的其他芯片的第二电压输入端相连。图4中，仅示例性地示出了其中部分芯片的连接关系，其他芯片的供电方式与已示出的相似，在图4中未示出。
图5是根据一示例性实施例示出的一种串联电路实施例五的示意图，如图5所示，该串联电路还包括第一电压钳制电路及第二电压钳制电路，第一电压钳制电路及第二电压钳制电路连接在电源和地之间。
其中，所述第一电压钳制电路包括至少一个第一输出端，所述第一输出端分别连接至所述第一芯片所在芯片组的某些芯片的第一电压输入端，所述第二电压钳制电路包括至少一个第二输出端，所述第二输出端分别连接至所述第三芯片所在芯片组的某些芯片的第一电压输入端。
当然，在图5中，对电压的钳制方式为：每隔两个芯片钳制一次。在实际应用中，还可每隔多个芯片钳制一次。或者，对每一个芯片的第一电压输入端的电压进行钳制，以提升芯片的安全性，保证电路板的正常运行。
再者，本实施例中，除了可针对一组芯片设置一个电压钳制电路，并通过这一个电压钳制电路的多个输出端进行各芯片的第一电压输入端的电压钳制之外，还可针对每一个芯片设置一个电压钳制电路，以分别对各芯片的第一电压输入端的电压进行钳制，从而保证每一个芯片都可以工作在目标工作电压，提升了串联电路的可适用性和芯片的安全性。
电压钳制电路的具体电路可以为现有技术中任意可实施的电路，本实施例不再赘述。
本实施例，通过为芯片组设置电压钳制电路可以为芯片组中相邻芯片之间的电压输入端提供相应的固定电压，提高串联电路的稳定性。
图6是根据一示例性实施例示出的一种串联电路实施例六的示意图，如图6所示，该串联电路中各芯片的控制信号的传递方向为：从所述第一芯片所在芯片组的第k个芯片传递至所述第三芯片所在芯片组中的第k个芯片，从所述第三芯片所在芯片组中的第k个芯片传递至所述第一芯片所在芯片组的第k+1个芯片，k＝1,2,…,m，m为所述第一芯片所在芯片组的芯片的个数，每个芯片组中的第1个芯片为靠近地的芯片。具体为从芯片组1中的第1个芯片传递至芯片组2中的第1个芯片，从芯片组2中的第1个芯片传递至芯片组1中的第2个芯片，从芯片组1中的第2个芯片传递至芯片组2中的第2个芯片，从芯片组2中的第2个芯片传递至芯片组1中的第3个芯片，依次类推，直至传递完所有芯片。图6中芯片间的连接关系未示出。其中，控制信号可以是指如复位信号、关闭信号、开启信号等控制芯片的信号。当然，也可为其它信号，只要是通过控制器或者控制芯片等发送至各个芯片的控制信号即可，对此不作任何限定。
需要说明的是，这里只是表示控制信号的传递方向，对于每个芯片在接收到控制信号后是先处理后传递还是先传递后处理，本实施例不做限定。比如控制信号为复位信号，芯片组1中第1个芯片接收到复位信号后，可以先进行复位动作，然后再传递给芯片组2中的第1个芯片，也可以是先传递给芯片组2中的第1个芯片，然后再进行复位动作，或者也可以是同时进行复位及传递。具体可以根据实际需求设置。
图7是根据一示例性实施例示出的一种串联电路实施例七的示意图，如图7所示，该串联电路包括：
至少一个第一芯片组及至少一个第二芯片组，在每个第一芯片组及每个第二芯片组中芯片之间串行连接；
针对每个第一芯片组，所述第一芯片组中的第i个芯片的第一电压输入端与同芯片组中的第i+1个芯片的电压输出端连接，所述第一芯片组中的第i个芯片的第二电压输入端与至少一个第二芯片组中的第i+1个芯片的电压输出端连接；其中，i＝1,2,…,m，m为第一芯片组中芯片的个数。
针对每个第二芯片组，所述第二芯片组中的第j个芯片的第一电压输入端与同芯片组中的第j+1个芯片的电压输出端连接，所述第二芯片组中的第j个芯片 的第二电压输入端与至少一个第一芯片组中的第j+2个芯片的电压输出端连接，其中，j＝1,2,…,n，n为第二芯片组中芯片的个数。
图7中，以第一芯片组包括5个芯片，第二芯片组包括5个芯片为例，针对第一芯片组，其第1个芯片的第一电压输入端与其第2个芯片的电压输出端连接，其第1个芯片的第二电压输入端与第二芯片组中的第2个芯片的电压输出端连接。第一芯片组中第i个芯片的第一电压输入端与其第i+1个芯片的电压输出端连接，其第i个芯片的第二电压输入端与第二芯片组中的第i+1个芯片的电压输出端连接。
针对第二芯片组，第二芯片组中的第1个芯片的第一电压输入端与其第2个芯片的电压输出端连接，其第1个芯片的第二电压输入端与第一芯片组中第3个芯片的电压输出端连接。第二芯片组中的第j个芯片的第一电压输入端与同芯片组中的第j+1个芯片的电压输出端连接，所述第二芯片组中的第j个芯片的第二电压输入端与至少一个第一芯片组中的第j+2个芯片的电压输出端连接。
在一些实施方式中，各第一芯片组可以并联连接，各第二芯片组可以并联连接。
在一些实施方式中，各第一芯片组可以分别与一个第二芯片组组成图7所示的串联电路。其中，可以是多个第一芯片组同时与同一个第二芯片组组对，也可以是每个第一芯片组与不同的第二芯片组组对。比如有4个第一芯片组和4个第二芯片组，可以分成4对图7所示的串联电路，再比如，有4个第一芯片组和一个第二芯片组，则4个第一芯片组中相应的芯片的各端并联，即每个第一芯片组都与同一个第二芯片组连接成图7所示的串联电路。具体都可以根据实际需求设置，在此不再赘述。
在一些实施方式中，若每个第一芯片组包括m个芯片，每个第二芯片组包括n个芯片。
针对每个第一芯片组，第1个芯片的电压输出端与地连接；第m个芯片的两个电压输入端与电源连接。
针对每个第二芯片组，第1个芯片的电压输出端通过负载器件与地连接；第n个芯片的两个电压输入端与电源连接。
若m>n，针对每个第一芯片组，第n个芯片至第m-1个芯片中各芯片的第二电压输入端与电源连接。
若m＝n，针对每个第二芯片组，第n-1个芯片的第二电压输入端与电源连接。
若m<n，针对每个第二芯片组，第m个芯片至第n-1个芯片中各芯片的第二电压输入端与电源连接。
示例性的，图7中，第一芯片组中芯片个数m与第二芯片组中芯片个数n相等，即m＝n＝5，第二芯片组中，第n-1(＝4)个芯片的第二电压输入端与电源连接。若图7中，第二芯片组中芯片个数n变为4，即m＝5>n＝4，则第一芯片组中，第n(＝4)个芯片的第二电压输入端与电源连接。若n变为3，则第一芯片组中，第n(＝3)个芯片及第m-1(＝4)个芯片这两个芯片的第二电压输入端均需要与电源连接进行供电，以此类推，不再赘述。若图7中，第一芯片组中芯片个数m变为4，即m＝4<n＝5，第二芯片组中第m(＝4)个芯片的第二电压输入端需要由电源供电，以此类推，在此不再赘述。
其中，与电源连接可以包括直接连接或者通过串联降压器件连接。降压器件可以是肖特基二极管、电阻、buck电路、DC-DC电路、钳制电路等等，具体可以根据实际需求设置。具体降压方式为现有技术，在此不再赘述。负载器件可以为肖特基二极管、电阻等等。
示例性的，图8是根据一示例性实施例示出的一种串联电路实施例八的示意图，如图8所示，每个芯片需要的两个主工作电压分别为：core电压0.5V，以及memory电压0.75V。左边第一芯片组中第1个芯片的电压输出端接地为0V，左边第1个芯片的第一电压输入端需要0.5V，第二电压输入端需要0.75V，左边第2个芯片的第一电压输入端则需要1V，第二电压输入端需要1.25V，左边第3个芯片分别需要1.5V和1.75V，左边第4个芯片2V和2.25V，以此类推，左边第m个芯片两个电压输入端分别需要(m/2)V和(m/2+0.25)V。
右边第二芯片组的第1个芯片可以通过负载器件(肖特基二极管、电阻等)与地连接，将第1个芯片的电压输出端的电压定位到0.25V，则第1个芯片的第一电压输入端需要0.75V，第二电压输入端需要1V，右边第2个芯片的第一电压输入端和第二电压输入端分别为1.25V和1.5V，右边第3个芯片1.75V和2V，右边第4个芯片为2.25V和2.5V，右边第n个芯片需要(0.5n+0.25)V和(0.5n+0.5)V。以图8为例，m＝n＝5，可见右边一些芯片的电压输出端电压正好等于左边某些芯片的第二电压输入端电压，左边一些芯片的电压输出端的电压又 正好等于右边一些芯片的第二电压输入端电压，因此，可以交叉进行第二电压输入端的供电。这样整个串联电路只需要有两个电源输入，一个为3V，一个为2.75V。3V的电压可以来自市电，经过AC-DC转换，变成12V直流电压，然后通过DC-DC转换，变成3V电压和2.75V电压。2.75V电压直接连接右边第二芯片组中的第5个芯片的第一电压输入端及左边第一芯片组中的第5个芯片的第二电压输入端，并通过降压器件(如肖特基二极管、电阻等)降压为2.5V连接左边第一芯片组中第5个芯片的第一电压输入端；3V电压直接连接右边第二芯片组中第5个芯片的第二电压输入端。
这里只是示例性说明，对于不同主工作电压的芯片可以根据实际需求设置电源输入的电压以及第二芯片组的第1个芯片的电压输出端的电压。对于每个芯片组，即使每个芯片的主工作电压不同，但是每个芯片组包括的芯片个数不同，也导致从电电源输入的电压不同，具体都可以根据实际需求设置。比如若图8所示的串联电路中，第一芯片组中包括11个芯片，第二芯片组中包括10个芯片，则第一芯片组中第11个芯片的两个电压输入端分别需要6V和6.25V，第二芯片组中第10个芯片的两个电压输入端分别需要5.75V和6V。具体不再赘述。
第一芯片组的主供电路径为各芯片的第一电压输入端从上到下，右边第二芯片组的主供电路径为各芯片的第一电压输入端从上到下。
另外，左边第一芯片组的第1个芯片的第一电压输入端0.5V处，还需要补充一个负载电路或者电压钳制电路，比如一个肖特基二极管、电阻、二极管、运放+MOS管等等，将多余的电流释放。
本实施例，通过第一芯片组和第二芯片组交叉提供各芯片的第二电压输入端电压，整个电路板只需要外部电源输入两个电压，辅助以一个降压器件，一个负载器件，即可实现电路板中各芯片的两个主工作电压需求，有效降低电路器件成本。
在一些实施方式中，该串联电路还可以包括第一辅助电源单元组和第二辅助电源单元组，其中第一辅助电源单元组负责为第一芯片组的各芯片提供两个辅助工作电压，第二辅助电源单元组负责为第二芯片组的各芯片提供的两个辅助工作电压。比如，每个芯片需要两个辅助工作电压分别为0.8V和1.8V。具体的辅助工作电压的供电方式可以与现有技术中的供电方式一致或相似，在此不 再赘述。
图9是根据一示例性实施例示出的一种串联电路实施例九的示意图，如图9所示，该串联电路包括2个第一芯片组及1个第二芯片组。其中，两个第一芯片组并联连接。
图10是根据一示例性实施例示出的一种串联电路实施例十的示意图，如图10所示，该串联电路包括1个第一芯片组及2个第二芯片组。其中，2个第二芯片组并联连接。
在一些实施例中，第一芯片组中的各芯片的第二电压输入端可以分别与不同的第二芯片组中的芯片的电压输出端连接。比如第一芯片组中第1个芯片的第二电压输入端与一个第二芯片组中的第2个芯片的电压输出端连接，该第一芯片组中第2个芯片的第二电压输入端与另一个第二芯片组中的第3个芯片的电压输出端连接。只要能够满足供电要求即可，不限于上述实施例附图中的连接方式。
在一些实施例中，还可以包括更多的第一芯片组及更多的第二芯片组，其具体连接方式与图9及图10相似，在此不再赘述。
本公开实施例还提供了一种电路板，该电路板可以设置在计算设备中。参见图11，图11是根据一示例性实施例示出的一种电路板实施例一的示意图，如图11所示，该电路板包括：上述任一实施例提供的串联电路。对于串联电路的具体连接关系已在上述实施例进行了详细说明，本实施例不再赘述。
本实施例中，电路板中除了可包括上述串联电路之外，还可设置信号接口，以实现和其他电路板、控制板、控制器或者其他控制设备之间的交互。当然，为了电路板的正常工作，电路板上还可设置电源接口以及其它电路等，对此不作赘述。
在一些实施例中，电路板可为计算设备中的主板、运算板、板卡等，对此不作任何限定。
图12是根据一示例性实施例示出的一种电路板实施例二的示意图，如图12所示，该电路板中的串联电路包括至少一个第一芯片组以及至少一个第二芯片组，以包括3个第一芯片组和3个第二芯片组为例，各第一芯片组排列在各第二芯片组的左侧。对于串联电路的具体连接关系已在上述实施例进行了详细说明，本实施例不再赘述。
当然，第一芯片组和第二芯片组的数量可以相同，也可以不同，比如可以包括4个第一芯片组和5个第二芯片组，或者包括3个第一芯片组和2个第二芯片组，等等，本实施例不做任何限定。当第一芯片组和第二芯片组的数量相同时，电流的均衡性较好。
图13是根据一示例性实施例示出的一种电路板实施例三的示意图，如图13所示，该电路板中，各第一芯片组均排列在各第二芯片组的右侧。对于串联电路的具体连接关系已在上述实施例进行了详细说明，本实施例不再赘述。
在一些实施例中，各第一芯片组还可排列在各第二芯片组的上侧或者下侧。当然，在另一些实施例中，各第一芯片组还可排列在电路板的第一面，各第二芯片组还可排列在电路板的第二面，对此不作任何限定。
图14是根据一示例性实施例示出的一种电路板实施例四的示意图，如图14所示，该电路板中，各第一芯片组与各第二芯片组相间排列。对于串联电路的具体连接关系已在上述实施例进行了详细说明，本实施例不再赘述。需要说明的是，这里的相间排列可以是严格的一个第一芯片组、一个第二芯片组、再一个第一芯片组、再一个第二芯片组，以此类推，也可以是不规则的相间排列，比如，如图14所示，第一芯片组、第二芯片组、第一芯片组、第二芯片组、第二芯片组，还可以是两个第一芯片组、两个第二芯片组、两个第一芯片组、两个第二芯片组等等。也即，可以根据实际需求在电路板上将各芯片组以任意排列方式进行排列。
需要说明的是，本实施例中，第一芯片组和第二芯片组的个数可设置为相同或者不同，各芯片组中串联的芯片的数量也可设置为相同或者不同，对此不作任何限定。
本公开实施例还提供了一种计算设备，用于进行相应的计算或处理。参见图15，图15是根据一示例性实施例示出的一种计算设备实施例一的示意图，如图15所示，该计算设备包含上述任一实施例提供的串联电路。
本实施例中，计算设备通常可为相应的计算机、超级计算机、AI(Artificial Intelligence，人工智能)处理设备、服务器等，只要能够实现数据的运算和处理即可，对此不作任何限定。
图16是根据一示例性实施例示出的一种计算设备实施例二的示意图，如图16所示，该计算设备包含上述任一实施例提供的电路板。
本实施例中，计算设备中可包括至少一个电路板，当包括的电路板个数为两个以上时，各电路板之间可以相互并联。
另外，计算设备中还可包括相应的控制板，控制板与各电路板之间信号连接，用于向电路板上的各个芯片下发控制信号。
需要说明的是，本发明实施例中，电路板上的各芯片、计算设备中的各电路板以及控制板，均可为可拆卸的模块，当其中有部分部件发生故障时，可单独拆卸，提升了计算设备以及控制板的实用性和可维修性。
在一些实施例中，计算设备的机箱上可设置相应的滑槽，以放置各电路板或者控制板，对此不作任何限定。
当用于本申请中时，虽然术语“第一”、“第二”等可能会在本申请中使用以描述各元件，但这些元件不应受到这些术语的限制。这些术语仅用于将一个元件与另一个元件区别开。比如，在不改变描述的含义的情况下，第一元件可以叫做第二元件，并且同样地，第二元件可以叫做第一元件，只要所有出现的“第一元件”一致重命名并且所有出现的“第二元件”一致重命名即可。第一元件和第二元件都是元件，但可以不是相同的元件。
本申请中使用的用词仅用于描述实施例并且不用于限制权利要求。如在实施例以及权利要求的描述中使用的，除非上下文清楚地表明，否则单数形式的“一个”(a)、“一个”(an)和“所述”(the)旨在同样包括复数形式。类似地，如在本申请中所使用的术语“和/或”是指包含一个或一个以上相关联的列出的任何以及所有可能的组合。另外，当用于本申请中时，术语“包括”(comprise)及其变型“包括”(comprises)和/或包括(comprising)等指陈述的特征、整体、步骤、操作、元素，和/或组件的存在，但不排除一个或一个以上其它特征、整体、步骤、操作、元素、组件和/或这些的分组的存在或添加。
所描述的实施例中的各方面、实施方式、实现或特征能够单独使用或以任意组合的方式使用。
上述技术描述可参照附图，这些附图形成了本申请的一部分，并且通过描述在附图中示出了依照所描述的实施例的实施方式。虽然这些实施例描述的足够详细以使本领域技术人员能够实现这些实施例，但这些实施例是非限制性的；这样就可以使用其它的实施例，并且在不脱离所描述的实施例的范围的情况下还可以做出变化。比如，流程图中所描述的操作顺序是非限制性的，因此在流 程图中阐释并且根据流程图描述的两个或两个以上操作的顺序可以根据若干实施例进行改变。作为另一个例子，在若干实施例中，在流程图中阐释并且根据流程图描述的一个或一个以上操作是可选的，或是可删除的。另外，某些步骤或功能可以添加到所公开的实施例中，或两个以上的步骤顺序被置换。所有这些变化被认为包含在所公开的实施例以及权利要求中。
另外，上述技术描述中使用术语以提供所描述的实施例的透彻理解。然而，并不需要过于详细的细节以实现所描述的实施例。因此，实施例的上述描述是为了阐释和描述而呈现的。上述描述中所呈现的实施例以及根据这些实施例所公开的例子是单独提供的，以添加上下文并有助于理解所描述的实施例。上述说明书不用于做到无遗漏或将所描述的实施例限制到本公开的精确形式。根据上述教导，若干修改、选择适用以及变化是可行的。在某些情况下，没有详细描述为人所熟知的处理步骤以避免不必要地影响所描述的实施例。

Claims (13)

  1. 一种串联电路，其特征在于，包括：
    至少两个芯片组，在每个所述芯片组中芯片之间串行连接；
    针对每个芯片组中的第一芯片，所述第一芯片的第一电压输入端与同芯片组中与其相邻的第二芯片的第一电压输出端连接，所述第一芯片的第二电压输入端与另一芯片组中的第三芯片的第二电压输出端连接，由所述第一电压输出端和所述第二电压输出端共同为所述第一芯片供电。
  2. 根据权利要求1所述的串联电路，其特征在于，所述第二电压输出端的输出电压等于所述第二电压输入端的标准输入电压。
  3. 根据权利要求1所述的串联电路，其特征在于，当所述第二电压输出端的输出电压高于所述第二电压输入端的标准输入电压时，所述第二电压输出端通过降压器件与所述第二电压输入端连接，以使输出到所述第二电压输入端的电压等于所述标准输入电压。
  4. 根据权利要求1-3任一项所述的串联电路，其特征在于，所述第三芯片的第二电压输出端同时为所述第一芯片所在芯片组中的其他芯片供电。
  5. 根据权利要求1-3任一项所述的串联电路，其特征在于，在所述第一芯片所在的芯片组中，所述第三芯片的第二电压输出端只为所述第一芯片供电。
  6. 根据权利要求1所述的串联电路，其特征在于，位于所述芯片组一端的第四芯片，其两个电压输入端由电源供电。
  7. 根据权利要求6所述的串联电路，其特征在于，在所述电源和地之间连接有第一电压钳制电路及第二电压钳制电路；
    所述第一电压钳制电路包括至少一个第一输出端，所述第一输出端分别连接至所述第一芯片所在芯片组的至少一个芯片的第一电压输入端，所述第二电压钳制电路包括至少一个第二输出端，所述第二输出端分别连接至所述第三芯片所在芯片组的至少一个芯片的第一电压输入端。
  8. 根据权利要求1所述的串联电路，其特征在于，所述串联电路中各芯片的控制信号的传递方向为：
    从所述第一芯片所在芯片组的第k个芯片传递至所述第三芯片所在芯片组中的第k个芯片，从所述第三芯片所在芯片组中的第k个芯片传递至所述第一 芯片所在芯片组的第k+1个芯片，k＝1,2,…,m，m为所述第一芯片所在芯片组的芯片的个数，每个芯片组中的第1个芯片为靠近地的芯片。
  9. 一种串联电路，其特征在于，包括：
    至少一个第一芯片组及至少一个第二芯片组，在每个第一芯片组及每个第二芯片组中芯片之间串行连接；
    针对每个第一芯片组，所述第一芯片组中的第i个芯片的第一电压输入端与同芯片组中的第i+1个芯片的电压输出端连接，所述第一芯片组中的第i个芯片的第二电压输入端与至少一个第二芯片组中的第i+1个芯片的电压输出端连接，i＝1,2,…,m，m为第一芯片组中芯片的个数；
    针对每个第二芯片组，所述第二芯片组中的第j个芯片的第一电压输入端与同芯片组中的第j+1个芯片的电压输出端连接，所述第二芯片组中的第j个芯片的第二电压输入端与至少一个第一芯片组中的第j+2个芯片的电压输出端连接，j＝1,2,…,n，n为第二芯片组中芯片的个数。
  10. 根据权利要求9所述的串联电路，其特征在于，每个第一芯片组包括m个芯片，每个第二芯片组包括n个芯片；
    针对每个第一芯片组，第1个芯片的电压输出端与地连接；第m个芯片的两个电压输入端与电源连接；
    针对每个第二芯片组，第1个芯片的电压输出端通过负载器件与地连接；第n个芯片的两个电压输入端与电源连接；
    若m>n，针对每个第一芯片组，第n个芯片至第m-1个芯片中各芯片的第二电压输入端与电源连接；
    若m＝n，针对每个第二芯片组，第n-1个芯片的第二电压输入端与电源连接；
    若m<n，针对每个第二芯片组，第m个芯片至第n-1个芯片中各芯片的第二电压输入端与电源连接。
  11. 一种电路板，其特征在于，包括：权利要求1-10任一项所述的串联电路。
  12. 一种电路板，其特征在于，包括：权利要求9或10所述的串联电路；
    其中，各第一芯片组均排列在各第二芯片组的左侧或右侧；或者，
    各第一芯片组与各第二芯片组相间排列。
  13. 一种计算设备，其特征在于，所述计算设备包括权利要求1-10任一项所述的串联电路。
PCT/CN2018/110141 2018-10-12 2018-10-12 串联电路、电路板及计算设备 WO2020073335A1 (zh)

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