WO2020071067A1 - Led driving circuit device and electronic instrument - Google Patents

Abstract

Each of a plurality of sets of LED drivers comprises: a plurality of LED constant current sources that can be connected individually through an LED connection terminal to one or more LED strings; a selection unit for selecting, as a subsequent-detection LED connection terminal, the LED connection terminal of the LED string among the one or more LED strings in which the LED forward-direction total voltage is the largest; a comparator for comparing the voltage of a detection LED connection terminal and a first reference voltage; and a feedback terminal for outputting a current based on the output of the comparator. A feedback voltage generation circuit of a power supply device comprises a first voltage division resistor connected to an output terminal and a second voltage division resistor connected to ground potential and serially connected to a first voltage division circuit. A plurality of sets of feedback terminals are connected to a common connection node between the first voltage division resistor and the second voltage division resistor.

Description

LED drive circuit device and electronic equipment

The present invention relates to an LED driving device that drives a plurality of LED (Light Emitting Diode) sets.

今 In recent years, LEDs are widely used, for example, in liquid crystal panels, lighting devices, traffic signals, various light sources, and the like. A switching regulator is used together with such various devices, and the switching regulator is controlled by a PWM (Pulse Width Modulation) method. In addition, LEDs are often PWM-controlled.

Patent Document 1 discloses a power supply control semiconductor integrated circuit that drives a switching element that allows current to flow intermittently through an inductor and rectifies the current flowing through the inductor to generate a drive current for an LED. The power supply control semiconductor integrated circuit includes a plurality of external terminals for drawing current from each of the plurality of LED units, a plurality of current sources respectively connected to the plurality of external terminals, a voltage of the plurality of external terminals and a predetermined voltage. And an error amplifier that outputs a voltage corresponding to a potential difference from the reference voltage. Then, a drive pulse for the switching element is generated based on the output corresponding to the one having the lowest voltage of the external terminal among the plurality of outputs of the error amplifier. According to this, it is possible to suppress an increase in the number of components and mounting area due to an increase in the number of LEDs, and to avoid occurrence of unevenness in screen brightness.

Patent Document 2 discloses a driving circuit of a light emitting element, a light emitting device and an electronic apparatus using the same. Patent Document 2 stabilizes the luminance of a light emitting element during a scanning operation. Therefore, the error amplifier generates a source current corresponding to the error when the reference voltage is higher, based on the error between the lowest voltage of each of the n LED terminals and a predetermined reference voltage. When it is lower, a sink current corresponding to the error is generated, and the feedback voltage generated at the feedback terminal is changed.

JP 2010-11808 A JP 2013-109921 A

Patent Document 1 generates a drive pulse corresponding to the voltage of an external terminal provided in a plurality of LED units and applies it to a switching element, but cannot expect to stabilize the brightness of the plurality of LED units. This is because detecting the voltage of the external terminal is different from applying appropriate voltages to the plurality of LED units.

In Patent Document 2, in addition to the circuit configuration disclosed in Patent Document 1, a driving voltage for applying a feedback voltage generated at a feedback terminal to a light emitting element by a sink current or a source current output from a transconductance amplifier is controlled, so that light is emitted. The luminance of the element can be stabilized. However, the feedback terminal in Patent Document 2 is an external terminal on the output side of the error amplifier, that is, a feedback capacitor (CFB) for phase compensation and a feedback resistor (RFB) connected in series. Therefore, it is not expected that the output voltage is controlled with high accuracy, and it is not expected that the stabilization of the luminance of the LED is controlled with high accuracy.

The present invention has been made in view of the above problems, and an object of the present invention is to provide an LED drive circuit device capable of stabilizing the luminance of a light emitting element.

One embodiment of the LED drive circuit device according to the present invention is an LED drive circuit device including a power supply device and including a plurality of sets of an LED driver and at least one LED string, wherein the power supply device outputs an output voltage of the power supply device. A feedback voltage generation circuit that generates a divided feedback voltage; and an output voltage adjustment unit that varies the output voltage according to the feedback voltage, wherein each of the at least one LED string drives the output voltage by a drive voltage. A plurality of LEDs are connected in series as a source, each of the LED drivers includes a plurality of LED constant current sources that can be individually connected to the at least one LED string via LED connection terminals, and the at least one LED string. Of the LED strings, the LED connection terminal of the LED string with the highest total LED forward voltage is A selection unit that selects the output LED connection terminal; a comparison unit that compares the voltage of the detection LED connection terminal with a first reference voltage; and a feedback terminal that outputs a current based on the output of the comparison unit. Wherein the feedback voltage generation circuit includes a first voltage dividing resistor connected to an output terminal of the power supply device and a second voltage dividing resistor connected to a ground potential and connected in series with the first voltage dividing circuit; The plurality of sets of the feedback terminals are connected to a common connection node between the first voltage dividing resistor and the second voltage dividing resistor (first configuration).

Further, in the first configuration, each of the LED drivers may include an operational amplifier having the selection unit and the comparison unit, and an output of the operational amplifier may be coupled to the feedback terminal (second embodiment). Constitution).

Further, in the second configuration, when the voltage of the detection LED connection terminal is lower than the first reference voltage, the feedback terminal outputs a sink current drawn from the common connection node to the feedback terminal. (Third configuration).

In the third configuration, each of the plurality of sets of third voltage-dividing resistors may be connected between the common connection node and each of the plurality of sets of the feedback terminals (fourth configuration). .

In the second configuration, the operational amplifier may be a transconductance amplifier (fifth configuration).

Further, in the fifth configuration, when the voltage of the detection LED connection terminal is lower than the first reference voltage, the feedback terminal outputs a sink current drawn from the common connection node to the feedback terminal. (Sixth configuration).

When the voltage of the detection LED connection terminal is higher than the first reference voltage, the feedback terminal may output a source current flowing from the feedback terminal to the common connection node (seventh embodiment). Constitution).

Further, in the first configuration, each of the LED drivers is configured to determine a source current flowing into a common connection node between the first voltage dividing resistor and the second voltage dividing resistor in accordance with an output of a comparator serving as the comparing unit. A source current supply unit for switching on and off may be provided (eighth configuration).

Further, in the eighth configuration, the source current supply unit includes a switch that is turned on / off according to an output of the comparator, a constant current circuit connected to the switch, and a current mirror circuit, The switch may be connected between both ends of one of the transistors in the current mirror circuit (a ninth configuration).

In any one of the first to ninth configurations, the LED constant current source may generate a current intermittently with a first pulse width modulation signal (tenth configuration).

In any one of the first to tenth configurations, the power supply device includes a switching element that intermittently supplies a current to the inductor, and smoothes an inductor current that flows through the inductor, and outputs the output voltage to the output terminal. And a slope signal generation circuit, an error amplifier, and a PWM comparator. The slope signal generation circuit generates a triangular or sawtooth-shaped slope signal, and the error amplifier generates the feedback voltage and a feedback voltage. The PWM comparator compares the error voltage with the slope signal, and outputs a second pulse having a pulse width corresponding to the pulse comparison result. Outputting a width modulation signal, wherein the switching element is controlled to be turned on or off by the second pulse width modulation signal. It may be a Rukoto (eleventh configuration).

の 一 Further, one embodiment of an electronic device according to the present invention includes the LED drive circuit device having any one of the above-described configurations.

According to the present invention, the lowest voltage among the plurality of LED strings to which the driving voltage is applied is compared with the predetermined reference voltage, and the magnitude of the feedback voltage generated by the feedback voltage generating circuit based on the comparison result. Since the driving voltage supplied to the LED string is controlled by controlling the output voltage, the output voltage can be adjusted to a voltage suitable for the voltage drop in the LED string, the brightness of the LED string is maintained at a predetermined brightness, and the output of the power supply The disadvantage that the output voltage of the terminal becomes unnecessarily high and power consumption in the LED drive circuit device increases can be eliminated.

It is a circuit diagram showing the LED drive circuit device according to the first embodiment. 2 is a timing chart showing signal waveforms at main nodes when the LED drive circuit device of FIG. 1 is driven by a PWM signal having a relatively wide pulse width. 2 is a timing chart showing signal waveforms at main nodes when the LED drive circuit device of FIG. 1 is driven by a PWM signal having a relatively narrow pulse width. It is a circuit diagram showing the LED drive circuit device according to the second embodiment. 3 is a timing chart showing signal waveforms at main nodes when the LED drive circuit device of FIG. 2 is driven by a PWM signal having a relatively wide pulse width. 3 is a timing chart showing signal waveforms at main nodes when the LED drive circuit device of FIG. 2 is driven by a PWM signal having a relatively narrow pulse width. It is a circuit diagram showing the LED drive circuit device concerning a 3rd embodiment. 6 is a timing chart showing signal waveforms at main nodes when the LED drive circuit device of FIG. 5 is driven by a PWM signal. It is a figure showing the composition of the LED driver concerning a modification of a 3rd embodiment. It is a figure showing an example of the composition which drives a plurality of LED sets. It is a top view showing an example of pin arrangement in an LED driver concerning a modification of a 3rd embodiment. It is a circuit diagram showing an LED drive circuit device according to a fourth embodiment. It is a top view showing an example of the pin arrangement in the LED driver concerning a 4th embodiment. 4 is a timing chart of dimming data and pulse signals output from the microcomputer.

(1st Embodiment)
FIG. 1 is a circuit diagram showing an LED drive circuit device 1 according to the first embodiment. The LED drive circuit device 1 includes a switching control circuit 2, an output circuit 3, an LED driver (constant current driver) 5, and LED strings 4_1 to 4_n (n is a natural number of 2 or more). The switching control circuit 2 has several external terminals. The output circuit 3 includes an inductor L1, a capacitor C1, and voltage dividing resistors R1 and R2. The switching control circuit 2 and the output circuit 3 constitute a switching regulator. The switching control circuit 2 cooperates with the output circuit 3 to reduce the input voltage Vin supplied to the input terminal IN and output a desired output voltage Vout to the output terminal OUT. The switching regulator shown in FIG. 1 constitutes a well-known step-down type. Note that the switching control circuit 2 and the output circuit 3 may be configured so as to be adapted to a step-up or step-up / step-down type instead of a step-down type. The LED drive circuit device described in this specification can be applied regardless of the step-down, step-up or step-up / step-down switching regulation.

The switching control circuit 2 is composed of a semiconductor integrated circuit, and includes a switching element S1, a synchronous rectification semiconductor element S2, an error amplifier 6, an oscillation circuit 7, a slope signal generation circuit 8, a PWM comparator 9, and a drive circuit 10. The switching element S1 operates complementarily to the synchronous rectification semiconductor element S2 as a switching element that allows current to flow intermittently through the inductor L1. When the switching element S1 is off, a current is supplied to the inductor L1. The switching element S1 and the synchronous rectification semiconductor element S2 are turned on / off to generate an output voltage Vout from the input voltage Vin. The synchronous rectification semiconductor element S2 can be replaced with a diode instead of a transistor.

(4) The input voltage Vin, the inductor L1, the capacitors C1 to C2, the voltage dividing resistors R1 to R3, the resistor R4, and the ground potential GND are connected to a plurality of external terminals prepared in the switching control circuit 2.

(4) The input terminal IN to which the input voltage Vin is applied is connected to the source of the switching element S1 composed of, for example, a p-channel MOS transistor. The drain of the switching element S1 is connected to the switching terminal SW and the drain of the synchronous rectification semiconductor element S2. For example, the source of the synchronous rectification semiconductor element S2 composed of an n-channel MOS transistor is connected to the ground potential GND.

一端 One end of the inductor L1 is connected to the switching terminal SW. The intermittent switching voltage Vsw output from the switching terminal SW causes the inductor current IL to flow through the inductor L1. The other end of the inductor L1 is connected to the output terminal OUT and one end of the capacitor C1, and is connected to the output terminal OUT. The other end of the capacitor C1 is grounded to the ground potential GND. Capacitor C1 smoothes the electromagnetic energy stored in inductor L1.

(4) The voltage dividing resistors R1 and R2 forming a part of the output circuit 3 are connected in series between the output terminal OUT and the ground potential GND to form a feedback voltage generating circuit. The feedback voltage generation circuit generates a feedback voltage Vfb at a common connection node Nc of the voltage dividing resistors R1 and R2. The feedback voltage Vfb is applied to the inverting input terminal (−) of the error amplifier 6 via the feedback terminal FB.

The error amplifier 6 compares the feedback voltage Vfb with the first reference voltage Vt1, and outputs an error signal Verr according to the comparison result.

(4) A phase compensation terminal COMP is provided in the signal path between the output of the error amplifier 6 and the inverting input terminal (-) of the PWM comparator 9. A capacitor C2 and a resistor R4 are connected in series between the phase compensation terminal COMP and the ground potential GND. The voltage gain of the error amplifier 6 is set by the capacitor C2 and the resistor R4. The error amplifier 6 is composed of, for example, a transconductance amplifier.

The capacitor C2 and the resistor R4 connected in series between the phase compensation terminal COMP and the ground potential GND determine the voltage gain of the error amplifier 6 and also determine the phase characteristics of the switching regulator. The frequency characteristics of the switching regulator including the switching control circuit 2 and the output circuit 3 are properly corrected by the capacitor C2 and the resistor R4.

The oscillation circuit 7 is constituted by, for example, a well-known CR oscillator or a ring oscillator in which inverters or differential amplifiers are connected in a ring shape. The oscillation circuit 7 generates a clock signal CLK. The clock signal CLK is used as a set signal Sset for the driving circuit 10 at the subsequent stage.

The slope signal generation circuit 8 includes, for example, a not-shown constant current source, a capacitor, a switching element, and the like, and generates a triangular or sawtooth-shaped slope voltage Vsl. Such a slope voltage Vsl is generated by a clock signal CLK applied from the oscillation circuit 7.

The PWM comparator 9 compares the error signal Verr with the slope signal Vsl, and outputs a reset signal Reset corresponding to the comparison result to the driving circuit 10 at the subsequent stage. The reset signal Reset is output as a pulse width modulation (PWM) signal whose pulse width is modulated according to the error signal Verr.

(4) The drive circuit 10 receives the set signal Sset and the reset signal Sreset, and drives the switching element S1 and the synchronous rectification semiconductor element S2. These are driven by complementary gate signals P1 and P2, respectively.

An unillustrated RS flip-flop, for example, is provided inside the drive circuit 10. The set terminal of the RS flip-flop receives a set signal Sset generated by the oscillation circuit 7, and a reset terminal outputs the set signal Sset from the PWM comparator 9. Reset signal Reset is applied.

The LED drive circuit device 1 shown in FIG. 1 includes a plurality of LED strings 4_1 to 4_n in addition to the above circuit configuration. The LED strings 4_1 to 4_n are used as a light source or a display device of a liquid crystal panel, a lighting device, a traffic signal, other various electronic devices, and the like. The output voltage Vout generated by the switching regulator is supplied as a drive voltage source to the common anode side of the LED strings 4_1 to 4_n, that is, the output terminal OUT. The total forward voltage of the LEDs up to the LED strings 4_1, 4_2, and 4_n is indicated by Vf1, Vf2, and Vfn, respectively.

The LED driver 5 supplies an LED current to each LED string. The LED driver 5 is configured by a semiconductor integrated circuit (IC) different from the switching control circuit 2 for providing versatility. Thereby, the versatility can be expanded by combining the LED string, the switching control circuit, and the output circuit according to various kinds. The LED driver 5 is provided with LED connection terminals LED1 to LEDn for coupling to the respective cathode sides of the LED strings 4_1 to 4_n. The LED terminal voltages generated at the LED connection terminals LED1, LED2, and LEDn as viewed from the ground potential GND are indicated by VLED1, VLED2, and VLEDn, respectively.

The LED driver 5 has LED constant current sources Cs1 to Csn that individually supply LED currents ILED1 to ILEDn to each LED string. The LED constant current sources Cs1 to Csn are intermittently controlled by, for example, a pulse width modulation (PWM) signal applied from the PWM dimming unit 11. Such control is also called burst dimming or burst control. The constant current sources Cs1 to Csn do not need to perform burst dimming and burst control, and may be configured by a general constant current source circuit.

The LED driver 5 further includes an operational amplifier 12. The input of the operational amplifier 12 is provided with (n + 1) input terminals obtained by adding a terminal for applying the reference voltage VREF to the number output to the LED connection terminals LED1 to LEDn. The reference voltage VREF is supplied to the inverting input terminal (−) of the operational amplifier 12. LED terminal voltages VLED1 to VLEDn are applied to at least two non-inverting input terminals (+). The operational amplifier 12 compares the lowest LED terminal voltage among the LED terminal voltages VLED1 to VLEDn with respect to the ground potential GND and the reference voltage VREF, and outputs the comparison result to the transistor Tr1 in the subsequent stage.

(4) The transistor Tr1 is connected to the output of the operational amplifier 12. The transistor Tr1 is, for example, a bipolar transistor, the emitter of which is connected to the ground potential GND, and the collector of which is connected to the external terminal OPFB. Such a circuit configuration of the transistor Tr1 can be generally called an open collector. Note that the transistor Tr1 may be configured by a MOS transistor and may have an open drain circuit configuration.

(4) The transistor Tr1 is turned on when the output of the operational amplifier 12 becomes high level H, and as a result, the sink current Isi flows. When the transistor Tr1 is turned on, the potential of the external terminal OPFB becomes a low level L which is almost close to the ground potential GND.

Here, the LED driver 5 also has an OR circuit 51. The pulse width modulation signals PWM1 to PWMn are input to the OR circuit 51. The output of the OR circuit 51 is input to the operational amplifier 12. When at least one of the pulse width modulation signals PWM1 to PWMn is at a high level, the output of the OR circuit 51 is at a high level. When all of the pulse width modulation signals PWM1 to PWMn are at a low level, the output of the OR circuit 51 is at a low level. Become. The operational amplifier 12 turns off the transistor Tr1 when the output of the OR circuit 51 is at a low level, and when the output of the OR circuit 51 is at a high level, the lowest LED terminal voltage among the LED terminal voltages VLED1 to VLEDn and the reference voltage VREF. Is output to the transistor Tr1.

一端 One end of the voltage dividing resistor R3 is connected to the external terminal OPFB, and the other end is connected to the feedback terminal FB. The voltage dividing resistor R3 is connected in parallel with the voltage dividing resistor R2 when the transistor Tr1 is turned on, that is, when the external terminal OPFB becomes low level L. The resistance value of the voltage dividing resistor R3 is selected to be sufficiently larger than the on-resistance of the transistor Tr1. The feedback voltage Vfb at the feedback terminal FB is lower than when the transistor Tr1 is off. At this time, the switching regulator formed by the switching control circuit 2 and the output circuit 3 controls the output voltage Vout to increase. .

に よ っ て Thereby, the PWM dimming unit 11 intermittently raises and controls the output voltage Vout. Thus, heat generation in the LED strings 4_1 to 4_n can be suppressed. However, due to the responsiveness of the switching regulator constituted by the switching control circuit 2 and the output circuit 3, the rise of the output voltage Vout may be delayed and the LED string may not be lit.

Note that, in the LED drive circuit device 1 shown in FIG. 1, the transistor Tr1 draws current from the feedback terminal FB side to the external terminal OPFB, that is, controls only a so-called sink current. Therefore, the output voltage Vout is controlled by the LED voltage. Only when any one of VLED1 to VLEDn reaches the reference voltage VREF and only the direction in which the output voltage Vout is increased can be controlled.

In the LED strings 4_1 to 4_n, for a certain LED string 4_i (1 ≦ i ≦ n), the LED forward total voltage Vf_max and the voltage at the LED connection terminal LED_i are set to the LED terminal voltage VLED_min. During a period in which the LED strings 4_1 to 4_n are lit, the following relational expression (1) holds.
Vout = Vf_max + VLED_min (1)

(4) The LED forward total voltages Vf1 to Vfn of the LED strings 4_1 to 4_n vary from channel to channel. Here, the LED forward total voltage Vf_max in the LED string 4_i is the maximum LED forward total voltage. At this time, from the equation (1), the LED terminal voltage VLED_min is the minimum LED terminal voltage. Hereinafter, it is assumed that the maximum LED forward total voltage Vf_max and the minimum LED terminal voltage VLED_min are generated for the LED string 4_i among the LED strings 4_1 to 4_n, and the LED current ILEDi flows.

FIG. 2A is a timing chart when the LED drive circuit device 1 is driven at a relatively large on-duty ratio, for example, when the on-duty ratio of the PWM signal is about 70%. FIG. 2A is a timing chart when the control of the output voltage Vout is performed only by the sink current as described with reference to FIG.

FIG. 2A (a) shows a pulse width modulation signal PWMi applied from the PWM dimming unit 11 of the LED driver 5 to the LED constant current source Csi. The pulse width modulation signal PWMi is at a high level H from time t0 to t4 and at a low level L from time t4 to t6. This indicates that the signal TH having a so-called pulse duty ratio is relatively large, that is, the section TH of the high level H is longer than the section TL of the low level L.

ＬＥＤThe LED current ILEDi in FIG. 2A (b) follows the high level H and the low level L of the pulse width modulation signal PWMi. A current flows in a high-level H section from time t0 to t4, and no current flows in a low-level L section from time t4 to t6, that is, a so-called intermittent current flows. In the section from time t0 to t1, the LED current ILEDi starts to flow a little more slowly.

2A (c) shows the LED terminal voltage VLED_min which is the voltage of the LED connection terminal LED_i. At time t0 when the LED current ILEDi starts to flow, the voltage suddenly becomes lower than the reference voltage VREF, and thereafter gradually rises in a section until time t3. This is because the LED current ILEDi flows through the LED string 4_i at the time t0, and at the same time, the voltage is reduced by the LED forward total voltage Vf_max. From time t0 to t3, feedback is applied by the operational amplifier 12 so that the LED terminal voltage VLED_min becomes the reference voltage VREF. In the section from time t3 to t4, the operation is performed so as to be maintained at the reference voltage VREF. When the LED current ILEDi stops flowing from the time t4 to t6, the LED terminal voltage VLED_min is boosted to follow the output voltage Vout. In the figure, reference numeral Vsi indicates a sink current adjustment voltage adjusted by a sink current Isi described later.

FIG. 2A (d) shows the sink current Isi flowing into the transistor Tr1 from the feedback terminal FB via the sink current output terminal OPFB provided on the LED driver 5 side. Whether the sink current Isi flows according to the LED terminal voltage VLED_min is determined. In particular, at time t0, the flow starts when the LED terminal voltage VLED_min falls below the reference voltage VREF, and increases as the LED terminal voltage VLED_min approaches the reference voltage VREF. At time t3, when the LED terminal voltage VLED_min reaches the reference voltage VREF, a constant sink current Isi flows until time t4. Since the output of the OR circuit 51 is at a low level in the period TL from time t4 to t6, the transistor Tr1 is turned off by the operational amplifier 12, and the sink current Isi stops flowing and becomes 0.

FIG. 2A (e) shows a transition state of the output voltage Vout. The output voltage Vout responds to the behavior of the sink current Isi. From time t0 to time t2, the sink current Isi acts to increase the output voltage Vout. The time from time t0 to time t2 is determined by the responsiveness of the previous stage regulator and the operational amplifier 12. From time t2 to time t4, the control effect on the output voltage Vout by the sink current Isi reaches the maximum, and the output voltage Vout is controlled so as to have a value (VREF + Vf_max) obtained by adding the LED forward total voltage Vf_max to the reference voltage VREF. You. The voltage drops sharply between times t4 and t5, and gradually drops between times t5 and t6.

(4) The output voltage Vout varies according to the high level and the low level of the pulse width modulation signal PWMi. This is because the LED driver 5 in FIG. 1 operates during the high level section of the pulse width modulation signal PWMi and stops during the low level section of the pulse width modulation signal PWMi. Accordingly, the output voltage Vout fluctuates due to the fluctuation of the feedback voltage Vfb.

When the pulse width modulation signal PWMi is at a high level, the following relational expression (2) holds for the output voltage Vout, the resistors R1, R2, R3, and the first reference voltage Vt1.
Vout = (R1 · R2 + R2 · R3 + R3 · R1) · Vt1 / (R2 · R3) (2)
When the pulse width modulation signal PWMi is at a low level, the following relational expression (3) holds for the output voltage Vout, the resistors R1, R2, and the first reference voltage Vt1.
Vout = (R1 + R2) · Vt1 / R2 (3)
That is, according to equations (2) and (3), when the pulse width modulation signal PWMi is at a high level, the output voltage Vout is boosted to a voltage of (VREF + Vf_max). Therefore, the output voltage Vout from time t4 to t5 drops sharply.

{Circle around (2)} The waveform operations from time t0 to t6 also transit similarly from time t6 to t12 and after time t12.

As described above, the LED drive circuit device 1 shown in FIG. 1 can suppress heat generation in the LED string by boosting and controlling the output voltage Vout only when the pulse width modulation signal is at the high level.

FIG. 2B is a timing chart when the LED drive circuit device 1 is driven with a relatively small on-duty ratio such as an on-duty ratio of a PWM signal of, for example, about 2%. The driving condition is not always in a good state as compared with the case where the on-duty ratio of FIG. 2A is relatively large. FIG. 2B is a timing chart in the case where the control of the output voltage Vout is performed only by the sink current Isi as in FIG. 2A.

FIG. 2B (a) shows a pulse width modulation signal PWMi applied from the PWM dimming unit 11 of the LED driver 5 to the LED constant current source Csi. The pulse width modulation signal PWMi is at a high level H between times T0 and T2 and at a low level L between times T2 and T4. This indicates that the signal TH having a shorter pulse duty ratio is shorter in the high level H section TH than in the low level L section TL.

ＬＥＤThe LED current ILEDi in FIG. 2B (b) follows the high level H and the low level L of the pulse width modulation signal PWMi. A current flows in a section of a high level H from time T0 to T2, and no current flows in a section of a low level L from time T2 to T4, that is, a so-called intermittent current flows. In the section from time T0 to T1, the LED current ILEDi starts to flow slightly slowly.

FIG. 2B (c) shows the LED terminal voltage VLED_min which is the voltage of the LED connection terminal LED_i. At time T0 at which the LED current ILEDi starts to flow, the voltage suddenly becomes lower than the reference voltage VREF, and thereafter gradually increases in a section up to time T2. Feedback is performed by the operational amplifier 12 so that the LED terminal voltage VLED_min becomes the reference voltage VREF. However, even at time T2, the LED terminal voltage VLED_min has not reached the reference voltage VREF. This is because the pulse width of the pulse width modulation signal PWMi is narrow, and the polarity of the pulse width modulation signal PWMi is inverted before the LED terminal voltage VLED_min reaches the reference voltage VREF. When the LED current ILEDi stops flowing between times T2 and T4, the LED terminal voltage VLED_min is boosted so as to follow the output voltage Vout.

FIG. 2B (d) shows the sink current Isi flowing into the transistor Tr1 from the feedback terminal FB via the sink current output terminal OPFB provided on the LED driver 5 side. At time T0, the flow starts when the LED terminal voltage VLED_min falls below the reference voltage VREF, and increases as the LED terminal voltage VLED_min approaches the reference voltage VREF. From time T2 to T4, the sink current Isi stops flowing and becomes 0.

FIG. 2B (e) shows a transition state of the output voltage Vout. The output voltage Vout responds to the behavior of the sink current Isi. From time T0 to time T2, the sink current Isi acts to increase the output voltage Vout. However, due to this effect, before the output voltage Vout reaches (VREF + Vf_max), the pulse width modulation signal PWMi goes to a low level, and the voltage drops sharply from time T2 to T3 and gradually from time T3 to T4. This is because the width of the pulse width modulation signal PWMi is extremely narrow, so that the response of the preceding regulator cannot catch up.

{Circle around (2)} From time T0 to time T4, each waveform operation similarly transits after time T4.

As described above, the LED drive circuit device 1 shown in FIG. 1 boosts and controls the output voltage Vout only when the pulse width modulation signal is at a high level. When the on-duty ratio of the pulse width modulation signal is low, the ability to adjust the output voltage Vout is insufficient. This causes a problem that the LED strings 4_1 to 4_n cannot maintain sufficient luminance.

(2nd Embodiment)
FIG. 3 is a circuit diagram showing an LED drive circuit device 1A according to the second embodiment. The LED drive circuit device 1A shown in FIG. 3 overcomes the above-mentioned disadvantages existing in the LED drive circuit device 1 shown in FIG.

The LED drive circuit device 1A is largely different from the LED drive circuit device 1 in the circuit configuration of the LED driver 5A. More specifically, the LED driver 5A is different from the LED driver 5 included in the LED drive circuit device 1 in that an operational amplifier 13 is used. The operational amplifier 13 is configured by a transconductance amplifier called OTA (Operative @ Transconductance @ Amp). The OTA has a high output impedance and outputs a current proportional to the difference between two input voltages of the OTA. The output stage of the OTA employed in the present embodiment is configured by a push-pull system. By the push-pull method, it is possible to control the output voltage Vout based on two currents, a source current flowing from the operational amplifier 13 to the feedback terminal FB side and a sink current drawn from the feedback terminal FB side to the operational amplifier 13 side. The use of OTA in an LED drive circuit device is disclosed in Patent Document 2.

When the minimum voltage of the LED terminal voltages VLED1 to VLEDn is lower than the reference voltage VREF, the sink current Isi that draws a constant current from the common connection node Nc to the operational amplifier 13 via the external terminal substantially causes the voltage dividing resistor R2 to operate. The output voltage Vout is controlled such that Vout = VREF + Vf_max so that the resistance value decreases.

On the other hand, when the LED terminal voltage VLED_min is higher than the reference voltage VREF, the source current Iso, which is a constant current, flows from the operational amplifier 13 side to the common connection node Nc side via the current output terminal TCFB, thereby realizing the voltage dividing resistor R2. The output voltage Vout is controlled such that Vout = VREF + Vf_max so that the actual resistance value increases. Control of the output voltage Vout by these two currents cannot be expected in the LED drive circuit device 1 shown in FIG.

Here, the LED driver 5A also has an OR circuit 51. The pulse width modulation signals PWM1 to PWMn are input to the OR circuit 51. The output of the OR circuit 51 is input to the operational amplifier 13. When at least one of the pulse width modulation signals PWM1 to PWMn is at a high level, the output of the OR circuit 51 is at a high level. When all of the pulse width modulation signals PWM1 to PWMn are at a low level, the output of the OR circuit 51 is at a low level. Become. The operational amplifier 13 stops current output when the output of the OR circuit 51 is at a low level, and outputs a current corresponding to a comparison result between the LED terminal voltage VLED_min and the reference voltage VREF when the output of the OR circuit 51 is at a high level, or And outputs a constant current.

In the LED drive circuit device 1A shown in FIG. 3, if the switching control circuit 2 and the LED driver 5A are formed of different semiconductor integrated circuits (ICs), some of them may be combined with the LED strings 4_1 to 4_n. Can be applied. For example, it is possible to control the output voltage Vout based on the lowest voltage among the LED terminal voltages VLED1 to VLEDn without controlling the feedback voltage Vfb. If such a circuit configuration is desired, the current output terminal TCFB provided on the output side of the operational amplifier 13 may be connected to the phase compensation terminal COMP without connecting to the feedback terminal FB. In such a circuit configuration, the operational amplifier 13 replaces the error amplifier 6. At this time, if the magnitude of the output voltage Vout can be detected while the voltage dividing resistors R1 and R2 are connected to the feedback terminal FB in the same manner as that shown in FIG. It can be used as an overvoltage protection (OVP) terminal.

FIG. 4A is a timing chart when the LED drive circuit device 1 of FIG. 3 is driven at a relatively large on-duty ratio such that the on-duty ratio of the PWM signal is, for example, about 70%. Note that FIG. 4A is different from the timing charts of FIGS. 2A and 2B in that the output voltage Vout is controlled by both the source current Iso and the sink current Isi.

FIG. 4A (a) shows a pulse width modulation signal PWMi applied to the LED constant current source Csi from the PWM dimmer 11 of the LED driver 5A. The pulse width modulation signal PWMi has a high level H from time t0 to t2 and a low level L from time t2 to t5, and the high level H section TH is longer than the low level L section TL. It shows that the signal is large. Note that the waveform of the pulse width modulation signal PWMi transitions from time t5 to t9 and after time t9 in the same manner as from time t0 to t5.

4A (b) shows that the LED current ILEDi follows the high level H and the low level L of the pulse width modulation signal PWMi. In the LED current ILEDi, the pulse width modulation signal PWMi from time t0 to t2 flows in the high level H section, and does not flow in the low level L section from time t2 to t5, that is, the current flows intermittently. Note that the waveform of the LED current ILEDi transitions from time t5 to t9 and after time t9 in the same manner as from time t0 to t5.

FIG. 4A (c) shows the LED terminal voltage VLED_min which is the voltage of the LED connection terminal LED_i. When the LED current ILEDi flows at time t0, the LED terminal voltage VLED_min sharply decreases by the LED forward total voltage Vf_max, but the magnitude of the voltage is schematically higher than the reference voltage VREF. I have. Thereafter, until the time t1, the feedback is applied by the operational amplifier 13 so that the LED terminal voltage VLED_min becomes the same potential as the reference voltage VREF. When the reference voltage VREF reaches the reference voltage VREF at time t1, the operation is performed so that the potential is maintained at the reference voltage VREF until time t2 when the LED current ILEDi becomes the low level L. When the LED current ILEDi stops flowing between times t2 and t5, the LED terminal voltage VLED_min rises to a stable output voltage Vst so as to follow the output voltage Vout. In the figure, reference numeral Vf_max indicates the total forward voltage of the LED, and reference numeral Vso indicates a source current adjustment voltage adjusted by the source current Iso. The stable output voltage Vst is (VREF + Vso + Vf_max) obtained by adding the source current adjustment voltage Vso and the LED forward total voltage Vf_max to the reference voltage VREF.

At time t6, the LED terminal voltage VLED_min suddenly drops to the reference voltage VREF or lower for some reason. Also at this time, feedback is applied by the operational amplifier 13 so that the LED terminal voltage VLED_min becomes the same potential as the reference voltage VREF. Note that after time t9, the transition is made in the same manner as at times t0 to t5.

4D shows the sink current Isi flowing into the operational amplifier 13 via the current output terminal TCFB provided on the LED driver 5A side and the source current Iso flowing from the operational amplifier 13 via the current output terminal TCFB, respectively. The source current Iso starts flowing at time t0 when the LED terminal voltage VLED_min is higher than the reference voltage VREF, and increases as the LED terminal voltage VLED_min approaches the reference voltage VREF. At time t1, when the LED terminal voltage VLED_min reaches the reference voltage VREF, a constant source current Iso flows thereafter until time t2. From time t2 to time t5 in the section TL, the output of the OR circuit 51 becomes low level, and the operational amplifier 13 stops outputting current, so that the source current Iso stops flowing and becomes zero.

From time t5 to time t6, when the pulse width modulation signal PWMi is at a high level and the LED terminal voltage VLED_min is higher than the reference voltage VREF, the source current Iso flows. From time t6 to time t7, when the pulse width modulation signal PWMi is at the high level and the LED terminal voltage VLED_min is lower than the reference voltage VREF, the sink current Isi flows. Note that after time t9, the transition is made in the same manner as at times t0 to t5.

FIG. 4A (e) shows a transition state of the output voltage Vout. The output voltage Vout responds to the behavior of the sink current Isi or the source current Iso. From time t0 to t2, the output voltage Vout is operated so as to be maintained from the stable output voltage Vst to (VREF + Vf_max). At time t2, when the pulse width modulation signal PWMi goes low, the output voltage Vout gradually increases from time t2 to t4. The time t4 to t5 is maintained at the stable output voltage Vst.

出力 From time t5 to t6, the output voltage Vout gradually decreases, and from time t6 to t7, the output voltage Vout gradually increases. Note that after time t9, the transition is made in the same manner as at times t0 to t5.

As described above, in the LED drive circuit device 1A shown in FIG. 3, when the LED terminal voltage VLED_min is higher than the reference voltage VREF, the output voltage Vout is controlled by the source current Iso so that Vout = VREF + Vf_max. When the LED terminal voltage VLED_min is lower than the reference voltage VREF, the output voltage Vout is controlled by the sink current Isi so that Vout = VREF + Vf_max. In any case, even if the magnitude relationship between the LED terminal voltage VLED_min and the reference voltage VREF is reversed, the LED drive circuit device 1A shown in FIG. 3 can control the output voltage Vout to a predetermined magnitude.

FIG. 4B is a timing chart when the LED drive circuit device 1A is driven with a relatively small on-duty ratio, such as when the on-duty ratio of the PWM signal is, for example, about 2%. The driving condition is not necessarily in a good state as compared with the case where the on-duty ratio in FIG. 4A is relatively large, but the behavior is different from that in FIG.

FIG. 4B (a) shows the pulse width modulation signal PWMi applied to the LED constant current source Csi from the PWM dimming unit 11 of the LED driver 5A. The pulse width modulation signal PWMi is at a high level H between times T0 and T1, and at a low level L between times T1 and T4. This indicates that the signal TH having a shorter pulse duty ratio is shorter in the high level H section TH than in the low level L section TL. Note that after time T4, the waveform of the pulse width modulation signal PWMi transitions similarly to times T0 to T4.

4B (b) shows that the LED current ILEDi follows the high level H and the low level L of the pulse width modulation signal PWMi. In the LED current ILEDi, the pulse width modulation signal PWMi from time T0 to T1 flows in the high level H section, and does not flow in the low level L section from time T1 to T4, that is, the current flows intermittently. Note that after time T4, the waveform of the LED current ILEDi transitions similarly to times T0 to T4.

FIG. 4B (c) shows the LED terminal voltage VLED_min which is the voltage of the LED connection terminal LED_i. At the time T0 at which the LED current ILEDi starts to flow, the LED current suddenly drops by the LED total forward voltage Vf_max, but is higher than the reference voltage VREF, so that it gradually decreases toward the reference voltage VREF in the section from time T0 to T1. This is because feedback is applied by the operational amplifier 13 so that the LED terminal voltage VLED_min becomes the reference voltage VREF. However, at time T1, the LED terminal voltage VLED_min has not reached the reference voltage VREF. This is because the pulse width of the pulse width modulation signal PWMi is narrow, and the polarity of the pulse width modulation signal PWMi is inverted from the high level H to the low level L before the LED terminal voltage VLED_min reaches the reference voltage VREF. . In the section from time T1 to T4, since the LED current ILEDi is 0, the stable output voltage Vst is maintained. In the section from time T4 to T5, in which the pulse width modulation signal PWMi is in the high level section, the LED terminal voltage VLED_min is higher than the reference voltage VREF again, so that the source current Iso flows again.

Time T5 indicates a state in which the LED terminal voltage VLED_min sharply falls below the reference voltage VREF for some reason. Also at this time, feedback is applied by the operational amplifier 13 so that the LED terminal voltage VLED_min becomes the same potential as the reference voltage VREF. Therefore, the sink current Isi flows in the section between times T5 and T6. Note that, after time T8, transition is made in the same manner as time T0 to T4.

4B (d) shows the sink current Isi flowing into the operational amplifier 13 via the current output terminal TCFB provided on the LED driver 5A side, and the source current Iso flowing from the operational amplifier 13 via the current output terminal TCFB. The source current Iso starts to flow at time T0 when the LED terminal voltage VLED_min is higher than the reference voltage VREF, and increases as the LED terminal voltage VLED_min approaches the reference voltage VREF. From time T1 to T4, the source current Iso stops flowing and becomes 0.

ま で From time T4 to T5, when the pulse width modulation signal PWMi is at a high level and the LED terminal voltage VLED_min is higher than the reference voltage VREF, the source current Iso flows. From time T5 to time T6, when the pulse width modulation signal PWMi is at the high level and the LED terminal voltage VLED_min is lower than the reference voltage VREF, the sink current Isi flows. Note that, after the time T8, the transition is made in the same manner as the times T0 to T4.

FIG. 4B (e) shows a transition state of the output voltage Vout. The output voltage Vout responds to the behavior of the sink current Isi or the source current Iso. From time T0 to T1, the output voltage Vout is stepped down from the stable output voltage Vst to (VREF + Vf_max), but stops at time T1 because the width of the pulse width modulation signal PWMi is narrow. At time T1, when the pulse width modulation signal PWMi goes low, the output voltage Vout gradually increases from time T1 to T3. From time T3 to T4, the stable output voltage Vst is maintained.

出力 From time T4 to T5, the output voltage Vout gradually decreases, and from time T5 to T8, the output voltage Vout gradually increases. Here, the boosting according to the operation of the sink current Isi is performed from time T5 to T6, and the time T6 to T8 is based on the capability of the switching regulator. Note that, after the time T8, the transition is made in the same manner as the times T0 to T4.

As described above, in the LED drive circuit device 1A shown in FIG. 3, even when the pulse width of the pulse width modulation signal PWMi is narrow (the pulse duty ratio is small), the LED terminal voltage is the same as when the pulse width is wide. When VLED_min is higher than the reference voltage VREF, the output voltage Vout is controlled by the source current Iso so that Vout = VREF + Vf_max. When the LED terminal voltage VLED_min is lower than the reference voltage VREF, the output voltage Vout is controlled by the sink current Isi so that Vout = VREF + Vf_max.

As described with reference to FIGS. 4A and 4B, the LED drive circuit device 1A of FIG. 3 is different from the LED drive device circuit 1 of FIG. When it is higher than VREF, the output voltage Vout is stepped down and controlled. With such control, the output voltage Vout is always maintained at (VREF + Vf_max) or more even when the on-duty ratio of the pulse width modulation signal is low. Therefore, heat generation in the LED strings 4_1 to 4_n can be suppressed, and the LED strings 4_1 to 4_n can always maintain sufficient luminance.

(Third embodiment)
FIG. 5 is a circuit diagram showing an LED drive circuit device 1B according to the third embodiment. The LED drive circuit device 1B has an LED driver 5B as a difference from the first and second embodiments. The LED driver 5B particularly includes a selection comparator 14 and a source current supply unit 15. The LED driver 5B has LED connection terminals LED1 to LEDn as external terminals, and also has a feedback terminal FB1. The feedback terminal FB1 is a terminal for connecting to the common connection node Nc.

The selection comparator 14 has a function as a selector for selecting the lowest voltage among the input LED terminal voltages VLED1 to VLEDn, and a function as a comparator for comparing the selected lowest voltage with the reference voltage VREF. The selection comparator 14 outputs a high-level or low-level signal according to the comparison result.

The source current supply section 15 is a circuit section that supplies a source current Iso as a constant current to the common connection node Nc side, and includes a switch 15A formed of a p-channel MOS transistor, a constant current circuit 15B, and a current mirror circuit. 15C.

The power supply voltage Vcc is applied to the source of the switch 15A, and a constant current circuit 15B is arranged between the drain of the switch 15A and the ground. The output signal from the selection comparator 14 is input to the gate of the switch 15A, and the switch 15A is turned on and off according to the output level from the selection comparator 14.

The current mirror circuit 15C is composed of two transistors composed of p-channel MOS transistors. The source of one of the two transistors is connected to the source of the switch 15A, that is, the power supply voltage Vcc is applied. The drain of one transistor is connected to the drain of switch 15A. The source of the other transistor is connected to the source of the other transistor. The gates of the other transistor and one transistor are connected. The connection node and the drain of one transistor are short-circuited. The drain of the other transistor is connected to the feedback terminal FB1.

Here, the LED driver 5B also has an OR circuit 51. The pulse width modulation signals PWM1 to PWMn are input to the OR circuit 51. The output of the OR circuit 51 is input to the selection comparator 14. When at least one of the pulse width modulation signals PWM1 to PWMn is at a high level, the output of the OR circuit 51 is at a high level. When all of the pulse width modulation signals PWM1 to PWMn are at a low level, the output of the OR circuit 51 is at a low level. Become.

When the output of the OR circuit 51 is at a low level, the selection comparator 14 outputs a low-level output signal to the switch 15A. As a result, the switch 15A is turned on, and the constant current from the constant current circuit 15B flows through the switch 15A and does not flow through one of the transistors of the current mirror circuit 15C. Therefore, the source current Iso does not flow from the feedback terminal FB1. When the output of the OR circuit 51 is at a high level, the selection comparator 14 outputs an output signal of a level corresponding to the comparison result to the switch 15A. Thus, the switch 15A is turned on or off. When the output of the selection comparator 14 is at a high level and the switch 15A is off, the constant current from the constant current circuit 15B does not flow through the switch 15A but flows through one transistor of the current mirror circuit 15C. Therefore, the source current Iso flows from the feedback terminal FB1.

FIG. 6 is a timing chart when the LED drive circuit device 1B is driven. FIG. 6A shows a pulse width modulation signal PWMi applied from the PWM dimming unit 11 of the LED driver 5B to the LED constant current source Csi. The pulse width modulation signal PWMi is at a high level H during a section TH between times t0 and t2 and at a low level L during a section TL between times t2 and t4.

FIG. 6B shows the LED current ILEDi. FIG. 6C shows the LED terminal voltage VLED_min which is the voltage of the LED connection terminal LED_i. FIG. 6D shows the source current Iso flowing into the common connection node Nc from the feedback terminal FB1 by the source current supply unit 15. FIG. 6E shows a transition state of the output voltage Vout.

前 Before time t0, since the pulse width modulation signal PWMi is at the low level L, the LED current ILEDi does not flow. Further, the output of the OR circuit 51 becomes low level, the switch 15A is turned on, and the source current Iso does not flow. As a result, the output voltage Vout is determined by the voltage dividing resistors R1 and R2, and is controlled to the stable output voltage Vst. At this time, the LED terminal voltage VLED_min becomes the same stable output voltage Vst as the output voltage Vout.

When the pulse width modulation signal PWMi becomes the high level H at the time t0, the LED current ILEDi flows, and the LED terminal voltage VLED_min sharply decreases from the stable output voltage Vst by the LED forward total voltage Vf_max. Is higher than the reference voltage VREF. At this time, the output of the OR circuit 51 becomes high level, the output of the selection comparator 14 becomes high level, and the switch 15A is turned off. Therefore, the constant current flowing to the constant current circuit 15B by the current mirror circuit 15C is used as the source current Iso. Flows.

(4) When the source current Iso flows, the output voltage Vout is controlled to decrease, and accordingly, the LED terminal voltage VLED_min also decreases toward the reference voltage VREF. While the LED terminal voltage VLED_min is equal to or higher than the reference voltage VREF, the selection comparator 14 is at a high level, and the source current Iso continues to flow.

When the LED terminal voltage VLED_min becomes lower than the reference voltage VREF at time t1, the output of the selection comparator 14 becomes low level, and the switch 15A turns on. As a result, the constant current from the constant current circuit 15B does not pass through the current mirror circuit 15C but flows through the switch 15A, so that the source current Iso stops flowing.

If the source current Iso does not flow, the output voltage Vout is determined by the voltage dividing resistors R1 and R2, and the output voltage Vout rises. Accordingly, the LED terminal voltage VLED_min increases. When the LED terminal voltage VLED_min becomes equal to or higher than the reference voltage VREF, the output of the selection comparator 14 becomes high level, the switch 15A is turned off, and the source current Iso flows. When the source current Iso flows, the output voltage Vout and the LED terminal voltage VLED_min decrease.

動作 The above operation is repeated until time t2 when the pulse width modulation signal PWMi becomes the low level L. Thus, the selection comparator 14 repeats the on / off of the source current Iso by the source current supply unit 15, the LED terminal voltage VLED_min is controlled to the reference voltage VREF, and the output voltage Vout is controlled to VREF + Vf_max.

When the pulse width modulation signal PWMi goes low at time t2, the current ILEDi does not flow, the output of the OR circuit 51 goes low, the switch 15A is turned on, the source current Iso stops flowing, and the output voltage Vout changes at time t2. At t3, it rises until it reaches the stable output voltage Vst, and is controlled to be constant. The LED terminal voltage VLED_min sharply rises to VREF + Vf_max at time t2, and then rises to a stable output voltage Vst at time t3, and is controlled to be constant.

According to the present embodiment, when the pulse width modulation signal PWMi is at the high level H, it is possible to adjust the output voltage Vout suitable for the LED forward voltage, to maintain the LED brightness at a predetermined brightness, In addition, the power consumption can be suppressed by suppressing the output voltage Vout.

(Modification of Third Embodiment)
FIG. 7 is a diagram illustrating a configuration of an LED driver 50B according to a modification of the above-described third embodiment. As will be described later, the LED driver 50B has a configuration that is effective when a plurality of sets each including the LED strings 4_1 to 4_n are used.

The LED driver 50B has, in particular, a first selector 141, a second selector 142, and a comparator 143, and as external terminals, a minimum voltage output terminal VMINOUT, other driver connection terminals VOM1 to VOM3, and PWM. It has an input terminal PWMIN and a PWM output terminal PWMOUT.

The first selector 141 selects and outputs the lowest voltage among the input LED terminal voltages VLED1 to VLEDn. The second selection unit 142 receives the lowest voltage selected by the first selection unit 141 and the voltages applied to the other driver connection terminals VOM1 to VOM3. The other driver connection terminals VOM1 to VOM3 are terminals for connection with the lowest voltage output terminal VMINOUT of the other driver 50B, and a predetermined internal voltage is applied when not connected to the other driver 50B.

(4) The second selector 142 selects and outputs the lowest voltage selected from the lowest voltage selected by the first selector 141 and the voltage applied to each of the other driver connection terminals VOM1 to VOM3. The lowest voltage output terminal VMINOUT is connected to the output terminal of the second selector 142. Therefore, the lowest voltage selected by the second selector 142 can be output from the lowest voltage output terminal VMINOUT.

(5) The non-inverting input terminal (+) of the comparator 143 is connected to the output terminal of the second selector 142. The reference voltage VREF is applied to the inverting input terminal (−) of the comparator 143. The comparator 143 compares the lowest voltage selected by the second selector 142 with the reference voltage VREF, and outputs a result of the comparison as a high-level or low-level signal. The output signal of the comparator 143 is applied to the gate of the switch 15A in the source current supply unit 15.

The LED driver 50B also has an OR circuit 51. The voltage of the PWM input terminal PWMIN is input to the OR circuit 51 together with the pulse width modulation signals PWM1 to PWMn. The output of the OR circuit 51 is input to the comparator 143 and can be output from the PWM output terminal PWMOUT to the outside. When at least one of the pulse width modulation signals PWM1 to PWMn and the voltage of the PWM input terminal PWMMIN is at a high level, the output of the OR circuit 51 is at a high level, and all the voltages of the pulse width modulation signals PWM1 to PWMn and the PWM input terminal PWMIN Is low level, the output of the OR circuit 51 is low level.

When the output of the OR circuit 51 is at a low level, the comparator 143 outputs a low-level output signal to the switch 15A. As a result, the switch 15A is turned on, and the source current Iso does not flow from the feedback terminal FB1. When the output of the OR circuit 51 is at a high level, the comparator 143 outputs an output signal of a level corresponding to the comparison result to the switch 15A.

FIG. 8 is a diagram showing an example of a configuration in which a plurality of LED sets, which are sets of LED strings 4_1 to 4_n, are driven using a plurality of LED drivers 50B having such a configuration. Here, an example in which three LED sets G1 to G3 are driven will be described. The anode of each LED string in the LED sets G1 to G3 is connected to a line where the output voltage Vout is generated.

As shown in FIG. 8, in order to drive the LED sets G1 to G3, an LED driver 50B1 as a master and LED drivers 50B2 and 50B3 as slaves are used. The configuration of each of the LED drivers 50B1 to 50B3 is the same as that of the LED driver 50B of FIG. 7 described above, that is, the LED drivers 50B1 to 50B3 are the same. The cathodes of the LED strings in each of the LED sets G1 to G3 are connected to the LED connection terminals LED1 to LEDn of the LED drivers 50B1 to 50B3, respectively.

最低 The lowest voltage output terminal VMINOUT of the LED driver 50B2 is connected to the other driver connection terminal VOM1 of the LED driver 50B1. The other driver connection terminal VOM2 of the LED driver 50B1 is connected to the lowest voltage output terminal VMINOUT of the LED driver 50B3. The other driver connection terminal VOM3 of the LED driver 50B1 is short-circuited to an external terminal (not shown) (not shown) to which the power supply voltage Vcc is applied because another LED driver is not connected. The other driver connection terminals VOM1 to VOM3 of the LED drivers 50B2 and 50B3 are short-circuited to the VCC terminal because no other LED driver is connected.

(4) The feedback terminal FB1 of the LED driver 50B1 is connected to the common connection node Nc, but is not connected to the feedback terminals FB1 of the LED drivers 50B2 and 50B3. No connection is made to the lowest voltage output terminal VMINOUT of the LED driver 50B1.

(4) The PWM input terminal PWMIN of the LED driver 50B1 is connected to the PWM output terminal PWMOUT of the LED driver 50B2. The PWM input terminal PWMIN of the LED driver 50B2 is connected to the PWM output terminal PWMOUT of the LED driver 50B3. A low-level voltage is applied to the PWM input terminal PWMIN of the LED driver 50B3. No connection is made to the PWM output terminal PWMOUT of the LED driver 50B1.

With the configuration shown in FIG. 8, the lowest voltage among the LED terminal voltages VLED1 to VLEDn of the LED group G2 is selected and output from the lowest voltage output terminal VMINOUT of the LED driver 50B2 as a slave. Similarly, the lowest voltage output terminal VMINOUT of the LED driver 50B3 as a slave selects and outputs the lowest voltage among the LED terminal voltages VLED1 to VLEDn of the LED group G3.

In the LED driver 50B1 as a master, the lowest voltage input from the LED driver 50B2 to the other driver connection terminal VOM1, the lowest voltage input from the LED driver 50B3 to the other driver connection terminal VOM2, and the LED terminal related to the LED group G1. The lowest voltage among the voltages VLED1 to VLEDn is selected, and is output from the second selector 142 to the comparator 143. In the LED driver 50B1, the comparator 143 compares the selected minimum voltage with the reference voltage VREF, and the source current supply unit 15 transmits the feedback signal from the feedback terminal FB1 to the common connection node Nc according to the comparison result of the comparator 143. The on / off of the source current Iso to be supplied is switched.

In the LED driver 50B3, the output signal of the OR circuit 51 is output from the PWM output terminal PWMOUT and is input to the PWM input terminal PWMIN of the LED driver 50B2. In the LED driver 50B2, the output signal of the OR circuit 51 is output from the PWM output terminal PWMOUT, and is input to the PWM input terminal PWMIN of the LED driver 50B1. Accordingly, the output of the OR circuit 51 in the LED driver 50B1 becomes a high level when at least one of the pulse width modulation signals PWM1 to PWMn of the LED drivers 50B1 to 50B3 is at a high level, and the pulse width modulation signals of the LED drivers 50B1 to 50B3 are output. When all of PWM1 to PWMn are at the low level, the level becomes the low level.

Thereby, when the pulse width modulation signal PWMi is at the high level H, the LED terminal voltage VLED_min of the LED string having the maximum total LED forward voltage Vf_max of the LED sets G1 to G3 is controlled to the reference voltage VREF. The output voltage Vout is controlled to VREF + Vf_max. As described above, the plurality of LED groups G1 to G3 can be driven using the LED drivers 50B1 to 50B3 having a common configuration.

The LED driver 50B is not limited to being used to drive a plurality of LED sets, but may be used to drive only one LED set. In this case, only one LED driver 50B is used, and in the LED driver 50B, all other driver connection terminals VOM1 to VOM3 are short-circuited to the VCC terminal, and a low-level voltage is applied to the PWM input terminal PWMIN.

FIG. 9 is a plan view showing an example of a pin arrangement in an LED driver 50B as a semiconductor integrated circuit device (package product). Each pin is formed on the bottom surface of the semiconductor integrated circuit device (package product). Here, as an example, the configuration is such that 16 LED strings (ie, LED strings 4_1 to 4_16) can be connected.

The first side 501 extending in the horizontal direction of the rectangular LED driver 50B in plan view includes, in order, a pin EXTCLK, a pin VSYNC, a non-connection pin, pins LED1 to LED4, a non-connection pin, a pin LGND, a non-connection pin, and a pin. The LEDs 5 and 6 are arranged side by side in the horizontal direction.

The pin EXTCLK is a pin for inputting a clock signal. The pin VSYNC is a pin for inputting a synchronization signal. The pins LED1 to LED6 are pins for connecting the cathode of the LED string. The pin LGND is a ground pin of the constant current circuit. Non-connection pins are pins that are not connected.

On the second side 502 extending vertically from one end of the first side 501, the pins LED7, LED8, the non-connection pin, the pin LGND, the pin SDO, the pin PWMOUT, the pin TEST, the pin PWMIN, the pin LGND, and the non-connection Pins, pins LED9 and LED10 are arranged side by side in the vertical direction. The pin LED 7 is arranged so as to sandwich the intersection of the first side 501 and the second side 502 with the pin LED 6.

Pins LED7 to LED10 are pins for connecting the cathode of the LED string. The pin SDO is a data output pin. The pin PWMOUT is a PWM output terminal. Pin PWMIN is a PWM input terminal. The pin TEST is a pin for a test mode.

The third side 503 extends laterally from an end of the second side 502 that is not on the first side 501 side. That is, the third side 503 is vertically opposed to the first side 501. On the third side 503, the pins LED11, LED12, non-connection pin, pin LGND, non-connection pin, pins LED13 to LED16, non-connection pin, pin FB1, and pin VOM3 are arranged in order in the horizontal direction. The pin LED 11 is arranged so as to sandwich the intersection of the second side 502 and the third side 503 with the pin LED 10.

The -pin LEDs 11 to 16 are pins for connecting the cathode of the LED string. The pin FB1 is a pin for a feedback terminal, and corresponds to the feedback terminal FB1 in FIG. The pin VOM3 is a pin for connecting the pin VMINOUT of another LED driver, and corresponds to the other driver connection terminal VOM3 in FIG.

The fourth side 504 extends in the vertical direction from the end of the third side 503 which is not on the second side 502 side. That is, the fourth side 504 faces the second side 502 in the lateral direction. On the fourth side 504, a pin VOM2, a pin VOM1, a pin VMINOUT, a pin ISET, a pin VREG, a pin VCC, a pin EN, a pin GND, a pin FAIL, a pin SCS, a pin SDI, and a pin SCLK are arranged in order in the vertical direction. Be placed. The pin VOM2 is arranged so as to sandwich the intersection of the third side 503 and the fourth side 504 with the pin VOM3. The pin SCLK is arranged so as to sandwich the intersection of the first side 501 and the fourth side 504 with the pin EXTCLK.

The pins VOM2 and VOM1 are pins for connecting the pin VMINOUT of another LED driver, and correspond to the other driver connection terminals VOM2 and VOM1 in FIG. The pin VMINOUT is a pin for outputting the lowest LED terminal voltage of the 16 LED strings, and corresponds to the lowest voltage output terminal VMINOUT in FIG. The pin ISET is a pin for connecting a resistor for setting the LED current. The pin VREG is a pin for outputting an internal voltage. Pin VCC is a VCC terminal. Pin EN is a pin for setting a standby mode or an operation mode. The pin GND is a pin for ground connection. The pin FAIL is a pin for abnormality detection output. The pin SCS is a chip selection setting pin. The pin SDI is a data input pin. The pin SCLK is a clock input pin.

7, the output terminal of the second selector 142 may be connected to the input terminal of the operational amplifier instead of the comparator 143, for example. As the operational amplifier, those described in the first and second embodiments can be used.

(Fourth embodiment)
FIG. 10 is a circuit diagram showing an LED drive circuit device according to the fourth embodiment. The LED drive circuit device according to the present embodiment has an advantage that the wiring can be simplified as compared with the LED drive circuit device shown in FIG.

The LED drive circuit device according to the present embodiment includes a switching regulator (not shown in FIG. 10), and includes a plurality of sets of LED drivers 5B and LED strings 4_1 to 4n. The switching regulator may have, for example, the same configuration as the above-described switching regulator of FIG. Here, an example in which three LED sets, which are sets composed of the LED strings 4_1 to 4n, are driven, that is, an example in which three LED sets G1 to G3 are driven will be described. The anode of each LED string in the LED sets G1 to G3 is connected to a line where the output voltage Vout is generated.

ＬＥＤAs shown in FIG. 10, the LED drivers 5B1 to 5B3 are used to drive the LED sets G1 to G3. The configuration of each of the LED drivers 5B1 to 5B3 is the same as that of the LED driver 5B of FIG. 5 described above, that is, the LED drivers 5B1 to 5B3 are the same. The cathodes of the LED strings in each of the LED sets G1 to G3 are connected to the LED connection terminals LED1 to LEDn of the LED drivers 5B1 to 5B3, respectively.

Then, as shown in FIG. 10, the feedback terminals FB1 of the LED drivers 5B1 to 5B3 are connected to the common connection node Nc.

Hereinafter, all the LED forward total voltages Vf1 to Vfn of the LED strings 4_1 to 4n forming the LED set G1 are 3.2 [V], and the total LED forward direction voltages of the LED strings 4_1 to 4n forming the LED set G2 are set. Vf1 to Vfn are all 3.1 [V], LED forward total voltages Vf1 to Vfn of the LED strings 4_1 to 4n constituting the LED group G3 are all 3.0 [V], and the LED drivers 5B1 to 5B3 The general operation of the LED drive circuit device according to the present embodiment will be described by taking as an example a case where the reference voltages VREF used in the above are all 1.0 [V].

For example, when the LED sets G1 to G3 are switched from the unlit state to the lit state while the output voltage Vout is 5.0 [V], the source current Iso from the feedback terminals FB1 of the LED drivers 5B1 to 5B3 to the common connection node Nc. Start flowing. As a result, the output voltage Vout starts to decrease.

(4) When the output voltage Vout drops to 4.2 [V], the LED terminal voltage LED_min becomes equal to or lower than the reference voltage VREF in the LED driver 5B1, so that the source current Iso is not output from the feedback terminal FB1 of the LED driver 5B1. Since the LED terminal voltage LED_min is still higher than the reference voltage VREF in the LED drivers 5B2 and 5B3, the source current Iso is output from each feedback terminal FB1 of the LED drivers 5B2 and 5B3.

When the output voltage Vout further decreases and reaches 4.1 [V], the LED terminal voltage LED_min becomes equal to or lower than the reference voltage VREF not only in the LED driver 5B1 but also in the LED driver 5B2, so that each feedback of the LED drivers 5B1 and 5B2 is performed. The source current Iso is no longer output from the terminal FB1. Since the LED terminal voltage LED_min is still higher than the reference voltage VREF in the LED driver 5B3, the source current Iso is output from the feedback terminal FB1 of the LED driver 5B3.

When the output voltage Vout further decreases and reaches 4.0 [V], the LED terminal voltage LED_min becomes equal to or lower than the reference voltage VREF not only in the LED drivers 5B1 and 5B but also in the LED driver 5B3, so that the LED drivers 5B1 to 5B3 The source current Iso is no longer output from each feedback terminal FB1. In this state, the respective cathode voltages applied to the LED connection terminals LED1 to LEDn of the LED driver 5B1 become 0.8 [V] (= 4.0 [V] -3.2 [V]), and the LED driver 5B2 The respective cathode voltages applied to the LED connection terminals LED1 to LEDn are 0.9 [V] (= 4.0 [V] -3.1 [V]), and the LED connection terminals LED1 to LEDn of the LED driver 5B3. Becomes 1.0 [V] (= 4.0 [V] -3.0 [V]). Therefore, if the minimum drive voltage of the LED constant current sources Cs1 to Csn (the minimum voltage required for driving the LED constant current sources) is 0.8 [V] or less, the LED sets G1 to G3 light without any problem. I do.

Actually, since the total forward voltage of each LED of each LED string varies, all LEDs are considered in consideration of the variation of the total forward voltage of each LED of each LED string and the minimum drive voltage of each LED constant current source. What is necessary is just to set the reference voltage VREF of each LED driver so that a string may be lighted without any problem.

FIG. 11 is a plan view showing an example of a pin arrangement in the LED drivers 5B1 to 5B3 according to the fourth embodiment. Each pin is formed on the bottom surface of the semiconductor integrated circuit device (package product). Here, as an example, the configuration is such that 16 LED strings (ie, LED strings 4_1 to 4_16) can be connected. A first side 501 extending in the horizontal direction of the LED driver 5B having a rectangular shape in a plan view includes, in order, a pin EXTCLK, a pin VSYNC, a non-connection pin, pins LED1 to LED4, a non-connection pin, a pin LGND, a non-connection pin, and a pin. The LEDs 5 and 6 are arranged side by side in the horizontal direction. The pin EXTCLK is a clock signal input pin. The pin VSYNC is a pin for inputting a synchronization signal. The pins LED1 to LED6 are pins for connecting the cathode of the LED string. The pin LGND is a ground pin of the constant current circuit. Non-connection pins are pins that are not connected. A second side 502 extending in the vertical direction from one end of the first side 501 has pins LED7, LED8, a non-connection pin, a pin LGND, a pin SDO, a pin TEST1, a pin TEST2, a non-connection pin, a pin LGND, and a non-pin. The connection pins, the pins LED9 and LED10 are arranged side by side in the vertical direction. The pin LED 7 is arranged so as to sandwich the intersection of the first side 501 and the second side 502 with the pin LED 6. The pins LED7 to LED10 are pins for connecting the cathode of the LED string. The pin SDO is a data output pin. The pins TEST1 and TEST2 are pins for a test mode. The third side 503 extends laterally from an end of the second side 502 that is not on the first side 501 side. That is, the third side 503 is vertically opposed to the first side 501. On the third side 503, the pins LED11, LED12, non-connection pin, pin LGND, non-connection pin, pins LED13 to LED16, non-connection pin, pin FB1, and non-connection pin are arranged in order in the horizontal direction. The pin LED 11 is arranged so as to sandwich the intersection of the second side 502 and the third side 503 with the pin LED 10. The pins LED11 to LED16 are pins for connecting the cathode of the LED string. The pin FB1 is a pin for a feedback terminal, and corresponds to the feedback terminal FB1 in FIG. The fourth side 504 extends in the vertical direction from an end of the third side 503 which is not on the second side 502 side. That is, the fourth side 504 faces the second side 502 in the lateral direction. On the fourth side 504, a non-connection pin, a non-connection pin, a non-connection pin, a pin ISET, a pin VREG, a pin VCC, a pin EN, a pin GND, a pin FAIL, a pin SCS, a pin SDI, and a pin SCLK are sequentially arranged in the vertical direction. Are arranged side by side. The pin SCLK is arranged so as to sandwich the intersection of the first side 501 and the fourth side 504 with the pin EXTCLK. The pin ISET is a pin for connecting a resistor for setting the LED current. The pin VREG is a pin for outputting an internal voltage. Pin VCC is a VCC terminal. Pin EN is a pin for setting a standby mode or an operation mode. The pin GND is a pin for ground connection. The pin FAIL is a pin for abnormality detection output. The pin SCS is a chip selection setting pin. The pin SDI is a data input pin. The pin SCLK is a clock input pin.

The dimming control of the LED drive circuit device shown in FIG. 10 is performed by, for example, a microcomputer (not shown). The microcomputer transmits, for example, the dimming data DATA shown in FIG. 12 to the pin SDI of the LED driver 5B1. The LED driver 5B1 outputs the dimming data DATA received at the pin SDI from the pin SDO.

(4) The pin SDO of the LED driver 5B1 and the pin SDI of the LED driver 5B2 are connected by wiring. Therefore, the LED driver 5B1 transmits the dimming data DATA to the pin SDI of the LED driver 5B2. The LED driver 5B2 outputs the dimming data DATA received at the pin SDI from a pin SDO.

(4) The pin SDO of the LED driver 5B2 and the pin SDI of the LED driver 5B3 are connected by wiring. Therefore, the LED driver 5B2 transmits the dimming data DATA to the pin SDI of the LED driver 5B3. The setting data of the reference voltage VREF is also transmitted via the pins SDI and SDO in the same manner as the dimming data DATA. Unlike the present embodiment, at least one of the non-connection pins in the present embodiment is replaced with a reference voltage VREF setting pin, and the reference voltage is set according to the circuit constant of a passive element connected to the reference voltage VREF setting pin. The value of VREF may be set.

The microcomputer sends the pulse signal P1 shown in FIG. 12 to the pin VSYNC of the LED driver 5B1, sends the pulse signal P2 shown in FIG. 12 to the pin VSYNC of the LED driver 5B2, and sends the pulse signal P3 shown in FIG. Send to pin 5SYNC of 5B3. The PWM dimming unit 11 of each of the LED drivers 5B1 to 5B3 recognizes the dimming data in the high level period of the pulse signal received at the pin VSYNC of each of the LED drivers 5B1 to 5B3, and determines the pulse width based on the recognized dimming data. Modulation signals PWM1 to PWMn are generated.

In the present embodiment, the LED driver 5B shown in FIG. 5 is used, but the LED driver 5 shown in FIG. 1 or the LED driver 5A shown in FIG. 3 may be used instead of the LED driver 5B. Further, in the present embodiment, the number of LED drivers is three, but the number of LED drivers may be a plurality other than three. Further, in the present embodiment, a plurality of LED strings are connected to each LED driver, but one LED string may be connected to one LED driver.

Each of the embodiments described above is an example in all respects, and should not be considered to be restrictive. The technical scope of the present invention is defined not by the description of the embodiments but by the claims. It is to be understood that all changes that fall within the meaning and scope equivalent to the appended claims are included.

For example, in each of the above embodiments, the switching regulator is used as the power supply device, but a linear regulator may be used instead of the switching regulator.

According to the present invention, the output voltage of the power supply device used for driving the light emitting element can be controlled to a predetermined value by a relatively simple circuit, so that the power supply efficiency can be improved. Therefore, industrial applicability is extremely high.

1, 1A LED drive circuit device 2 Switching control circuit 3 Output circuit 4_1 to 4_n LED string 5, 5A LED driver (constant current driver)
Reference Signs List 6 error amplifier 7 oscillator 8 slope signal generation circuit 9 PWM comparator 10 PWM control circuit 11 PWM dimming unit 12 operational amplifier
13 Operational amplifier (transconductance amplifier)
C1, C2 Capacitor COMP Phase compensation terminal Cs1 to Csn LED constant current source ILED1 to ILEDn LED current Isi Sink current Iso Source current L1 Inductor LED1 to LEDn LED connection terminal OPFB, TCFB Current output terminal PWM1 to PWMn PWM dimming signal R1 to R3 Voltage dividing resistor R4 Resistance S1 Switching element S2 Synchronous rectification element TCFB Current output terminal Tr1 Transistor Vf1 to Vfn LED forward total voltage VLED1 to VLEDn LED terminal voltage VREF Reference voltage Vt1 First reference voltage Vsl Slope voltage Vst Stable output voltage 1B LED Drive circuit device 5B, 50B, 50B1 to 50B3 LED driver 51 OR circuit 14 Selection comparator 15 Source current supply Supply unit 15A Switch 15B Constant current circuit 15C Current mirror circuit FB1 Feedback terminal 141 First selection unit 142 Second selection unit 143 Comparator VOM1 to VOM3 Other driver connection terminal VMINOUT Minimum voltage output terminal PWMIN PWM input terminal PWMOUT PWM output terminal G1 to G3 LED group

Claims (12)

1. An LED drive circuit device including a power supply device, a plurality of sets of an LED driver and at least one LED string,
   The power supply,
   A feedback voltage generation circuit that generates a feedback voltage obtained by dividing the output voltage of the power supply device;
   An output voltage adjustment unit that varies the output voltage according to the feedback voltage,
   Each of the at least one LED string is
   A plurality of LEDs are connected in series using the output voltage as a driving voltage source,
   Each of the LED drivers,
   A plurality of LED constant current sources that can be individually connected to the at least one LED string via LED connection terminals;
   A selection unit that selects, as the detection LED connection terminal, the LED connection terminal of the LED string having the largest LED forward total voltage among the at least one LED string;
   A comparing unit that compares the voltage of the detection LED connection terminal with a first reference voltage;
   A feedback terminal that outputs a current based on the output of the comparison unit,
   The feedback voltage generation circuit includes a first voltage dividing resistor connected to an output terminal of the power supply device and a second voltage dividing resistor connected to a ground potential and connected in series with the first voltage dividing circuit,
   The LED drive circuit device, wherein the plurality of sets of the feedback terminals are connected to a common connection node between the first voltage dividing resistor and the second voltage dividing resistor.
2. 2. The LED drive circuit device according to claim 1, wherein each of the LED drivers has an operational amplifier having the selection unit and the comparison unit, and an output of the operational amplifier is coupled to the feedback terminal.
3. The LED drive circuit according to claim 2, wherein the feedback terminal outputs a sink current drawn from the common connection node to the feedback terminal when a voltage of the detection LED connection terminal is lower than the first reference voltage. apparatus.
4. 4. The LED drive circuit device according to claim 3, wherein each of the plurality of sets of third voltage dividing resistors is connected between the common connection node and each of the plurality of sets of the feedback terminals. 5.
5. The LED drive circuit device according to claim 2, wherein the operational amplifier is a transconductance amplifier.
6. The LED drive circuit according to claim 5, wherein the feedback terminal outputs a sink current drawn from the common connection node to the feedback terminal when a voltage of the detection LED connection terminal is lower than the first reference voltage. apparatus.
7. The LED drive circuit according to claim 5, wherein when the voltage of the detection LED connection terminal is higher than the first reference voltage, the feedback terminal outputs a source current flowing from the feedback terminal to the common connection node. apparatus.
8. Each of the LED drivers has a source current supply unit that switches on and off a source current flowing to a common connection node between the first voltage dividing resistor and the second voltage dividing resistor according to an output of a comparator serving as the comparing unit. The LED drive circuit device according to claim 1.
9. The source current supply unit includes a switch that is turned on and off according to an output of the comparator, a constant current circuit connected to the switch, and a current mirror circuit,
   The LED drive circuit device according to claim 8, wherein the switch is connected between both ends of one transistor in the current mirror circuit.
10. 10. The LED drive circuit device according to claim 1, wherein the LED constant current source generates a current intermittently according to a first pulse width modulation signal.
11. The power supply,
    A switching element that allows current to flow intermittently through the inductor,
    A smoothing unit that smoothes an inductor current flowing through the inductor, and outputs the output voltage to the output terminal;
    A slope signal generation circuit, an error amplifier, and a PWM comparator;
    The slope signal generation circuit generates a triangular or sawtooth waveform slope signal, the error amplifier compares the feedback voltage and a second reference voltage, and outputs a difference voltage between the two as an error voltage, and the PWM comparator Comparing the error voltage with the slope signal, outputting a second pulse width modulation signal having a pulse width according to the pulse comparison result, and turning on or off the switching element according to the second pulse width modulation signal. The LED drive circuit device according to any one of claims 1 to 10, which is controlled to:
12. An electronic device comprising the LED drive circuit device according to any one of claims 1 to 11.

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