WO2020065816A1 - Comparison circuit, zero-point detection circuit, ac power regulator, and signal comparison method - Google Patents

Comparison circuit, zero-point detection circuit, ac power regulator, and signal comparison method Download PDF

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Publication number
WO2020065816A1
WO2020065816A1 PCT/JP2018/035897 JP2018035897W WO2020065816A1 WO 2020065816 A1 WO2020065816 A1 WO 2020065816A1 JP 2018035897 W JP2018035897 W JP 2018035897W WO 2020065816 A1 WO2020065816 A1 WO 2020065816A1
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low
comparison
signal
hysteresis
output
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PCT/JP2018/035897
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French (fr)
Japanese (ja)
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茂文 後藤
裕久 吉川
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理化工業株式会社
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Priority to PCT/JP2018/035897 priority Critical patent/WO2020065816A1/en
Priority to JP2020547709A priority patent/JPWO2020065816A1/en
Publication of WO2020065816A1 publication Critical patent/WO2020065816A1/en

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    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00Details of apparatus for conversion
    • H02M1/08Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K5/00Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01Shaping pulses
    • H03K5/08Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding

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  • the present invention relates to a comparison circuit, a zero point detection circuit, an AC power regulator, and a signal comparison method.
  • a comparison circuit for the comparison.
  • a zero point detection circuit for detecting a zero cross point of an AC power supply.
  • the zero point detection circuit is used, for example, in an AC power regulator that adjusts the voltage of a commercial AC power supply by a phase control method and supplies the voltage to a load.
  • Patent Document 1 discloses a technique for more accurately detecting a zero-cross point in such a phase control type AC power regulator.
  • a filter circuit for removing noise is provided.
  • a comparator When a comparator is used as the comparison circuit, a comparator with hysteresis is used.
  • a filter circuit When a filter circuit is provided, there is a problem that the phase of a signal is delayed by the filter circuit, and the detection of a zero cross point is delayed in a zero point detection circuit or the like.
  • the circuit becomes complicated and the cost increases.
  • a comparator with hysteresis there is a problem that detection of a zero-cross point in a zero-point detection circuit or the like is delayed according to the hysteresis width.
  • the present invention has been made in view of the above circumstances, and is a comparison circuit for comparing the magnitudes of signals.
  • the comparison circuit can prevent a delay from occurring in the comparison result and has a relatively simple circuit configuration. , A zero point detection circuit, an AC power regulator, and a signal comparison method.
  • a comparison circuit that outputs a comparison result of a level of a reference signal and a comparison signal, wherein the two input circuits input the reference signal and the comparison signal to each of the two hysteresis comparators; The output signal is changed from High to Low or from Low to High based on a bias circuit for applying a different bias to the reference signal input to the hysteresis comparator and the output inversion of one of the two hysteresis comparators from High to Low.
  • An output circuit that inverts the output signal from Low to High or from High to Low based on the output inversion of the other hysteresis comparator from Low to High.
  • (Configuration 2) The comparison circuit according to Configuration 1, wherein a positive bias is applied to a reference signal input to one of the hysteresis comparators, and a negative bias is applied to a reference signal input to the other hysteresis comparator.
  • a comparison circuit that outputs a comparison result of a level of a reference signal and a comparison signal, wherein the two input circuits input the reference signal and the comparison signal to each of the two hysteresis comparators; The output signal is changed from High to Low or from Low to High based on a bias circuit for applying a different bias to the comparison signal input to the hysteresis comparator and the output inversion of one of the two hysteresis comparators from High to Low.
  • An output circuit that inverts the output signal from Low to High or from High to Low based on the output inversion of the other hysteresis comparator from Low to High.
  • (Configuration 8) A zero point detection circuit that performs zero point detection of an AC power supply waveform by using the comparison circuit according to any one of Configurations 1 to 7, setting the reference signal to a zero point, and using the comparison signal as an AC power supply waveform signal.
  • An AC power regulator comprising: a trigger angle output unit that outputs an angle; and a thyristor control unit that controls a thyristor based on the trigger angle.
  • a comparison method for outputting a comparison result of a level of a reference signal and a comparison signal wherein two hysteresis comparators are used to input the reference signal and the comparison signal to each of the two hysteresis comparators. Applying a different bias to the reference signal input to the hysteresis comparator, and inverting the output signal from high to low or from low to high based on the output inversion of one of the two hysteresis comparators from high to low. And inverting the output signal from low to high or from high to low based on the output inversion of the other hysteresis comparator from low to high.
  • a comparison method for outputting a comparison result between a reference signal and a comparison signal wherein two hysteresis comparators, the reference signal and the comparison signal are input to each of the two hysteresis comparators, and the two hysteresis comparators Applying a different bias to the comparison signal input to the comparator, and inverting the output signal from high to low or from low to high based on the output inversion of one of the two hysteresis comparators from high to low. And inverting the output signal from Low to High or from High to Low based on the output inversion of the other hysteresis comparator from Low to High.
  • comparison circuit of the present invention it is possible to provide a comparison circuit capable of preventing a delay in the comparison result with a relatively simple circuit configuration.
  • FIG. 1 is a schematic block diagram illustrating a configuration of an AC power regulator according to an embodiment of the present invention.
  • FIG. 2 is a diagram illustrating a configuration of a zero-point detection circuit (comparison circuit) according to the embodiment.
  • the flowchart which shows the outline of the processing operation of the microcomputer (output circuit) with which the zero point detection circuit (comparison circuit) is provided Explanatory drawing for explaining the operation of the zero point detection circuit (comparison circuit) Explanatory diagram for explaining a conventional problem in zero point detection Diagram showing the configuration of the comparison circuit Explanatory diagram for explaining another operation example of the zero point detection circuit (comparison circuit)
  • FIG. 1 is a block diagram schematically illustrating a configuration of an AC power regulator according to Embodiment 1 of the present invention.
  • the AC power regulator 100 of the present embodiment is an AC power regulator that controls power supply to a load by phase control. More specifically, the AC power regulator 100 switches the switch 600 (for example, a relay or a breaker) and the fuse 60 based on a target value input from a controller (temperature controller) 200 which is an external device.
  • a controller temperature controller
  • the AC power regulator 100 includes a zero point detection unit 10 for detecting a zero point of an AC power supply waveform, an output target value trigger angle conversion unit 20 for converting an output target value to a trigger angle, and an AC detected by the zero point detection unit 10.
  • a trigger angle output unit 30 that outputs a trigger angle based on a zero-cross point of the power supply waveform, a thyristor control unit 40 that controls a thyristor based on the trigger angle, and an AC power supply 500 that receives a timing of the firing angle and the zero-cross point.
  • a thyristor 50 that switches power supply to the heater of the control target 300 and a fuse 60 are provided.
  • the phase control method in the AC power regulator 100 and the configuration therefor are the same as the conventional AC power regulator except for the zero point detection unit 10, so that a further detailed description is omitted here.
  • the zero point detecting unit 10 will be described.
  • FIG. 1 the configuration is described separately for each function. However, it does not necessarily indicate that the configuration is divided into hardware.
  • a known general-purpose device such as a PLC, an MCU, or a microcomputer may be used.
  • Each configuration may be implemented as software by using.
  • each component may be configured as hardware, for example, may be configured using an FPGA or the like, or may be configured as dedicated hardware using an ASIC or the like.
  • FIG. 2 is a diagram illustrating a circuit configuration (zero point detection circuit) of the zero point detection unit 10.
  • the zero point detection unit (zero point detection circuit) 10 inputs two hysteresis comparators 2A and 2B, and a reference signal (zero point) and a comparison signal (AC power supply waveform signal) to each of the two hysteresis comparators 2A and 2B.
  • An output circuit that inverts the output signal from High to Low or Low to High on the basis of the output inversion to, and inverts the output signal from Low to High or from High to Low based on the output inversion from the other hysteresis comparator Low to High.
  • a microcomputer Comprises a Tsu bets 5, the level adjusting circuit 4A of the input signal to the microcomputer unit 5 (hysteresis comparator 2A, the output signal from 2B), and 4B, the.
  • the resistors R1A, R2A (R1B, R2B) provided in the input circuit 1A (1B) are voltage dividing circuits for adjusting the amplitude of the AC power supply 500 to an appropriate level as an input to the hysteresis comparator 2A (2B). (In this embodiment, the amplitude is adjusted to ⁇ 4 V).
  • the resistors R3A, R4A (R3B, R4B) provided in the hysteresis comparator 2A (2B) are voltage dividing circuits for adjusting the hysteresis width. In the present embodiment, the hysteresis width of each of the hysteresis comparators 2A and 2B is 2V.
  • the resistors R4A, R5A (R4B, R5B) provided in the bias circuit 3A (3B) are voltage dividing circuits for adjusting a bias amount.
  • the absolute value of the positive bias is substantially the same as the absolute value of the negative bias, and the absolute value of the bias is substantially 1 / of the hysteresis width of the hysteresis comparator.
  • steps 301 to 304 is a loop processing that repeatedly operates while detecting the zero-cross point of the AC power supply 500.
  • step 301 it is monitored whether or not the signal from the hysteresis comparator 2A has changed from low to high. If the signal has changed from low to high, the process proceeds to step 303.
  • step 303 the output from the output terminal 6 is inverted from Low to High.
  • step 302 it is monitored whether or not the signal from the hysteresis comparator 2B has changed from High to Low.
  • Step 304 the output from the output terminal 6 is inverted from High to Low.
  • FIG. 4 is an explanatory diagram for explaining the operation of the zero point detection unit (zero point detection circuit) 10.
  • 4 shows the waveform of the AC power supply 500 and the hysteresis of each of the hysteresis comparators 2A and 2B, and the lower side of FIG. 4 shows the output waveforms of the hysteresis comparators 2A and 2B and the microcomputer unit 5 (output terminal 6).
  • 3 shows an output waveform from the oscilloscope.
  • the output waveform of the hysteresis comparator 2A switches between High / Low when the waveform of the AC power supply 500 exceeds + 2V which is the upper end of the hysteresis, and when the waveform of the AC power supply 500 falls below 0V which is the lower end of the hysteresis. Is switched between Low / High. Therefore, when the voltage falls below 0 V which is the lower end side of the hysteresis, the zero cross point is represented without delay.
  • the output waveform of the hysteresis comparator 2B switches between High / Low when the waveform of the AC power supply 500 exceeds 0V which is the upper end of the hysteresis, and the waveform of the AC power supply 500 falls below -2V which is the lower end of the hysteresis. At this time, Low / High is switched. Therefore, when the voltage exceeds 0 V, which is the upper end of the hysteresis, the zero cross point is represented without delay.
  • a signal for switching between High and Low is output from the output terminal 6 based on the switching between High and Low when the waveform exceeds 0 V, which is the upper end of the hysteresis. Therefore, the output from the output terminal 6 has a waveform representing the zero-cross point of the AC power supply 500 without delay.
  • the zero point detection unit (zero point detection circuit) 10 in the AC power regulator 100 of the present embodiment the zero cross point of the AC power supply 500 can be detected without delay. Further, a circuit capable of detecting the zero-cross point without delay and reducing the influence of noise can be realized with a relatively simple circuit configuration.
  • FIG. 5 is a diagram for explaining a problem that occurs in the conventional AC power regulator 100 due to a certain delay in measuring the zero-cross point of the AC power supply.
  • FIG. 5A when the power supply waveform of the AC power supply is a normal waveform, even if the circuit configuration has a certain delay in the measurement of the zero-cross point, the delay time is subtracted. There is no problem if processing is performed. That is, there is no problem if the call timing of the trigger point is calculated from the time point at which the (n-1) -th zero point is detected, taking into account the delay time of the zero point detection.
  • FIG. 5B shows a situation in which the phase of the power supply waveform has advanced in this manner.
  • the trigger point is set at the same timing as in FIG. 5A, but as a result of the advance of the phase of the power supply waveform, in FIG. 5B, the zero-cross point comes before the trigger point.
  • the device cannot determine whether the phase is advanced or not, and, as in FIG. 5A, triggers after taking into account the delay time of zero point detection from the time point at which the (n-1) th zero point is detected. This is because the points are set.
  • the zero point detection unit (zero point detection circuit) 10 in the AC power regulator 100 of the present embodiment the zero cross point of the AC power supply 500 can be detected without delay as described above. It is also possible to deal with such a problem.
  • the output signal of the hysteresis comparator 2A (2B) switches from High to Low when the waveform of the AC power supply 500 exceeds the upper end of the hysteresis.
  • the signal changes from low to high.
  • the output signal changes from low to high in response to the switching from low to high in the hysteresis comparator 2A, and changes from high to low in the hysteresis comparator 2B.
  • An example in which the output signal is switched from High to Low according to the switching of Low is described as an example, but the difference between High and Low in each signal can be changed as appropriate. That is, for example, High and Low of each output waveform on the lower side of FIG. 4 may be inverted (arbitrary combinations are possible, such as inverting all or inverting only one of the output waveforms). .
  • the zero point detection circuit in the AC power regulator has been described as an example.
  • the present invention is not limited to this, and a comparison circuit that outputs a comparison result of the level of a reference signal and a comparison signal, a signal comparison method Can be widely used as. That is, as shown in FIG. 6, a comparator circuit 12 having two hysteresis comparators and input terminals 111 and 112 to which a reference signal and a comparison signal are input are provided. (Which terminal receives the reference signal is arbitrary.
  • the output signal is inverted from High to Low or from Low to High based on the output inversion of the hysteresis comparator from High to Low, and the output signal is output from Low to High or High based on the output inversion of the other hysteresis comparator from Low to High.
  • Low An output circuit 15 for inverting, by the comparison circuit comprising a can compare any signals.
  • the output circuit is configured as software on the microcomputer unit 5 as an example. However, the output circuit may be configured as hardware using a dedicated circuit or the like.
  • a bias is applied to a reference signal, but a bias may be applied to a comparison signal.
  • a plus bias is applied to the signal input to one hysteresis comparator, and a minus bias is applied to the signal input to the other hysteresis comparator, so that the absolute values of the plus and minus biases are substantially the same.
  • the bias is approximately ⁇ of the hysteresis width.
  • the present invention is not limited to this, and the absolute values of the positive and negative biases are different, and the bias is input to both hysteresis comparators. It may be possible to apply a plus (or minus) bias to such a signal.
  • the upper end of the hysteresis of one hysteresis comparator and the lower end of the hysteresis of the other hysteresis comparator are the same, but some regions of both hysteresis overlap. Or may be such that there is an interval between both hysteresis.
  • the above points can be appropriately selected according to the signal to be compared and the purpose thereof. For example, FIG. 7 shows a case where an interval is provided between both hysteresis in a zero point detection circuit similar to the embodiment.
  • a point earlier than the actual zero-cross point is detected by setting both hysteresis positions at intervals above and below the zero point (the output of High / Low is inverted). Will be).

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Measurement Of Current Or Voltage (AREA)
  • Manipulation Of Pulses (AREA)
  • Power Conversion In General (AREA)

Abstract

A comparison circuit for outputting the result of a high/low comparison of a reference signal and a comparison signal is provided with: two hysteresis comparators 2A and 2B; input circuits 1A and 1B that each input a reference signal and a comparison signal to the two hysteresis comparators 2A and 2B, respectively; bias circuits 3A and 3B that apply different biases to the reference signals input to the two hysteresis comparators 2A and 2B; and an output circuit 5 which inverts an output signal from High to Low or from Low to High on the basis of an output inversion from High to Low of one of the two hysteresis comparators 2A and 2B, and which inverts the output signal from Low to High or from High to Low on the basis of an output inversion from Low to High of the other hysteresis comparator. Thus, the comparision circuit is configured to produce no delay in the comparison result.

Description

比較回路、ゼロ点検知回路、交流電力調整器及び信号比較方法Comparison circuit, zero point detection circuit, AC power regulator, and signal comparison method
 本発明は、比較回路、ゼロ点検知回路、交流電力調整器及び信号比較方法に関する。 The present invention relates to a comparison circuit, a zero point detection circuit, an AC power regulator, and a signal comparison method.
 各種の電気、電子回路においては、その処理動作において各種の信号の大きさを比較することが行われており、そのための比較回路を備えている。
 このような比較回路の一例として、交流電源のゼロクロス点を検知するためのゼロ点検知回路がある。ゼロ点検知回路は、例えば、位相制御方式によって商用の交流電源の電圧を調整して負荷に供給する交流電力調整器において使用されている。
 このような位相制御方式の交流電力調整器における、ゼロクロス点をより正確に検知するための技術が特許文献1によって開示されている。
In various electric and electronic circuits, the magnitudes of various signals are compared in the processing operation, and a comparison circuit is provided for the comparison.
As an example of such a comparison circuit, there is a zero point detection circuit for detecting a zero cross point of an AC power supply. The zero point detection circuit is used, for example, in an AC power regulator that adjusts the voltage of a commercial AC power supply by a phase control method and supplies the voltage to a load.
Patent Document 1 discloses a technique for more accurately detecting a zero-cross point in such a phase control type AC power regulator.
特開2011-39648号公報JP 2011-39648 A
 比較回路における信号の比較では、ノイズの影響等によって信号が理想の波形から歪んだ場合においても誤作動をしないようにすることが望ましい。
 このようなノイズ対策として、例えばノイズを除去するフィルター回路を設けることが行われる。また、比較回路としてコンパレータを使用する場合には、ヒステリシス付きコンパレータを用いることが行われる。
 しかしながら、フィルター回路を設ける場合、フィルター回路によって信号の位相に遅れが生じ、ゼロ点検知回路などにおいてはゼロクロス点の検知が遅れる等の問題がある。位相に遅れが出ないような回路構成とすることも可能であるが、回路が複雑となりコスト増となる問題がある。また、ヒステリシス付きコンパレータを用いる場合においても、ゼロ点検知回路などにおいてゼロクロス点の検知がヒステリシス幅に応じて遅れるという問題がある。
In the comparison of signals in the comparison circuit, it is desirable that malfunction does not occur even when the signal is distorted from an ideal waveform due to the influence of noise or the like.
As a countermeasure against such noise, for example, a filter circuit for removing noise is provided. When a comparator is used as the comparison circuit, a comparator with hysteresis is used.
However, when a filter circuit is provided, there is a problem that the phase of a signal is delayed by the filter circuit, and the detection of a zero cross point is delayed in a zero point detection circuit or the like. Although it is possible to adopt a circuit configuration in which the phase is not delayed, there is a problem that the circuit becomes complicated and the cost increases. Further, even when a comparator with hysteresis is used, there is a problem that detection of a zero-cross point in a zero-point detection circuit or the like is delayed according to the hysteresis width.
 本発明は、上記の点に鑑み、信号の大きさを比較する比較回路であって、その比較結果に遅延が生じないようすることが可能であり、且つ、比較的簡易な回路構成の比較回路、ゼロ点検知回路、交流電力調整器及び信号比較方法を提供することを目的とする。 The present invention has been made in view of the above circumstances, and is a comparison circuit for comparing the magnitudes of signals. The comparison circuit can prevent a delay from occurring in the comparison result and has a relatively simple circuit configuration. , A zero point detection circuit, an AC power regulator, and a signal comparison method.
(構成1)
 基準信号と比較信号の高低の比較結果を出力する比較回路であって、2つのヒステリシスコンパレータと、前記基準信号と比較信号を、前記2つのヒステリシスコンパレータのそれぞれに入力する入力回路と、前記2つのヒステリシスコンパレータに入力される基準信号に、異なるバイアスを加えるバイアス回路と、前記2つのヒステリシスコンパレータの一方のヒステリシスコンパレータのHighからLowへの出力反転に基づき、出力信号をHighからLow若しくはLowからHighに反転させ、他方のヒステリシスコンパレータのLowからHighへの出力反転に基づき、出力信号をLowからHigh若しくはHighからLowに反転させる出力回路と、を備えることを特徴とする比較回路。
(Configuration 1)
A comparison circuit that outputs a comparison result of a level of a reference signal and a comparison signal, wherein the two input circuits input the reference signal and the comparison signal to each of the two hysteresis comparators; The output signal is changed from High to Low or from Low to High based on a bias circuit for applying a different bias to the reference signal input to the hysteresis comparator and the output inversion of one of the two hysteresis comparators from High to Low. An output circuit that inverts the output signal from Low to High or from High to Low based on the output inversion of the other hysteresis comparator from Low to High.
(構成2)
 一方の前記ヒステリシスコンパレータに入力される基準信号にプラスのバイアスを加え、他方の前記ヒステリシスコンパレータに入力される基準信号にマイナスのバイアスを加えることを特徴とする構成1に記載の比較回路。
(Configuration 2)
2. The comparison circuit according to Configuration 1, wherein a positive bias is applied to a reference signal input to one of the hysteresis comparators, and a negative bias is applied to a reference signal input to the other hysteresis comparator.
(構成3)
 前記プラスのバイアスの絶対値と、前記マイナスのバイアスの絶対値が略同一であることを特徴とする構成2に記載の比較回路。
(Configuration 3)
3. The comparison circuit according to Configuration 2, wherein the absolute value of the positive bias is substantially the same as the absolute value of the negative bias.
(構成4)
 基準信号と比較信号の高低の比較結果を出力する比較回路であって、2つのヒステリシスコンパレータと、前記基準信号と比較信号を、前記2つのヒステリシスコンパレータのそれぞれに入力する入力回路と、前記2つのヒステリシスコンパレータに入力される比較信号に、異なるバイアスを加えるバイアス回路と、前記2つのヒステリシスコンパレータの一方のヒステリシスコンパレータのHighからLowへの出力反転に基づき、出力信号をHighからLow若しくはLowからHighに反転させ、他方のヒステリシスコンパレータのLowからHighへの出力反転に基づき、出力信号をLowからHigh若しくはHighからLowに反転させる出力回路と、を備えることを特徴とする比較回路。
(Configuration 4)
A comparison circuit that outputs a comparison result of a level of a reference signal and a comparison signal, wherein the two input circuits input the reference signal and the comparison signal to each of the two hysteresis comparators; The output signal is changed from High to Low or from Low to High based on a bias circuit for applying a different bias to the comparison signal input to the hysteresis comparator and the output inversion of one of the two hysteresis comparators from High to Low. An output circuit that inverts the output signal from Low to High or from High to Low based on the output inversion of the other hysteresis comparator from Low to High.
(構成5)
 一方の前記ヒステリシスコンパレータに入力される比較信号にプラスのバイアスを加え、他方の前記ヒステリシスコンパレータに入力される比較信号にマイナスのバイアスを加えることを特徴とする構成4に記載の比較回路。
(Configuration 5)
The comparison circuit according to Configuration 4, wherein a plus bias is applied to the comparison signal input to the one hysteresis comparator, and a minus bias is applied to the comparison signal input to the other hysteresis comparator.
(構成6)
 前記プラスのバイアスの絶対値と、前記マイナスのバイアスの絶対値が略同一であることを特徴とする構成5に記載の比較回路。
(Configuration 6)
The comparison circuit according to Configuration 5, wherein the absolute value of the plus bias is substantially the same as the absolute value of the minus bias.
(構成7)
 前記バイアスの絶対値が、前記ヒステリシスコンパレータのヒステリシス幅の略1/2であることを特徴とする構成1から6の何れかに記載の比較回路。
(Configuration 7)
The comparison circuit according to any one of Configurations 1 to 6, wherein the absolute value of the bias is approximately half the hysteresis width of the hysteresis comparator.
(構成8)
 構成1から7の何れかに記載の比較回路を用い、前記基準信号をゼロ点とし、前記比較信号を交流電源波形信号とすることで、交流電源波形のゼロ点検知を行うゼロ点検知回路。
(Configuration 8)
A zero point detection circuit that performs zero point detection of an AC power supply waveform by using the comparison circuit according to any one of Configurations 1 to 7, setting the reference signal to a zero point, and using the comparison signal as an AC power supply waveform signal.
(構成9)
 構成8に記載のゼロ点検知回路と、出力目標値をトリガ角に変換する出力目標値トリガ角変換部と、前記ゼロ点検知回路によって検知される交流電源波形のゼロクロス点に基づいて、前記トリガ角を出力するトリガ角出力部と、前記トリガ角に基づいてサイリスタを制御するサイリスタ制御部と、を備えることを特徴とする交流電力調整器。
(Configuration 9)
The zero point detection circuit according to Configuration 8, an output target value trigger angle conversion unit for converting an output target value to a trigger angle, and the trigger based on a zero crossing point of the AC power supply waveform detected by the zero point detection circuit. An AC power regulator, comprising: a trigger angle output unit that outputs an angle; and a thyristor control unit that controls a thyristor based on the trigger angle.
(構成10)
 基準信号と比較信号の高低の比較結果を出力する比較方法であって、2つのヒステリシスコンパレータを用い、前記基準信号と比較信号を、前記2つのヒステリシスコンパレータのそれぞれに入力するステップと、前記2つのヒステリシスコンパレータに入力される基準信号に、異なるバイアスを加えるステップと、前記2つのヒステリシスコンパレータの一方のヒステリシスコンパレータのHighからLowへの出力反転に基づき、出力信号をHighからLow若しくはLowからHighに反転させ、他方のヒステリシスコンパレータのLowからHighへの出力反転に基づき、出力信号をLowからHigh若しくはHighからLowに反転させるステップと、を備えることを特徴とする信号比較方法。
(Configuration 10)
A comparison method for outputting a comparison result of a level of a reference signal and a comparison signal, wherein two hysteresis comparators are used to input the reference signal and the comparison signal to each of the two hysteresis comparators. Applying a different bias to the reference signal input to the hysteresis comparator, and inverting the output signal from high to low or from low to high based on the output inversion of one of the two hysteresis comparators from high to low. And inverting the output signal from low to high or from high to low based on the output inversion of the other hysteresis comparator from low to high.
(構成11)
 基準信号と比較信号の高低の比較結果を出力する比較方法であって、2つのヒステリシスコンパレータと、前記基準信号と比較信号を、前記2つのヒステリシスコンパレータのそれぞれに入力するステップと、前記2つのヒステリシスコンパレータに入力される比較信号に、異なるバイアスを加えるステップと、前記2つのヒステリシスコンパレータの一方のヒステリシスコンパレータのHighからLowへの出力反転に基づき、出力信号をHighからLow若しくはLowからHighに反転させ、他方のヒステリシスコンパレータのLowからHighへの出力反転に基づき、出力信号をLowからHigh若しくはHighからLowに反転させるステップと、を備えることを特徴とする信号比較方法。
(Configuration 11)
A comparison method for outputting a comparison result between a reference signal and a comparison signal, wherein two hysteresis comparators, the reference signal and the comparison signal are input to each of the two hysteresis comparators, and the two hysteresis comparators Applying a different bias to the comparison signal input to the comparator, and inverting the output signal from high to low or from low to high based on the output inversion of one of the two hysteresis comparators from high to low. And inverting the output signal from Low to High or from High to Low based on the output inversion of the other hysteresis comparator from Low to High.
 本発明の比較回路によれば、比較結果に遅延が生じないようすることが可能な比較回路を、比較的簡易な回路構成にて提供することが出来る。 According to the comparison circuit of the present invention, it is possible to provide a comparison circuit capable of preventing a delay in the comparison result with a relatively simple circuit configuration.
本発明に係る実施形態の交流電力調整器の構成を示す概略ブロック図1 is a schematic block diagram illustrating a configuration of an AC power regulator according to an embodiment of the present invention. 実施形態のゼロ点検知回路(比較回路)の構成を示す図FIG. 2 is a diagram illustrating a configuration of a zero-point detection circuit (comparison circuit) according to the embodiment. ゼロ点検知回路(比較回路)が備えるマイコン(出力回路)の処理動作の概略を示すフローチャートThe flowchart which shows the outline of the processing operation of the microcomputer (output circuit) with which the zero point detection circuit (comparison circuit) is provided ゼロ点検知回路(比較回路)の動作を説明するための説明図Explanatory drawing for explaining the operation of the zero point detection circuit (comparison circuit) ゼロ点検知における従来の問題点を説明するための説明図Explanatory diagram for explaining a conventional problem in zero point detection 比較回路の構成を示す図Diagram showing the configuration of the comparison circuit ゼロ点検知回路(比較回路)の別の動作例を説明するための説明図Explanatory diagram for explaining another operation example of the zero point detection circuit (comparison circuit)
 以下、本発明の実施形態について、図面を参照しながら具体的に説明する。なお、以下の実施形態は、本発明を具体化する際の一形態であって、本発明をその範囲内に限定するものではない。 Hereinafter, embodiments of the present invention will be specifically described with reference to the drawings. Note that the following embodiment is one mode for embodying the present invention, and does not limit the present invention within the scope thereof.
 図1は、本発明に係る実施形態1の交流電力調整器の構成の概略を示すブロック図である。本実施形態の交流電力調整器100は、負荷に対する電力供給の制御を位相制御によって行う交流電力調整器である。より具体的には、交流電力調整器100は、外部装置である調節計(温度調節器)200から入力される目標値に基づいて、開閉器600(例えば、リレーやブレーカーなど)及びヒューズ60を介して交流電源500と接続されるサイリスタ50を制御することで、トランス400の1次側に供給する電力を位相制御によって調整し、被制御対象300のヒータに対する交流電源500からの電力供給の制御を行うものである。
 本実施形態では、スイッチング素子としてサイリスタ50が実装されている例を示しているが、これに限るものではなく、例えば、スイッチング素子としてトライアックなどが実装されていてもよい。
FIG. 1 is a block diagram schematically illustrating a configuration of an AC power regulator according to Embodiment 1 of the present invention. The AC power regulator 100 of the present embodiment is an AC power regulator that controls power supply to a load by phase control. More specifically, the AC power regulator 100 switches the switch 600 (for example, a relay or a breaker) and the fuse 60 based on a target value input from a controller (temperature controller) 200 which is an external device. By controlling the thyristor 50 connected to the AC power supply 500 via the AC power supply, the power supplied to the primary side of the transformer 400 is adjusted by phase control, and the power supply from the AC power supply 500 to the heater of the controlled object 300 is controlled. Is what you do.
In the present embodiment, an example is shown in which the thyristor 50 is mounted as a switching element. However, the present invention is not limited to this. For example, a triac may be mounted as a switching element.
 交流電力調整器100は、交流電源波形のゼロ点検知を行う零点検出部10と、出力目標値をトリガ角に変換する出力目標値トリガ角変換部20と、零点検出部10によって検知される交流電源波形のゼロクロス点に基づいて、トリガ角を出力するトリガ角出力部30と、トリガ角に基づいてサイリスタを制御するサイリスタ制御部40と、点弧角及びゼロクロス点のタイミングで交流電源500から被制御対象300のヒータへの電力供給をスイッチングするサイリスタ50と、ヒューズ60と、を備える。
 交流電力調整器100における位相制御方法や、そのための構成については、零点検出部10部分を除き、従来の交流電力調整器と同様であるため、ここでのこれ以上の詳しい説明を省略し、以下主に零点検出部10部分について説明する。
 なお、図1では機能ごとに構成を分けて記載しているが、必ずしもハード的にこれらの構成に分かれていることを示すものではなく、例えば、PLC、MCU、マイコン等の周知の汎用デバイスを用いて各構成がソフトウェア的に実装されるものであってもよい。もちろん各構成がハード的に構成されるものであってよく、例えばFPGA等を利用して構成されるものや、ASICなどによって専用のハードとして構成されるもの等であってもよい。
The AC power regulator 100 includes a zero point detection unit 10 for detecting a zero point of an AC power supply waveform, an output target value trigger angle conversion unit 20 for converting an output target value to a trigger angle, and an AC detected by the zero point detection unit 10. A trigger angle output unit 30 that outputs a trigger angle based on a zero-cross point of the power supply waveform, a thyristor control unit 40 that controls a thyristor based on the trigger angle, and an AC power supply 500 that receives a timing of the firing angle and the zero-cross point. A thyristor 50 that switches power supply to the heater of the control target 300 and a fuse 60 are provided.
The phase control method in the AC power regulator 100 and the configuration therefor are the same as the conventional AC power regulator except for the zero point detection unit 10, so that a further detailed description is omitted here. Mainly, the zero point detecting unit 10 will be described.
In FIG. 1, the configuration is described separately for each function. However, it does not necessarily indicate that the configuration is divided into hardware. For example, a known general-purpose device such as a PLC, an MCU, or a microcomputer may be used. Each configuration may be implemented as software by using. Of course, each component may be configured as hardware, for example, may be configured using an FPGA or the like, or may be configured as dedicated hardware using an ASIC or the like.
 図2は、零点検出部10の回路構成(ゼロ点検知回路)を示す図である。
 零点検出部(ゼロ点検知回路)10は、2つのヒステリシスコンパレータ2A、2Bと、基準信号(ゼロ点)と比較信号(交流電源波形信号)を、2つのヒステリシスコンパレータ2A、2Bのそれぞれに入力する入力回路1A、1Bと、2つのヒステリシスコンパレータ2A、2Bに入力される基準信号(ゼロ点)に、異なるバイアスを加えるバイアス回路3A、3Bと、2つのヒステリシスコンパレータの一方のヒステリシスコンパレータのHighからLowへの出力反転に基づき、出力信号をHighからLow若しくはLowからHighに反転させ、他方のヒステリシスコンパレータLowからHighへの出力反転に基づき、出力信号をLowからHigh若しくはHighからLowに反転させる出力回路であるマイコンユニット5と、マイコンユニット5への入力信号(ヒステリシスコンパレータ2A、2Bからの出力信号)のレベル調節回路4A、4Bと、を備える。
FIG. 2 is a diagram illustrating a circuit configuration (zero point detection circuit) of the zero point detection unit 10.
The zero point detection unit (zero point detection circuit) 10 inputs two hysteresis comparators 2A and 2B, and a reference signal (zero point) and a comparison signal (AC power supply waveform signal) to each of the two hysteresis comparators 2A and 2B. The input circuits 1A and 1B, the bias circuits 3A and 3B for applying different biases to the reference signals (zero points) input to the two hysteresis comparators 2A and 2B, and one of the two hysteresis comparators from High to Low. An output circuit that inverts the output signal from High to Low or Low to High on the basis of the output inversion to, and inverts the output signal from Low to High or from High to Low based on the output inversion from the other hysteresis comparator Low to High. Is a microcomputer Comprises a Tsu bets 5, the level adjusting circuit 4A of the input signal to the microcomputer unit 5 (hysteresis comparator 2A, the output signal from 2B), and 4B, the.
 入力回路1A(1B)に備えられる、抵抗R1A、R2A(R1B、R2B)は、交流電源500の振幅を、ヒステリシスコンパレータ2A(2B)への入力として適当なレベルに調節するための分圧回路である(本実施形態では振幅を±4Vに調節)。
 ヒステリシスコンパレータ2A(2B)に備えられる抵抗R3A、R4A(R3B、R4B)は、ヒステリシス幅を調整するための分圧回路である。本実施形態では、ヒステリシスコンパレータ2A、2Bのヒステリシス幅は、何れも2Vである。
The resistors R1A, R2A (R1B, R2B) provided in the input circuit 1A (1B) are voltage dividing circuits for adjusting the amplitude of the AC power supply 500 to an appropriate level as an input to the hysteresis comparator 2A (2B). (In this embodiment, the amplitude is adjusted to ± 4 V).
The resistors R3A, R4A (R3B, R4B) provided in the hysteresis comparator 2A (2B) are voltage dividing circuits for adjusting the hysteresis width. In the present embodiment, the hysteresis width of each of the hysteresis comparators 2A and 2B is 2V.
 バイアス回路3A(3B)に備えられる抵抗R4A、R5A(R4B、R5B)は、バイアス量を調整するための分圧回路である。
 本実施形態においては、バイアス回路3Aは+5Vの電源ラインが接続され、抵抗R4A、R5Aの分圧回路によって、コンパレータAに入力される基準信号(ゼロ点=0V)を+1V分バイアスする。これにより、図4に示されるように、ヒステリシスコンパレータ2Aのヒステリシスの下端がゼロ点=0Vとなり、上端が+2Vとなる。
 一方、バイアス回路3Bは-5Vの電源ラインが接続され、抵抗R4B、R5Bの分圧回路によって、コンパレータBに入力される基準信号(ゼロ点=0V)を-1V分バイアスする。これにより、図4に示されるように、ヒステリシスコンパレータ2Bのヒステリシスの下端が-2Vとなり、上端がゼロ点=0Vとなる。
 即ち、一方のヒステリシスコンパレータに入力される基準信号にプラスのバイアスを加え、他方のヒステリシスコンパレータに入力される基準信号にマイナスのバイアスを加えるものである。また、プラスのバイアスの絶対値と、マイナスのバイアスの絶対値が略同一であり、バイアスの絶対値が、ヒステリシスコンパレータのヒステリシス幅の略1/2である。
The resistors R4A, R5A (R4B, R5B) provided in the bias circuit 3A (3B) are voltage dividing circuits for adjusting a bias amount.
In the present embodiment, the power supply line of +5 V is connected to the bias circuit 3A, and the reference signal (zero point = 0 V) input to the comparator A is biased by +1 V by the voltage dividing circuit of the resistors R4A and R5A. Thereby, as shown in FIG. 4, the lower end of the hysteresis of the hysteresis comparator 2A becomes zero point = 0V, and the upper end becomes + 2V.
On the other hand, a -5V power supply line is connected to the bias circuit 3B, and a reference signal (zero point = 0V) input to the comparator B is biased by -1V by a voltage dividing circuit of resistors R4B and R5B. Thereby, as shown in FIG. 4, the lower end of the hysteresis of the hysteresis comparator 2B becomes -2V, and the upper end becomes the zero point = 0V.
That is, a positive bias is applied to the reference signal input to one hysteresis comparator, and a negative bias is applied to the reference signal input to the other hysteresis comparator. Further, the absolute value of the positive bias is substantially the same as the absolute value of the negative bias, and the absolute value of the bias is substantially 1 / of the hysteresis width of the hysteresis comparator.
 レベル調節回路4A(4B)は、+5Vの電源ラインが接続され、抵抗R6A、R7A(R6B、R7B)の分圧回路によって、マイコンユニット5への入力信号(ヒステリシスコンパレータ2A、2Bからの出力信号)のレベルを適当な値に調節する(本実施形態ではHigh=5V、Low=0Vに調節する)。 The level adjustment circuit 4A (4B) is connected to a + 5V power supply line, and is input to the microcomputer unit 5 (output signals from the hysteresis comparators 2A and 2B) by a voltage divider circuit of resistors R6A and R7A (R6B and R7B). Is adjusted to an appropriate value (in this embodiment, High = 5V and Low = 0V).
 次に、上述した構成の回路によってヒステリシスコンパレータ2A、2Bからの入力を受けるマイコンユニット5の処理動作について、図3のフローチャートを参照しつつ説明する。
 ステップ301~304の処理は、交流電源500のゼロクロス点検知を行う間において繰り返し動作するループ処理である。
 ステップ301では、ヒステリシスコンパレータ2Aからの信号がLowからHighに変化したか否かを監視し、LowからHighに変化した場合には、ステップ303へと移行する。ステップ303では、出力端子6からの出力をLowからHighに反転させる。
 ステップ302では、ヒステリシスコンパレータ2Bからの信号がHighからLowに変化したか否かを監視し、HighからLowに変化した場合には、ステップ304へと移行する。ステップ304では、出力端子6からの出力をHighからLowに反転させる。
 上記の処理を繰り返すことにより、交流電源500のゼロクロス点において遅延無くHighとLowが反転する信号が出力端子6から出力される。
Next, the processing operation of the microcomputer unit 5 which receives the input from the hysteresis comparators 2A and 2B by the circuit having the above configuration will be described with reference to the flowchart of FIG.
The processing of steps 301 to 304 is a loop processing that repeatedly operates while detecting the zero-cross point of the AC power supply 500.
In step 301, it is monitored whether or not the signal from the hysteresis comparator 2A has changed from low to high. If the signal has changed from low to high, the process proceeds to step 303. In step 303, the output from the output terminal 6 is inverted from Low to High.
In step 302, it is monitored whether or not the signal from the hysteresis comparator 2B has changed from High to Low. If the signal has changed from High to Low, the process proceeds to Step 304. In step 304, the output from the output terminal 6 is inverted from High to Low.
By repeating the above processing, a signal in which High and Low are inverted at the zero cross point of the AC power supply 500 without delay is output from the output terminal 6.
 図4は、零点検出部(ゼロ点検知回路)10の動作を説明するための説明図である。
 図4の上側には交流電源500の波形と、ヒステリシスコンパレータ2A、2Bのそれぞれのヒステリシスを図示し、下側にはヒステリシスコンパレータ2A、2Bのそれぞれの出力波形と、マイコンユニット5(出力端子6)からの出力波形を示している。
FIG. 4 is an explanatory diagram for explaining the operation of the zero point detection unit (zero point detection circuit) 10.
4 shows the waveform of the AC power supply 500 and the hysteresis of each of the hysteresis comparators 2A and 2B, and the lower side of FIG. 4 shows the output waveforms of the hysteresis comparators 2A and 2B and the microcomputer unit 5 (output terminal 6). 3 shows an output waveform from the oscilloscope.
 図4に示されるように、ヒステリシスコンパレータ2Aではヒステリシスの上端が+2Vである一方、ヒステリシスの下端がゼロ点=0Vである。従って、ヒステリシスコンパレータ2Aの出力波形としては、交流電源500の波形がヒステリシスの上端側である+2Vを越える際にHigh/Lowが切り替わり、交流電源500の波形がヒステリシスの下端側である0Vを下回る際にLow/Highが切り替わる。よって、ヒステリシスの下端側である0Vを下回る際においては、ゼロクロス点を遅延無く表す。
 一方、ヒステリシスコンパレータ2Bではヒステリシスの上端がゼロ点=0Vである一方、ヒステリシスの下端が-2Vである。従って、ヒステリシスコンパレータ2Bの出力波形としては、交流電源500の波形がヒステリシスの上端側である0Vを越える際にHigh/Lowが切り替わり、交流電源500の波形がヒステリシスの下端側である-2Vを下回る際にLow/Highが切り替わる。よって、ヒステリシスの上端側である0Vを越える際においては、ゼロクロス点を遅延無く表す。
 マイコンユニット5では、前述した図3の処理により、ヒステリシスコンパレータ2Aにおける交流電源500の波形がヒステリシスの下端側である0Vを下回る際のLow/Highの切り替わりと、ヒステリシスコンパレータ2Bにおける、交流電源500の波形がヒステリシスの上端側である0Vを越える際のHigh/Lowの切り替わりに基づいて、HighとLowを切り替える信号を出力端子6から出力する。
 従って、出力端子6から出力は、交流電源500のゼロクロス点を遅延無く表す波形となる。
As shown in FIG. 4, in the hysteresis comparator 2A, the upper end of the hysteresis is + 2V, while the lower end of the hysteresis is zero point = 0V. Accordingly, the output waveform of the hysteresis comparator 2A switches between High / Low when the waveform of the AC power supply 500 exceeds + 2V which is the upper end of the hysteresis, and when the waveform of the AC power supply 500 falls below 0V which is the lower end of the hysteresis. Is switched between Low / High. Therefore, when the voltage falls below 0 V which is the lower end side of the hysteresis, the zero cross point is represented without delay.
On the other hand, in the hysteresis comparator 2B, the upper end of the hysteresis is zero point = 0V, while the lower end of the hysteresis is -2V. Accordingly, the output waveform of the hysteresis comparator 2B switches between High / Low when the waveform of the AC power supply 500 exceeds 0V which is the upper end of the hysteresis, and the waveform of the AC power supply 500 falls below -2V which is the lower end of the hysteresis. At this time, Low / High is switched. Therefore, when the voltage exceeds 0 V, which is the upper end of the hysteresis, the zero cross point is represented without delay.
In the microcomputer unit 5, the low / high switching when the waveform of the AC power supply 500 in the hysteresis comparator 2A falls below 0V, which is the lower end side of the hysteresis, and the processing of the AC power supply 500 in the hysteresis comparator 2B are performed by the processing of FIG. A signal for switching between High and Low is output from the output terminal 6 based on the switching between High and Low when the waveform exceeds 0 V, which is the upper end of the hysteresis.
Therefore, the output from the output terminal 6 has a waveform representing the zero-cross point of the AC power supply 500 without delay.
 以上のごとく、本実施形態の交流電力調整器100における零点検出部(ゼロ点検知回路)10によれば、交流電源500のゼロクロス点を遅延無く検知することができる。また、ゼロクロス点を遅延無く検知することができ、且つ、ノイズの影響を低減することができる回路を、比較的簡易な回路構成にて実現することができる。 As described above, according to the zero point detection unit (zero point detection circuit) 10 in the AC power regulator 100 of the present embodiment, the zero cross point of the AC power supply 500 can be detected without delay. Further, a circuit capable of detecting the zero-cross point without delay and reducing the influence of noise can be realized with a relatively simple circuit configuration.
 図5は、従来の交流電力調整器100において、交流電源のゼロクロス点の測定に一定の遅延があることが原因となって生じる問題を説明するための図である。
 図5(a)に示されるように、交流電源の電源波形が通常の波形である場合には、ゼロクロス点の測定に一定の遅延が生じる回路構成であっても、その遅延時間分を差し引いて処理を行えば問題はない。即ち、トリガ点の発呼タイミングを、ゼロ点検知の遅延時間を加味した上で、n-1回目のゼロ点を検知した時点から算出すれば問題ない。
 しかしながら、例えば三相の交流電源の一相において、他の相の電力供給の影響によって電源波形の位相が一時的に進んでしまう現象が起きる場合がある。
 このように電源波形の位相が進んだ状況を示しているのが図5(b)である。
 図5(b)では、トリガ点を図5(a)と同じタイミングとしているが、電源波形の位相が進んだ結果、図5(b)ではトリガ点よりゼロクロス点が先に到来している。装置としては、位相が進んでいるか否かの判別ができず、図5(a)と同様に、n-1回目のゼロ点を検知した時点からゼロ点検知の遅延時間を加味した上でトリガ点を定めているからである。
 その結果、本来小さな電力供給とすべきところで、大きな電力供給となってしまうことが起こり得る。このような過大な出力となってしまうと、トランスの磁気飽和によって過大な突入電流が流れ、ヒューズが切れたり、トランスの破損を起こしてしまう問題が発生する場合がある。
 交流電源のゼロクロス点の測定に一定の遅延が生じてしまう場合、図5(b)のような瞬間的な位相のズレを、トリガ点の到来前に検知することが難しい状況が生じるため、上記のような問題に対処することが難しいものである。
 これに対し、本実施形態の交流電力調整器100における零点検出部(ゼロ点検知回路)10によれば、前述のごとく、交流電源500のゼロクロス点を遅延無く検知することができるため、上記のような問題に対処することも可能となるものである。
FIG. 5 is a diagram for explaining a problem that occurs in the conventional AC power regulator 100 due to a certain delay in measuring the zero-cross point of the AC power supply.
As shown in FIG. 5A, when the power supply waveform of the AC power supply is a normal waveform, even if the circuit configuration has a certain delay in the measurement of the zero-cross point, the delay time is subtracted. There is no problem if processing is performed. That is, there is no problem if the call timing of the trigger point is calculated from the time point at which the (n-1) -th zero point is detected, taking into account the delay time of the zero point detection.
However, for example, in one phase of a three-phase AC power supply, a phenomenon may occur in which the phase of the power supply waveform is temporarily advanced due to the influence of power supply of another phase.
FIG. 5B shows a situation in which the phase of the power supply waveform has advanced in this manner.
In FIG. 5B, the trigger point is set at the same timing as in FIG. 5A, but as a result of the advance of the phase of the power supply waveform, in FIG. 5B, the zero-cross point comes before the trigger point. The device cannot determine whether the phase is advanced or not, and, as in FIG. 5A, triggers after taking into account the delay time of zero point detection from the time point at which the (n-1) th zero point is detected. This is because the points are set.
As a result, a large power supply may occur where a small power supply is originally required. If the output becomes excessive, an excessive rush current flows due to the magnetic saturation of the transformer, which may cause a problem that the fuse is blown or the transformer is damaged.
When a certain delay occurs in the measurement of the zero-cross point of the AC power supply, it is difficult to detect the instantaneous phase shift before the arrival of the trigger point as shown in FIG. It is difficult to deal with such problems.
On the other hand, according to the zero point detection unit (zero point detection circuit) 10 in the AC power regulator 100 of the present embodiment, the zero cross point of the AC power supply 500 can be detected without delay as described above. It is also possible to deal with such a problem.
 なお、本実施形態では、図4に示されるように、ヒステリシスコンパレータ2A(2B)の出力信号が、交流電源500の波形がヒステリシスの上端側を越える際にHighからLowに切り替わり、交流電源500の波形がヒステリシスの下端側を下回る際にLowからHighに切り替わるものであり、マイコンユニット5では、ヒステリシスコンパレータ2AにおけるLowからHighの切り替わりに応じて出力信号をLowからHighとし、ヒステリシスコンパレータ2BにおけるHighからLowの切り替わりに応じて出力信号をHighからLowに切り替えるものを例としているが、各信号におけるHighかLowかの違いは、適宜変更できるものである。即ち、例えば図4の下側における各出力波形のHighとLowを反転するものであってよい(全て反転するものや、何れかの出力波形のみ反転するもの等、任意の組み合わせが可能である)。 In this embodiment, as shown in FIG. 4, the output signal of the hysteresis comparator 2A (2B) switches from High to Low when the waveform of the AC power supply 500 exceeds the upper end of the hysteresis. When the waveform falls below the lower end of the hysteresis, the signal changes from low to high. In the microcomputer unit 5, the output signal changes from low to high in response to the switching from low to high in the hysteresis comparator 2A, and changes from high to low in the hysteresis comparator 2B. An example in which the output signal is switched from High to Low according to the switching of Low is described as an example, but the difference between High and Low in each signal can be changed as appropriate. That is, for example, High and Low of each output waveform on the lower side of FIG. 4 may be inverted (arbitrary combinations are possible, such as inverting all or inverting only one of the output waveforms). .
 本実施形態では、交流電力調整器におけるゼロ点検知回路を例として説明したが、本発明をこれに限るものではなく、基準信号と比較信号の高低の比較結果を出力する比較回路、信号比較方法として広く利用することができる。
 即ち、図6に示したように、2つのヒステリシスコンパレータを有するコンパレータ回路12と、基準信号と比較信号が入力される入力端子111、112を備え(何れの端子に基準信号を入力するかは任意)、2つのヒステリシスコンパレータのそれぞれに基準信号と比較信号を入力する入力回路11と、2つのヒステリシスコンパレータに入力される基準信号に、異なるバイアスを加えるバイアス回路13と、2つのヒステリシスコンパレータの一方のヒステリシスコンパレータのHighからLowへの出力反転に基づき、出力信号をHighからLow若しくはLowからHighに反転させ、他方のヒステリシスコンパレータLowからHighへの出力反転に基づき、出力信号をLowからHigh若しくはHighからLowに反転させる出力回路15と、を備える比較回路により、任意の信号を比較することができる。
 なお、本実施形態では、出力回路がマイコンユニット5上でソフト的に構成されるものを例としたが、出力回路を専用回路等によってハード的に構成するものとしてもよい。
In the present embodiment, the zero point detection circuit in the AC power regulator has been described as an example. However, the present invention is not limited to this, and a comparison circuit that outputs a comparison result of the level of a reference signal and a comparison signal, a signal comparison method Can be widely used as.
That is, as shown in FIG. 6, a comparator circuit 12 having two hysteresis comparators and input terminals 111 and 112 to which a reference signal and a comparison signal are input are provided. (Which terminal receives the reference signal is arbitrary. ) An input circuit 11 for inputting a reference signal and a comparison signal to each of the two hysteresis comparators, a bias circuit 13 for applying different biases to the reference signals input to the two hysteresis comparators, and one of the two hysteresis comparators The output signal is inverted from High to Low or from Low to High based on the output inversion of the hysteresis comparator from High to Low, and the output signal is output from Low to High or High based on the output inversion of the other hysteresis comparator from Low to High. Low An output circuit 15 for inverting, by the comparison circuit comprising a can compare any signals.
In the present embodiment, the output circuit is configured as software on the microcomputer unit 5 as an example. However, the output circuit may be configured as hardware using a dedicated circuit or the like.
 本実施形態では、基準信号にバイアスを加えるものを例としているが、比較信号に対してバイアスを加えるものであってもよい。
 また、本実施形態では、一方のヒステリシスコンパレータに入力される信号にプラスのバイアスを加え、他方のヒステリシスコンパレータに入力される信号にマイナスのバイアスを加え、プラスとマイナスのバイアスの絶対値が略同一、且つバイアスがヒステリシス幅の略1/2であるものを例としたが、本発明をこれに限るものではなく、プラスとマイナスのバイアスの絶対値が異なるものや、双方のヒステリシスコンパレータに入力される信号にプラス(若しくはマイナス)のバイアスを加えるもの等としてもよい。
 加えて、本実施形態では、上記構成により、一方のヒステリシスコンパレータのヒステリシスの上端と、他方のヒステリシスコンパレータのヒステリシスの下端が同一になるようにしているが、双方のヒステリシスの一部の領域が重なるものや、双方のヒステリシスの間に間隔ができるようなものであってもよい。
 上記した点は、比較したい信号やその目的に応じて適宜選択すればよいものである。
 例えば、図7には、実施形態と同様のゼロ点検知回路において、双方のヒステリシスの間に間隔ができるようにした場合を示した。同図から理解されるように、ゼロ点の上下に間隔をあけて双方のヒステリシスが位置するようにすることで、実際のゼロクロス点よりも早い時点が検知される(High/Lowの出力が反転される)ものとなる。用途によっては、実際のゼロクロス点よりも少し早い時点を検知したいということもあり得、そのような要請に応えることができるものである。
In the present embodiment, an example is given in which a bias is applied to a reference signal, but a bias may be applied to a comparison signal.
Further, in the present embodiment, a plus bias is applied to the signal input to one hysteresis comparator, and a minus bias is applied to the signal input to the other hysteresis comparator, so that the absolute values of the plus and minus biases are substantially the same. And the bias is approximately の of the hysteresis width. However, the present invention is not limited to this, and the absolute values of the positive and negative biases are different, and the bias is input to both hysteresis comparators. It may be possible to apply a plus (or minus) bias to such a signal.
In addition, in the present embodiment, with the above configuration, the upper end of the hysteresis of one hysteresis comparator and the lower end of the hysteresis of the other hysteresis comparator are the same, but some regions of both hysteresis overlap. Or may be such that there is an interval between both hysteresis.
The above points can be appropriately selected according to the signal to be compared and the purpose thereof.
For example, FIG. 7 shows a case where an interval is provided between both hysteresis in a zero point detection circuit similar to the embodiment. As can be understood from the figure, a point earlier than the actual zero-cross point is detected by setting both hysteresis positions at intervals above and below the zero point (the output of High / Low is inverted). Will be). Depending on the application, it may be desirable to detect a point slightly earlier than the actual zero-cross point, and it is possible to meet such a demand.
 100...交流電力調整器
  10...零点検出部(ゼロ点検知回路、比較回路)
   1A、1B...入力回路
   2A、2B...ヒステリシスコンパレータ
   3A、3B...バイアス回路
   5...マイコンユニット(出力回路)
  20...出力目標値トリガ角変換部
  30...トリガ角出力部
  40...サイリスタ制御部
  50...サイリスタ
100. . . AC power regulator 10. . . Zero point detection unit (zero point detection circuit, comparison circuit)
1A, 1B. . . Input circuits 2A, 2B. . . Hysteresis comparator 3A, 3B. . . Bias circuit 5. . . Microcomputer unit (output circuit)
20. . . Output target value trigger angle conversion unit 30. . . Trigger angle output unit 40. . . Thyristor control unit 50. . . Thyristor

Claims (11)

  1.  基準信号と比較信号の高低の比較結果を出力する比較回路であって、
     2つのヒステリシスコンパレータと、
     前記基準信号と比較信号を、前記2つのヒステリシスコンパレータのそれぞれに入力する入力回路と、
     前記2つのヒステリシスコンパレータに入力される基準信号に、異なるバイアスを加えるバイアス回路と、
     前記2つのヒステリシスコンパレータの一方のヒステリシスコンパレータのHighからLowへの出力反転に基づき、出力信号をHighからLow若しくはLowからHighに反転させ、他方のヒステリシスコンパレータのLowからHighへの出力反転に基づき、出力信号をLowからHigh若しくはHighからLowに反転させる出力回路と、
     を備えることを特徴とする比較回路。
    A comparison circuit that outputs a comparison result of the level of the reference signal and the comparison signal,
    Two hysteresis comparators,
    An input circuit for inputting the reference signal and the comparison signal to each of the two hysteresis comparators;
    A bias circuit for applying different biases to the reference signals input to the two hysteresis comparators;
    The output signal is inverted from High to Low or from Low to High based on the output inversion from High to Low of one of the two hysteresis comparators, and based on the output inversion from Low to High on the other hysteresis comparator. An output circuit for inverting the output signal from Low to High or from High to Low;
    A comparison circuit comprising:
  2.  一方の前記ヒステリシスコンパレータに入力される基準信号にプラスのバイアスを加え、他方の前記ヒステリシスコンパレータに入力される基準信号にマイナスのバイアスを加えることを特徴とする請求項1に記載の比較回路。 2. The comparison circuit according to claim 1, wherein a positive bias is applied to the reference signal input to one of the hysteresis comparators, and a negative bias is applied to the reference signal input to the other hysteresis comparator.
  3.  前記プラスのバイアスの絶対値と、前記マイナスのバイアスの絶対値が略同一であることを特徴とする請求項2に記載の比較回路。 3. The comparison circuit according to claim 2, wherein the absolute value of the positive bias is substantially equal to the absolute value of the negative bias.
  4.  基準信号と比較信号の高低の比較結果を出力する比較回路であって、
     2つのヒステリシスコンパレータと、
     前記基準信号と比較信号を、前記2つのヒステリシスコンパレータのそれぞれに入力する入力回路と、
     前記2つのヒステリシスコンパレータに入力される比較信号に、異なるバイアスを加えるバイアス回路と、
     前記2つのヒステリシスコンパレータの一方のヒステリシスコンパレータのHighからLowへの出力反転に基づき、出力信号をHighからLow若しくはLowからHighに反転させ、他方のヒステリシスコンパレータのLowからHighへの出力反転に基づき、出力信号をLowからHigh若しくはHighからLowに反転させる出力回路と、
     を備えることを特徴とする比較回路。
    A comparison circuit that outputs a comparison result of the level of the reference signal and the comparison signal,
    Two hysteresis comparators,
    An input circuit for inputting the reference signal and the comparison signal to each of the two hysteresis comparators;
    A bias circuit for applying different biases to comparison signals input to the two hysteresis comparators;
    The output signal is inverted from High to Low or from Low to High based on the output inversion from High to Low of one of the two hysteresis comparators, and based on the output inversion from Low to High on the other hysteresis comparator. An output circuit for inverting the output signal from Low to High or from High to Low;
    A comparison circuit comprising:
  5.  一方の前記ヒステリシスコンパレータに入力される比較信号にプラスのバイアスを加え、他方の前記ヒステリシスコンパレータに入力される比較信号にマイナスのバイアスを加えることを特徴とする請求項4に記載の比較回路。 5. The comparison circuit according to claim 4, wherein a plus bias is applied to the comparison signal input to the one hysteresis comparator, and a minus bias is applied to the comparison signal input to the other hysteresis comparator.
  6.  前記プラスのバイアスの絶対値と、前記マイナスのバイアスの絶対値が略同一であることを特徴とする請求項5に記載の比較回路。 6. The comparison circuit according to claim 5, wherein the absolute value of the positive bias is substantially equal to the absolute value of the negative bias.
  7.  前記バイアスの絶対値が、前記ヒステリシスコンパレータのヒステリシス幅の略1/2であることを特徴とする請求項1から6の何れかに記載の比較回路。 7. The comparison circuit according to claim 1, wherein the absolute value of the bias is substantially half the hysteresis width of the hysteresis comparator.
  8.  請求項1から7の何れかに記載の比較回路を用い、前記基準信号をゼロ点とし、前記比較信号を交流電源波形信号とすることで、交流電源波形のゼロ点検知を行うゼロ点検知回路。 A zero point detection circuit that performs zero point detection of an AC power supply waveform by using the comparison circuit according to any one of claims 1 to 7, wherein the reference signal is a zero point, and the comparison signal is an AC power supply waveform signal. .
  9.  請求項8に記載のゼロ点検知回路と、
     出力目標値をトリガ角に変換する出力目標値トリガ角変換部と、
     前記ゼロ点検知回路によって検知される交流電源波形のゼロ点に基づいて、前記トリガ角を出力するトリガ角出力部と、
     前記トリガ角に基づいてサイリスタを制御するサイリスタ制御部と、
     を備えることを特徴とする交流電力調整器。
    A zero point detection circuit according to claim 8,
    An output target value trigger angle conversion unit for converting an output target value into a trigger angle,
    A trigger angle output unit that outputs the trigger angle based on a zero point of the AC power supply waveform detected by the zero point detection circuit,
    A thyristor control unit that controls a thyristor based on the trigger angle;
    An AC power regulator comprising:
  10.  基準信号と比較信号の高低の比較結果を出力する比較方法であって、
     2つのヒステリシスコンパレータを用い、
     前記基準信号と比較信号を、前記2つのヒステリシスコンパレータのそれぞれに入力するステップと、
     前記2つのヒステリシスコンパレータに入力される基準信号に、異なるバイアスを加えるステップと、
     前記2つのヒステリシスコンパレータの一方のヒステリシスコンパレータのHighからLowへの出力反転に基づき、出力信号をHighからLow若しくはLowからHighに反転させ、他方のヒステリシスコンパレータのLowからHighへの出力反転に基づき、出力信号をLowからHigh若しくはHighからLowに反転させるステップと、
     を備えることを特徴とする信号比較方法。
    A comparison method for outputting a high / low comparison result of a reference signal and a comparison signal,
    Using two hysteresis comparators,
    Inputting the reference signal and the comparison signal to each of the two hysteresis comparators;
    Applying different biases to the reference signals input to the two hysteresis comparators;
    The output signal is inverted from High to Low or from Low to High based on the output inversion from High to Low of one of the two hysteresis comparators, and based on the output inversion from Low to High on the other hysteresis comparator. Inverting the output signal from Low to High or from High to Low;
    A signal comparison method comprising:
  11.  基準信号と比較信号の高低の比較結果を出力する比較方法であって、
     2つのヒステリシスコンパレータと、
     前記基準信号と比較信号を、前記2つのヒステリシスコンパレータのそれぞれに入力するステップと、
     前記2つのヒステリシスコンパレータに入力される比較信号に、異なるバイアスを加えるステップと、
     前記2つのヒステリシスコンパレータの一方のヒステリシスコンパレータのHighからLowへの出力反転に基づき、出力信号をHighからLow若しくはLowからHighに反転させ、他方のヒステリシスコンパレータのLowからHighへの出力反転に基づき、出力信号をLowからHigh若しくはHighからLowに反転させるステップと、
     を備えることを特徴とする信号比較方法。
    A comparison method for outputting a high / low comparison result of a reference signal and a comparison signal,
    Two hysteresis comparators,
    Inputting the reference signal and the comparison signal to each of the two hysteresis comparators;
    Applying different biases to the comparison signals input to the two hysteresis comparators;
    The output signal is inverted from High to Low or from Low to High based on the output inversion from High to Low of one of the two hysteresis comparators, and based on the output inversion from Low to High on the other hysteresis comparator. Inverting the output signal from Low to High or from High to Low;
    A signal comparison method comprising:
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