WO2020062422A1 - 一种阵列基板及显示面板 - Google Patents

一种阵列基板及显示面板 Download PDF

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WO2020062422A1
WO2020062422A1 PCT/CN2018/113345 CN2018113345W WO2020062422A1 WO 2020062422 A1 WO2020062422 A1 WO 2020062422A1 CN 2018113345 W CN2018113345 W CN 2018113345W WO 2020062422 A1 WO2020062422 A1 WO 2020062422A1
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layer
semiconductor active
gate
etch barrier
source
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French (fr)
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黄北洲
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HKC Co Ltd
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HKC Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6732—Bottom-gate only TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6745—Polycrystalline or microcrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6746—Amorphous silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs

Definitions

  • the present application relates to the field of display devices, and in particular, to an array substrate and a display panel.
  • the active liquid crystal display includes an active array substrate, a color filter substrate, and a liquid crystal layer located between the two substrates.
  • the organic light emitting diode display is mainly composed of an active array substrate and an organic light emitting diode. Both display methods require a stable and reliable array substrate.
  • Thin film transistors are the main functional devices of array substrates.
  • TFTs Thin film transistors
  • holes are usually formed on the etching barrier layer to expose the semiconductor active layer, and then the source and drain are partially etched through.
  • the hole on the barrier layer overlaps the middle region of the semiconductor active layer. In this way, the overlapping area between the source and drain and the gate below the semiconductor active layer is large, which will cause a large parasitic capacitance of the thin film transistor, which is not conducive Make large size, high resolution displays.
  • An object of the present application is to provide an array substrate, including but not limited to solving the problem of large parasitic capacitance of the array substrate.
  • an array substrate including:
  • a gate provided on the base layer
  • a semiconductor active layer provided on a side of the gate insulating layer remote from the gate;
  • a first etch barrier layer is provided on a side of the semiconductor active layer away from the gate insulating layer, and two ends of the semiconductor active layer are opposite to the first etch layer; Exposed etch barriers; and
  • the source-drain layer includes a source electrode and a drain electrode, which respectively cover both ends of the first etch barrier layer, and at least cover exposed ends of the semiconductor active layer with respect to the first etch barrier layer.
  • Another object of the present application is to provide a display panel, including:
  • a gate provided on the base layer
  • a semiconductor active layer provided on a side of the gate insulating layer remote from the gate;
  • a first etch barrier layer is provided on a side of the semiconductor active layer away from the gate insulating layer, and two ends of the semiconductor active layer are opposite to the first etch layer; The etch barrier is exposed;
  • the source-drain layer includes a source electrode and a drain electrode, respectively covering both ends of the first etch barrier layer, and covering at least the exposed ends of the semiconductor active layer relative to the first etch barrier layer;
  • Liquid crystal which is filled between the color filter substrate and the source-drain layer.
  • Another object of the present application is to provide an array substrate, including:
  • a gate provided on the base layer
  • a semiconductor active layer provided on a side of the gate insulating layer remote from the gate, the semiconductor active layer being an oxide semiconductor active layer;
  • a first etch barrier layer is provided on a side of the semiconductor active layer away from the gate insulating layer, and two ends of the semiconductor active layer are opposite to the first etch layer; The etch barrier is exposed;
  • a second etch barrier layer which is disposed on the gate insulating layer, is spaced apart from the first etch barrier layer and the semiconductor active layer, and is offset from the gate; as well as
  • the source-drain layer includes a source electrode and a drain electrode, respectively covering both ends of the first etch barrier layer, and covering at least an exposed end of the semiconductor active layer with respect to the first etch barrier layer.
  • the array substrate provided in the embodiment of the present application removes the positions corresponding to the edges of the etch stop layer and the semiconductor active layer. At this time, the distance between the source and the drain can be increased, so that the overlapping area with the gate is reduced, The parasitic capacitance generated between the source-drain layer and the gate is reduced, and the display quality of the corresponding display panel is improved.
  • FIG. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of an array substrate in another embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of an array substrate in a comparative example of the present application.
  • an embodiment of the present application provides an array substrate, which includes a base layer 6, a gate 2, a gate insulating layer 1, a semiconductor active layer, a first etch barrier layer 7, and a source-drain layer. 5; the gate 2 is provided on the base layer 6; the gate insulating layer 1 covers at least the gate 2; the semiconductor active layer is provided on the side of the gate insulating layer 1 away from the gate 2; the first etch barrier layer 7 The semiconductor active layer is located on a side away from the gate insulating layer 1 and both ends of the semiconductor active layer are exposed relative to the first etch barrier layer 7; the source-drain layer 5 includes a source and a drain, and the source and the drain Both ends of the first etch barrier layer 7 are covered, and the source-drain layer 5 covers at least the exposed ends of the semiconductor active layer relative to the first etch barrier layer 7.
  • both ends of the semiconductor active layer are exposed relative to the first etch barrier layer 7, and the source and drain of the source-drain layer 5 are respectively covered at both ends of the first etch barrier layer 7. , After ensuring that the source and drain are electrically connected, after the source and drain are moved away from the middle of the semiconductor active layer, the area of overlap between the source and drain and the gate 2 is reduced, The reduction of parasitic capacitance is finally achieved.
  • an array substrate provided by a comparative example of the present application is provided with a connection via hole in the etch barrier layer 4, and a source and a drain of the source-drain layer 5 realize active connection with the semiconductor through the connection via hole.
  • the layers are overlapped to achieve the electrical connection between the source and the drain.
  • this arrangement of the source-drain layer 5 makes the area of the overlap between the source-drain layer 5 and the gate 2 larger, which leads to a larger parasitic capacitance. Facilitates the production of high-resolution displays.
  • the array substrate provided in the embodiment of the present application effectively reduces the area of overlap between the source and drain electrodes and the gate electrode 2, thereby reducing the parasitic capacitance and meeting the large size and high resolution. Production requirements for the display.
  • the array substrate further includes a protective layer 9.
  • the protective layer 9 covers the source-drain layer 5.
  • the protective layer 9 at least covers the exposed middle portion of the first etch barrier layer 7 relative to the source-drain layer 5.
  • the protective layer 9 completely covers the source-drain layer 5 so as to isolate the source-drain layer 5 from the outside and ensure the electrical safety of the source-drain layer 5.
  • the protective layer 9 covers the first etch barrier layer 7 and is exposed to the source-drain layer 5 simultaneously The portion is specifically the middle of the first etch barrier layer 7 to protect the exposed portion of the first etch layer.
  • the protective layer 9 also covers exposed ends of the gate insulating layer 1 relative to the semiconductor active layer and the source-drain layer 5.
  • the semiconductor active layer and the source-drain layer 5 cover a part of the gate insulating layer 1.
  • the protective layer 9 is used to cover the positions of the gate insulating layer 1 that are not covered by the semiconductor active layer and the source-drain layer 5 to realize the gate.
  • the electrode insulating layer 1 is completely covered, so that the side of the gate insulating layer 1 away from the gate 2 is covered and protected by the protective layer 9, the semiconductor active layer, and the source-drain layer 5.
  • the semiconductor active layer is an amorphous silicon semiconductor active layer, a polysilicon semiconductor active layer, or an oxide semiconductor active layer.
  • An oxide semiconductor active layer is optional in this embodiment.
  • the array substrate further includes: a second etch barrier layer 8, the second etch barrier layer 8 is disposed on the gate insulating layer 1, the second etch barrier layer 8 and the first
  • the etch stop layer 7 and the semiconductor active layer are arranged at intervals, and the second etch stop layer 8 and the gate 2 are offset from each other.
  • the etch stop layer includes the first etch stop layer 7 provided on a side of the semiconductor active layer remote from the gate 2, and the second etch stop provided on opposite sides of the first etch stop layer 7.
  • the second etch barrier layer 8 is offset from the gate 2, that is, the second etch barrier layer 8 is provided at a portion of the gate insulating layer 1 that does not cover the gate 2; that is, during the manufacturing process of the etch barrier Only the area between the first etch barrier layer 7 and the second etch barrier layer 8 needs to be etched. Compared to retaining only the first etch barrier layer 7, the etched area is reduced, and the substrate with a larger area is significantly less. It has reduced the etching time and processing cost.
  • the array substrate further includes a protective layer 9.
  • the protective layer 9 covers the source-drain layer 5.
  • the protective layer 9 at least covers a part of the second etching layer exposed from the source-drain layer 5.
  • the protective layer 9 completely covers the source-drain layer 5 so as to isolate the source-drain layer 5 from the outside and ensure the electrical safety of the source-drain layer 5.
  • the protective layer 9 simultaneously covers the exposed portion of the second etching layer relative to the source-drain layer 5 To protect the exposed portion of the second etching layer.
  • the protective layer 9 also covers the exposed portion of the first etch barrier layer 7 relative to the source-drain layer 5.
  • the protective layer 9 covers the exposed portion of the first etch barrier layer 7 relative to the source / drain layer 5 synchronously, specifically, the middle portion of the first etch barrier layer 7 to protect the exposed portion of the first etch layer.
  • the projection of the semiconductor active layer on the gate 2 is within the boundary of the gate 2. Both ends of the semiconductor active layer are exposed relative to the first etch barrier layer 7, and the projection of the semiconductor active layer on the gate 2 is within the boundary of the gate 2, which can ensure that the source and drain are far away from the semiconductor. After the middle direction of the source layer is moved, the area of overlap between the source-drain layer 5 and the gate 2 is significantly reduced, thereby reducing parasitic capacitance.
  • an embodiment of the present application further provides a display panel including the above-mentioned array substrate and other necessary components.
  • the liquid crystal display panel further includes a color filter substrate, a liquid crystal, and a frame.
  • the display panel provided in the embodiment has a higher resolution and can be set to a larger size.
  • the display panel may also be an organic light-emitting display panel, including the above-mentioned array substrate and other necessary components, and the required components include components such as an organic material coating that emits light by itself when powered on.

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  • Microelectronics & Electronic Packaging (AREA)
  • Engineering & Computer Science (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
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Abstract

一种阵列基板及显示面板。其中，阵列基板包括基层(6)、栅极(2)、栅极绝缘层(1)、半导体有源层、第一刻蚀阻挡层(4)以及源漏层(5)；栅极(2)设于基层(6)上；栅极绝缘层(1)覆盖于栅极(2)上。

Description

一种阵列基板及显示面板 技术领域
本申请涉及显示设备领域，尤其涉及一种阵列基板及显示面板。
背景技术
随着显示科技的日渐进步，平板显示成为人们不可缺少的必备品之一。主动式液晶显示器包括主动阵列基板，彩色滤光片基板以及与位于两基板之间的液晶层所构成。有机发光二极管显示器主要由主动阵列基板和有机发光二极管组成。两种显示方式均需要有稳定可靠的阵列基板。
薄膜晶体管(Thin Film Transistor，TFT)是阵列基板的主要功能器件，制作TFT时，通常在刻蚀阻挡层上采用挖孔的方式，使半导体有源层部分露出，然后源漏极局部贯穿刻蚀阻挡层上的孔与半导体有源层的中部区域搭接，这样，源极和漏极与半导体有源层下方的栅极的重叠区域较大，会导致薄膜晶体管的寄生电容较大，不利于制作大尺寸高分辨显示器。
申请内容
本申请一目的在于提供一种阵列基板，包括但不限于解决阵列基板的寄生电容较大的问题。
为解决上述技术问题，本申请实施例采用的技术方案是：提供一种阵列基板，包括：
基层；
栅极，所述栅极设于所述基层上；
栅极绝缘层，至少覆盖于所述栅极上；
半导体有源层，所述半导体有源层设于所述栅极绝缘层远离所述栅极的一侧；
第一刻蚀阻挡层，所述第一刻蚀阻挡层设于所述半导体有源层远离所述栅极绝缘层的一侧，所述半导体有源层的两端相对于所述第一刻蚀阻挡层外露；以及
源漏层，包括源极和漏极，分别覆盖于所述第一刻蚀阻挡层的两端，并至少覆盖所述半导体有源层相对第一刻蚀阻挡层外露的端部。
本申请的另一目的在于提供一种显示面板，包括：
基层；
栅极，所述栅极设于所述基层上；
栅极绝缘层，至少覆盖于所述栅极上；
半导体有源层，所述半导体有源层设于所述栅极绝缘层远离所述栅极的一侧；
第一刻蚀阻挡层，所述第一刻蚀阻挡层设于所述半导体有源层远离所述栅极绝缘层的一侧，所述半导体有源层的两端相对于所述第一刻蚀阻挡层外露；
源漏层，包括源极和漏极，分别覆盖于所述第一刻蚀阻挡层的两端，并至少覆盖所述半导体有源层相对第一刻蚀阻挡层外露的端部；
彩色滤光片基板；以及
液晶，所述液晶填充于所述彩色滤光片基板与所述源漏层之间。
本申请的再一目的在于提供一种一种阵列基板，包括：
基层；
栅极，所述栅极设于所述基层上；
栅极绝缘层，至少覆盖于所述栅极上；
半导体有源层，所述半导体有源层设于所述栅极绝缘层远离所述栅极的一侧，所述半导体有源层为氧化物半导体有源层；
第一刻蚀阻挡层，所述第一刻蚀阻挡层设于所述半导体有源层远离所述栅极绝缘层的一侧，所述半导体有源层的两端相对于所述第一刻蚀阻挡层外露；
第二刻蚀阻挡层，所述第二刻蚀阻挡层设于所述栅极绝缘层上，与所述第一刻蚀阻挡层及半导体有源层间隔设置，与所述栅极相互错位；以及
源漏层，包括源极和漏极，分别覆盖所述第一刻蚀阻挡层的两端，并至少覆盖所述半导体有源层相对第一刻蚀阻挡层外露的端部。
本申请实施例提供的阵列基板将刻蚀阻挡层与半导体有源层的边缘对应的位置去除，此时源极和漏极的间距得以增大，使其与栅极的重叠面积减小，减小了源漏层与栅极之间产生的寄生电容，提高相应显示面板的显示品质。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图。
图1为本申请的一个实施例中的阵列基板的结构示意图；
图2为本申请的另一个实施例中的阵列基板的结构示意图；
图3为本申请的对比例中的阵列基板的结构示意图。
具体实施方式
为了使本发明的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅 用以解释本发明，并不用于限定本发明。
需说明的是，当部件被称为“固定于”或“设置于”另一个部件，它可以直接在另一个部件上或者间接在该另一个部件上。当一个部件被称为是“连接于”另一个部件，它可以是直接或者间接连接至该另一个部件上。术语“上”、“下”、“左”、“右”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本专利的限制，对于本领域的普通技术人员而言，可以根据具体情况理解上述术语的具体含义。术语“第一”、“第二”仅用于便于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明技术特征的数量。“多个”的含义是两个或两个以上，除非另有明确具体的限定。
为了说明本申请所述的技术方案，以下结合具体附图及实施例进行详细说明。
如图1-图2所示，本申请实施例提出了一种阵列基板，包括基层6、栅极2、栅极绝缘层1、半导体有源层、第一刻蚀阻挡层7以及源漏层5；栅极2设于基层6上；栅极绝缘层1至少覆盖于栅极2上；半导体有源层设于栅极绝缘层1远离栅极2的一侧；第一刻蚀阻挡层7设于半导体有源层远离栅极绝缘层1的一侧，半导体有源层的两端相对于第一刻蚀阻挡层7外露；源漏层5包括源极和漏极，源极和漏极分别覆盖于第一刻蚀阻挡层7的两端，源漏层5并至少覆盖半导体有源层相对第一刻蚀阻挡层7外露的端部。
在本申请的实施例中，半导体有源层的两端相对于第一刻蚀阻挡层7外露，将源漏层5的源极和漏极分别覆盖于第一刻蚀阻挡层7的两端，在保证源极和漏极电连接的情况下实现了源极和漏极向远离半导体有源层的中部的方 向移动后，进而减小了源漏极与栅极2之间重叠的面积，最终实现寄生电容的减小。
如图3所示，本申请的对比例提供的一种阵列基板，在刻蚀阻挡层4上开设连接通孔，源漏层5的源极和漏极通过该连接通孔实现与半导体有源层搭接，从而实现源极和漏极的电连接，但源漏层5的此种设置方式使得源漏层5与栅极2之间重叠的面积较大，进而导致寄生电容较大，不利于制作高分辨率显示器。而本申请的实施例中提供的阵列基板相对于对比例提供的阵列基板有效减少了源漏极与栅极2之间重叠的面积，进而实现寄生电容的减小，满足了大尺寸高分辨率显示器的制作要求。
在一个实施例中，请参阅图2，阵列基板还包括保护层9，保护层9覆盖源漏层5，保护层9并至少覆盖第一刻蚀阻挡层7相对源漏层5外露的中部。保护层9完全覆盖源漏层5，以实现将源漏层5与外部隔离，保证源漏层5的电性安全；保护层9同步覆盖于第一刻蚀阻挡层7相对源漏层5外露的部分，具体为第一刻蚀阻挡层7的中部以实现对第一刻蚀层外露的部分进行保护。
在一个实施例中，请参阅图2，保护层9还覆盖栅极绝缘层1相对于半导体有源层和源漏层5外露的端部。半导体有源层和源漏层5覆盖于栅极绝缘层1的部分区域，利用保护层9对栅极绝缘层1未被半导体有源层和源漏层5未覆盖的位置进行覆盖，实现栅极绝缘层1被完全覆盖，进而实现栅极绝缘层1远离栅极2的一侧被保护层9、半导体有源层和源漏层5覆盖保护。
在一个实施例中，半导体有源层为非晶硅半导体有源层、多晶硅半导体有源层或氧化物半导体有源层。于本实施例中可选为氧化物半导体有源层。
在一个实施例中，请参阅图1，阵列基板还包括：第二刻蚀阻挡层8，第二刻蚀阻挡层8设于栅极绝缘层1上，第二刻蚀阻挡层8与第一刻蚀阻挡层7 及半导体有源层间隔设置，第二刻蚀阻挡层8与栅极2相互错位。刻蚀阻挡层包括设于半导体有源层远离栅极2的一侧的上述第一刻蚀阻挡层7、以及设于第一刻蚀阻挡层7的相对的两侧的上述第二刻蚀阻挡层8，第二刻蚀阻挡层8与栅极2错位设置，即第二刻蚀阻挡层8设置于栅极绝缘层1未覆盖栅极2的部位；也即在刻蚀阻挡层的制作过程中只需要蚀刻第一刻蚀阻挡层7与第二刻蚀阻挡层8之间的区域，相对于只保留第一刻蚀阻挡层7减少了蚀刻的面积，对于面积较大的基板显著较少了蚀刻的时间及加工成本。
在一个实施例中，请参阅图1，阵列基板还包括保护层9，保护层9覆盖源漏层5，保护层9并至少覆盖第二刻蚀层相对源漏层5外露的部位。保护层9完全覆盖源漏层5，以实现将源漏层5与外部隔离，保证源漏层5的电性安全；保护层9同步覆盖于第二刻蚀层相对源漏层5外露的部分，以实现对第二刻蚀层外露的部分进行保护。
在一个实施例中，请参阅图1，保护层9还覆盖第一刻蚀阻挡层7相对源漏层5外露的部位。保护层9同步覆盖于第一刻蚀阻挡层7相对源漏层5外露的部分，具体为第一刻蚀阻挡层7的中部以实现对第一刻蚀层外露的部分进行保护。
在一个实施例中，请参阅图1-图2，半导体有源层于栅极2上的投影位于栅极2的边界范围内。半导体有源层的两端相对于第一刻蚀阻挡层7外露，且半导体有源层于栅极2上的投影位于栅极2的边界范围内，可确保源极和漏极向远离半导体有源层的中部方向移动后，源漏层5与栅极2之间重叠的面积显著减小，进而减小了寄生电容。
本申请实施例还提出了一种显示面板，包括上述的阵列基板及其他必备组件，例如液晶显示面板中，还包括彩色滤光片基板、液晶以及边框，彩色滤光 片基板和阵列基板对组设置，边框密封彩色滤光片基板和阵列基板的周边部位，液晶则填充于彩色滤光片基板和阵列基板之间。如前所述，该显示面板由于阵列基板中源漏极与栅极2之间的重叠面积较小，也即产生的寄生电容较小，能够满足大尺寸高分辨率显示器的制作要求，因此本实施例提供的显示面板的分辨率较高且可设置为较大的尺寸。
当然，于本申请的实施例中，上述显示面板也可为有机发光显示面板，包括上述的阵列基板及其他必备组件，必备组件包括在通电情况下自行发光的有机材料涂层等组件。
显然，本申请的上述实施例仅仅是为了清楚说明本申请所作的举例，而并非是对本申请的实施方式的限定。对于所属领域的普通技术人员来说，在上述说明的基础上还可以做出其它不同形式的变化或变动。这里无需也无法对所有的实施方式予以穷举。凡在本申请的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本申请权利要求的保护范围之内。

Claims (20)

  1. 一种阵列基板，包括：
    基层；
    栅极，所述栅极设于所述基层上；
    栅极绝缘层，至少覆盖于所述栅极上；
    半导体有源层，所述半导体有源层设于所述栅极绝缘层远离所述栅极的一侧；
    第一刻蚀阻挡层，所述第一刻蚀阻挡层设于所述半导体有源层远离所述栅极绝缘层的一侧，所述半导体有源层的两端相对于所述第一刻蚀阻挡层外露；以及
    源漏层，包括源极和漏极，分别覆盖于所述第一刻蚀阻挡层的两端，并至少覆盖所述半导体有源层相对第一刻蚀阻挡层外露的端部。
  2. 根据权利要求1所述的阵列基板，所述阵列基板还包括保护层，所述保护层覆盖所述源漏层，所述保护层并至少覆盖所述第一刻蚀阻挡层相对所述源漏层外露的部位。
  3. 根据权利要求2所述的阵列基板，所述保护层还覆盖所述栅极绝缘层相对于所述半导体有源层和所述源漏层外露的部位。
  4. 根据权利要求1所述的阵列基板，所述半导体有源层为非晶硅半导体有源层、多晶硅半导体有源层或氧化物半导体有源层。
  5. 根据权利要求1所述的阵列基板，所述阵列基板还包括：
    第二刻蚀阻挡层，所述第二刻蚀阻挡层设于所述栅极绝缘层上，与所述第一刻蚀阻挡层及半导体有源层间隔设置，与所述栅极相互错位。
  6. 根据权利要求5所述的阵列基板，所述阵列基板还包括保护层，所述保护层覆盖所述源漏层，所述保护层并至少覆盖所述第二刻蚀层相对所述源漏层外露的部位。
  7. 根据权利要求6所述的阵列基板，所述保护层还覆盖所述第一刻蚀阻挡层相对所述源漏层外露的部位。
  8. 根据权利要求1所述的阵列基板，所述半导体有源层于所述栅极上的投影位于所述栅极的边界范围内。
  9. 根据权利要求3所述的阵列基板，所述半导体有源层于所述栅极上的投影位于所述栅极的边界范围内。
  10. 根据权利要求7所述的阵列基板，所述半导体有源层于所述栅极上的投影位于所述栅极的边界范围内。
  11. 显示面板，包括：
    基层；
    栅极，所述栅极设于所述基层上；
    栅极绝缘层，至少覆盖于所述栅极上；
    半导体有源层，所述半导体有源层设于所述栅极绝缘层远离所述栅极的一侧；
    第一刻蚀阻挡层，所述第一刻蚀阻挡层设于所述半导体有源层远离所述栅极绝缘层的一侧，所述半导体有源层的两端相对于所述第一刻蚀阻挡层外露；
    源漏层，包括源极和漏极，分别覆盖于所述第一刻蚀阻挡层的两端，并至少覆盖所述半导体有源层相对第一刻蚀阻挡层外露的端部；
    彩色滤光片基板；以及
    液晶，所述液晶填充于所述彩色滤光片基板与所述源漏层之间。
  12. 根据权利要求11所述的显示面板，所述显示面板还包括边框，所述边框密封所述彩色滤光片基板和所述基层的周边部位。
  13. 根据权利要求11所述的显示面板，所述显示面板还包括保护层，所述保护层覆盖所述源漏层以及所述第一刻蚀阻挡层相对所述源漏层外露的部位。
  14. 根据权利要求13所述的显示面板，所述保护层还覆盖所述栅极绝缘层相对于所述半导体有源层和所述源漏层外露的部位。
  15. 根据权利要求11所述的显示面板，所述半导体有源层为非晶硅半导体有源层、多晶硅半导体有源层或氧化物半导体有源层。
  16. 根据权利要求11所述的显示面板，所述显示面板还包括：
    第二刻蚀阻挡层，所述第二刻蚀阻挡层设于所述栅极绝缘层上，与所述第一刻蚀阻挡层及半导体有源层间隔设置，与所述栅极相互错位。
  17. 根据权利要求16所述的显示面板，所述显示面板还包括保护层，所述保护层覆盖所述源漏层以及所述第二刻蚀阻挡层相对所述源漏层外露的部位。
  18. 根据权利要求17所述的显示面板，所述保护层还覆盖所述第一刻蚀阻挡层相对所述源漏层外露的部位。
  19. 根据权利要求11所述的显示面板，所述半导体有源层于所述栅极上的投影位于所述栅极的边界范围内。
  20. 阵列基板，包括：
    基层；
    栅极，所述栅极设于所述基层上；
    栅极绝缘层，至少覆盖于所述栅极上；
    半导体有源层，所述半导体有源层设于所述栅极绝缘层远离所述栅极的一侧，所述半导体有源层为氧化物半导体有源层；
    第一刻蚀阻挡层，所述第一刻蚀阻挡层设于所述半导体有源层远离所述栅极绝缘层的一侧，所述半导体有源层的两端相对于所述第一刻蚀阻挡层外露；
    第二刻蚀阻挡层，所述第二刻蚀阻挡层设于所述栅极绝缘层上，与所述第一刻蚀阻挡层及半导体有源层间隔设置，与所述栅极相互错位；以及
    源漏层，包括源极和漏极，分别覆盖所述第一刻蚀阻挡层的两端，并至少覆盖所述半导体有源层相对第一刻蚀阻挡层外露的端部。
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Families Citing this family (2)

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Publication number Priority date Publication date Assignee Title
CN109244085A (zh) * 2018-09-27 2019-01-18 惠科股份有限公司 一种阵列基板及显示面板
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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09203908A (ja) * 1996-01-25 1997-08-05 Furontetsuku:Kk 液晶表示装置用薄膜トランジスタおよび液晶表示装置
CN102738243A (zh) * 2012-06-06 2012-10-17 北京京东方光电科技有限公司 晶体管、阵列基板及其制造方法、液晶面板和显示装置
KR20130032082A (ko) * 2011-09-22 2013-04-01 엘지디스플레이 주식회사 액정 표시 장치용 박막 트랜지스터 및 이의 제조 방법
KR20140014447A (ko) * 2012-07-24 2014-02-06 엘지디스플레이 주식회사 어레이 기판 및 그 제조방법
CN103681688A (zh) * 2012-08-31 2014-03-26 乐金显示有限公司 包含氧化物薄膜晶体管的基板、其制造方法及驱动电路
CN103744240A (zh) * 2013-12-27 2014-04-23 深圳市华星光电技术有限公司 阵列基板及用该阵列基板的液晶显示面板
CN107390406A (zh) * 2017-06-20 2017-11-24 惠科股份有限公司 一种显示面板、显示面板的制造方法和显示装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102365668A (zh) * 2009-04-10 2012-02-29 夏普株式会社 有源矩阵基板、显示面板、显示装置和激光照射方法
KR20120065854A (ko) * 2010-12-13 2012-06-21 엘지디스플레이 주식회사 산화물 박막 트랜지스터의 제조방법
CN104064601B (zh) * 2014-06-30 2017-12-26 上海天马微电子有限公司 Tft、tft阵列基板及其制造方法、显示面板、显示装置
CN109244085A (zh) * 2018-09-27 2019-01-18 惠科股份有限公司 一种阵列基板及显示面板

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09203908A (ja) * 1996-01-25 1997-08-05 Furontetsuku:Kk 液晶表示装置用薄膜トランジスタおよび液晶表示装置
KR20130032082A (ko) * 2011-09-22 2013-04-01 엘지디스플레이 주식회사 액정 표시 장치용 박막 트랜지스터 및 이의 제조 방법
CN102738243A (zh) * 2012-06-06 2012-10-17 北京京东方光电科技有限公司 晶体管、阵列基板及其制造方法、液晶面板和显示装置
KR20140014447A (ko) * 2012-07-24 2014-02-06 엘지디스플레이 주식회사 어레이 기판 및 그 제조방법
CN103681688A (zh) * 2012-08-31 2014-03-26 乐金显示有限公司 包含氧化物薄膜晶体管的基板、其制造方法及驱动电路
CN103744240A (zh) * 2013-12-27 2014-04-23 深圳市华星光电技术有限公司 阵列基板及用该阵列基板的液晶显示面板
CN107390406A (zh) * 2017-06-20 2017-11-24 惠科股份有限公司 一种显示面板、显示面板的制造方法和显示装置

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