WO2020062415A1 - 显示面板及其制造方法 - Google Patents

显示面板及其制造方法 Download PDF

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Publication number
WO2020062415A1
WO2020062415A1 PCT/CN2018/113268 CN2018113268W WO2020062415A1 WO 2020062415 A1 WO2020062415 A1 WO 2020062415A1 CN 2018113268 W CN2018113268 W CN 2018113268W WO 2020062415 A1 WO2020062415 A1 WO 2020062415A1
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Prior art keywords
doped region
layer
type
region
doped
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French (fr)
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颜源
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Priority to US16/311,693 priority Critical patent/US11869895B2/en
Publication of WO2020062415A1 publication Critical patent/WO2020062415A1/zh
Anticipated expiration legal-status Critical
Priority to US18/522,222 priority patent/US20240096899A1/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/803—Pixels having integrated switching, control, storage or amplification elements
    • H10F39/8037—Pixels having integrated switching, control, storage or amplification elements the integrated elements comprising a transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6745—Polycrystalline or microcrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F30/00—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors
    • H10F30/20—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors
    • H10F30/21—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors the devices being sensitive to infrared, visible or ultraviolet radiation
    • H10F30/22—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors the devices being sensitive to infrared, visible or ultraviolet radiation the devices having only one potential barrier, e.g. photodiodes
    • H10F30/221—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors the devices being sensitive to infrared, visible or ultraviolet radiation the devices having only one potential barrier, e.g. photodiodes the potential barrier being a PN homojunction
    • H10F30/2218—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors the devices being sensitive to infrared, visible or ultraviolet radiation the devices having only one potential barrier, e.g. photodiodes the potential barrier being a PN homojunction the devices comprising active layers made of only Group IV-VI materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/011—Manufacture or treatment of image sensors covered by group H10F39/12
    • H10F39/014—Manufacture or treatment of image sensors covered by group H10F39/12 of CMOS image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/011—Manufacture or treatment of image sensors covered by group H10F39/12
    • H10F39/016—Manufacture or treatment of image sensors covered by group H10F39/12 of thin-film-based image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/011—Manufacture or treatment of image sensors covered by group H10F39/12
    • H10F39/026—Wafer-level processing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10—Integrated devices
    • H10F39/12—Image sensors
    • H10F39/18—Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F71/00—Manufacture or treatment of devices covered by this subclass
    • H10F71/10—Manufacture or treatment of devices covered by this subclass the devices comprising amorphous semiconductor material
    • H10F71/103—Manufacture or treatment of devices covered by this subclass the devices comprising amorphous semiconductor material including only Group IV materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/10—Semiconductor bodies
    • H10F77/16—Material structures, e.g. crystalline structures, film structures or crystal plane orientations
    • H10F77/162—Non-monocrystalline materials, e.g. semiconductor particles embedded in insulating materials
    • H10F77/166—Amorphous semiconductors
    • H10F77/1662—Amorphous semiconductors including only Group IV materials
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to a display panel and a manufacturing method thereof, and more particularly, to a display panel for touch control and a manufacturing method thereof.
  • the medical amorphous silicon flat panel detector in the prior art is a traditional optical sensor, which includes an amorphous silicon photodiode and a thin film transistor.
  • FIG. 1 it is a schematic diagram of a pixel unit of a flat panel detector in the prior art.
  • a plurality of pixel units are formed on a transparent substrate 11, and each pixel unit includes a thin film transistor 12 and an amorphous silicon photoelectric device.
  • the diode 13, wherein the amorphous silicon photodiode 13 includes: a first light-shielding layer 131, a first insulating layer 132, a drain electrode layer 133, and an N-type layer 134 formed on the surface of the transparent substrate 11 in order.
  • an insulating layer 14 insulates the thin film transistor 12 from the amorphous silicon photodiode 13, and a second light-shielding layer 15 is formed on the surface of the thin film transistor 12 and the insulating layer 14 in an area that does not require light, A connection electrode 16 is formed on the contact electrode 137, and the passivation layer 17 is formed above the second light-shielding layer 15 and the connection electrode 16.
  • the first light-shielding layer 131 is in the same metal layer as the gate of the thin film transistor 12, and the drain electrode layer 133 is in the same metal layer as the drain of the thin film transistor 12.
  • the main part of the amorphous silicon photodiode is a stack of the P-type layer 136, the intermediate layer 135, and the N-type layer 134, wherein the intermediate layer 135 is lightly doped, and therefore,
  • the thickness of the flat panel detector is approximately the same as the thickness of the stacked layer of the amorphous silicon photodiode 13 above the drain of the thin film transistor 12, and the thickness of the intermediate layer 135 of the amorphous silicon photodiode is approximately 1 micron makes the thickness of the flat panel detector larger, and the optical path length of the incident light in the pixel unit of the flat panel detector is longer, which easily enters the adjacent pixel unit and causes interference.
  • the pixel unit includes the thin film transistor 12 and the amorphous silicon photodiode 13 separately disposed, wherein the thin film transistor 12 and the amorphous silicon photodiode 13 are separated by a distance, so that the occupied area of the pixel unit Larger and lower resolution.
  • the amorphous silicon photodiode 13 needs to be manufactured separately after the thin film transistor 12 is formed, and multiple steps of film formation and photolithography processes are required, so that the production cost is high.
  • An object of the present invention is to provide a display panel and a manufacturing method thereof.
  • the thin film transistor is formed by using polysilicon on a glass substrate, and an amorphous silicon photodiode is formed by using an ion implantation technology, so that the intensity of light reflected by a fingerprint can be changed. Recognized by an amorphous silicon photodiode.
  • an embodiment of the present invention provides a display panel, the display panel includes: a glass substrate; an insulating layer formed on the glass substrate; and an insulating layer formed on the insulating layer.
  • the three doped regions have different doping types, so that the first doped region and the third doped region form a PN structure, and the first doped region and the second doped region have the same Doping type.
  • the first doped region is two N-type heavily doped regions and is configured as an N + type layer
  • the third doped region is a P-type doped region and is configured Used as a P-type layer.
  • the polysilicon layer further defines a non-doped region, and the second doped region is two N-type lightly doped regions, and the N-type lightly doped regions are respectively located in the Opposite sides of the undoped region.
  • the PN structure formed by the N-type heavily doped region and the P-type doped region is defined as an amorphous silicon photodiode, the N-type lightly doped region, the The N-type heavily doped region and the gate layer are defined as a thin film transistor.
  • the display panel further includes a light shielding layer, the light shielding layer is formed on the glass substrate, and the insulating layer covers the light shielding layer.
  • another embodiment of the present invention provides a method for manufacturing a display panel.
  • the manufacturing method includes a polysilicon layer forming step, a first doped region doping step, and a second doped region.
  • a first doped region is defined in the polysilicon layer, and the first doped region is doped.
  • a gate insulating layer and a first metal layer are sequentially deposited, and the first metal layer is patterned as a gate layer, followed by the polysilicon layer.
  • a second doped region is defined in the second doped region, and the first doped region and the second doped region have the same doping type;
  • Three-doped region A third doped region is defined on a portion of a surface of the first doped region, and the third doped region is doped, wherein the first doped region and the third doped region are doped.
  • the regions have different doping types, so that the first doped region and the third doped region form a PN structure; in the step of forming the interlayer insulating layer, an interlayer insulating layer is deposited, and Forming a plurality of openings on the interlayer insulating layer; in the step of forming the source-drain contact layer, depositing a second metal layer on the openings, and patterning the second metal layer as a source-drain The contact layer makes the source-drain contact layer contact the first doped region and the third doped region.
  • the first doped region in the doping step of the first doped region, is two N-type heavily doped regions, and the N-type heavily doped region is subjected to N Type doping, so that the N-type heavily doped region is converted into an N + type layer.
  • the second doping region in the second doping region doping step, is two N-type lightly doped regions, and N is performed on the N-type lightly doped regions.
  • Type doping so that the N-type lightly doped region is converted into an N - type layer.
  • the third doping region is a P-type doped region, and the P-type doped region is P-type doped. Doped, so that the P-type doped region is converted into a P-type layer, and the P-type layer is located on the N + -type layer.
  • another embodiment of the present invention provides a display panel, the display panel includes: a glass substrate; an insulating layer formed on the glass substrate; and an insulating layer formed on the insulating layer.
  • the first doped region is two N-type heavily doped regions and is configured as an N + type layer
  • the third doped region is a P-type doped region and is configured Used as a P-type layer.
  • the polysilicon layer further defines a non-doped region, and the second doped region is two N-type lightly doped regions, and the N-type lightly doped regions are respectively located in the Opposite sides of the undoped region.
  • the PN structure formed by the N-type heavily doped region and the P-type doped region is defined as an amorphous silicon photodiode, the N-type lightly doped region, the The N-type heavily doped region and the gate layer are defined as a thin film transistor.
  • the display panel further includes a light shielding layer, the light shielding layer is formed on the glass substrate, and the insulating layer covers the light shielding layer.
  • the beneficial effect of the present invention is that: the thin film transistor is formed of polysilicon on the glass substrate, and the amorphous silicon photodiode is formed by using ion implantation technology, so that the intensity change of the light reflected by the fingerprint can be changed by the amorphous Silicon photodiode identification. Because the thin film transistor has a low leakage current, a better signal-to-noise ratio can be obtained by identifying the current of the amorphous silicon photodiode.
  • the PN structure can realize N-type and P-type doping through the depth of ion implantation and ion complementation effects, so that the thin film transistor and the amorphous silicon photodiode are prepared simultaneously in the manufacturing process, and there is no need to separately Add complex structures and processes.
  • FIG. 1 is a schematic diagram of a pixel unit of a flat panel detector in the prior art.
  • FIG. 2 is a schematic diagram of a preferred embodiment of the display panel of the present invention.
  • FIG. 3 is a flowchart of a preferred embodiment of a method for manufacturing a display panel according to the present invention.
  • FIG. 4 is a schematic diagram of a step of forming a light-shielding layer in a preferred embodiment of a method for manufacturing a display panel according to the present invention.
  • FIG. 5 is a schematic diagram of a polysilicon layer forming step in a preferred embodiment of a method for manufacturing a display panel according to the present invention.
  • FIG. 6 is a schematic diagram of an N-type doping step in a preferred embodiment of a method for manufacturing a display panel according to the present invention.
  • FIG. 7 is a schematic diagram of a gate layer forming step in a preferred embodiment of a method for manufacturing a display panel according to the present invention.
  • FIG. 8 is a schematic diagram of a P-type doping step in a preferred embodiment of a method for manufacturing a display panel of the present invention.
  • FIG. 9 is a schematic diagram of a step of forming an interlayer insulating layer in a preferred embodiment of a method for manufacturing a display panel according to the present invention.
  • FIG. 2 is a schematic diagram of a preferred embodiment of a display panel according to the present invention.
  • the display panel includes a glass substrate 21, a light-shielding layer 22, an insulating layer 23, a polysilicon layer 24, and a gate.
  • the present invention will explain in detail the relationship between the above components of each embodiment and its operating principle. .
  • a TFT with a top-gate structure is used for description.
  • the same method can also be applied to a TFT-structured display panel with a bottom-gate structure.
  • the TFTs of different semiconductor types are also applicable. For example, those skilled in the art can adjust the doping type of the N-type TFT and the P-type TFT.
  • the light shielding layer 22 is formed on the glass substrate 21, and the light shielding layer 22 has a first light shielding portion 221 and a second light shielding portion 222.
  • the first light shielding portion 221 and The second light shielding portions 222 are disposed on the glass substrate 21 at intervals.
  • the insulating layer 23 is formed on the light shielding layer 22 and the glass substrate 21, and the polysilicon layer 24 is formed on the insulating layer 23, wherein the polysilicon layer 24 defines a non- The doped region 241, a first doped region 243, a second doped region 242, and a third doped region 244, wherein the first doped region 243 and the third doped region 244 have different Doping type, so that the first doped region 243 and the third doped region 244 form a PN structure, and the first doped region 243 and the second doped region 242 have the same doping Types of.
  • the second doped region 242 is N-type lightly doped by ion implantation to form two N-type lightly doped regions
  • the first doped region 243 is N-type heavily doped by ion implantation.
  • Doping forms two N-type heavily doped regions
  • the third doped region 244 is p-type doped by ion implantation to form a p-type doped region.
  • different types may be doped, such as :
  • the second doped region 242 is P-type lightly doped
  • the first doped region 243 is P-type heavily doped
  • the third doped region 244 is N-type doped.
  • the second doped regions 242 are respectively located on two opposite sides of the non-doped region 241, and the two first doped regions 243 are respectively adjacent to the two second doped regions 242 away from the two One side of the undoped region 241, and the third doped region 244 overlaps one of the N-type heavily doped regions 243.
  • the non-doped region 241 overlaps with a projection of the gate layer 26 on the glass substrate 21, and the second light-shielding portion 222 of the light-shielding layer 22 and the second doped region A projection 242 on the glass substrate 21 overlaps.
  • the third doped region 244 overlaps a projection of the first light-shielding portion 221 of the light-shielding layer 22 on the glass substrate 21.
  • the gate insulating layer 25 is formed on the polysilicon layer 24, and the gate layer 26 is formed on the gate insulating layer 25, wherein the gate layer 26 is a pattern A first metal layer.
  • the interlayer insulating layer 27 is formed on the gate layer 26 and the gate insulating layer 25, and a plurality of openings 271 are formed in the interlayer insulating layer 27.
  • the opening 271 is configured to form the source-drain contact layer 28, so that the source-drain contact layer 28 is formed on the interlayer insulating layer 27.
  • the passivation layer 29 is formed on the source-drain contact layer 27 and the interlayer insulating layer 27.
  • the first doped region 243 is configured as an N + -type layer
  • the third doped region 244 is configured as a P-type layer, so that the first doped region 243 and the The third doped region 244 forms a PN structure, and the source-drain contact layer 28 contacts the N + -type layer and the P-type layer.
  • the PN structure formed by the first doped region 243 and the third doped region 244 is located above the first light-shielding portion 221, and can be defined as an amorphous silicon photodiode.
  • the anode of the amorphous silicon photodiode that is, the P-type layer is applied with a negative voltage between -3 and -9V, and when an optical signal is irradiated to the amorphous silicon photodiode At the time, the amorphous silicon photodiode generates an electron-hole pair.
  • the holes are collected in the P-type layer (anode), and electrons are collected in the N-type layer (cathode).
  • the second doped region 242, the first doped region 243, and the gate layer 26 are located above the second light shielding portion 222, and may be defined as a thin film transistor, such as a TFT thin film transistor.
  • a thin film transistor such as a TFT thin film transistor.
  • the thin film transistor is formed of polysilicon on the glass substrate 21, and the amorphous silicon photodiode is formed by using an ion implantation technology, so that the intensity change of the reflected light of the fingerprint can be changed by the amorphous silicon photoelectricity. Diode identification. Because the thin film transistor has a low leakage current, a better signal-to-noise ratio can be obtained by identifying the current of the amorphous silicon photodiode.
  • the PN structure can realize N-type and P-type doping through the depth of ion implantation and ion complementation effects, so that the thin film transistor and the amorphous silicon photodiode are prepared simultaneously in the manufacturing process, and there is no need to separately Add complex structures and processes.
  • FIGS. 2 to 9 are flowcharts of a preferred embodiment of a method for manufacturing a display panel according to the present invention.
  • the manufacturing method includes a light-shielding layer forming step S201, a polysilicon layer forming step S202, a first doped region doping step S203, a second doped region doping step S204, and a third doped region doping step.
  • S205 an interlayer insulating layer forming step S206, a source and drain contact layer forming step S207, and a passivation layer forming step S208.
  • the present invention will explain the relationship between each step and its operation principle in detail below.
  • a glass substrate 21 is provided, and an opaque material layer, such as metal, is deposited on the glass substrate 21, and the pattern is described.
  • An opaque material layer serves as a light shielding layer 22, and the light shielding layer 22 has a first light shielding portion 221 and a second light shielding portion 222, and the first light shielding portion 221 and the second light shielding portion 222 are disposed at intervals.
  • the glass substrate 21 On the glass substrate 21.
  • an insulating layer 23 is deposited on the glass substrate 21, and a polysilicon layer 24 is formed on the insulating layer 23.
  • a first doped region 243 is defined in the polysilicon layer 24, and the first doped region 243 is defined.
  • N-type doping is performed so that the first doped region 243 forms two N-type heavily doped regions and is converted into an N + -type layer.
  • a gate insulating layer 25 and a first metal layer are sequentially deposited, and the first metal layer is patterned as a gate. ⁇ ⁇ 26 ⁇ Polar layer 26.
  • a second doped region 242 is defined in the polysilicon layer 24, and the second doped region 242 is N-type doped, so that the second doped region 242 forms two N-type lightly doped regions.
  • the impurity region is converted into an N - type layer, wherein the first doped region 243 and the second doped region 242 have the same doping type.
  • a third doped region 244 is defined on a part of a surface of the first doped region 243, and The third doped region 244 is P-type doped, so that the third doped region 244 forms a P-type doped region and is converted into a P-type layer, wherein the first doped region 243 and the third The doped regions 244 have different doping types, and the P-type layer is located on the N + -type layer.
  • an interlayer insulating layer 27 is deposited, and a plurality of openings 271 are formed in the interlayer insulating layer 27.
  • a second metal layer is deposited in the opening 271, and the second metal layer is patterned as a source-drain.
  • the electrode contact layer 28 makes the source-drain contact layer 28 contact the first doped region 243 and the third doped region 244.
  • a high dielectric constant material layer is deposited as an passivation layer 29 in an atomic layer deposition manner.
  • the thin film transistor is formed of polysilicon on the glass substrate 21, and the amorphous silicon photodiode is formed by using an ion implantation technology, so that the intensity change of the reflected light of the fingerprint can be changed by the amorphous silicon photoelectricity. Diode identification. Because the thin film transistor has a low leakage current, a better signal-to-noise ratio can be obtained by identifying the current of the amorphous silicon photodiode.
  • the PN structure can realize N-type and P-type doping through the depth of ion implantation and ion complementation effects, so that the thin film transistor and the amorphous silicon photodiode are prepared simultaneously in the manufacturing process, and there is no need to separately Add complex structures and processes.

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  • Thin Film Transistor (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

提供一种显示面板及其制造方法。显示面板包括一玻璃基板（21）、一绝缘层（23）、一多晶硅层（24）、一栅极绝缘层（25）、一栅极层（26）、一层间绝缘层（27）及一源漏极接触层（28）。多晶硅层定义有一第一掺杂区域（243）、一第二掺杂区域（242）及一第三掺杂区域（244），且源漏极接触层接触第一掺杂区域及第三掺杂区域，第一掺杂区域及第三掺杂区域具有不同的掺杂类型，使得第一掺杂区域及第三掺杂区域形成一PN结构，而第一掺杂区域及第二掺杂区域具有相同的掺杂类型。

Description

显示面板及其制造方法 技术领域
本发明是有关于一种显示面板及其制造方法，特别是有关于一种用于触控的显示面板及其制造方法。
 背景技术
现有技术中的医疗用非晶硅平板探测器即是一种传统光学传感器，包括非晶硅光电二极管与薄膜晶体管。如图1所示，为现有技术一种平板探测器像素单元的一示意图，在一透明基板11上形成有多个像素单元，每个像素单元包括：一薄膜晶体管12及一非晶硅光电二极管13，其中所述非晶硅光电二极管13包括：形成于所述透明基板11表面依次形成一第一遮光层131、一第一绝缘层132，一漏极电极层133，一N型层134，一中间层135，一P型层136以及一接触电极137。
进一步来说，一绝缘层14将所述薄膜晶体管12与所述非晶硅光电二极管13绝缘，在所述薄膜晶体管12以及部分无需光照的区域的绝缘层14表面形成有一第二遮光层15，在所述接触电极137上形成有连接电极16，在所述第二遮光层15及所述连接电极16的上方形成所述钝化层17。其中所述第一遮光层131与所述薄膜晶体管12的栅极在同一金属层，所述漏极电极层133与所述薄膜晶体管12的漏极在同一金属层。
然而，所述非晶硅光电二极管的主要部分为所述P型层136、所述中间层135以及所述N型层134的叠层，其中所述中间层135经过轻掺杂处理，因此，所述平板探测器的厚度近似于在所述薄膜晶体管12的漏极以上又叠加所述非晶硅光电二极管13的叠层厚度，而且所述非晶硅光电二极管的中间层135的厚度约为1微米，使得平板探测器的厚度较大，入射光在所述平板探测器的像素单元中的光程较长，容易进入相邻的像素单元而产生干扰。
另外，所述像素单元包括分开设置的所述薄膜晶体管12与非晶硅光电二极管13，其中所述薄膜晶体管12与非晶硅光电二极管13之间相隔有一距离，使得所述像素单元的占据面积较大，分辨率较低。此外，所述非晶硅光电二极管13需要在形成所述薄膜晶体管12之后单独制作，需要多个步骤成膜与光刻工艺，使得生产成本较高。
因此，有必要提供改良的一种显示面板及其制造方法，以解决现有技术所存在的问题。
 技术问题
本发明的目的在于提供一种显示面板及其制造方法，利用在玻璃基板上以多晶硅形成所述薄膜晶体管，同时利用离子植入技术形成非晶硅光电二极管，使得指纹反射光的强弱变化可被非晶硅光电二极管识别。
 技术解决方案
为解决上述问题，本发明提供的技术方案如下：
为达成本发明的前述目的，本发明一实施例提供一种显示面板，所述显示面板包括：一玻璃基板；形成在所述玻璃基板上的一绝缘层；形成在所述绝缘层上的一多晶硅层；形成在所述多晶硅层上的一栅极绝缘层；形成在所述栅极绝缘层上的一栅极层；形成在所述栅极层上的一层间绝缘层；及形成在所述层间绝缘层的一源漏极接触层；形成在所述源漏极接触层及所述层间绝缘层上的一钝化层；其中所述多晶硅层定义有一第一掺杂区域、一第二掺杂区域及一第三掺杂区域，且所述源漏极接触层接触所述第一掺杂区域及所述第三掺杂区域，所述第一掺杂区域及所述第三掺杂区域具有不同的掺杂类型，使得所述第一掺杂区域及所述第三掺杂区域形成一PN结构，而所述第一掺杂区域及所述第二掺杂区域具有相同的掺杂类型。
在本发明的一实施例中，所述第一掺杂区域为二N型重掺杂区，配置用以作为N +型层，所述第三掺杂区域为一P型掺杂区，配置用以作为P型层。
在本发明的一实施例中，所述多晶硅层还定义有一非掺杂区，所述第二掺杂区域为二N型轻掺杂区，其中所述N型轻掺杂区分别位于所述非掺杂区的相对二侧。
在本发明的一实施例中，所述N型重掺杂区及所述P型掺杂区所形成的PN结构定义为一非晶硅光电二极管，所述N型轻掺杂区、所述N型重掺杂区及所述栅极层定义为一薄膜晶体管。
在本发明的一实施例中，所述非掺杂区与所述栅极层在所述玻璃基板的一投影重叠，所述P型掺杂区与所述N型重掺杂区在所述玻璃基板的一投影重叠。
在本发明的一实施例中，所述显示面板还包含一遮光层，所述遮光层形成在所述玻璃基板上，而且所述绝缘层覆盖在所述遮光层上。
为达成本发明的前述目的，本发明另一实施例提供一种显示面板的制造方法，所述制造方法包括一多晶硅层形成步骤、一第一掺杂区域掺杂步骤、一第二掺杂区域掺杂步骤、一第三掺杂区域掺杂步骤、一层间绝缘层形成步骤及一源漏极接触层形成步骤；在所述多晶硅层形成步骤中，在一玻璃基板上沉积一绝缘层，并且在所述绝缘层形成一多晶硅层；在所述第一掺杂区域掺杂步骤中，在所述多晶硅层中定义出一第一掺杂区域，并对所述第一掺杂区域进行掺杂；在所述第二掺杂区域掺杂步骤中，依次沉积一栅极绝缘层及一第一金属层，并图案化所述第一金属层作为一栅极层，接着在所述多晶硅层中定义出一第二掺杂区域，并对所述第二掺杂区域进行掺杂，其中所述第一掺杂区域及所述第二掺杂区域具有相同的掺杂类型；在所述第三掺杂区域掺杂步骤中，在所述第一掺杂区域的一表面的一部分定义出一第三掺杂区域，并对所述第三掺杂区域进行掺杂，其中所述第一掺杂区域及所述第三掺杂区域具有不同的掺杂类型，使得所述第一掺杂区域及所述第三掺杂区域形成一PN结构；在所述层间绝缘层形成步骤中，沉积一层间绝缘层，并且在所述层间绝缘层上形成多个开孔；在所述源漏极接触层形成步骤中，在所述开孔沉积一第二金属层，并图案化所述第二金属层作为一源漏极接触层，使得所述源漏极接触层接触所述第一掺杂区域及所述第三掺杂区域。
在本发明的一实施例中，在所述第一掺杂区域掺杂步骤中，所述第一掺杂区域为二N型重掺杂区，其中对所述N型重掺杂区进行N型掺杂，使得所述N型重掺杂区转化为N +型层。
在本发明的一实施例中，在所述第二掺杂区域掺杂步骤中，所述第二掺杂区域为二N型轻掺杂区，并且对所述N型轻掺杂区进行N型掺杂，使得所述N型轻掺杂区转化为N -型层。
在本发明的一实施例中，在所述第三掺杂区域掺杂步骤中，所述第三掺杂区域为一P型掺杂区，其中对所述P型掺杂区进行P型掺杂，使得所述P型掺杂区转化为P型层，且所述P型层位于在所述N +型层上。
为达成本发明的前述目的，本发明另一实施例提供一种显示面板，所述显示面板包括：一玻璃基板；形成在所述玻璃基板上的一绝缘层；形成在所述绝缘层上的一多晶硅层；形成在所述多晶硅层上的一栅极绝缘层；形成在所述栅极绝缘层上的一栅极层；形成在所述栅极层上的一层间绝缘层；及形成在所述层间绝缘层的一源漏极接触层；其中所述多晶硅层定义有一第一掺杂区域、一第二掺杂区域及一第三掺杂区域，且所述源漏极接触层接触所述第一掺杂区域及所述第三掺杂区域，所述第一掺杂区域及所述第三掺杂区域具有不同的掺杂类型，使得所述第一掺杂区域及所述第三掺杂区域形成一PN结构，而所述第一掺杂区域及所述第二掺杂区域具有相同的掺杂类型。
在本发明的一实施例中，所述第一掺杂区域为二N型重掺杂区，配置用以作为N +型层，所述第三掺杂区域为一P型掺杂区，配置用以作为P型层。
在本发明的一实施例中，所述多晶硅层还定义有一非掺杂区，所述第二掺杂区域为二N型轻掺杂区，其中所述N型轻掺杂区分别位于所述非掺杂区的相对二侧。
在本发明的一实施例中，所述N型重掺杂区及所述P型掺杂区所形成的PN结构定义为一非晶硅光电二极管，所述N型轻掺杂区、所述N型重掺杂区及所述栅极层定义为一薄膜晶体管。
在本发明的一实施例中，所述非掺杂区与所述栅极层在所述玻璃基板的一投影重叠，所述P型掺杂区与所述N型重掺杂区在所述玻璃基板的一投影重叠。
在本发明的一实施例中，所述显示面板还包含一遮光层，所述遮光层形成在所述玻璃基板上，而且所述绝缘层覆盖在所述遮光层上。
 有益效果
本发明的有益效果为：在所述玻璃基板上以多晶硅形成所述薄膜晶体管，同时利用离子植入技术形成所述非晶硅光电二极管，使得指纹反射光的强弱变化可被所述非晶硅光电二极管识别。由于所述薄膜晶体管具有低的漏电流，识别所述非晶硅光电二极管的电流可获得较佳的信噪比。另外，所述PN结构可通过离子植入的深度及离子互补效应来实现N型及P型掺杂，使得所述薄膜晶体管及所述非晶硅光电二极管在制程中同时备置，不用另外再增加复杂的结构及工艺。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是现有技术一种平板探测器像素单元的一示意图。
图2是本发明显示面板的一优选实施例的一示意图。
图3是本发明显示面板的制造方法的一优选实施例的一流程图。
图4是本发明显示面板的制造方法的一优选实施例在遮光层形成步骤的一示意图。
图5是本发明显示面板的制造方法的一优选实施例在多晶硅层形成步骤的一示意图。
图6是本发明显示面板的制造方法的一优选实施例在N型掺杂步骤的一示意图。
图7是本发明显示面板的制造方法的一优选实施例在栅极层形成步骤的一示意图。
图8是本发明显示面板的制造方法的一优选实施例在P型掺杂步骤的一示意图。
图9是本发明显示面板的制造方法的一优选实施例在层间绝缘层形成步骤的一示意图。
 本发明的最佳实施方式
以上对本发明实施例提供的液晶显示组件进行了详细介绍，本文中应用了具体个例对本发明的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本发明。同时，对于本领域的技术人员，依据本发明的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本发明的限制。以下各实施例的说明是参考附加的图示，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是用以相同标号表示。
请参照图2所示，为本发明显示面板的一优选实施例的一示意图，其中所述显示面板包括一玻璃基板21、一遮光层22、一绝缘层23、一多晶硅层24、一栅极绝缘层25、一栅极层26、一层间绝缘层27、一源漏极接触层28及一钝化层29，本发明将于下文详细说明各实施例上述各组件的关系及其运作原理。需要说明的是，本实施例中采用顶栅结构的TFT进行说明，同样的方式也可以应用于底栅结构的TFT结构的显示面板中。同理的，不同半导体类型的TFT本申请中的方案也同样适用。例如，领域技术人员可以按N型TFT与P型TFT的掺杂类型进行调整。
续参照图2所示，所述遮光层22形成在所述玻璃基板21上，而且所述遮光层22具有一第一遮光部221及一第二遮光部222，所述第一遮光部221及所述第二遮光部222间隔设置在所述玻璃基板21上。
续参照图2所示，所述绝缘层23形成在所述遮光层22及所述玻璃基板21上，所述多晶硅层24形成在所述绝缘层23上，其中所述多晶硅层24定义有一非掺杂区241、一第一掺杂区域243、一第二掺杂区域242及一第三掺杂区域244，其中所述第一掺杂区域243及所述第三掺杂区域244具有不同的掺杂类型，使得所述第一掺杂区域243及所述第三掺杂区域244形成一PN结构，而所述第一掺杂区域243及所述第二掺杂区域242具有相同的掺杂类型。在本实施例中，所述第二掺杂区域242通过离子植入进行N型轻掺杂形成二N型轻掺杂区，所述第一掺杂区域243通过离子植入进行N型重掺杂形成二N型重掺杂区，所述第三掺杂区域244通过离子植入进行P型掺杂形成一P型掺杂区，在其他实施例中，也可以掺杂不同的类型，例如：所述第二掺杂区域242进行P型轻掺杂、所述第一掺杂区域243进行P型重掺杂及所述第三掺杂区域244进行N型掺杂。
进一步来说，所述第二掺杂区域242分别位于所述非掺杂区241的相对二侧，所述两第一掺杂区域243分别邻接于所述两第二掺杂区域242远离所述非掺杂区241的一侧，而且所述第三掺杂区域244重叠在其中一所述N型重掺杂区上243。在本实施例中，所述非掺杂区241与所述栅极层26在所述玻璃基板21的一投影重叠，所述遮光层22的第二遮光部222与所述第二掺杂区域242在所述玻璃基板21的一投影重叠。所述第三掺杂区域244与所述遮光层22的第一遮光部221在所述玻璃基板21的一投影重叠。
续参照图2所示，所述栅极绝缘层25形成在所述多晶硅层24上，而且所述栅极层26形成在所述栅极绝缘层25上，其中所述栅极层26为图案化的一第一金属层。
续参照图2所示，所述层间绝缘层27形成在所述栅极层26及所述栅极绝缘层25上，其中所述层间绝缘层27上形成多个开孔271，所述开孔271配置用以形成所述源漏极接触层28，使得所述源漏极接触层28形成在所述层间绝缘层27上。所述钝化层29形成在所述源漏极接触层27及所述层间绝缘层27上。
续参照图2所示，所述第一掺杂区域243配置作为一N +型层，所述第三掺杂区域244配置作为一P型层，使得所述第一掺杂区域243及所述第三掺杂区域244形成一PN结构，而且所述源漏极接触层28接触所述N +型层及所述P型层。
依据上述的结构，所述第一掺杂区域243及所述第三掺杂区域244形成的PN结构位于所述第一遮光部221的上方，可被定义为一非晶硅光电二极管，以传感手指的反射光，其中所述非晶硅光电二极管的阳极，即所述P型层上加一个在-3至-9V之间的负电压，当光信号照射到所述非晶硅光电二极管上时，所述非晶硅光电二极管产生电子空穴对。在电场作用下，所述空穴汇聚在所述P型层(阳极)，电子汇聚到所述N型层(阴极)。另外，所述第二掺杂区域242、所述第一掺杂区域243及所述栅极层26位于所述第二遮光部222的上方，可被定义为一薄膜晶体管，例如TFT薄膜晶体管，当所述薄膜晶体管关断时，信号不断积累，当所述薄膜晶体管打开时，电荷输出至数据线，接着依据检测到的电荷信号的大小来判定光信号的强弱，以达到指纹识别的效果。
如上所述，在所述玻璃基板21上以多晶硅形成所述薄膜晶体管，同时利用离子植入技术形成所述非晶硅光电二极管，使得指纹反射光的强弱变化可被所述非晶硅光电二极管识别。由于所述薄膜晶体管具有低的漏电流，识别所述非晶硅光电二极管的电流可获得较佳的信噪比。另外，所述PN结构可通过离子植入的深度及离子互补效应来实现N型及P型掺杂，使得所述薄膜晶体管及所述非晶硅光电二极管在制程中同时备置，不用另外再增加复杂的结构及工艺。
请参照图2至9所示，为本发明显示面板的制造方法的一优选实施例的一流程图。所述制造方法包括一遮光层形成步骤S201、一多晶硅层形成步骤S202、一第一掺杂区域掺杂步骤S203、一第二掺杂区域掺杂步骤S204、一第三掺杂区域掺杂步骤S205、一层间绝缘层形成步骤S206、一源漏极接触层形成步骤S207及一钝化层形成步骤S208。本发明将于下文详细说明各步骤的关系及其运作原理。
请参照图3及4所示，在所述遮光层形成步骤S201中，提供一玻璃基板21，并且在所述玻璃基板21上沉积一不透光材料层，例如：金属，并图案化所述不透光材料层作为一遮光层22，而且所述遮光层22具有一第一遮光部221及一第二遮光部222，所述第一遮光部221及所述第二遮光部222间隔设置在所述玻璃基板21上。
请参照图3及5所示，在所述多晶硅层形成步骤S202中，在所述玻璃基板21上沉积一绝缘层23，并且在所述绝缘层23上形成一多晶硅层24。
请参照图3及6所示，在所述第一掺杂区域掺杂步骤S203中，在所述多晶硅层24中定义出一第一掺杂区域243，并且对所述第一掺杂区域243进行N型掺杂，使得所述第一掺杂区域243形成二N型重掺杂区而转化为一N +型层。
请参照图3及7所示，在所述第二掺杂区域掺杂步骤S204中，依次沉积一栅极绝缘层25及一第一金属层，并且图案化所述第一金属层作为一栅极层26。接着，在所述多晶硅层24中定义出一第二掺杂区域242，并且对所述第二掺杂区域242进行N型掺杂，使得所述第二掺杂区域242形成二N型轻掺杂区而转化为一N -型层，其中所述第一掺杂区域243及所述第二掺杂区域242具有相同的掺杂类型。
请参照图3及8所示，在所述第三掺杂区域掺杂步骤S205中，在所述第一掺杂区域243的一表面的一部分定义出一第三掺杂区域244，并且对所述第三掺杂区域244进行P型掺杂，使得所述第三掺杂区域244形成P型掺杂区而转化为一P型层，其中所述第一掺杂区域243及所述第三掺杂区域244具有不同的掺杂类型，而且所述P型层位于在所述N +型层上。
请参照图3及9所示，在所述层间绝缘层形成步骤S206中，沉积一层间绝缘层27，并且在所述层间绝缘层27上形成多个开孔271。
请参照图2、3及9所示，在所述源漏极接触层形成步骤S207中，在所述开孔271沉积一第二金属层，并图案化所述第二金属层作为一源漏极接触层28，使得所述源漏极接触层28接触所述第一掺杂区域243及所述第三掺杂区域244。另外，在所述钝化层形成步骤S208中，以原子层沉积方式沉积一高介电常数材料层作为一钝化层29。
如上所述，在所述玻璃基板21上以多晶硅形成所述薄膜晶体管，同时利用离子植入技术形成所述非晶硅光电二极管，使得指纹反射光的强弱变化可被所述非晶硅光电二极管识别。由于所述薄膜晶体管具有低的漏电流，识别所述非晶硅光电二极管的电流可获得较佳的信噪比。另外，所述PN结构可通过离子植入的深度及离子互补效应来实现N型及P型掺杂，使得所述薄膜晶体管及所述非晶硅光电二极管在制程中同时备置，不用另外再增加复杂的结构及工艺。
本发明已由上述相关实施例加以描述，然而上述实施例仅为实施本发明的范例。必需指出的是，已公开的实施例并未限制本发明的范围。相反地，包含于权利要求书的精神及范围的修改及均等设置均包括于本发明的范围内。

Claims (16)

  1. 一种显示面板，其特征在于：所述显示面板包括：一玻璃基板；形成在所述玻璃基板上的一绝缘层；形成在所述绝缘层上的一多晶硅层；形成在所述多晶硅层上的一栅极绝缘层；形成在所述栅极绝缘层上的一栅极层；形成在所述栅极层上的一层间绝缘层；及形成在所述层间绝缘层的一源漏极接触层；形成在所述源漏极接触层及所述层间绝缘层上的一钝化层；
    其中所述多晶硅层定义有一第一掺杂区域、一第二掺杂区域及一第三掺杂区域，且所述源漏极接触层接触所述第一掺杂区域及所述第三掺杂区域，所述第一掺杂区域及所述第三掺杂区域具有不同的掺杂类型，使得所述第一掺杂区域及所述第三掺杂区域形成一PN结构，而所述第一掺杂区域及所述第二掺杂区域具有相同的掺杂类型。
  2. 如权利要求1所述的显示面板，其特征在于：所述第一掺杂区域为二N型重掺杂区，配置用以作为N +型层，所述第三掺杂区域为一P型掺杂区，配置用以作为P型层。
  3. 如权利要求2所述的显示面板，其特征在于：所述多晶硅层还定义有一非掺杂区，所述第二掺杂区域为二N型轻掺杂区，其中所述N型轻掺杂区分别位于所述非掺杂区的相对二侧。
  4. 如权利要求3所述的显示面板，其特征在于：所述N型重掺杂区及所述P型掺杂区所形成的PN结构定义为一非晶硅光电二极管，所述N型轻掺杂区、所述N型重掺杂区及所述栅极层定义为一薄膜晶体管。
  5. 如权利要求3所述的显示面板，其特征在于：所述非掺杂区与所述栅极层在所述玻璃基板的一投影重叠，所述P型掺杂区与所述N型重掺杂区在所述玻璃基板的一投影重叠。
  6. 如权利要求1所述的显示面板，其特征在于：所述显示面板还包含一遮光层，所述遮光层形成在所述玻璃基板上，而且所述绝缘层覆盖在所述遮光层上。
  7. 一种如权利要求1的显示面板的制造方法，其特征在于：所述制造方法包括步骤：
    一多晶硅层形成步骤，在一玻璃基板上沉积一绝缘层，并且在所述绝缘层形成一多晶硅层；
    一第一掺杂区域掺杂步骤，在所述多晶硅层中定义出一第一掺杂区域，并对所述第一掺杂区域进行掺杂；
    一第二掺杂区域掺杂步骤，依次沉积一栅极绝缘层及一第一金属层，并图案化所述第一金属层作为一栅极层，接着在所述多晶硅层中定义出一第二掺杂区域，并对所述第二掺杂区域进行掺杂，其中所述第一掺杂区域及所述第二掺杂区域具有相同的掺杂类型；
    一第三掺杂区域掺杂步骤，在所述第一掺杂区域的一表面的一部分定义出一第三掺杂区域，并对所述第三掺杂区域进行掺杂，其中所述第一掺杂区域及所述第三掺杂区域具有不同的掺杂类型，使得所述第一掺杂区域及所述第三掺杂区域形成一PN结构；
    一层间绝缘层形成步骤，沉积一层间绝缘层，并且在所述层间绝缘层上形成多个开孔；及
    一源漏极接触层形成步骤，在所述开孔沉积一第二金属层，并图案化所述第二金属层作为一源漏极接触层，使得所述源漏极接触层接触所述第一掺杂区域及所述第三掺杂区域。
  8. 如权利要求7所述的制造方法，其特征在于：在所述第一掺杂区域掺杂步骤中，所述第一掺杂区域为二N型重掺杂区，其中对所述N型重掺杂区进行N型掺杂，使得所述N型重掺杂区转化为N +型层。
  9. 如权利要求7所述的制造方法，其特征在于：在所述第二掺杂区域掺杂步骤中，所述第二掺杂区域为二N型轻掺杂区，并且对所述N型轻掺杂区进行N型掺杂，使得所述N型轻掺杂区转化为N -型层。
  10. 如权利要求8所述的制造方法，其特征在于：在所述第三掺杂区域掺杂步骤中，所述第三掺杂区域为一P型掺杂区，其中对所述P型掺杂区进行P型掺杂，使得所述P型掺杂区转化为P型层，且所述P型层位于在所述N +型层上。
  11. 一种显示面板，其特征在于：所述显示面板包括：一玻璃基板；形成在所述玻璃基板上的一绝缘层；形成在所述绝缘层上的一多晶硅层；形成在所述多晶硅层上的一栅极绝缘层；形成在所述栅极绝缘层上的一栅极层；形成在所述栅极层上的一层间绝缘层；及形成在所述层间绝缘层的一源漏极接触层；
    其中所述多晶硅层定义有一第一掺杂区域、一第二掺杂区域及一第三掺杂区域，且所述源漏极接触层接触所述第一掺杂区域及所述第三掺杂区域，所述第一掺杂区域及所述第三掺杂区域具有不同的掺杂类型，使得所述第一掺杂区域及所述第三掺杂区域形成一PN结构，而所述第一掺杂区域及所述第二掺杂区域具有相同的掺杂类型。
  12. 如权利要求11所述的显示面板，其特征在于：所述第一掺杂区域为二N型重掺杂区，配置用以作为N +型层，所述第三掺杂区域为一P型掺杂区，配置用以作为P型层。
  13. 如权利要求12所述的显示面板，其特征在于：所述多晶硅层还定义有一非掺杂区，所述第二掺杂区域为二N型轻掺杂区，其中所述N型轻掺杂区分别位于所述非掺杂区的相对二侧。
  14. 如权利要求13所述的显示面板，其特征在于：所述N型重掺杂区及所述P型掺杂区所形成的PN结构定义为一非晶硅光电二极管，所述N型轻掺杂区、所述N型重掺杂区及所述栅极层定义为一薄膜晶体管。
  15. 如权利要求13所述的显示面板，其特征在于：所述非掺杂区与所述栅极层在所述玻璃基板的一投影重叠，所述P型掺杂区与所述N型重掺杂区在所述玻璃基板的一投影重叠。
  16. 如权利要求11所述的显示面板，其特征在于：所述显示面板还包含一遮光层，所述遮光层形成在所述玻璃基板上，而且所述绝缘层覆盖在所述遮光层上。
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