WO2020042329A1 - 驱动电路及驱动系统 - Google Patents

驱动电路及驱动系统 Download PDF

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Publication number
WO2020042329A1
WO2020042329A1 PCT/CN2018/113071 CN2018113071W WO2020042329A1 WO 2020042329 A1 WO2020042329 A1 WO 2020042329A1 CN 2018113071 W CN2018113071 W CN 2018113071W WO 2020042329 A1 WO2020042329 A1 WO 2020042329A1
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WIPO (PCT)
Prior art keywords
circuit
electrically connected
input terminal
switch
output terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2018/113071
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English (en)
French (fr)
Inventor
黄笑宇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HKC Co Ltd
Chongqing HKC Optoelectronics Technology Co Ltd
Original Assignee
HKC Co Ltd
Chongqing HKC Optoelectronics Technology Co Ltd
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Publication date
Application filed by HKC Co Ltd, Chongqing HKC Optoelectronics Technology Co Ltd filed Critical HKC Co Ltd
Priority to US17/043,440 priority Critical patent/US11238822B2/en
Publication of WO2020042329A1 publication Critical patent/WO2020042329A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/04—Display protection
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/08—Details of image data interface between the display device controller and the data line driver circuit

Definitions

  • the present application relates to the field of liquid crystal display technology, and more particularly, to a driving circuit and a driving system.
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • the main driving principle of TFT-LCD is: the system motherboard passes the R / G / B compression signal (three primary color signals), control signals and power through the connector on the wire and the PCB (Printed Circuit Board).
  • the data is processed by the TCON (Timing Controller) IC on the PCB (Printed Circuit Board), and then passed through the PCB through the S-COF (Source-Chip on Film) source film Drive chip) and G-COF (Gate-Chip On Film) are connected to the display area; the voltage is transmitted through the Dataline (data transmission line) and Scanline (scan line) on the Array to make the voltage LCD realizes display function.
  • the abnormality of the front-end voltage input may cause EOS (Electrical Over Stress), that is, the input voltage exceeds the withstand voltage value of the chip voltage inside the PCB, which may cause chip damage.
  • EOS Electro Mechanical Over Stress
  • the present application discloses a driving circuit and a driving system, so as to realize real-time protection of the internal chip of the printed circuit board from being damaged when the input voltage exceeds the withstand voltage of the internal chip voltage of the printed circuit board. damage.
  • a driving circuit includes:
  • a first circuit inputting a preset protection value through a first input terminal of the first circuit, and inputting a first voltage through a second input terminal of the first circuit;
  • a first switch circuit a first input terminal of the first switch circuit is electrically connected to an output terminal of the first circuit, and a second input terminal of the first switch circuit is electrically connected to an output terminal of a power source;
  • a trigger circuit wherein a first input terminal of the trigger circuit is electrically connected to an output terminal of the power supply, and a second input terminal of the trigger circuit is electrically connected to an output terminal of the first switch circuit;
  • a second switch circuit a first input terminal of the second switch circuit is electrically connected to the first voltage, a second input terminal of the second switch circuit is electrically connected to an output terminal of the trigger circuit, and the first The output end of the two switch circuits is electrically connected to the input end of the printed circuit board;
  • the first circuit is used to control the closing and opening of the first switch circuit.
  • the trigger circuit controls the second switch circuit to open.
  • the trigger circuit controls the second switch circuit to close.
  • a driving system includes a driving circuit, and the driving circuit includes:
  • a first circuit inputting a preset protection value through a first input terminal of the first circuit, and inputting a first voltage through a second input terminal of the first circuit;
  • a first switch circuit a first input terminal of the first switch circuit is electrically connected to an output terminal of the first circuit, and a second input terminal of the first switch circuit is electrically connected to an output terminal of a power source;
  • a trigger circuit wherein a first input terminal of the trigger circuit is electrically connected to an output terminal of the power supply, and a second input terminal of the trigger circuit is electrically connected to an output terminal of the first switch circuit;
  • a second switch circuit a first input terminal of the second switch circuit is electrically connected to the first voltage, a second input terminal of the second switch circuit is electrically connected to an output terminal of the trigger circuit, and the first The output end of the two switch circuits is electrically connected to the input end of the printed circuit board;
  • the first circuit is used to control the closing and opening of the first switch circuit.
  • the trigger circuit controls the second switch circuit to open.
  • the trigger circuit controls the second switch circuit to close.
  • the present application discloses a driving circuit including the first circuit, the first switch circuit, the trigger circuit, and the second switch circuit.
  • a preset protection value is input through a first input terminal of the first circuit.
  • a first voltage is input through a second input terminal of the first circuit.
  • a first input terminal of the first switching circuit is electrically connected to an output terminal of the first circuit.
  • a second input terminal of the first switch circuit is electrically connected to an output terminal of the power source.
  • a first input terminal of the trigger circuit is electrically connected to an output terminal of the power source.
  • a second input terminal of the trigger circuit is electrically connected to an output terminal of the first switch circuit.
  • a first input terminal of the second switching circuit is electrically connected to the first voltage.
  • a second input terminal of the second switch circuit is electrically connected to an output terminal of the trigger circuit.
  • An output terminal of the second switch circuit is electrically connected to an input terminal of the printed circuit board.
  • the first circuit is used to control closing and opening of the first switching circuit. When the first switch circuit is closed, the trigger circuit controls the second switch circuit to open. When the first switch circuit is opened, the trigger circuit controls the second switch circuit to close.
  • This application uses the cooperation of the first circuit, the first switch circuit, the trigger circuit, and the second switch circuit. That is, the closing of the first switch circuit is controlled by the first circuit, so that the trigger circuit controls the second switch circuit to be opened, and then the chip inside the printed circuit board can be protected from damage in real time. Greatly improved security. At the same time, the application also improves the reliability of the product.
  • FIG. 1 is a structural block diagram of a driving circuit disclosed in an embodiment of the present application
  • FIG. 2 is a schematic circuit diagram of a driving circuit disclosed in an embodiment of the present application.
  • FIG. 3 is a structural block diagram of another driving circuit disclosed in an embodiment of the present application.
  • FIG. 4 is a schematic circuit diagram of another driving circuit disclosed in an embodiment of the present application.
  • FIG. 5 is a structural block diagram of a driving system disclosed in an embodiment of the present application.
  • the embodiment of the present application discloses a driving circuit, a driving system, and a display, so as to realize real-time protection of the chip inside the printed circuit board when the input voltage exceeds the withstand voltage of the chip voltage inside the printed circuit board. Damaged.
  • a driving circuit 10 disclosed in an embodiment of the present application includes a first circuit 100, a first switch circuit 200, a trigger circuit 300, and a second switch circuit 400.
  • a preset protection value 110 is input through a first input terminal of the first circuit 100.
  • a first voltage 120 is input through a second input terminal of the first circuit 100.
  • a first input terminal of the first switching circuit 200 is electrically connected to an output terminal of the first circuit 100.
  • the second input terminal of the first switch circuit 200 is electrically connected to the output terminal of the power source 130.
  • a first input terminal of the trigger circuit 300 is electrically connected to an output terminal of the power source 130.
  • a second input terminal of the trigger circuit 300 is electrically connected to an output terminal of the first switch circuit 200.
  • a first input terminal of the second switching circuit 400 is electrically connected to the first voltage 120.
  • a second input terminal of the second switching circuit 400 is electrically connected to an output terminal of the trigger circuit 300.
  • An output terminal of the second switching circuit 400 is electrically connected to an input terminal of the printed circuit board 500.
  • the first circuit 100 is configured to control closing and opening of the first switching circuit 200. When the first switch circuit 200 is closed, the trigger circuit 300 controls the second switch circuit 400 to open. When the first switch circuit 200 is turned off, the trigger circuit 300 controls the second switch circuit 400 to be closed.
  • the preset protection value 110 can be set by the first circuit 100. It can be understood that the specific value of the preset protection value 110 is not limited, as long as the internal chip of the printed circuit board can be protected from being damaged. In one embodiment, the preset protection value 110 is 14V. In one embodiment, the preset protection value 110 is 15V.
  • the first voltage 120 is input through the first circuit 100. The first voltage 120 refers to an input voltage at an input terminal of the printed circuit board. Specifically, the first voltage 120 may be 12V. The output terminal of the power source 130 outputs a logic high level.
  • the specific structure of the first circuit 100 may not be specifically limited, as long as it is possible to control the closing and opening of the first switching circuit 200 based on the preset protection value 110 and the first voltage.
  • the first circuit 100 may include an operational amplifier and a first resistor electrically connected to the operational amplifier.
  • the preset protection value 110 and the first voltage 120 are input to the operational amplifier, and the operation of the first switching circuit 200 is controlled by the operational amplifier.
  • the first resistor is used to limit the current to protect the operational amplifier. That is, the above functions can be achieved through the operational amplifier and the first resistor.
  • the operational amplifier may also be replaced with a first comparator, which can easily implement the above functions.
  • the first switching circuit 200 receives a control signal of the first circuit 100. When the control signal is at a low level, the first switching circuit 200 is in an off state. When the control signal is at a high level, the first switch circuit 200 is in a closed state. At this time, the first switch circuit 200 sends a signal to the second input terminal of the trigger circuit 300 through an output terminal.
  • the specific structure of the first switch circuit 200 may not be specifically limited, as long as the function of switching according to the control signal output by the first circuit 100 can be guaranteed.
  • the first switching circuit 200 is a relay-controlled switch.
  • the first switching circuit 200 is a MOS transistor (field effect transistor) control switch.
  • the trigger circuit 300 controls the second switch circuit 400 to open and close based on the current state of the first switch circuit 200. Specifically, when the first switch circuit 200 is in a closed state, the trigger circuit 300 controls the second switch circuit 400 to open. When the first switch circuit 200 is turned off, the trigger circuit 300 controls the second switch circuit 400 to be closed.
  • the specific structure of the trigger circuit 300 may not be specifically limited, as long as the function of controlling the opening and closing of the second switch circuit 400 based on the current state of the first switch circuit 200 can be achieved.
  • the trigger circuit 300 may be composed of a D flip-flop and a second resistor electrically connected to the D flip-flop.
  • the Q output terminal of the D flip-flop When the pulse signal input terminal of the D flip-flop receives a rising edge control signal, the Q output terminal of the D flip-flop outputs a trigger signal that triggers the second switch circuit 400 to turn off. When the pulse signal input terminal of the D flip-flop receives a falling edge control signal, the Q output terminal of the D flip-flop outputs a trigger signal that triggers the closing of the second switch circuit 400. At the same time, the second flip-flop is protected by the second resistor.
  • the second switch circuit 400 receives a trigger signal from the trigger circuit 300. When the trigger signal is a rising edge control signal, the second switch circuit 400 is in an off state. When the trigger signal is a falling edge control signal, the second switch circuit 400 is in a closed state.
  • the specific structure of the second switch circuit 400 may not be specifically limited, as long as the function of switching according to the trigger signal output by the trigger circuit 300 can be guaranteed.
  • the second switching circuit 400 is a relay trigger switch.
  • the second switch circuit 400 is a MOS tube trigger switch.
  • the cooperation of the first circuit 100, the first switch circuit 200, the trigger circuit 300, and the second switch circuit 400 is cooperated. That is, the first circuit 100 controls the closing of the first switch circuit 200, so that the trigger circuit 300 controls the second switch circuit 400 to be opened, thereby protecting the inside of the printed circuit board 500 in real time.
  • the chip is not damaged, greatly improving security. It also improves product reliability.
  • the first circuit 100 includes a comparator 140.
  • the preset protection value 110 is input through a first input terminal of the comparator 140.
  • the first voltage 120 is input through a second input terminal of the comparator 140.
  • An output terminal of the comparator 140 is electrically connected to a first input terminal of the first switching circuit 200.
  • the comparator 140 outputs a high level
  • the first switching circuit 200 is closed.
  • the comparator 140 outputs a low level, the first switching circuit 200 is turned off.
  • the first circuit 100 includes, but is not limited to, the comparator 140.
  • the comparator 140 may be replaced with a first operational amplifier.
  • the preset protection value 110 and the first voltage 120 are input to the comparator 140, and when the preset protection value 110 is less than or equal to the value of the first voltage 120, the first A switch circuit 200 is in an off state.
  • the preset protection value 110 is greater than the value of the first voltage 120, the first switch circuit 200 is in a closed state.
  • the first circuit 100 further includes a first current limiting resistor 150.
  • One end of the first current limiting resistor 150 is electrically connected to an output terminal of the comparator 140.
  • the other end of the first current limiting resistor 150 is grounded. It can be understood that the specific structure of the first current-limiting resistor 150 may not be specifically limited, as long as the current-limiting function can be achieved.
  • the first current limiting resistor 150 is a sliding varistor with a variable resistance.
  • the first current limiting resistor 150 is a fixed resistance resistor.
  • the first circuit includes an operational amplifier 160.
  • the preset protection value 110 is input through a first input terminal of the operational amplifier 160.
  • the first voltage 120 is input through a second input terminal of the operational amplifier 160.
  • An output terminal of the operational amplifier 160 is electrically connected to a first input terminal of the first switching circuit 200. When the operational amplifier 160 outputs a high level, the first switching circuit 200 is closed; when the operational amplifier 160 outputs a low level, the first switching circuit 200 is turned off.
  • the preset protection value 110 and the first voltage 120 are input to the operational amplifier 160.
  • the operational amplifier 160 When the operational amplifier 160 outputs a low level, the first switching circuit 200 is in an off state. status. When the operational amplifier 160 outputs a high level, the first switching circuit 200 is in a closed state.
  • the first switching circuit 200 includes a first switching transistor 210.
  • a first input terminal of the first switch tube 210 is electrically connected to an output terminal of the first circuit 100.
  • a second input terminal of the first switching tube 210 is electrically connected to an output terminal of the power source 130.
  • An output terminal of the first switching tube 210 is electrically connected to a second input terminal of the trigger circuit 300.
  • the specific structure of the first switch tube 210 may not be specifically limited, as long as the function of switching according to the control signal output by the first circuit 100 can be guaranteed.
  • the first switch 210 is a relay-controlled switch.
  • the first switch 210 is a MOS control switch.
  • the first switch 210 includes a first field effect transistor 220.
  • the gate of the first field effect transistor 220 is electrically connected to the output terminal of the first circuit 100.
  • a drain of the first field effect transistor 220 is electrically connected to an output terminal of the power source 130; a source of the first field effect transistor 220 is electrically connected to a second input terminal of the trigger circuit 300.
  • a source of the first field-effect transistor 220 is electrically connected to an output terminal of the power source 130; a drain of the first field-effect transistor 220 is electrically connected to a second input terminal of the trigger circuit 300.
  • the drain of the first field effect transistor 220 when the drain of the first field effect transistor 220 is electrically connected to the output terminal of the power source 130, the source of the first field effect transistor 220 is connected to the second input terminal of the trigger circuit 300. Electrical connection. When the source of the first field effect transistor 220 is electrically connected to the output terminal of the power source 130, the drain of the first field effect transistor 220 is electrically connected to the second input terminal of the trigger circuit 300. That is, the drain and source of the first field effect transistor 220 can be selected according to actual needs, and the positional relationship between the two is not specifically limited.
  • the first field effect transistor 220 may be an N-channel trench MOS transistor.
  • the first field effect transistor 220 may also be a P-channel trench MOS transistor. The specific structure of the first field effect transistor 220 can be selected according to actual needs.
  • the trigger circuit 300 includes a trigger 310.
  • the D input terminal of the flip-flop 310 is electrically connected to the output terminal of the power source 130.
  • a pulse input terminal of the flip-flop 310 is electrically connected to an output terminal of the first switching circuit 200.
  • the Q output terminal of the flip-flop 310 is electrically connected to the second input terminal of the second switching circuit 400.
  • the flip-flop 310 may be a rising-edge D flip-flop. Specifically, when a rising edge control signal is received at a pulse signal input terminal of the D flip-flop, a Q output terminal of the D flip-flop outputs a trigger signal that triggers the second switch circuit 400 to turn off. When the pulse signal input terminal of the D flip-flop receives a falling edge control signal, the Q output terminal of the D flip-flop does not output a trigger signal (that is, the operating state of the second switch circuit 400 is not changed at this time).
  • the trigger circuit 300 further includes a second current limiting resistor 320.
  • One end of the second current limiting resistor 320 is electrically connected to the Q output terminal of the flip-flop 310 and the second input terminal of the second switching circuit 400, and the other end of the second current limiting resistor 320 is grounded.
  • the specific structure of the second current limiting resistor 320 may not be specifically limited, as long as it can ensure that the current limiting function can be achieved.
  • the second current limiting resistor 320 is a sliding rheostat with a variable resistance.
  • the second current limiting resistor 320 is a fixed resistance resistor.
  • the second switching circuit 400 includes a second switching transistor 410.
  • a second input terminal of the second switch tube 410 is electrically connected to an output terminal of the trigger circuit 300.
  • a first input terminal of the second switch tube 410 is electrically connected to the first voltage 120.
  • An output terminal of the second switch tube 410 is electrically connected to an input terminal of the printed circuit board 500.
  • the specific structure of the second switch tube 410 may not be specifically limited, as long as the function of switching according to the trigger signal output by the trigger circuit 300 can be guaranteed.
  • the second switch tube 410 is a relay-controlled switch.
  • the second switch 410 is a MOS control switch.
  • the second switching transistor 410 includes a second field effect transistor 420.
  • a gate of the second field effect transistor 420 is electrically connected to an output terminal of the trigger circuit 300.
  • a source of the second field effect transistor 420 is electrically connected to the first voltage 120; a drain of the second field effect transistor 420 is electrically connected to an input terminal of the printed circuit board 500.
  • the drain of the second field effect transistor 420 is electrically connected to the first voltage 120; the source of the second field effect transistor 420 is electrically connected to the input terminal of the printed circuit board 500.
  • the drain of the second field effect transistor 420 is electrically connected to the input terminal of the printed circuit board 500.
  • the source of the second field effect transistor 420 is electrically connected to the input terminal of the printed circuit board 500. That is, the drain and source of the second field effect transistor 420 can be selected according to actual needs, and the positional relationship between the two is not specifically limited.
  • the second field effect transistor 420 may be an N-channel trench MOS transistor.
  • the second field effect transistor 420 may also be a P-channel trench MOS transistor. The specific structure can be selected according to actual needs.
  • the second field effect transistor 420 is a P-channel trench MOS transistor, and the first field effect transistor 220 is an N-channel trench MOS transistor. In one embodiment, the second field-effect transistor 420 is an N-channel trench MOS transistor, and the first field-effect transistor 220 is a P-channel trench MOS transistor.
  • the driving circuit 10 further includes a third current limiting resistor 600.
  • One end of the third current limiting resistor 600 is electrically connected to an output terminal of the first switch circuit 200 and a second input terminal of the trigger circuit 300, respectively.
  • the other end of the third current limiting resistor 600 is grounded. It can be understood that the specific structure of the third current limiting resistor 600 may not be specifically limited, as long as the current limiting function can be achieved.
  • the third current limiting resistor 600 is a sliding rheostat with a variable resistance.
  • the third current limiting resistor 600 is a fixed resistance resistor.
  • a driving circuit 10 disclosed in an embodiment of the present application includes a comparator 140, a first switching tube 210, a trigger circuit 300, and a second switching tube 410.
  • a preset protection value 110 is input through a first input terminal of the comparator 140.
  • a first voltage 120 is input through a second input terminal of the comparator 140.
  • a first input terminal of the first switching tube 210 is electrically connected to an output terminal of the comparator 140.
  • the second input terminal of the first switching tube 210 is electrically connected to the output terminal of the power source 130.
  • a first input terminal of the trigger circuit 300 is electrically connected to an output terminal of the power source 130.
  • a second input terminal of the trigger circuit 300 is electrically connected to an output terminal of the first switch 210.
  • a first input terminal of the second switch tube 410 is electrically connected to the first voltage 120.
  • a second input terminal of the second switch tube 410 is electrically connected to an output terminal of the trigger circuit 300.
  • An output terminal of the second switch tube 410 is electrically connected to an input terminal of the printed circuit board 500.
  • the comparator 140 is used to control closing and opening of the first switching tube 210. When the first switch tube 210 is closed, the trigger circuit 300 controls the second switch tube 410 to open. When the first switching tube 210 is turned off, the trigger circuit 300 controls the second switching tube 410 to be closed.
  • the comparator 140 can set the preset protection value 110. It can be understood that the specific value of the preset protection value 110 is not limited, as long as the internal chip of the printed circuit board can be protected from being damaged. In one embodiment, the preset protection value 110 is 14V. In one embodiment, the preset protection value 110 is 15V.
  • the comparator 140 inputs the first voltage 120.
  • the first voltage 120 refers to an input voltage at an input terminal of the printed circuit board. Specifically, the first voltage 120 may be 12V.
  • the output terminal of the power source 130 outputs a logic high level.
  • the operational amplifier can be replaced with a second comparator, which can easily implement the above functions.
  • the first switch 210 receives a control signal from the comparator 140. When the control signal is at a low level, the first switching tube 210 is in an off state. When the control signal is at a high level, the first switching tube 210 is in a closed state. At this time, the first switching tube 210 sends a signal to the second input terminal of the trigger circuit 300 through an output terminal.
  • the specific structure of the first switching tube 210 may not be specifically limited, as long as the function of switching according to the control signal output from the comparator 140 can be guaranteed.
  • the first switch 210 is a relay-controlled switch. In one embodiment, the first switch 210 is a MOS control switch.
  • the trigger circuit 300 controls the second switch tube 410 to open and close based on the current state of the first switch tube 210. Specifically, when the first switching tube 210 is in a closed state, the trigger circuit 300 controls the second switching tube 410 to be turned off. When the first switching tube 210 is turned off, the trigger circuit 300 controls the second switching tube 410 to be closed.
  • the specific structure of the trigger circuit 300 may not be specifically limited, as long as the function of controlling the opening and closing of the second switching tube 410 based on the current state of the first switching tube 210 can be achieved.
  • the trigger circuit 300 may be composed of a D flip-flop and a second resistor electrically connected to the D flip-flop.
  • the Q output terminal of the D flip-flop When the pulse signal input terminal of the D flip-flop receives a rising edge control signal, the Q output terminal of the D flip-flop outputs a trigger signal that triggers the second switch 410 to turn off. When the pulse signal input terminal of the D flip-flop receives a falling edge control signal, the Q output terminal of the D flip-flop outputs a trigger signal that triggers the closing of the second switch 410. At the same time, the second flip-flop is protected by the second resistor.
  • the second switch 410 receives a trigger signal from the trigger circuit 300.
  • the trigger signal is a rising edge control signal
  • the second switch tube 410 is in an off state.
  • the trigger signal is a falling edge control signal
  • the second switch tube 410 is in a closed state.
  • the specific structure of the second switch tube 410 may not be specifically limited, as long as the function of switching according to the trigger signal output by the trigger circuit 300 can be guaranteed.
  • the second switch tube 410 is a relay trigger switch.
  • the second switch 410 is a MOS trigger switch.
  • the comparator 140 is used to control the closing of the first switching tube 210, so that the trigger circuit 300 controls the second switching tube 410 to open, thereby protecting the chip inside the printed circuit board 500 in real time. It is not damaged and greatly improves safety. It also improves product reliability.
  • the trigger circuit 300 includes a trigger 310 and a second current limiting resistor 320.
  • the D input terminal of the flip-flop 310 is electrically connected to the output terminal of the power source 130.
  • the pulse input terminal of the flip-flop 310 is electrically connected to the output terminal of the first switching tube 210.
  • the Q output terminal of the flip-flop 310 is electrically connected to the second input terminal of the second switch tube 410.
  • One end of the second current limiting resistor 320 is electrically connected to the Q output terminal of the flip-flop 310 and the second input terminal of the second switch tube 410, respectively.
  • the other end of the second current limiting resistor 320 is grounded.
  • the flip-flop 310 may use a rising edge D flip-flop. Specifically, when a rising edge control signal is received at a pulse signal input terminal of the D flip-flop, a Q output terminal of the D flip-flop outputs a trigger signal that triggers the second switch 410 to turn off. When the pulse signal input terminal of the D flip-flop receives a falling edge control signal, the Q output terminal of the D flip-flop does not output a trigger signal (that is, the operating state of the second switch 410 is not changed at this time).
  • the specific structure of the second current limiting resistor 320 may not be specifically limited, as long as it can ensure that the current limiting function can be achieved.
  • the second current limiting resistor 320 is a sliding rheostat with a variable resistance.
  • the second current limiting resistor 320 is a fixed resistance resistor.
  • the second switching circuit 400 is a P-channel trench MOS transistor.
  • the first switching circuit 200 is an N-channel trench MOS transistor.
  • the gate control signal of the N-channel trench MOS tube is at a high level, the N-channel trench MOS tube is turned on.
  • the gate control signal of the N-channel trench MOS tube is at a low level, the N-channel trench MOS tube is turned off.
  • the trigger circuit 300 is composed of a rising edge D flip-flop and a second resistor. When a rising edge signal is received at the pulse signal input terminal of the rising edge D flip-flop, the logic level of the D input terminal of the rising edge D flip-flop is assigned to the Q output terminal.
  • the first circuit 100 is composed of a first comparator and a third resistor.
  • the first comparator When the voltage of the positive input terminal (that is, the first voltage 120) of the first comparator is less than or equal to the negative input terminal (that is, the preset protection value 110), the first comparator outputs a logic low voltage. level.
  • the first comparator When the voltage of the positive input terminal (ie, the first voltage 120) of the first comparator is greater than the negative input terminal (ie, the preset protection value 110), the first comparator outputs a logic high level.
  • the positive input terminal of the first comparator is a constant DC voltage (usually 12V).
  • the first comparator outputs a logic low level.
  • the N-channel trench MOS tube is disconnected. Because of the ground effect of the third current limiting resistor 600, the pulse input terminal of the rising edge D flip-flop is at a low level at this time.
  • the trigger signal received by the gate of the P-channel trench MOS tube is closed. At this time, the P-channel trench MOS tube is turned on, that is, it works normally.
  • the first comparator When the positive input terminal of the first comparator is abnormal and the voltage of the positive input terminal exceeds the voltage of the negative input terminal, the first comparator outputs a logic high level at this time.
  • the N-channel trench MOS tube is turned on. At this time, the pulse input terminal of the rising edge D flip-flop changes from low level to high level (that is, a rising edge), that is, the rising edge D flip-flop outputs a disconnection trigger signal to the P channel trench MOS transistor. Grid.
  • the P channel trench MOS tube is closed. At this time, the input terminal of the printed circuit board 500 is disconnected from the first voltage 120, thereby avoiding the problem that the internal chip of the printed circuit board 500 is burnt due to the abnormal input terminal.
  • the present application cooperates with the first circuit 100, the first switch circuit 200, the trigger circuit 300, and the second switch circuit 400. That is, the first circuit 100 controls the closing of the first switch circuit 200, so that the trigger circuit 300 controls the second switch circuit 400 to be opened, thereby protecting the inside of the printed circuit board 500 in real time.
  • the chip is not damaged, greatly improving security. It also improves product reliability.
  • an embodiment of the present application provides a driving system 20 including the driving circuit 10 according to any one of the foregoing embodiments.

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Abstract

一种驱动电路（10）和包括该驱动电路（10）的驱动系统（20），该驱动电路（10）通过第一电路（100）输入预设保护值（110）和第一电压（120），第一开关电路（200）与第一电路（100）和触发电路（300）电连接，第二开关电路（400）与第一电压（120）、触发电路（300）和印制电路板（500）电连接。该驱动电路（10）能够在第一电压（100）过压时，保护印制电路板（500）内部芯片不受损坏。

Description

驱动电路及驱动系统
相关申请
本申请要求2018年08月31日申请的，申请号为201811014947.2，名称为“驱动电路、驱动系统及显示器”的中国专利申请的优先权，在此将其全文引入作为参考。
技术领域
本申请涉及液晶显示技术领域，更具体的说，涉及一种驱动电路及驱动系统。
背景技术
TFT-LCD(Thin Film Transistor Liquid Crystal Display，薄膜晶体管液晶显示器)是当前平板显示的主要品种之一，已经成为了现代IT、视讯产品中重要的显示平台。
TFT-LCD主要驱动原理为：系统主板将R/G/B压缩信号(三基色信号)、控制信号及电源通过线材与PCB板(Printed Circuit Board，印制电路板)上的Connector(连接器)相连接；数据经过PCB板(Printed Circuit Board，印制电路板)上的TCON(Timing Controller，时序控制器)IC处理后，经PCB板，通过S-COF(Source-Chip on Film，源极薄膜驱动芯片)和G-COF(Gate-Chip on Film，栅极薄膜驱动芯片)与显示区连接；通过Array(阵列)上的Dataline(数据传输线)和Scanline(扫描线)对电压进行传输，从而使LCD实现显示功能。
因为前端电压输入的异常，可能会造成EOS(Electrical Over Stress，电气过应力)，即输入电压超过PCB板内部芯片电压的耐压值，从而造成芯片损坏的情况。
申请内容
有鉴于此，本申请公开一种驱动电路及驱动系统，以实现在输入电压超过印制电路板内部芯片电压的耐压值的情况下，能够实时的保护所述印制电路板内部芯片不受损坏。
一种驱动电路，包括：
第一电路，通过所述第一电路的第一输入端输入预设保护值，通过所述第一电路的第二输入端输入第一电压；
第一开关电路，所述第一开关电路的第一输入端与所述第一电路的输出端电连接，所述第一开关电路的第二输入端与电源的输出端电连接；
触发电路，所述触发电路的第一输入端与所述电源的输出端电连接，所述触发电路的第二输入端与所述第一开关电路的输出端电连接；
第二开关电路，所述第二开关电路的第一输入端与所述第一电压电连接，所述第二开关电路的第二输入端与所述触发电路的输出端电连接，所述第二开关电路的输出端与印制电路板的输入端电连接；
所述第一电路用于控制所述第一开关电路的闭合与断开，当所述第一开关电路闭合时，所述触发电路控制所述第二开关电路断开，当所述第一开关电路断开时，所述触发电路控制所述第二开关电路闭合。
一种驱动系统，包括驱动电路，所述驱动电路包括：
第一电路，通过所述第一电路的第一输入端输入预设保护值，通过所述第一电路的第二输入端输入第一电压；
第一开关电路，所述第一开关电路的第一输入端与所述第一电路的输出端电连接，所述第一开关电路的第二输入端与电源的输出端电连接；
触发电路，所述触发电路的第一输入端与所述电源的输出端电连接，所述触发电路的第二输入端与所述第一开关电路的输出端电连接；
第二开关电路，所述第二开关电路的第一输入端与所述第一电压电连接，所述第二开关电路的第二输入端与所述触发电路的输出端电连接，所述第二开关电路的输出端与印制电路板的输入端电连接；
所述第一电路用于控制所述第一开关电路的闭合与断开，当所述第一开关电路闭合时，所述触发电路控制所述第二开关电路断开，当所述第一开关电路断开时，所述触发电路控制所述第二开关电路闭合。
从上述的技术方案可知，本申请公开了一种驱动电路，包括所述第一电路、所述第一开关电路、所述触发电路以及所述第二开关电路。通过所述第一电路的第一输入端输入预设保护值。通过所述第一电路的第二输入端输入第一电压。所述第一开关电路的第一输入端与所述第一电路的输出端电连接。所述第一开关电路的第二输入端与电源的输出端电连接。所述触发电路的第一输入端与所述电源的输出端电连接。所述触发电路的第二输入端与所述第一开关电路的输出端电连接。所述第二开关电路的第一输入端与所述第一电压电连接。所述第二开关电路的第二输入端与所述触发电路的输出端电连接。所述第二开关电路的输出端与印制电路板的输入端电连接。所述第一电路用于控制所述第一开关电路的闭合与断开。当所述第一开关电路闭合时，所述触发电路控制所述第二开关电路断开。当所述第一开关电路断开时，所述触发电路控制所述第二开关电路闭合。
本申请通过所述第一电路、所述第一开关电路、所述触发电路以及所述第二开关电路的配合。即通过所述第一电路控制所述第一开关电路的闭合，从而使得所述触发电路控制所述第二开关电路断开，进而能够实时的保护所述印制电路板内部芯片不受损坏，大大提高了安全性。同时本申请还提高了产品的可靠性。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据公开的附图获得其他的附图。
图1为本申请实施例公开的一种驱动电路的结构框图；
图2为本申请实施例公开的一种驱动电路的电路示意图；
图3为本申请实施例公开的另一种驱动电路的结构框图；
图4为本申请实施例公开的另一种驱动电路的电路示意图；
图5为本申请实施例公开的一种驱动系统的结构框图。
附图标记
10  驱动电路
100 第一电路
110 预设保护值
120 第一电压
130 电源
140 比较器
150 第一限流电阻
160 运算放大器
20  驱动系统
200 第一开关电路
210 第一开关管
220 第一场效应晶体管
300 触发电路
310 触发器
320 第二限流电阻
400 第二开关电路
410 第二开关管
420 第二场效应晶体管
500 印制电路板
600 第三限流电阻
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请实施例公开了一种驱动电路、驱动系统及显示器，以实现在输入电压超过印制电路板内部芯片电压的耐压值的情况下，能够实时的保护所述印制电路板内部芯片不受损坏。
请参见图1，本申请一实施例公开的一种驱动电路10，包括第一电路100、第一开关电路200、触发电路300以及第二开关电路400。通过所述第一电路100的第一输入端输入预设保护值110。通过所述第一电路100的第二输入端输入第一电压120。所述第一开关电路200的第一输入端与所述第一电路100的输出端电连接。所述第一开关电路200的第二输入端与电源130的输出端电连接。所述触发电路300的第一输入端与所述电源130的输出端电连接。所述触发电路300的第二输入端与所述第一开关电路200的输出端电连接。
所述第二开关电路400的第一输入端与所述第一电压120电连接。所述第二开关电路400的第二输入端与所述触发电路300的输出端电连接。所述第二开关电路400的输出端与印制电路板500的输入端电连接。所述第一电路100 用于控制所述第一开关电路200的闭合与断开。当所述第一开关电路200闭合时，所述触发电路300控制所述第二开关电路400断开。当所述第一开关电路200断开时，所述触发电路300控制所述第二开关电路400闭合。
通过所述第一电路100可设定所述预设保护值110。可以理解，所述预设保护值110的具体数值不做限定，只要保证能够保护所述印制电路板内部芯片不受损坏即可。在一个实施例中，所述预设保护值110为14V。在一个实施例中，所述预设保护值110为15V。通过所述第一电路100输入所述第一电压120。所述第一电压120是指所述印制电路板输入端的输入电压。具体的，所述第一电压120可为12V。所述电源130的输出端输出的为逻辑高电平。
可以理解，所述第一电路100的具体结构可以不做具体的限定，只要能够实现基于所述预设保护值110和所述第一电压控制所述第一开关电路200的闭合与断开的功能即可。在一个实施例中，所述第一电路100可由运算放大器和与所述运算放大器电连接的第一电阻组成。将所述预设保护值110和所述第一电压120输入至上述所述运算放大器，并通过所述运算放大器控制所述第一开关电路200的闭合与断开。同时通过所述第一电阻进行限流保护所述运算放大器。即通过所述运算放大器和所述第一电阻即能实现上述功能。在一个实施例中，也可将所述运算放大器替换为第一比较器，易能实现上述功能。
所述第一开关电路200接收所述第一电路100的控制信号。当所述控制信号为低电平时，所述第一开关电路200处于断开状态。当所述控制信号为高电平时，所述第一开关电路200处于闭合状态。此时所述第一开关电路200通过输出端将信号发送至所述触发电路300的第二输入端。所述第一开关电路200的具体结构可以不做具体的限定，只要能够保证依据所述第一电路100输出的控制信号进行切换的功能即可。在一个实施例中，所述第一开关电路200为继电器控制开关。在一个实施例中，所述第一开关电路200为MOS管(场效应晶 体管)控制开关。
所述触发电路300基于所述第一开关电路200的当前状态控制所述第二开关电路400断开与闭合。具体的，当所述第一开关电路200处于闭合状态时，所述触发电路300控制所述第二开关电路400断开。当所述第一开关电路200断开时，所述触发电路300控制所述第二开关电路400闭合。所述触发电路300的具体结构可以不做具体的限定，只要能够实现基于所述第一开关电路200的当前状态控制所述第二开关电路400断开与闭合的功能即可。在一个实施例中，所述触发电路300可由D触发器和与所述D触发器电连接的第二电阻构成。
当所述D触发器的脉冲信号输入端接收到上升沿控制信号时，所述D触发器的Q输出端输出触发所述第二开关电路400断开的触发信号。当所述D触发器的脉冲信号输入端接收到下降沿控制信号时，所述D触发器的Q输出端输出触发所述第二开关电路400闭合的触发信号。同时通过所述第二电阻进行限流保护所述D触发器。
所述第二开关电路400接收所述触发电路300的触发信号。当所述触发信号为上升沿控制信号时，所述第二开关电路400处于断开状态。当所述触发信号为下降沿控制信号时，所述第二开关电路400处于闭合状态。所述第二开关电路400的具体结构可以不做具体的限定，只要能够保证依据所述触发电路300输出的触发信号进行切换的功能即可。在一个实施例中，所述第二开关电路400为继电器触发开关。在一个实施例中，所述第二开关电路400为MOS管触发开关。
本实施例中，通过所述第一电路100、所述第一开关电路200、所述触发电路300以及所述第二开关电路400的配合。即通过所述第一电路100控制所述第一开关电路200的闭合，从而使得所述触发电路300控制所述第二开关电路400断开，进而能够实时的保护所述印制电路板500内部芯片不受损坏，大大提 高了安全性。同时还提高了产品的可靠性。
请参见图2，在一个实施例中，所述第一电路100包括比较器140。通过所述比较器140的第一输入端输入所述预设保护值110。通过所述比较器140的第二输入端输入所述第一电压120。所述比较器140的输出端与所述第一开关电路200的第一输入端电连接。当所述比较器140输出高电平时，所述第一开关电路200闭合。当所述比较器140输出低电平时，所述第一开关电路200断开。
可以理解，所述第一电路100包括但不限于所述比较器140。在一个实施例中，所述比较器140可替换为第一运算放大器。具体的，将所述预设保护值110和所述第一电压120输入至所述比较器140，当所述预设保护值110小于或等于所述第一电压120的数值时，所述第一开关电路200处于断开状态。当所述预设保护值110大于所述第一电压120的数值时，所述第一开关电路200处于闭合状态。
在一个实施例中，所述第一电路100还包括第一限流电阻150。所述第一限流电阻150的一端与所述比较器140的输出端电连接。所述第一限流电阻150的另一端接地。可以理解，所述第一限流电阻150的具体结构可以不做具体的限定，只要保证能实现限流的功能即可。在一个实施例中，所述第一限流电阻150为阻值可变的滑动变阻器。在一个实施例中，所述第一限流电阻150为固定阻值电阻。
在一个实施例中，所述第一电路包括运算放大器160。通过所述运算放大器160的第一输入端输入所述预设保护值110。通过所述运算放大器160的第二输入端输入所述第一电压120。所述运算放大器160的输出端与所述第一开关电路200的第一输入端电连接。当所述运算放大器160输出高电平时，所述第一开关电路200闭合；当所述运算放大器160输出低电平时，所述第一开关电路200断开。
在一个实施例中，将所述预设保护值110和所述第一电压120输入至所述运算放大器160，当所述运算放大器160输出低电平时，所述第一开关电路200处于断开状态。当所述运算放大器160输出高电平时，所述第一开关电路200处于闭合状态。
在一个实施例中，所述第一开关电路200包括第一开关管210。所述第一开关管210的第一输入端与所述第一电路100的输出端电连接。所述第一开关管210的第二输入端与所述电源130的输出端电连接。所述第一开关管210的输出端与所述触发电路300的第二输入端电连接。
可以理解，所述第一开关管210的具体结构可以不做具体的限定，只要能够保证依据所述第一电路100输出的控制信号进行切换的功能即可。在一个实施例中，所述第一开关管210为继电器控制开关。在一个实施例中，所述第一开关管210为MOS管控制开关。
在一个实施例中，所述第一开关管210包括第一场效应晶体管220。所述第一场效应晶体管220的栅极与所述第一电路100的输出端电连接。所述第一场效应晶体管220的漏极与所述电源130的输出端电连接；所述第一场效应晶体管220的源极与所述触发电路300的第二输入端电连接。或者，所述第一场效应晶体管220的源极与所述电源130的输出端电连接；所述第一场效应晶体管220的漏极与所述触发电路300的第二输入端电连接。
可以理解，当所述第一场效应晶体管220的漏极与所述电源130的输出端电连接时，则所述第一场效应晶体管220的源极与所述触发电路300的第二输入端电连接。当所述第一场效应晶体管220的源极与所述电源130的输出端电连接时，则所述第一场效应晶体管220的漏极与所述触发电路300的第二输入端电连接。即所述第一场效应晶体管220的漏极与源极是可以根据实际需求进行选择的，二者的位置关系不做具体的限定。所述第一场效应晶体管220可采 用N道沟MOS管。所述第一场效应晶体管220也可采用P道沟MOS管。所述第一场效应晶体管220具体的结构，可根据实际需求进行选择。
在一个实施例中，所述触发电路300包括触发器310。所述触发器310的D输入端与所述电源130的输出端电连接。所述触发器310的脉冲输入端与所述第一开关电路200的输出端电连接。所述触发器310的Q输出端与所述第二开关电路400的第二输入端电连接。所述触发器310可采用上升沿D触发器。具体的，当所述D触发器的脉冲信号输入端接收到上升沿控制信号时，所述D触发器的Q输出端输出触发所述第二开关电路400断开的触发信号。当所述D触发器的脉冲信号输入端接收到下降沿控制信号时，所述D触发器的Q输出端不输出触发信号(即不改变此时所述第二开关电路400的运行状态)。
在一个实施例中，所述触发电路300还包括第二限流电阻320。所述第二限流电阻320的一端与所述触发器310的Q输出端和所述第二开关电路400的第二输入端分别电连接，所述第二限流电阻320的另一端接地。可以理解，所述第二限流电阻320的具体结构可以不做具体的限定，只要保证能实现限流的功能即可。在一个实施例中，所述第二限流电阻320为阻值可变的滑动变阻器。在一个实施例中，所述第二限流电阻320为固定阻值电阻。
在一个实施例中，所述第二开关电路400包括第二开关管410。所述第二开关管410的第二输入端与所述触发电路300的输出端电连接。所述第二开关管410的第一输入端与所述第一电压120电连接。所述第二开关管410的输出端与所述印制电路板500的输入端电连接。
可以理解，所述第二开关管410的具体结构可以不做具体的限定，只要能够保证依据所述触发电路300输出的触发信号进行切换的功能即可。在一个实施例中，所述第二开关管410为继电器控制开关。在一个实施例中，所述第二开关管410为MOS管控制开关。
在一个实施例中，所述第二开关管410包括第二场效应晶体管420。所述第二场效应晶体管420的栅极与所述触发电路300的输出端电连接。所述第二场效应晶体管420的源极与所述第一电压120电连接；所述第二场效应晶体管420的漏极与所述印制电路板500的输入端电连接。或者，所述第二场效应晶体管420的漏极与所述第一电压120电连接；所述第二场效应晶体管420的源极与所述印制电路板500的输入端电连接。
可以理解，当所述第二场效应晶体管420的源极与所述第一电压120电连接，则所述第二场效应晶体管420的漏极与所述印制电路板500的输入端电连接。当所述第二场效应晶体管420的漏极与所述第一电压120电连接，则所述第二场效应晶体管420的源极与所述印制电路板500的输入端电连接。即所述第二场效应晶体管420的漏极与源极是可以根据实际需求进行选择的，二者的位置关系不做具体的限定。所述第二场效应晶体管420可采用N道沟MOS管。所述第二场效应晶体管420也可采用P道沟MOS管。具体的结构，可根据实际需求进行选择。在一个实施例中，所述第二场效应晶体管420采用P道沟MOS管，所述第一场效应晶体管220采用N道沟MOS管。在一个实施例中，所述第二场效应晶体管420采用N道沟MOS管，所述第一场效应晶体管220采用P道沟MOS管。
在一个实施例中，所述驱动电路10还包括第三限流电阻600。所述第三限流电阻600的一端分别与所述第一开关电路200的输出端和所述触发电路300的第二输入端电连接。所述第三限流电阻600的另一端接地。可以理解，所述第三限流电阻600的具体结构可以不做具体的限定，只要保证能实现限流的功能即可。在一个实施例中，所述第三限流电阻600为阻值可变的滑动变阻器。在一个实施例中，所述第三限流电阻600为固定阻值电阻。
请参见图3，本申请一实施例公开的一种驱动电路10，包括比较器140、第 一开关管210、触发电路300以及第二开关管410。通过所述比较器140的第一输入端输入预设保护值110。通过所述比较器140的第二输入端输入第一电压120。所述第一开关管210的第一输入端与所述比较器140的输出端电连接。所述第一开关管210的第二输入端与电源130的输出端电连接。所述触发电路300的第一输入端与所述电源130的输出端电连接。所述触发电路300的第二输入端与所述第一开关管210的输出端电连接。
所述第二开关管410的第一输入端与所述第一电压120电连接。所述第二开关管410的第二输入端与所述触发电路300的输出端电连接。所述第二开关管410的输出端与印制电路板500的输入端电连接。所述比较器140用于控制所述第一开关管210的闭合与断开。当所述第一开关管210闭合时，所述触发电路300控制所述第二开关管410断开。当所述第一开关管210断开时，所述触发电路300控制所述第二开关管410闭合。
通过所述比较器140可设定所述预设保护值110。可以理解，所述预设保护值110的具体数值不做限定，只要保证能够保护所述印制电路板内部芯片不受损坏即可。在一个实施例中，所述预设保护值110为14V。在一个实施例中，所述预设保护值110为15V。通过所述比较器140输入所述第一电压120。所述第一电压120是指所述印制电路板输入端的输入电压。具体的，所述第一电压120可为12V。所述电源130的输出端输出的为逻辑高电平。在一个实施例中，所述运算放大器可替换为第二比较器，易能实现上述功能。
所述第一开关管210接收所述比较器140的控制信号。当所述控制信号为低电平时，所述第一开关管210处于断开状态。当所述控制信号为高电平时，所述第一开关管210处于闭合状态。此时所述第一开关管210通过输出端将信号发送至所述触发电路300的第二输入端。所述第一开关管210的具体结构可以不做具体的限定，只要能够保证依据所述比较器140输出的控制信号进行切 换的功能即可。在一个实施例中，所述第一开关管210为继电器控制开关。在一个实施例中，所述第一开关管210为MOS管控制开关。
所述触发电路300基于所述第一开关管210的当前状态控制所述第二开关管410断开与闭合。具体的，当所述第一开关管210处于闭合状态时，所述触发电路300控制所述第二开关管410断开。当所述第一开关管210断开时，所述触发电路300控制所述第二开关管410闭合。所述触发电路300的具体结构可以不做具体的限定，只要能够实现基于所述第一开关管210的当前状态控制所述第二开关管410断开与闭合的功能即可。在一个实施例中，所述触发电路300可由D触发器和与所述D触发器电连接的第二电阻构成。
当所述D触发器的脉冲信号输入端接收到上升沿控制信号时，所述D触发器的Q输出端输出触发所述第二开关管410断开的触发信号。当所述D触发器的脉冲信号输入端接收到下降沿控制信号时，所述D触发器的Q输出端输出触发所述第二开关管410闭合的触发信号。同时通过所述第二电阻进行限流保护所述D触发器。
所述第二开关管410接收所述触发电路300的触发信号。当所述触发信号为上升沿控制信号时，所述第二开关管410处于断开状态。当所述触发信号为下降沿控制信号时，所述第二开关管410处于闭合状态。所述第二开关管410的具体结构可以不做具体的限定，只要能够保证依据所述触发电路300输出的触发信号进行切换的功能即可。在一个实施例中，所述第二开关管410为继电器触发开关。在一个实施例中，所述第二开关管410为MOS管触发开关。
本实施例中，通过所述比较器140、所述第一开关管210、所述触发电路300以及所述第二开关管410的配合。即通过所述比较器140控制所述第一开关管210的闭合，从而使得所述触发电路300控制所述第二开关管410断开，进而能够实时的保护所述印制电路板500内部芯片不受损坏，大大提高了安全性。同 时还提高了产品的可靠性。
请参见图4，在一个实施例中，所述触发电路300包括触发器310和第二限流电阻320。所述触发器310的D输入端与所述电源130的输出端电连接。所述触发器310的脉冲输入端与所述第一开关管210的输出端电连接。所述触发器310的Q输出端与所述第二开关管410的第二输入端电连接。所述第二限流电阻320的一端与所述触发器310的Q输出端和所述第二开关管410的第二输入端分别电连接。所述第二限流电阻320的另一端接地。
在一个实施例中，所述触发器310可采用上升沿D触发器。具体的，当所述D触发器的脉冲信号输入端接收到上升沿控制信号时，所述D触发器的Q输出端输出触发所述第二开关管410断开的触发信号。当所述D触发器的脉冲信号输入端接收到下降沿控制信号时，所述D触发器的Q输出端不输出触发信号(即不改变此时所述第二开关管410的运行状态)。
可以理解，所述第二限流电阻320的具体结构可以不做具体的限定，只要保证能实现限流的功能即可。在一个实施例中，所述第二限流电阻320为阻值可变的滑动变阻器。在一个实施例中，所述第二限流电阻320为固定阻值电阻。
本申请的工作过程如下：
所述第二开关电路400采用P道沟MOS管。当所述P道沟MOS管的栅极接收的控制讯号为低电平时，所述P道沟MOS管开启。当所述P道沟MOS管的栅极接收的控制讯号为高电平时，所述P道沟MOS管断开。所述第一开关电路200采用N道沟MOS管。当所述N道沟MOS管的栅极控制讯号为高电平时，所述N道沟MOS管开启。当所述N道沟MOS管的栅极控制讯号为低电平时，所述N道沟MOS管断开。所述触发电路300采用上升沿D触发器和第二电阻组成。当所述上升沿D触发器的脉冲信号输入端接收到上升沿信号时，将所述上升沿D触发器的D输入端的逻辑准位赋值给Q输出端。
所述第一电路100采用第一比较器和第三电阻组成。当所述第一比较器的正输入端(即所述第一电压120)的电压小于或等于负输入端(即所述预设保护值110)时，所述第一比较器输出逻辑低电平。当所述第一比较器的正输入端(即所述第一电压120)的电压大于负输入端(即所述预设保护值110)时，所述第一比较器输出逻辑高电平。
在正常工作时，所述第一比较器的正输入端为恒定的直流电压(通常为12V)。所述述第一比较器的正输入端的电压小于或等于负输入端电压时，所述第一比较器输出逻辑低电平。所述N道沟MOS管断开。因为所述第三限流电阻600的接地作用，此时所述上升沿D触发器的脉冲输入端为低电平。所述P道沟MOS管的栅极接收的触发信号为闭合，此时所述P道沟MOS管开启，即正常工作。
当所述第一比较器的正输入端异常导致正输入端电压超过所述负输入端电压时，此时所述第一比较器输出逻辑高电平。所述N道沟MOS管开启。此时所述上升沿D触发器的脉冲输入端由低电平变为高电平(即上升沿)，即所述上升沿D触发器输出断开触发信号至所述P道沟MOS管的栅极。所述P道沟MOS管关闭。此时所述印制电路板500的输入端与所述第一电压120断开，避免了因为输入端异常导致的所述印制电路板500内部芯片烧毁的问题。
综上所述，本申请通过所述第一电路100、所述第一开关电路200、所述触发电路300以及所述第二开关电路400的配合。即通过所述第一电路100控制所述第一开关电路200的闭合，从而使得所述触发电路300控制所述第二开关电路400断开，进而能够实时的保护所述印制电路板500内部芯片不受损坏，大大提高了安全性。同时还提高了产品的可靠性。
请参见图5，本申请一实施例提供一种驱动系统20，包括上述任一项实施例所述的驱动电路10。
最后，还需要说明的是，在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语″包括″、″包含″或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句″包括一个......″限定的要素，并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。
本说明书中各个实施例采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分互相参见即可。
对所公开的实施例的上述说明，使本领域专业技术人员能够实现或使用本申请。对这些实施例的多种修改对本领域的专业技术人员来说将是显而易见的，本文中所定义的一般原理可以在不脱离本申请的精神或范围的情况下，在其它实施例中实现。因此，本申请将不会被限制于本文所示的这些实施例，而是要符合与本文所公开的原理和新颖特点相一致的最宽的范围。

Claims (20)

  1. 一种驱动电路，其中，包括：
    第一电路，通过所述第一电路的第一输入端输入预设保护值，通过所述第一电路的第二输入端输入第一电压；
    第一开关电路，所述第一开关电路的第一输入端与所述第一电路的输出端电连接，所述第一开关电路的第二输入端与电源的输出端电连接；
    触发电路，所述触发电路的第一输入端与所述电源的输出端电连接，所述触发电路的第二输入端与所述第一开关电路的输出端电连接；
    第二开关电路，所述第二开关电路的第一输入端与所述第一电压电连接，所述第二开关电路的第二输入端与所述触发电路的输出端电连接，所述第二开关电路的输出端与印制电路板的输入端电连接；
    所述第一电路用于控制所述第一开关电路的闭合与断开，当所述第一开关电路闭合时，所述触发电路控制所述第二开关电路断开，当所述第一开关电路断开时，所述触发电路控制所述第二开关电路闭合。
  2. 根据权利要求1所述的驱动电路，其中，所述第一电路包括：
    比较器，通过所述比较器的第一输入端输入所述预设保护值，通过所述比较器的第二输入端输入所述第一电压，所述比较器的输出端与所述第一开关电路的第一输入端电连接；
    当所述比较器输出高电平时，所述第一开关电路闭合，当所述比较器输出低电平时，所述第一开关电路断开。
  3. 根据权利要求2所述的驱动电路，其中，所述第一电路还包括：
    第一限流电阻，所述第一限流电阻的一端与所述比较器的输出端电连接，所述第一限流电阻的另一端接地。
  4. 根据权利要求1所述的驱动电路，其中，所述第一电路包括：
    运算放大器，通过所述运算放大器的第一输入端输入所述预设保护值，通过所述运算放大器的第二输入端输入所述第一电压，所述运算放大器的输出端与所述第一开关电路的第一输入端电连接；
    当所述运算放大器输出高电平时，所述第一开关电路闭合，当所述运算放大器输出低电平时，所述第一开关电路断开。
  5. 根据权利要求1所述的驱动电路，其中，所述第一开关电路包括：
    第一开关管，所述第一开关管的第一输入端与所述第一电路的输出端电连接，所述第一开关管的第二输入端与所述电源的输出端电连接，所述第一开关管的输出端与所述触发电路的第二输入端电连接。
  6. 根据权利要求5所述的驱动电路，其中，所述第一开关管包括：
    第一场效应晶体管，所述第一场效应晶体管的栅极与所述第一电路的输出端电连接，所述第一场效应晶体管的漏极与所述电源的输出端电连接，所述第一场效应晶体管的源极与所述触发电路的第二输入端电连接。
  7. 根据权利要求5所述的驱动电路，其中，所述第一开关管包括：
    第一场效应晶体管，所述第一场效应晶体管的栅极与所述第一电路的输出端电连接，所述第一场效应晶体管的源极与所述电源的输出端电连接，所述第一场效应晶体管的漏极与所述触发电路的第二输入端电连接。
  8. 根据权利要求1所述的驱动电路，其中，所述触发电路包括：
    触发器，所述触发器的D输入端与所述电源的输出端电连接，所述触发器的脉冲输入端与所述第一开关电路的输出端电连接，所述触发器的Q输出端与所述第二开关电路的第二输入端电连接。
  9. 根据权利要求8所述的驱动电路，其中，所述触发电路还包括：
    第二限流电阻，所述第二限流电阻的一端与所述触发器的Q输出端和所述第二开关电路的第二输入端分别电连接，所述第二限流电阻的另一端接地。
  10. 根据权利要求1所述的驱动电路，其中，所述第二开关电路包括：
    第二开关管，所述第二开关管的第二输入端与所述触发电路的输出端电连接，所述第二开关管的第一输入端与所述第一电压电连接，所述第二开关管的输出端与所述印制电路板的输入端电连接。
  11. 根据权利要求10所述的驱动电路，其中，所述第二开关管包括：
    第二场效应晶体管，所述第二场效应晶体管的栅极与所述触发电路的输出端电连接，所述第二场效应晶体管的源极与所述第一电压电连接，所述第二场效应晶体管的漏极与所述印制电路板的输入端电连接。
  12. 根据权利要求10所述的驱动电路，其中，所述第二开关管包括：
    第二场效应晶体管，所述第二场效应晶体管的栅极与所述触发电路的输出端电连接，所述第二场效应晶体管的漏极与所述第一电压电连接，所述第二场效应晶体管的源极与所述印制电路板的输入端电连接。
  13. 根据权利要求1所述的驱动电路，其中，还包括：
    第三限流电阻，所述第三限流电阻的一端分别与所述第一开关电路的输出端和所述触发电路的第二输入端电连接，所述第三限流电阻的另一端接地。
  14. 一种驱动电路，其中，包括：
    比较器，通过所述比较器的第一输入端输入预设保护值，通过所述比较器的第二输入端输入第一电压；
    第一开关管，所述第一开关管的第一输入端与所述第一开关管的输出端电连接，所述第一开关管的第二输入端与电源的输出端电连接；
    触发电路，所述触发电路的第一输入端与所述电源的输出端电连接，所述触发电路的第二输入端与所述第一开关管的输出端电连接；
    第二开关管，所述第二开关管的第一输入端与所述第一电压电连接，所述第二开关管的第二输入端与所述触发电路的输出端电连接，所述第二管电路的 输出端与印制电路板的输入端电连接；
    所述比较器用于控制所述第一开关管的闭合与断开，当所述第一开关管闭合时，所述触发电路控制所述第二开关管断开，当所述第一开关管断开时，所述触发电路控制所述第二开关管闭合。
  15. 根据权利要求14所述的驱动电路，其中，所述第一开关管包括：
    第一场效应晶体管，所述第一场效应晶体管的栅极与所述比较器的输出端电连接，所述第一场效应晶体管的漏极与所述电源的输出端电连接，所述第一场效应晶体管的源极与所述触发电路的第二输入端电连接。
  16. 根据权利要求14所述的驱动电路，其中，所述第一开关管包括：
    第一场效应晶体管，所述第一场效应晶体管的栅极与所述比较器的输出端电连接，所述第一场效应晶体管的源极与所述电源的输出端电连接，所述第一场效应晶体管的漏极与所述触发电路的第二输入端电连接。
  17. 根据权利要求14所述的驱动电路，其中，所述触发电路包括：
    触发器，所述触发器的D输入端与所述电源的输出端电连接，所述触发器的脉冲输入端与所述第一开关管的输出端电连接，所述触发器的Q输出端与所述第二开关管的第二输入端电连接；
    第二限流电阻，所述第二限流电阻的一端与所述触发器的Q输出端和所述第二开关管的第二输入端分别电连接，所述第二限流电阻的另一端接地。
  18. 根据权利要求14所述的驱动电路，其中，所述第二开关管包括：
    第二场效应晶体管，所述第二场效应晶体管的栅极与所述触发电路的输出端电连接，所述第二场效应晶体管的源极与所述第一电压电连接，所述第二场效应晶体管的漏极与所述印制电路板的输入端电连接。
  19. 根据权利要求14所述的驱动电路，其中，所述第二开关管包括：
    第二场效应晶体管，所述第二场效应晶体管的栅极与所述触发电路的输出 端电连接，所述第二场效应晶体管的漏极与所述第一电压电连接，所述第二场效应晶体管的源极与所述印制电路板的输入端电连接。
  20. 一种驱动系统，其中，包括驱动电路，所述驱动电路包括：
    第一电路，通过所述第一电路的第一输入端输入预设保护值，通过所述第一电路的第二输入端输入第一电压；
    第一开关电路，所述第一开关电路的第一输入端与所述第一电路的输出端电连接，所述第一开关电路的第二输入端与电源的输出端电连接；
    触发电路，所述触发电路的第一输入端与所述电源的输出端电连接，所述触发电路的第二输入端与所述第一开关电路的输出端电连接；
    第二开关电路，所述第二开关电路的第一输入端与所述第一电压电连接，所述第二开关电路的第二输入端与所述触发电路的输出端电连接，所述第二开关电路的输出端与印制电路板的输入端电连接；
    所述第一电路用于控制所述第一开关电路的闭合与断开，当所述第一开关电路闭合时，所述触发电路控制所述第二开关电路断开，当所述第一开关电路断开时，所述触发电路控制所述第二开关电路闭合。
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