WO2018209742A1 - 液晶显示面板的时序驱动电路、驱动电路及液晶显示面板 - Google Patents
液晶显示面板的时序驱动电路、驱动电路及液晶显示面板 Download PDFInfo
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- WO2018209742A1 WO2018209742A1 PCT/CN2017/087822 CN2017087822W WO2018209742A1 WO 2018209742 A1 WO2018209742 A1 WO 2018209742A1 CN 2017087822 W CN2017087822 W CN 2017087822W WO 2018209742 A1 WO2018209742 A1 WO 2018209742A1
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- liquid crystal
- level shifter
- driving circuit
- display panel
- crystal display
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
Definitions
- the present invention claims the prior application priority of the application No. CN201710358681.2, entitled “Sequence Driving Circuit, Driving Circuit and Liquid Crystal Display Panel of Liquid Crystal Display Panel”, which was filed on May 19, 2017, the content of which is hereby incorporated by reference. The manner of introduction is incorporated into this text.
- the present invention relates to the field of display technologies, and in particular to a timing driving circuit, a driving circuit, and a liquid crystal display panel of a liquid crystal display panel.
- the existing liquid crystal display panel requires higher and higher resolution.
- the HD (High Definition) resolution liquid crystal display panel uses four control signals, and the four control signals are controlled by a leverl shifter (level). Converter)), in order to speed up the discharge speed, improve the shutdown afterimage, and make the screen disappear faster, the leverl shifter will detect the voltage of the system board to the control board.
- the voltage is generally 12V when working, and the voltage will be turned off when the power is turned off.
- the leverl shifter will continue to output a high level, which is transmitted to the thin film transistor of the display area to turn on the thin film transistor, thereby realizing discharge of all liquid crystal capacitors as soon as possible.
- the existing UD (Ultra High Definition) resolution liquid crystal display panel needs to use 8 control signals.
- two leverl shifters which can generate 4 control signals are generally used.
- Level shifter which produces 8 control signals, resulting in more lines.
- OCP over-current
- the leverl shifter may cause a difference in the voltage of the continuous output high level due to the error in the process, such as a leverl.
- the shifter triggers the continuous output high level voltage to be 10.1V, while the other leverl shifter triggers the continuous output high level voltage to be 9.8V.
- a leverl shifter triggers the continuous output high level.
- a normal output of the leverl shifter (rectangular wave) causes excessive current, causing the leverl shifter to falsely trigger overcurrent protection.
- the technical problem to be solved by the present invention is to provide a timing driving circuit, a driving circuit, and a liquid crystal display panel of a liquid crystal display panel.
- the problem of erroneously triggering overcurrent protection of the first level shifter and the second level shifter can be prevented.
- the first aspect of the present invention provides a timing driving circuit for a liquid crystal display panel, wherein the liquid crystal display panel includes a display area, and the thin film transistor is disposed in the display area and electrically connected to the thin film transistor a liquid crystal display, the liquid crystal display panel further includes a gate driver, and the gate driver outputs an on voltage or a shutdown voltage to the thin film transistor, including:
- control board electrically coupled to the system board for receiving the power supply voltage
- a first level shifter and a second level shifter each including a first pin, a second pin, a third pin, and a fourth pin, and the two first pins are used for detecting a power supply voltage, two of the fourth pins are electrically connected to the gate driver respectively;
- An AND gate unit comprising two input terminals, two of the input terminals being electrically connected to two of the second pins, respectively, and an output end of the AND gate unit is electrically connected to two of the third pins respectively ;among them,
- the second pin of the second level shifter outputs a high level to the input end of the AND gate unit, and the output end of the AND gate unit outputs a high level to two
- the third pin, the first level shifter and the second level shifter respectively continuously output a high level to the gate driver through the fourth pin, and the gate driver outputs an turn-on voltage to The thin film transistor of the display area realizes discharge of the liquid crystal capacitor.
- the first level converter and the second level converter are normally output.
- the timing driving circuit further includes a detecting branch, the detecting branch includes a first resistor and a second resistor, and the first end of the first resistor is connected to the control board for receiving a power voltage, a second end of the first resistor is respectively connected to the first pin of the first level shifter, the first pin of the second level shifter, and the first end of the second resistor; The second end of the two resistors is grounded.
- the detecting branch includes a first resistor and a second resistor, and the first end of the first resistor is connected to the control board for receiving a power voltage, a second end of the first resistor is respectively connected to the first pin of the first level shifter, the first pin of the second level shifter, and the first end of the second resistor; The second end of the two resistors is grounded.
- the resistance of the first resistor is smaller than the resistance of the second resistor.
- the AND gate unit is implemented by CMOS logic, NMOS logic, PMOS logic or diode.
- the first threshold voltage ranges from 9V to 11V; and the second threshold voltage ranges from 9V to 11V.
- a second aspect of the present invention provides a driving circuit for a liquid crystal display panel, wherein the liquid crystal display panel includes a display area, and the display area is provided with a thin film transistor and a liquid crystal capacitor electrically connected to the thin film transistor, including:
- timing driving circuit which is a timing driving circuit of the liquid crystal display panel described above;
- a gate driver electrically connected to the first level converter and the fourth level of the second level shifter, the gate driver is also electrically connected to the scan line, the scan line is electrically connected The gate of the thin film transistor.
- the gate driver is fabricated on the array substrate of the liquid crystal display panel.
- the driving circuit further includes a source driver, the timing driving circuit is electrically connected to the source driver, the source driver is further electrically connected to the data line, and the data line and the source of the thin film transistor Electrically connected, the liquid crystal capacitor is electrically connected to a drain of the thin film transistor.
- a third aspect of the present invention provides a liquid crystal display panel including the above-described driving circuit of the liquid crystal display panel.
- the timing driving circuit of the liquid crystal display panel includes an AND gate unit
- the two input ends of the AND gate unit are electrically connected to the two second pins, respectively, and the output ends of the AND gate unit are respectively associated with the two of the third terminals.
- the pins are electrically connected such that the first level shifter and the second level shifter pass the fourth lead even if the first threshold voltage of the first level shifter and the second threshold voltage of the second level shifter are different
- the continuous output high level of the pin is controlled by the output terminal of the AND unit, so that the problem that the excessive current erroneously triggers the overcurrent protection of the first level converter and the second level shifter is not caused.
- FIG. 1 is a schematic diagram of a timing driving circuit of a liquid crystal display panel according to an embodiment of the present invention.
- the present invention provides a timing driving circuit for a liquid crystal display panel, the liquid crystal display panel including a display area and a peripheral area, the display area generally refers to an area for displaying a pattern, and the display area is provided with a thin film transistor and a thin film transistor Connected liquid crystal capacitors, the peripheral area is disposed around the display area, the peripheral area is provided with some electrical components and lines, for example, a source driver and a gate driver are provided, that is, the liquid crystal display panel further includes And a gate driver that outputs an on voltage or a off voltage to the thin film transistor.
- the timing driving circuit includes:
- the system board 110 provides a power supply voltage, and the supplied power supply voltage is generally 12V. When the display panel is turned off, the power supply voltage is gradually lowered.
- the system board 110 is a movement board for converting video and audio signals or the like into signals displayable by the liquid crystal display panel.
- the control board 120 is electrically connected to the system board 110 through a line for receiving a power supply voltage, the power supply voltage is used as an input power of the control board 120, and the control board 120 is provided with a level shifter.
- IC level shifter controller
- TCON IC timing controller
- a first level shifter 130 and a second level shifter 140 each including a first pin 131, 141, a second pin 132, 142, a third pin 133, 143, and a fourth pin (illustration The fourth pin is not illustrated, and the first pins 131, 141 of the first level shifter 130 and the second level shifter 140 are used to detect the power supply voltage in real time, thereby the first level shifter 130 and the first
- the two-level converter 140 can obtain information of the power supply voltage in real time.
- Two of the fourth pins are electrically connected to the gate driver, respectively.
- the AND gate unit 150 includes two input terminals, and the two input terminals are electrically connected to the two second pins 132, 142, respectively, that is, one of the input terminals and the first level shifter 130
- the second pin 132 is electrically connected, and the other input is electrically connected to the second pin 142 of the second level shifter 140; the output of the AND gate unit 150 is respectively associated with two of the third lead
- the legs 133, 143 are electrically connected, that is, the output of the AND gate unit 150 is electrically connected to the third pin 133 of the first level shifter 130, and the output of the AND gate unit 150 is also connected to the second level.
- the third pin 143 of the converter 140 is electrically connected. In the embodiment, the third pins 133, 143 are control terminals.
- the timing driving circuit includes a first level shifter 130 and a second level shifter 140, and the first level shifter 130 and the second level shifter 140 are due to factors such as errors in the process.
- the threshold voltage may be different, that is, the first threshold voltage of the first level shifter 130 and the second threshold voltage of the second level shifter 140 may be different.
- the first threshold voltage ranges from 9V to 11V, for example, 9V, 9.5V, 10V, 10.2V, 10.5V, 11V, etc.
- the second threshold voltage ranges from 9V to 11V, for example, 9V, 9.5V, 9.8V, 10V, 10.5V, 11V, etc.
- the first threshold voltage is 10.2 V and the second threshold voltage is 9.8 V.
- the first threshold voltage and the second threshold voltage may be the same, in order to prevent the first threshold voltage and the second threshold voltage from being different.
- the second pin 132 of the level shifter 130 and the second pin 142 of the second level shifter 140 output a high level to the input of the gate unit 150, at this time, the two inputs of the AND gate unit 150 All of them are high level, and the logic output of the AND gate unit 150, the output terminal of the AND gate unit 150 outputs a high level, and the high level output by the AND gate unit 150 is output to the two third pins 133 and 143, respectively.
- the first level shifter 130 and the second level shifter 140 continuously output a high level to the gate driver through the fourth pin, that is, the first level shifting.
- the device 130 continues to output a high level
- the second level shifter 140 continues to output a high level
- the gate driver outputs an open voltage to the thin film transistor of the display area, so that the thin film transistor of the display area is turned on, and the liquid crystal capacitor is discharged. This improves the shutdown afterimage and makes the picture disappear faster.
- the abnormality of the liquid crystal display panel causes the power supply voltage to suddenly drop, for example, when the power supply voltage drops to 10.1V, the power supply voltage is lower than the first threshold voltage, but higher than the second threshold voltage.
- the first level converter The first pin 131 of 130 outputs a high level, but the first pin 141 of the second level shifter 140 outputs a low level, and the two input terminals of the AND gate unit 150 respectively receive a high level and a low level.
- the output of the AND gate unit 150 outputs a low level, so that the third pins 133, 143 of the first level shifter 130 and the second level shifter 140 receive a low level, at which time the first power
- the flat converter 130 and the second level shifter 140 output normally, and the normal output is a rectangular wave, that is, the output voltage has a high level and a low level, and the gate driver performs normal driving, that is, the gate driver output. Turning on the voltage or turning off the voltage, so that the liquid crystal capacitor in the display area of the liquid crystal display panel performs normal charging, discharging or holding, that is, the gate driver performs normal output, so that the super large current does not cause the first level converter and the second electric power to be erroneously triggered. level Converter overcurrent protection.
- the abnormality of the liquid crystal display panel causes the power supply voltage to suddenly drop, for example, when the power supply voltage drops to 10.5V, the power supply voltage is higher than the first threshold voltage and higher than the second threshold voltage.
- the first level shifter 130 The first pin 131 and the first pin 141 of the second level shifter 140 both output a low level, and the two input terminals of the AND gate unit 150 respectively receive a low level, and through logic operation, the AND unit 150
- the output terminal outputs a low level, so that the first level converter 130 and the third pins 133, 143 of the second level shifter 140 receive a low level, at which time the first level shifter 130 and the second level
- the flat converter 140 is normally output through the fourth pin, so that the pixels in the display area of the liquid crystal display panel perform normal charging and discharging, that is, normal output, so that the overcurrent protection is not caused by the excessive current.
- the timing driving circuit of the liquid crystal display panel includes the AND gate unit 150
- the two input ends of the AND gate unit 150 are electrically connected to the two second pins 132, 142, respectively, and the AND gate unit
- the output terminals of 150 are electrically connected to the two third pins 133, 143, respectively, such that even if the first threshold voltage of the first level shifter 130 and the second threshold voltage of the second level shifter 140 are different,
- the first level shifter 130 and the second level shifter 140 are continuously controlled by the fourth pin to continuously output a high level by the output terminal of the AND unit 150, so that the problem of excessive current erroneously triggering overcurrent protection is not caused.
- the timing driving circuit further includes a detecting branch 160, and the detecting branch 160 includes a first resistor R1 and a second resistor R2, and the first resistor R1
- the first end is connected to the control board for receiving the power supply voltage
- the second end of the first resistor R1 is respectively connected to the first pin 131 of the first level converter 130 and the second level converter 140.
- a pin 141, a first end of the second resistor R2, and a second end of the second resistor R2 is grounded.
- the AND gate unit 150 passes CMOS (Complementary Metal Oxide Semiconductor) logic, NMOS (N-Metal-Oxide-Semiconductor, N-type metal-oxidation).
- CMOS, NMOS, PMOS, diode implementation of the circuit of the gate unit 150 is a common knowledge in the field, in the field of semiconductor-to-semiconductor logic, PMOS (positive channel metal oxide semiconductor) logic or diode implementation, This will not go into details.
- the present invention also provides a driving circuit for a liquid crystal display panel, wherein the liquid crystal display panel includes a display area, and the display area is provided with a thin film transistor and a liquid crystal capacitor electrically connected to the thin film transistor, and the driving circuit includes the above a timing driving circuit and a gate driver, the gate driver being electrically connected to the first level converter 130 and the fourth pin of the second level converter 140, respectively, the gate driver also scanning The line is electrically connected, and the scan line is electrically connected to the thin film transistor of the display area.
- the gate driver normally outputs a signal, that is, a normal output turn-on voltage or The voltage is turned off, and the thin film transistor is turned on or off, so that the liquid crystal capacitor is normally charged, discharged, or held.
- the liquid crystal display panel includes an array substrate and a color filter substrate.
- the gate driver is fabricated on the array substrate (GOA), thereby the first level shifter 130, the second The level shifter 140 and the AND gate unit 150 are located on the array substrate.
- the driving circuit further includes a source driver, the timing driving circuit is electrically connected to the source driver, the source driver is further electrically connected to the data line, the data line and the film A source of the transistor is electrically connected, and the liquid crystal capacitor is electrically connected to a drain of the thin film transistor.
- the present invention also provides a liquid crystal display panel comprising the above-described driving circuit of the liquid crystal display panel.
- the present invention has the following advantages:
- the timing driving circuit of the liquid crystal display panel includes an AND gate unit
- the two input ends of the AND gate unit are electrically connected to the two second pins, respectively, and the output ends of the AND gate unit are respectively associated with the two of the third terminals.
- the pins are electrically connected such that the first level shifter and the second level shifter pass the fourth lead even if the first threshold voltage of the first level shifter and the second threshold voltage of the second level shifter are different
- the continuous output high level of the pin is controlled by the output terminal of the AND unit, so that the problem that the excessive current erroneously triggers the overcurrent protection of the first level converter and the second level shifter is not caused.
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Abstract
一种液晶显示面板的时序驱动电路，包括：系统板（110），其提供电源电压；控制板（120），其与系统板（110）电连接以用于接收电源电压；第一电平转换器（130）和第二电平转换器（140），其均包括第一引脚（131、141）、第二引脚（132、142）、第三引脚（133、143）和第四引脚，两个所述第一引脚（131、141）用于侦测所述电源电压，两个所述第四引脚分别与栅极驱动器电连接；与门单元（150），其包括两个输入端，两个所述输入端分别与两个第二引脚（132、142）电连接，与门单元（150）的输出端分别与两个所述第三引脚（133、143）电连接。可防止误触发第一电平转换器（130）和第二电平转换器（140）过流保护的问题。
Description
本发明要求2017年5月19日递交的发明名称为“液晶显示面板的时序驱动电路、驱动电路及液晶显示面板”的申请号CN201710358681.2的在先申请优先权，上述在先申请的内容以引入的方式并入本文本中。
本发明属于显示技术领域，具体地讲，涉及一种液晶显示面板的时序驱动电路、驱动电路及液晶显示面板。
现有的液晶显示面板，要求分辨率越来越高，目前HD(High Definition，高清)分辨率的液晶显示面板是使用4个控制信号，该4个控信号是由一颗leverl shifter(电平转换器)产生，为了加快放电速度，改善关机残影，使画面消失更快，leverl shifter会侦测系统板给控制板的电压，工作状态时该电压一般为12V，在关机时，该电压会逐渐降低，当低于某个阈值时，leverl shifter会持续输出高电平，该高电平会传输给显示区的薄膜晶体管以打开所述薄膜晶体管，从而实现所有液晶电容尽快放电(discharge)。
现有UD(Ultra High Definition，超高清)分辨率的液晶显示面板需要使用8个控制信号，为了产生8个控制信号，同时考虑通用性，一般采用两颗可产生4个控制信号的leverl shifter(电平转换器)，搭配产生8个控制信号，从而导致线路较多，为了防止液晶显示面板由于线路短路而造成损坏，leverl shifter通常有做过流(OCP)保护。
然而，现有UD分辨率的液晶显示面板需要使用两个leverl shifter时，leverl shifter由于制程上的误差等因素，两颗leverl shifter触发持续输出高电平的电压会有所差别，例如一颗leverl shifter触发持续输出高电平的电压为10.1V，而另一颗leverl shifter触发持续输出高电平的电压为9.8V，这种情况下，会出现有时一个leverl shifter触发持续输出高电平，另一个leverl shifter正常输出(矩形波)，从而造成超大电流，导致leverl shifter误触发过流保护。
发明内容
本发明所要解决的技术问题在于，提供一种液晶显示面板的时序驱动电路、驱动电路及液晶显示面板。可防止误触发第一电平转换器和第二电平转换器过流保护的问题。
为了解决上述技术问题，本发明第一方面实施例提供了一种液晶显示面板的时序驱动电路，所述液晶显示面板包括显示区，所述显示区内设有薄膜晶体管和与所述薄膜晶体管电连接的液晶电容，所述液晶显示面板还包括栅极驱动器，所述栅极驱动器输出开启电压或关闭电压给所述薄膜晶体管，包括：
系统板，其提供电源电压；
控制板，其与所述系统板电连接以用于接收所述电源电压；
第一电平转换器和第二电平转换器，其均包括第一引脚、第二引脚、第三引脚和第四引脚，两个所述第一引脚用于侦测所述电源电压，两个所述第四引脚分别与所述栅极驱动器电连接；
与门单元，其包括两个输入端，两个所述输入端分别与两个所述第二引脚电连接，所述与门单元的输出端分别与两个所述第三引脚电连接；其中，
当所述电源电压低于所述第一电平转换器的第一阈值电压和所述第二电平转换器的第二阈值电压时，所述第一电平转换器的所述第二引脚和所述第二电平转换器的所述第二引脚输出高电平给所述与门单元的所述输入端，所述与门单元的所述输出端分别输出高电平给两个所述第三引脚，所述第一电平转换器和所述第二电平转换器通过第四引脚分别持续输出高电平给栅极驱动器，所述栅极驱动器输出开启电压给所述显示区的所述薄膜晶体管，实现所述液晶电容放电。
其中，当所述电源电压高于所述第一阈值电压和所述第二阈值电压至少一个时，所述第一电平转换器和所述第二电平转换器正常输出。
其中，所述时序驱动电路还包括侦测支路，所述侦测支路包括第一电阻和第二电阻，所述第一电阻的第一端连接控制板，用于接收电源电压，所述第一电阻的第二端分别连接所述第一电平转换器的第一引脚、所述第二电平转换器的第一引脚、所述第二电阻的第一端；所述第二电阻的第二端接地。
其中，所述第一电阻的阻值小于所述第二电阻的阻值。
其中，所述与门单元通过CMOS逻辑、NMOS逻辑、PMOS逻辑或者二极管实现。
其中，所述第一阈值电压的范围为9V-11V；所述第二阈值电压的范围为9V-11V。
本发明第二方面提供一种液晶显示面板的驱动电路，所述液晶显示面板包括显示区，所述显示区内设有薄膜晶体管和与所述薄膜晶体管电连接的液晶电容，包括：
时序驱动电路，其为上述的液晶显示面板的时序驱动电路；
栅极驱动器，其分别与所述第一电平转换器和所述第二电平转换器的第四引脚电连接，所述栅极驱动器还与扫描线电连接，所述扫描线电连接所述薄膜晶体管的栅极。
其中，所述栅极驱动器制作在所述液晶显示面板的阵列基板上。
其中，所述驱动电路还包括源极驱动器，所述时序驱动电路与所述源极驱动器电连接，所述源极驱动器还与数据线电连接，所述数据线与所述薄膜晶体管的源极电连接，所述液晶电容与所述薄膜晶体管的漏极电连接。
本发明第三方面实施例提供了一种液晶显示面板，包括上述的液晶显示面板的驱动电路。
实施本发明，具有如下有益效果：
由于液晶显示面板的时序驱动电路包括与门单元，与门单元的两个输入端分别与两个所述第二引脚电连接，所述与门单元的输出端分别与两个所述第三引脚电连接，从而，即使第一电平转换器的第一阈值电压和第二电平转换器的第二阈值电压不同，第一电平转换器和第二电平转换器通过第四引脚分别持续输出高电平由与门单元的输出端控制，从而不会造成超大电流误触发第一电平转换器和第二电平转换器过流保护的问题。
为了更清楚地说明本发明或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明一实施例液晶显示面板的时序驱动电路的示意图。
下面将结合本发明中的附图，对本发明中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本申请说明书、权利要求书和附图中出现的术语“包括”和“具有”以及它们任何变形，意图在于覆盖不排他的包含。例如包含了一系列步骤或单元的过程、方法、系统、产品或设备没有限定于已列出的步骤或单元，而是可选地还包括没有列出的步骤或单元，或可选地还包括对于这些过程、方法、产品或设备固有的其它步骤或单元。此外，术语“第一”、“第二”和“第三”等是用于区别不同的对象，而并非用于描述特定的顺序。
本发明提供一种液晶显示面板的时序驱动电路，所述液晶显示面板包括显示区和外围区，所述显示区一般指显示图形的区域，所述显示区内设有薄膜晶体管和与薄膜晶体管电连接的液晶电容，所述外围区围绕所述显示区设置，所述外围区设有一些电性元器件及线路，例如设有源极驱动器、栅极驱动器，也即所述液晶显示面板还包括栅极驱动器，所述栅极驱动器输出开启电压或关闭电压给所述薄膜晶体管。请参见图1，所述时序驱动电路包括：
系统板110，其提供电源电压，该提供的电源电压一般为12V，当显示面板关机时，该电源电压慢慢降低。系统板110为机芯板，其用于把视频和音频信号或者类似信号的转化为液晶显示面板可显示的信号。
控制板120，其与所述系统板110通过线路电连接以用于接收电源电压，所述电源电压作为控制板120的输入电源，所述控制板120上设有level shifter
IC(电平转换器控制器)和TCON IC(时序控制器)。
第一电平转换器130和第二电平转换器140，其均包括第一引脚131、141、第二引脚132、142、第三引脚133、143和第四引脚(图示中未示意第四引脚)，第一电平转换器130和第二电平转换器140的第一引脚131、141用于实时侦测电源电压，从而第一电平转换器130和第二电平转换器140可以实时获得电源电压的信息。两个所述第四引脚分别与所述栅极驱动器电连接。
与门单元150，其包括两个输入端，两个所述输入端分别与两个所述第二引脚132、142电连接，也即其中一个所述输入端与第一电平转换器130的第二引脚132电连接，另一个所述输入端与第二电平转换器140的第二引脚142电连接；所述与门单元150的输出端分别与两个所述第三引脚133、143电连接，也即所述与门单元150的输出端与第一电平转换器130的第三引脚133电连接，所述与门单元150的输出端也与第二电平转换器140的第三引脚143电连接，在本实施例中，所述第三引脚133、143为控制端。
在本实施例中，时序驱动电路包括第一电平转换器130和第二电平转换器140，由于制程上的误差等因素，第一电平转换器130和第二电平转换器140的阈值电压可能不同，也即第一电平转换器130的第一阈值电压和第二电平转换器140的第二阈值电压可能不同，在本实施例中，第一阈值电压的范围为9V-11V，例如为9V、9.5V、10V、10.2V、10.5V、11V等，第二阈值电压的范围为9V-11V，例如为9V、9.5V、9.8V、10V、10.5V、11V等，在此处以第一阈值电压为10.2V、第二阈值电压为9.8V为例进行说明，当然，第一阈值电压和第二阈值电压也可以相同，为了防止第一阈值电压和第二阈值电压不同而造成的过流保护，在本实施例中，当电源电压低于第一电平转换器130的第一阈值电压和第二电平转换器140的第二阈值电压时，例如电源电压为9.5V时，此时代表液晶显示面板在执行关机操作，第一电平转换器130的第二引脚132和第二电平转换器140的第二引脚142输出高电平给与门单元150的输入端，此时，与门单元150的两个输入端均为高电平，经过与门单元150的逻辑运算，与门单元150的输出端输出高电平，与门单元150输出的高电平分别输出给两个所述第三引脚133、143，此时，第一电平转换器130和第二电平转换器140通过第四引脚分别持续输出高电平给栅极驱动器，也即第一电平转换
器130持续输出高电平，第二电平转换器140持续输出高电平，所述栅极驱动器输出开启电压给显示区的薄膜晶体管，从而显示区的薄膜晶体管被打开，液晶电容进行放电，从而改善关机残影，使画面消失更快。
当液晶显示面板异常导致电源电压突然降低时，例如电源电压突降到10.1V时，此时电源电压低于第一阈值电压，但高于第二阈值电压，此时，第一电平转换器130的第一引脚131输出高电平，但第二电平转换器140的第一引脚141输出低电平，与门单元150的两个输入端分别接收高电平和低电平，经过逻辑运算，与门单元150的输出端输出低电平，从而第一电平转换器130和第二电平转换器140的第三引脚133、143接收到低电平，此时第一电平转换器130和第二电平转换器140正常输出，该正常输出为矩形波，也即输出的电压有高电平也有低电平，栅极驱动器进行正常的驱动，也即栅极驱动器输出开启电压或者关闭电压，从而液晶显示面板显示区的液晶电容执行正常的充放电或保持，也即栅极驱动器进行正常输出，从而不会造成超大电流误触发第一电平转换器和第二电平转换器过流保护。
当液晶显示面板异常导致电源电压突然降低时，例如电源电压突降到10.5V时，此时电源电压高于第一阈值电压和高于第二阈值电压，此时，第一电平转换器130的第一引脚131和第二电平转换器140的第一引脚141均输出低电平，与门单元150的两个输入端分别接收低电平，经过逻辑运算，与门单元150的输出端输出低电平，从而第一电平转换器130和第二电平转换器140的第三引脚133、143接收到低电平，此时第一电平转换器130和第二电平转换器140通过第四引脚正常输出，从而液晶显示面板显示区的像素执行正常的充放电，也即进行正常输出，从而不会造成超大电流误触发过流保护。
在本实施例中，由于液晶显示面板的时序驱动电路包括与门单元150，与门单元150的两个输入端分别与两个所述第二引脚132、142电连接，所述与门单元150的输出端分别与两个所述第三引脚133、143电连接，从而，即使第一电平转换器130的第一阈值电压和第二电平转换器140的第二阈值电压不同，第一电平转换器130和第二电平转换器140分别通过第四引脚持续输出高电平由与门单元150的输出端控制，从而不会造成超大电流误触发过流保护的问题。
请继续参见图1，在本实施例中，所述时序驱动电路还包括侦测支路160，所述侦测支路160包括第一电阻R1和第二电阻R2，所述第一电阻R1的第一端连接控制板，用于接收电源电压，所述第一电阻R1的第二端分别连接所述第一电平转换器130的第一引脚131、第二电平转换器140的第一引脚141、所述第二电阻R2的第一端，所述第二电阻R2的第二端接地。从而实现电源电压的实时侦测。在本实施例中，所述第一电阻R1的阻值小于第二电阻R2的阻值，例如R2＝10R1，R2＝20R1，等。
在本实施例中，为了实现与门单元150，所述与门单元150通过CMOS(Complementary Metal Oxide Semiconductor，互补金属氧化物半导体)逻辑、NMOS(N-Metal-Oxide-Semiconductor，N型金属-氧化物-半导体)逻辑、PMOS(positive channel Metal Oxide Semiconductor，P沟道金属氧化物半导体)逻辑或者二极管实现，CMOS、NMOS、PMOS、二极管具体实现与门单元150的电路为本领域的公知常识，在此就不再赘述。
本发明还提供一种液晶显示面板的驱动电路，所述液晶显示面板包括显示区，所述显示区内设有薄膜晶体管和与所述薄膜晶体管电连接的液晶电容，所述驱动电路包括上述的时序驱动电路和栅极驱动器，所述栅极驱动器分别与所述第一电平转换器130和所述第二电平转换器140的第四引脚电连接，所述栅极驱动器还与扫描线电连接，所述扫描线电连接所述显示区的薄膜晶体管。从而，当所述与门单元150的所述输出端分别输出高电平给两个所述第三引脚133、143，所述第一电平转换器130和所述第二电平转换器140通过第四引脚分别持续输出高电平给栅极驱动器，所述栅极驱动器输出开启电压经由扫描线给所述显示区的所述薄膜晶体管，实现所述液晶电容放电。当所述第一电平转换器130和第二电平转换器140听过第四引脚输出低电平给栅极驱动器时，所述栅极驱动器正常输出信号，也即正常输出开启电压或关闭电压，所述薄膜晶体管开启或关闭，从而所述液晶电容正常充放电或者保持。
在本实施例中，所述液晶显示面板包括阵列基板和彩色滤光片基板，为了降低成本，所述栅极驱动器制作在阵列基板上(GOA)，从而第一电平转换器130、第二电平转换器140和与门单元150位于阵列基板上。
在本实施例中，所述驱动电路还包括源极驱动器，所述时序驱动电路与所述源极驱动器电连接，所述源极驱动器还与数据线电连接，所述数据线与所述薄膜晶体管的源极电连接，所述液晶电容与所述薄膜晶体管的漏极电连接。
本发明还提供一种液晶显示面板，所述液晶显示面板包括上述的液晶显示面板的驱动电路。
需要说明的是，本说明书中的各个实施例均采用递进的方式描述，每个实施例重点说明的都是与其它实施例的不同之处，各个实施例之间相同相似的部分互相参见即可。对于装置实施例而言，由于其与方法实施例基本相似，所以描述的比较简单，相关之处参见方法实施例的部分说明即可。
通过上述实施例的描述，本发明具有以下优点：
由于液晶显示面板的时序驱动电路包括与门单元，与门单元的两个输入端分别与两个所述第二引脚电连接，所述与门单元的输出端分别与两个所述第三引脚电连接，从而，即使第一电平转换器的第一阈值电压和第二电平转换器的第二阈值电压不同，第一电平转换器和第二电平转换器通过第四引脚分别持续输出高电平由与门单元的输出端控制，从而不会造成超大电流误触发第一电平转换器和第二电平转换器过流保护的问题。
以上所揭露的仅为本发明较佳实施例而已，当然不能以此来限定本发明之权利范围，因此依本发明权利要求所作的等同变化，仍属本发明所涵盖的范围。
Claims (20)
- 一种液晶显示面板的时序驱动电路，所述液晶显示面板包括显示区，所述显示区内设有薄膜晶体管和与所述薄膜晶体管电连接的液晶电容，所述液晶显示面板还包括栅极驱动器，所述栅极驱动器输出开启电压或关闭电压给所述薄膜晶体管，其中，包括：系统板，其提供电源电压；控制板，其与所述系统板电连接以用于接收所述电源电压；第一电平转换器和第二电平转换器，其均包括第一引脚、第二引脚、第三引脚和第四引脚，两个所述第一引脚用于侦测所述电源电压，两个所述第四引脚分别与所述栅极驱动器电连接；与门单元，其包括两个输入端，两个所述输入端分别与两个所述第二引脚电连接，所述与门单元的输出端分别与两个所述第三引脚电连接；其中，当所述电源电压低于所述第一电平转换器的第一阈值电压和所述第二电平转换器的第二阈值电压时，所述第一电平转换器的所述第二引脚和所述第二电平转换器的所述第二引脚输出高电平给所述与门单元的所述输入端，所述与门单元的所述输出端分别输出高电平给两个所述第三引脚，所述第一电平转换器和所述第二电平转换器通过第四引脚分别持续输出高电平给栅极驱动器，所述栅极驱动器输出开启电压给所述显示区的所述薄膜晶体管，实现所述液晶电容放电。
- 如权利要求1所述的液晶显示面板的时序驱动电路，其中，当所述电源电压高于所述第一阈值电压和所述第二阈值电压至少一个时，所述第一电平转换器和所述第二电平转换器正常输出。
- 如权利要求1所述的液晶显示面板的时序驱动电路，其中，所述时序驱动电路还包括侦测支路，所述侦测支路包括第一电阻和第二电阻，所述第一电阻的第一端连接控制板，用于接收电源电压，所述第一电阻的第二端分别连接所述第一电平转换器的第一引脚、所述第二电平转换器的第一引脚、所述第 二电阻的第一端；所述第二电阻的第二端接地。
- 如权利要求2所述的液晶显示面板的时序驱动电路，其中，所述时序驱动电路还包括侦测支路，所述侦测支路包括第一电阻和第二电阻，所述第一电阻的第一端连接控制板，用于接收电源电压，所述第一电阻的第二端分别连接所述第一电平转换器的第一引脚、所述第二电平转换器的第一引脚、所述第二电阻的第一端；所述第二电阻的第二端接地。
- 如权利要求3所述的液晶显示面板的时序驱动电路，其中，所述第一电阻的阻值小于所述第二电阻的阻值。
- 如权利要求4所述的液晶显示面板的时序驱动电路，其中，所述第一电阻的阻值小于所述第二电阻的阻值。
- 如权利要求1所述的液晶显示面板的时序驱动电路，其中，所述与门单元通过CMOS逻辑、NMOS逻辑、PMOS逻辑或者二极管实现。
- 如权利要求2所述的液晶显示面板的时序驱动电路，其中，所述与门单元通过CMOS逻辑、NMOS逻辑、PMOS逻辑或者二极管实现。
- 如权利要求1所述的液晶显示面板的时序驱动电路，其中，所述第一阈值电压的范围为9V-11V；所述第二阈值电压的范围为9V-11V。
- 如权利要求2所述的液晶显示面板的时序驱动电路，其中，所述第一阈值电压的范围为9V-11V；所述第二阈值电压的范围为9V-11V。
- 一种液晶显示面板的驱动电路，所述液晶显示面板包括显示区，所述显示区内设有薄膜晶体管和与所述薄膜晶体管电连接的液晶电容，其中，所述驱动电路包括时序驱动电路和栅极驱动器；所述时序驱动电路，包括：系统板，其提供电源电压；控制板，其与所述系统板电连接以用于接收所述电源电压；第一电平转换器和第二电平转换器，其均包括第一引脚、第二引脚、第三引脚和第四引脚，两个所述第一引脚用于侦测所述电源电压，两个所述第四引脚分别与所述栅极驱动器电连接；与门单元，其包括两个输入端，两个所述输入端分别与两个所述第二引脚电连接，所述与门单元的输出端分别与两个所述第三引脚电连接；其中，当所述电源电压低于所述第一电平转换器的第一阈值电压和所述第二电平转换器的第二阈值电压时，所述第一电平转换器的所述第二引脚和所述第二电平转换器的所述第二引脚输出高电平给所述与门单元的所述输入端，所述与门单元的所述输出端分别输出高电平给两个所述第三引脚，所述第一电平转换器和所述第二电平转换器通过第四引脚分别持续输出高电平给栅极驱动器，所述栅极驱动器输出开启电压给所述显示区的所述薄膜晶体管，实现所述液晶电容放电；所述栅极驱动器分别与所述第一电平转换器和所述第二电平转换器的第四引脚电连接，所述栅极驱动器还与扫描线电连接，所述扫描线电连接所述薄膜晶体管的栅极。
- 如权利要求11所述的液晶显示面板的驱动电路，其中，所述栅极驱动器制作在所述液晶显示面板的阵列基板上。
- 如权利要求11所述的液晶显示面板的驱动电路，其中，所述驱动电路还包括源极驱动器，所述时序驱动电路与所述源极驱动器电连接，所述源极驱动器还与数据线电连接，所述数据线与所述薄膜晶体管的源极电连接，所述液晶电容与所述薄膜晶体管的漏极电连接。
- 如权利要求12所述的液晶显示面板的驱动电路，其中，所述驱动电路还包括源极驱动器，所述时序驱动电路与所述源极驱动器电连接，所述源极 驱动器还与数据线电连接，所述数据线与所述薄膜晶体管的源极电连接，所述液晶电容与所述薄膜晶体管的漏极电连接。
- 如权利要求11所述的液晶显示面板的驱动电路，其中，当所述电源电压高于所述第一阈值电压和所述第二阈值电压至少一个时，所述第一电平转换器和所述第二电平转换器正常输出。
- 如权利要求11所述的液晶显示面板的驱动电路，其中，所述时序驱动电路还包括侦测支路，所述侦测支路包括第一电阻和第二电阻，所述第一电阻的第一端连接控制板，用于接收电源电压，所述第一电阻的第二端分别连接所述第一电平转换器的第一引脚、所述第二电平转换器的第一引脚、所述第二电阻的第一端；所述第二电阻的第二端接地。
- 如权利要求11所述的液晶显示面板的驱动电路，其中，所述与门单元通过CMOS逻辑、NMOS逻辑、PMOS逻辑或者二极管实现。
- 一种液晶显示面板，其中，所述液晶显示面板包括显示区，所述显示区内设有薄膜晶体管和与所述薄膜晶体管电连接的液晶电容，所述液晶显示面板包括液晶显示面板的驱动电路，所述液晶显示面板的驱动电路包括时序驱动电路和栅极驱动器；所述时序驱动电路，包括：系统板，其提供电源电压；控制板，其与所述系统板电连接以用于接收所述电源电压；第一电平转换器和第二电平转换器，其均包括第一引脚、第二引脚、第三引脚和第四引脚，两个所述第一引脚用于侦测所述电源电压，两个所述第四引脚分别与所述栅极驱动器电连接；与门单元，其包括两个输入端，两个所述输入端分别与两个所述第二引脚电连接，所述与门单元的输出端分别与两个所述第三引脚电连接；其中，当所述电源电压低于所述第一电平转换器的第一阈值电压和所述第二 电平转换器的第二阈值电压时，所述第一电平转换器的所述第二引脚和所述第二电平转换器的所述第二引脚输出高电平给所述与门单元的所述输入端，所述与门单元的所述输出端分别输出高电平给两个所述第三引脚，所述第一电平转换器和所述第二电平转换器通过第四引脚分别持续输出高电平给栅极驱动器，所述栅极驱动器输出开启电压给所述显示区的所述薄膜晶体管，实现所述液晶电容放电；所述栅极驱动器分别与所述第一电平转换器和所述第二电平转换器的第四引脚电连接，所述栅极驱动器还与扫描线电连接，所述扫描线电连接所述薄膜晶体管的栅极。
- 如权利要求18所述的液晶显示面板，其中，所述栅极驱动器制作在所述液晶显示面板的阵列基板上。
- 如权利要求18所述的液晶显示面板，其中，当所述电源电压高于所述第一阈值电压和所述第二阈值电压至少一个时，所述第一电平转换器和所述第二电平转换器正常输出。
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