WO2020040072A1 - Wiring board, package, and module - Google Patents

Wiring board, package, and module Download PDF

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Publication number
WO2020040072A1
WO2020040072A1 PCT/JP2019/032221 JP2019032221W WO2020040072A1 WO 2020040072 A1 WO2020040072 A1 WO 2020040072A1 JP 2019032221 W JP2019032221 W JP 2019032221W WO 2020040072 A1 WO2020040072 A1 WO 2020040072A1
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WIPO (PCT)
Prior art keywords
pad pair
wiring path
wiring
pad
ground pattern
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Application number
PCT/JP2019/032221
Other languages
French (fr)
Japanese (ja)
Inventor
正人 石▲崎▼
久保 昇
Original Assignee
Ngkエレクトロデバイス株式会社
日本碍子株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ngkエレクトロデバイス株式会社, 日本碍子株式会社 filed Critical Ngkエレクトロデバイス株式会社
Priority to CN201980032015.7A priority Critical patent/CN112119489B/en
Priority to JP2020538367A priority patent/JP7026804B2/en
Publication of WO2020040072A1 publication Critical patent/WO2020040072A1/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components

Definitions

  • the present invention relates to a wiring board, a package, and a module.
  • the high-frequency module has a high-frequency package, a semiconductor element, and a lid.
  • the high-frequency package includes a frame having a through-hole and a high-frequency board attached to the through-hole.
  • the high-frequency substrate has an insulating base, a first line conductor, a second line conductor, a capacitor, a first bonding material, and a second bonding material.
  • the insulating base has a concave portion on the upper surface.
  • the first electrode pad is provided at an end of the recess on the upper surface of the insulating base.
  • the first line conductor is provided on the upper surface of the insulating base so as to extend from the first electrode pad.
  • the second electrode pad is provided on the upper surface of the insulating base so as to face the first electrode pad with the concave portion interposed therebetween.
  • the second line conductor is provided on the upper surface of the insulating base so as to extend from the second electrode pad.
  • the capacitor overlaps the recess.
  • the first bonding material bonds the capacitor and the first electrode pad.
  • the second joining material joins the capacitor and the second electrode pad, and is provided with a space between the first joining material.
  • the gap between the first bonding material and the second bonding material is maintained by the concave portion. Can be. Thereby, the possibility that the first bonding material and the second bonding material come into contact with each other can be reduced. Further, since a space is provided between the electrode portions of the capacitor by the concave portion, between the electrode portions of the capacitor, between the first electrode pad and the second electrode pad, and between the first bonding material and the second bonding material. Can be reduced, and the characteristic impedance of the transmission line for the high-frequency signal can be adjusted to a desired value.
  • the characteristic impedance of the transmission line for the high-frequency signal can be adjusted by the concave portion arranged to overlap the capacitor.
  • a local sudden change in the characteristic impedance at a portion where the concave portion is provided becomes remarkable.
  • Local sudden changes in characteristic impedance result in higher return losses at higher frequencies.
  • the present invention has been made to solve the above-described problems, and an object of the present invention is to provide a wiring board, a package, and a module that can obtain good transmission characteristics in a high-frequency region.
  • a wiring board includes a ceramic base, a first ground pattern, a first wiring path, a second wiring path, a second ground pattern, a first pad pair, and a second pad. Have a pair.
  • the first ground pattern is provided on the ceramic base.
  • the first wiring path is provided on the ceramic base, is disposed apart from the first ground pattern, and has a portion extending in one direction on the ceramic base.
  • the second wiring path is provided on the ceramic base, is separated from the first ground pattern by the first wiring path on the ceramic base, and extends in one direction alongside the first wiring path.
  • the second ground pattern is provided on the ceramic base, is separated from the first wiring path by the second wiring path on the ceramic base, and is separated from the second wiring path on the ceramic base. .
  • the first pad pair is for mounting a capacitor, is provided in the middle of the first wiring path, and has a width larger than the width of the first wiring path.
  • the second pad pair is for mounting a capacitor, is provided in the middle of the second wiring path, and has a width larger than the width of the second wiring path.
  • the first pad pair includes a pair of first pads opposed in one direction.
  • the second pad pair includes a pair of second pads opposed in one direction.
  • the first pad pair and the second pad pair face each other in a direction orthogonal to one direction.
  • the ceramic base includes a first concave portion provided between the first ground pattern and the first pad pair, and a second concave portion provided between the second ground pattern and the second pad pair.
  • the package of the present invention includes a wiring board and a casing having a cavity. At least a part of the wiring board is located inside the cavity.
  • the module of the present invention has a package, a lid for sealing the cavity of the package, and an integrated circuit mounted in the cavity.
  • the first wiring path and the second wiring path form a differential line electrically connected to the integrated circuit.
  • a differential line is formed by extending the first wiring path provided with the first pad pair and the second wiring path provided with the second pad pair side by side.
  • FIG. 2 is a top view schematically illustrating a configuration of a module according to Embodiment 1 of the present invention.
  • FIG. 2 is a top view schematically showing a configuration of the package according to the first embodiment of the present invention.
  • FIG. 3 is a schematic partial sectional view taken along a line III-III in FIG. 2.
  • FIG. 2 is a circuit diagram schematically showing a configuration of a wiring board according to Embodiment 1 of the present invention.
  • FIG. 5 is a schematic diagram showing a part of the circuit of the wiring board in FIG. 4 in a view parallel to the view in FIG. 3.
  • FIG. 5 is a schematic diagram showing a part of the circuit of the wiring board in FIG. 4 in a view parallel to the view in FIG. 3.
  • FIG. 2 is a partial top view schematically showing a configuration of a surface wiring of the wiring board according to Embodiment 1 of the present invention.
  • FIG. 8 is a schematic partial sectional view taken along line VIII-VIII in FIG. 7.
  • FIG. 4 is a partial top view schematically showing a configuration of a surface wiring of a wiring board of a first comparative example.
  • FIG. 10 is a schematic partial sectional view taken along line XX of FIG. 9.
  • FIG. 9 is a partial top view schematically showing a configuration of a surface wiring of a wiring board of a second comparative example.
  • FIG. 12 is a schematic partial sectional view taken along line XII-XII in FIG. 11.
  • FIG. 13 is a partial top view schematically illustrating a configuration of a surface wiring of a wiring board of a third comparative example.
  • FIG. 14 is a schematic partial cross-sectional view taken along a line XIV-XIV in FIG. 13.
  • FIG. 13 is a graph showing, as time-domain reflection, simulation results of characteristic impedances of the wiring boards of the example of the present embodiment and the first to third comparative examples.
  • FIG. 10 is a graph showing simulation results of reflection characteristics in the band of 0 to 75 GHz for the wiring boards of the example of the present embodiment and the first to third comparative examples.
  • FIG. 14 is a graph showing simulation results of crosstalk characteristics in a band of 25 to 75 GHz for the wiring board of the example of the present embodiment and the first to third comparative examples.
  • FIG. 10 is a graph showing simulation results of the ratio of energy loss in the band of 25 to 75 GHz for the wiring board of the example of the present embodiment and the first to third comparative examples.
  • FIG. 14 is a graph showing simulation results of pass characteristics in the band of 25 to 75 GHz for the wiring board of the example of the present embodiment and the first to third comparative examples.
  • FIG. 8 is a partial top view showing a modification of FIG. 7.
  • FIG. 9 is a partial top view showing another modification of FIG. 7.
  • FIG. 11 is a top view schematically showing a configuration of a package according to a second embodiment of the present invention.
  • FIG. 1 is a top view schematically showing a configuration of high-frequency module 701 according to the first embodiment. Note that, for the lid 730, only the outer edge is indicated by a two-dot chain line in order to make the drawing easy to see.
  • FIG. 2 is a top view schematically illustrating a configuration of a high-frequency package 501 used to obtain the high-frequency module 701. Note that the external terminals of the high-frequency module 701 (FIG. 1) and the high-frequency package 501 (FIG. 2) are not limited to those illustrated, and for example, power is supplied into the high-frequency module 701 (high-frequency package 501). A power supply terminal (not shown) may be provided.
  • FIG. 3 is a schematic partial sectional view taken along line III-III of FIG.
  • the high-frequency module 701 (FIG. 1) includes the high-frequency package 501 (FIG. 2), the lid 730, and the internal circuit 750.
  • the internal circuit 750 has an IC (integrated circuit) 751.
  • Each of the high-frequency module 701 and the high-frequency package 501 is a high-frequency module and a high-frequency package, and the IC 751 may have a high operating frequency, specifically, an operating frequency of 55 GHz or more.
  • the internal circuit 750 further has an optical component 752, and thus the high-frequency module 701 and the high-frequency package 501 are an optical module and an optical package, respectively.
  • the optical component 752 is, for example, a photodiode.
  • the high-frequency package 501 includes the high-frequency board 301 (wiring board) and the casing 530.
  • the casing 530 has a cavity CV by having a bottom 531 and a frame 532 surrounding the bottom 531.
  • the cover 730 seals the cavity CV.
  • the internal circuit 750 is mounted in the cavity CV.
  • a cable is provided to receive light from an optical fiber (not shown) disposed outside the high-frequency module 701 or to secure a path for transmitting light to the optical fiber.
  • An opening 535 is provided in the frame 532 of the thing 530.
  • a cylindrical member for fixing an optical fiber may be attached to the opening 535.
  • a translucent material may be attached inside the cylindrical member.
  • the high-frequency substrate 301 has a portion located inside the cavity CV and a portion located outside the cavity CV. Thus, the high-frequency substrate 301 forms an electric path connecting the inside and the outside of the cavity CV. In order to obtain this configuration, the high-frequency board 301 penetrates through holes TH provided in the frame portion 532 of the casing 530.
  • the high-frequency board 301 has internal terminals 71 to 74 and external terminals 81 to 84.
  • the internal terminals 71 to 74 are arranged inside the cavity CV, and the external terminals 81 to 84 are arranged outside the cavity CV.
  • the external terminals 81 to 84 are only schematically shown in the drawing, the external terminals 81 to 84 may be, for example, projecting lead terminals.
  • FIG. 4 is a circuit diagram schematically showing a configuration of the high-frequency board 301.
  • the high-frequency substrate 301 constitutes at least one differential line, and in this embodiment, constitutes two differential lines CA and CB.
  • One set of internal terminals 71 to 74 and external terminals 81 to 84 is provided corresponding to each differential line.
  • the first ground pattern 41 connects between the internal terminal 71 and the external terminal 81.
  • the second ground pattern 42 connects between the internal terminal 74 and the external terminal 84.
  • the “ground pattern” is a conductor pattern that is normally assumed to be at a ground potential when the high-frequency module 701 is used. Therefore, it is preferable that the ground patterns on the high-frequency substrate 301 are electrically short-circuited to each other.
  • the high-frequency board 301 has the first wiring path 51 and the pair of first pads 61a and 61b between the internal terminal 72 and the external terminal 82.
  • the whole of the pair of first pads 61a and 61b is also referred to as a first pad pair 61.
  • the first pad pair 61 is provided in the middle of the first wiring path 51.
  • the first pad pair 61 is for mounting the capacitor 90, and is provided in the middle of the first wiring path 51.
  • the high-frequency substrate 301 has the second wiring path 52 and a pair of second pads 62a and 62b between the internal terminal 73 and the external terminal 83.
  • the whole of the pair of second pads 62a and 62b is also referred to as a second pad pair 62.
  • the second pad pair 62 is provided in the middle of the second wiring path 52.
  • the second pad pair 62 is for mounting the capacitor 90 and is provided in the middle of the second wiring path 52.
  • first pad pair 61 and the second pad pair 62 will be described later with reference to FIG. 7, but the first pad pair 61 and the second pad pair 62 51 and the second wiring path 52 are arranged symmetrically with respect to an imaginary line extending along the extending direction. This is for the following reason. Since the capacitor 90 usually has a member having a high dielectric constant, it is assumed that the phase of the signal changes inside the capacitor 90. For example, when the phase inside the capacitor 90 mounted on the first pad pair 61 and the phase of the second wiring path 52 adjacent to the capacitor 90 are different from each other and capacitive coupling occurs between them, the impedance is changed from the design value. Shift.
  • first pad pair 61 and the second pad pair 62 are arranged so as to be shifted from each other in the extending direction of the wiring path, there is a possibility that the impedance is largely shifted from the design value.
  • first pad pair 61 and the second pad pair 62 are arranged in line symmetry, that is, if the first pad pair 61 and the second pad pair 62 are extended If they are arranged facing each other in a direction orthogonal to the existing direction, it is possible to prevent the impedance from greatly deviating from the design value.
  • the first wiring path 51 and the second wiring path 52 constitute a differential line electrically connected to the IC 751.
  • signals of opposite phases are propagated through the first wiring path 51 and the second wiring path 52.
  • the capacitor 90 By providing the capacitor 90 on the differential line, the flow of the DC component in the differential line can be inhibited.
  • the capacitor 90 as a blocking capacitor prevents the bias voltage used in the IC 751 from being applied to the external terminals 82 and 83.
  • FIG. 5 is a schematic diagram showing a portion between the internal terminal 71 and the external terminal 81 in the circuit of the high-frequency board 301 in a view parallel to the view in FIG.
  • the portion between the internal terminal 74 and the external terminal 84 has the same configuration.
  • FIG. 6 is a schematic diagram showing a portion between the internal terminal 72 and the external terminal 82 in the circuit of the high-frequency board 301 in a view parallel to the view of FIG.
  • the portion between the internal terminal 73 and the external terminal 83 has the same configuration.
  • the wiring WR (the circuit shown in FIG. 4) in the high-frequency substrate 301 has a surface wiring WRS arranged on the surface of the high-frequency substrate 301. Further, the wiring WR may include an internal wiring WRB which is disposed in the high-frequency substrate 301 and has a portion extending in the thickness direction.
  • the above-described capacitor 90 is mounted on the surface wiring WRS. In other words, the first pad pair 61 and the second pad pair 62 described above are provided on the surface wiring WRS.
  • a specific configuration of the surface wiring WRS will be described in detail.
  • FIG. 7 is a partial top view schematically showing the configuration of surface wiring WRS (FIGS. 5 and 6) of high-frequency substrate 301.
  • FIG. 8 is a schematic partial sectional view taken along line VIII-VIII of FIG.
  • the high frequency substrate 301 has the ceramic base 10 made of an insulator. On the ceramic base 10, a first ground pattern 41, a first wiring path 51, a second wiring path 52, a second ground pattern 42, first pads 61a, 61b, and a second pad 62a , 62b.
  • the first pad 61a and the first pad 61b face each other in one direction (the horizontal direction in FIG. 7) with an interval therebetween.
  • the first wiring path 51 is electrically separated by this interval.
  • the second pad 62a and the second pad 62b face each other in one direction (the horizontal direction in FIG. 7) with an interval therebetween.
  • the second wiring path 52 is electrically separated by this interval.
  • the first wiring path 51 is arranged apart from the first ground pattern 41.
  • the first wiring path 51 has a portion that extends on the ceramic base 10 in one direction (the horizontal direction in FIGS. 7 and 8).
  • the second wiring path 52 is separated from the first ground pattern 41 by the first wiring path 51 on the ceramic base 10.
  • the second wiring path 52 has a portion extending in one direction (the horizontal direction in FIGS. 7 and 8) alongside the first wiring path 51.
  • the second ground pattern 42 is separated from the first wiring path 51 by a second wiring path 52 on the ceramic base 10 and is separated from the second wiring path 52 on the ceramic base 10.
  • the high frequency substrate 301 may further have a third ground pattern 43.
  • the third ground pattern 43 is disposed between the first wiring path 51 and the second wiring path 52 on the ceramic base 10.
  • the third ground pattern 43 is separated from the first wiring path 51 and the second wiring path 52.
  • the second wiring path 52 is arranged on the first wiring path 51 via the third ground pattern 43.
  • a curved portion is provided in the first wiring path 51 and the second wiring path 52 running in parallel.
  • the third ground pattern 43 is not arranged between the first pad pair 61 and the second pad pair 62. Thereby, the effect of the present embodiment is further increased.
  • the first pad pair 61 including the first pads 61a and 61b has a width larger than the width of the first wiring path 51.
  • the second pad pair 62 including the second pads 62a and 62b has a width larger than the width of the second wiring path 52.
  • the width is a dimension in a direction perpendicular to the extending direction of the wiring path (horizontal direction in FIG. 7), and is a vertical dimension in FIG. Since the pad pair has a width larger than the width of the wiring path, the capacitor 90 having a width larger than the width of the wiring path can be easily mounted.
  • the width of the wiring path is about 100 ⁇ m, and the width of the pad pair is about 300 ⁇ m.
  • the mounting of the capacitor 90 can be performed using a bonding material (for example, solder).
  • the high-frequency substrate 301 After the step of mounting the capacitors on the high-frequency substrate 301 is performed, the high-frequency substrate 301 includes a capacitor 90 mounted on the first pad pair 61 and a capacitor 90 mounted on the second pad pair 62. have. Conversely, before the step of mounting the capacitor on the high-frequency substrate 301 is performed, the high-frequency substrate 301 does not have the capacitor 90 yet.
  • a concave portion RC1 (first concave portion) and a concave portion RC2 (second concave portion) are provided.
  • the concave portion RC1 is arranged between the first ground pattern 41 and the first pad pair 61.
  • the concave portion RC2 is disposed between the second ground pattern 42 and the second pad pair 62.
  • the “recess” in the present specification is a region that is clearly deeper than its periphery, and specifically, a region that has a depth of 50 ⁇ m or more.
  • the high-frequency substrate 301 has a first inner-layer ground pattern 31 and a second inner-layer ground pattern 32 inside the ceramic base 10.
  • the second inner-layer ground pattern 32 is provided deeper than the first inner-layer ground pattern 31. That is, the depth D2 of the second inner-layer ground pattern 32 is greater than the depth D1 of the first inner-layer ground pattern 31.
  • the first inner-layer ground pattern 31 has a portion facing the first wiring path 51 and the second wiring path 52 (not shown in FIG. 8) in the thickness direction (vertical direction in the figure), Further, an opening OP is provided below the first pad pair 61 and the second pad pair 62 (not shown in FIG. 8).
  • the second inner layer ground pattern 32 has a portion facing the first pad pair 61 and the second pad pair 62 (not shown in FIG. 8) via the opening OP of the first inner layer ground pattern 31. are doing.
  • the distance between each of the first pad pair 61 and the second pad pair 62 and the inner-layer ground pattern can be set to a depth D2 larger than the depth D1.
  • the first ground pattern 41 and the second ground pattern 42 are electrically short-circuited to each other. Generally, these are electrically connected to each other via a vertical portion (a portion passing through a through hole) and a horizontal portion (an inner layer ground pattern) of internal wiring WRB (FIG. 5). However, as a modification, only the surface wiring WRS (FIG. 5) may be provided, and the internal wiring WRB may not be provided. In this case, the first ground pattern 41 and the second ground pattern 42 (FIG. 7) It may be electrically short-circuited to each other by any other method.
  • the inner-layer ground pattern is usually a pattern parallel to the surface of the ceramic base 10, and may be a pattern arranged over substantially the entire ceramic base 10 in a planar layout, in other words, a solid pattern.
  • a pseudo coaxial structure can be formed by surrounding the internal wiring WRB (FIG. 6) connecting the internal terminal 72 and the external terminal 82 for transmitting signals with an inner layer ground pattern.
  • FIG. 9 is a partial top view schematically showing the configuration of the surface wiring WRS (see FIGS. 5 and 6) of the high-frequency substrate 301A of the first comparative example.
  • FIG. 10 is a schematic partial sectional view taken along line XX of FIG. In the high-frequency substrate 301A, no recess is provided in the ceramic base 10. Other configurations are the same as those of the high-frequency substrate 301 (FIGS. 7 and 8).
  • FIG. 11 is a partial top view schematically showing the configuration of surface wiring WRS (see FIGS. 5 and 6) of high-frequency substrate 301B of the second comparative example.
  • FIG. 12 is a schematic partial sectional view taken along line XII-XII in FIG.
  • the ceramic base 10 does not have the recesses RC1 and RC2 (FIGS. 7 and 8), but instead has the recesses RC4 (fourth recess) and the recess RC5 (fifth recess). are doing.
  • the recess RC4 is arranged between the first pad 61a and the first pad 61b, and the recess RC5 is arranged between the second pad 62a and the second pad 62b.
  • the recess RC4 and the recess RC5 may be connected as shown in FIG. As a variant, the recesses RC4 and RC5 may be separated from each other.
  • FIG. 13 is a partial top view schematically showing the configuration of surface wiring WRS (see FIGS. 5 and 6) of high-frequency substrate 301C of the third comparative example.
  • FIG. 14 is a schematic partial cross-sectional view taken along line XIV-XIV in FIG.
  • the ceramic base 10 does not have the concave portions RC1 and RC2 (FIGS. 7 and 8), but has a concave portion RC3 (third concave portion) instead.
  • the recess RC3 is arranged between the first pad pair 61 and the second pad pair 62.
  • the simulation is performed with a model in which a metal block is mounted as a substitute for the capacitor 90. Further, in order to facilitate comparison of the simulation results, the size of the concave portion formed on the surface of the ceramic substrate 10 in the high-frequency substrates 301, 301B, and 301C is described in detail with reference to FIG. The average correction of the characteristic impedance performed by the recess is selected to be approximately the same.
  • the simulation is performed under the following conditions.
  • the dimension in the extending direction of the wiring path (for example, the horizontal direction in FIG. 7) is referred to as length, and the dimension in the width direction of the wiring path (vertical direction in FIG. 7) is referred to as width.
  • the configurations of the first inner-layer ground pattern 31 and the second inner-layer ground pattern 32 are set under the same conditions. These inner-layer ground patterns are almost solid patterns.
  • Width of first wiring path 51 (second wiring path 52): 0.1 mm Distance D1 (FIG. 8): 0.15 mm Distance D2 (FIG. 8): 0.5 mm
  • Dimensions of recesses RC1 (RC2) (FIG. 7): width 0.25 mm, length 0.80 mm, depth 0.4 mm (rectangle) Dimensions of recess RC3 (FIG.
  • FIG. 15 is a graph showing the simulation result of the characteristic impedance as time domain reflection (TDR: Time Domain Reflectometry) at a frequency of 67 GHz.
  • TDR Time Domain Reflectometry
  • the time axis represented by the horizontal axis can be regarded as a space axis, and a pair of arrows roughly corresponds to the positions of the pair of first pads 61a and 61b.
  • the average value of the characteristic impedance between the arrows is greatly reduced. This is due to an increase in the capacitance component due to the presence of the first pad pair 61.
  • the concave portions are formed in the ceramic base 10
  • a decrease in the average value of the characteristic impedance between the arrows is corrected. That is, the average value of the characteristic impedance approaches the designed value of 100 ⁇ .
  • the sizes of the concave portions of the high-frequency boards 301, 301B, and 301C are selected so that the effect of this correction is substantially the same. Comparing the characteristic impedances of the high-frequency boards 301, 301B, and 301C, a local sudden change in the characteristic impedance between the arrows is remarkable in the high-frequency boards 301B.
  • FIG. 16 is a graph showing simulation results of reflection characteristics.
  • the high-frequency board 301B has a large reflection over a wide range from 40 GHz to 60 GHz as compared with other wiring boards. This reason is considered to be due to the sudden change in the characteristic impedance described above.
  • FIG. 17 is a graph showing simulation results of crosstalk characteristics. Specifically, referring to FIG. 4, the magnitude of signal energy leakage from differential line CA to differential line CB is simulated. Large crosstalk means that this undesirable leakage is large.
  • the high-frequency substrate 301C has the poorest crosstalk characteristics in most of the band of about 40 GHz or higher. On the other hand, the high frequency substrate 301 has the most excellent crosstalk characteristics in most of the band of 40 GHz or more.
  • FIG. 18 is a graph showing a simulation result of an energy loss ratio.
  • the energy loss referred to here is a difference obtained by removing a loss due to reflection (see FIG. 16) and a signal energy passing through the circuit (see FIG. 19) from the signal energy input to the circuit.
  • Such energy loss is generally considered to be due to dielectric loss, conductor loss, radiation loss, and the like.
  • Below 55 GHz there is no significant difference in energy loss characteristics.
  • the high-frequency substrate 301 has the most excellent characteristics, and at 60 GHz or higher, the effect is more remarkable. This is presumably because radiation loss due to mode conversion into a surface wave (described later in detail) and loss due to crosstalk (FIG. 17) can be suppressed.
  • the high-frequency substrate 301 can be used at least up to about 70 GHz in many applications. Therefore, it is considered that the high-frequency substrate 301 has excellent energy loss characteristics at least in a high-frequency region of 55 GHz or more and 70 GHz or less. In addition, it can be assumed that such a high frequency region is used particularly in an optical module (optical package).
  • FIG. 19 is a graph showing a simulation result of the passage characteristic.
  • the high frequency substrate 301B has inferior transmission characteristics over a wide range from 40 GHz to 60 GHz as compared with the high frequency substrate 301A having no concave portion. This reason is considered to be due to the above-mentioned sudden change in the characteristic impedance.
  • the high-frequency substrate 301C has a transmission characteristic similar to that of the high-frequency substrate 301A having no concave portion. Therefore, it can be seen that the concave portion RC3 of the high-frequency substrate 301C does not have the effect of widening the signal pass band from the viewpoint of the pass characteristics.
  • the high-frequency substrate 301 has excellent transmission characteristics at a high frequency, particularly at a frequency of 60 GHz or higher, as compared with other wiring substrates. This is a result corresponding to the small energy loss (FIG. 18).
  • first pad pair 61 and second pad pair 61 are formed by combining first inner layer ground pattern 31 and second inner layer ground pattern 32.
  • the local decrease in the characteristic impedance due to the presence of the two pad pairs 62 can be suppressed to some extent. If the local decrease in the characteristic impedance, that is, the deviation from the design value of 100 ⁇ , is sufficiently suppressed only depending on the optimization of this configuration, the width of the pad becomes larger than the width of the wiring path.
  • the depth D2 must be increased accordingly. In other words, the distance between the second inner layer ground pattern 32 and each of the first pad pair 61 and the second pad pair 62 (not shown in FIG.
  • the configuration of the surface wiring of the wiring board be as symmetrical as possible. For example, in FIG.
  • the path 51 and the second wiring path 52 and the first ground pattern 41 and the second ground pattern 42 preferably have the same dimensions (including the depth of the concave portion and the thickness of the wiring path and the like). These are preferably arranged symmetrically with respect to the center line of the third ground pattern 43 (if shown in FIG. 7, the center line extending in the horizontal direction).
  • the capacitors 90 mounted on the first pad pair 61 and the second pad pair 62 also preferably have the above-mentioned symmetry. This is the same for the differential lines in other comparative examples and modified examples.
  • the ceramic base 10 may have a recess RC3 (FIG. 13) in addition to the recesses RC1 and RC2 (FIG. 7). Due to the design, there is an upper limit to the depth of the concave portions RC1 and RC2. Specifically, the depths of the concave portions RC1 and RC2 must be smaller than the depth D2 (FIG. 8). Due to this, there is a case where the local decrease in the characteristic impedance in the vicinity of the first pad pair 61 and the second pad pair 62 cannot be sufficiently suppressed. In such a case, by providing the concave portion RC3, it is possible to sufficiently suppress the local decrease in the characteristic impedance.
  • the length of the recess RC3 is preferably equal to or longer than the length LP of the first pad pair 61 (FIG. 20). Further, it is preferable that the depth of the recess RC3 is smaller than the depth of each of the recesses RC1 and RC2. Thereby, it is possible to suppress the local loss of the characteristic impedance while suppressing the energy loss due to the crosstalk in the high frequency region caused by providing the concave portion RC3.
  • the ceramic base 10 may have concave portions RC4 and RC5 (FIG. 11) in addition to the concave portions RC1 and RC2 (FIG. 7).
  • a bonding material (typical) is provided between the first pad 61a and the first pad 61b (and between the second pad 62a and the second pad 62b) when the capacitor 90 is mounted. Is unintentionally formed between the first pad 61a and the first pad 61b (and between the second pad 62a and the second pad 62b). Thus, an electrical short circuit between the first pad 61a and the first pad 61b (and between the second pad 62a and the second pad 62b) can be prevented.
  • the width of the concave portion RC4 (and RC5) is preferably equal to or larger than the width of the first pad 61a (and the second pad 62a). As a result, an electrical short circuit can be reliably prevented.
  • each of the recesses RC4 and RC5 is preferably smaller than the depth of each of the recesses RC1 and RC2, and is between the first pad 61a and the first pad 61b (and between the second pad 62a and the second pad 62b). ) Is sufficient to prevent an electrical short circuit. Thus, unnecessary abrupt changes in the characteristic impedance caused by the concave portions RC4 and RC5 can be avoided.
  • the ceramic base 10 may have the concave portions RC3 to RC5 in addition to the concave portions RC1 and RC2 (FIG. 7).
  • FIG. 20 is a partial top view showing a high-frequency board 301v (wiring board) of the third modification.
  • the length LR of the recess RC1 is longer than the length LP of the first pad pair 61.
  • the length of the recess RC2 is longer than the length of the second pad pair 62. If the length LR is too large, the area where the first ground pattern 41 is provided is reduced. Therefore, in an actual design, the upper limit of the length LR is up to about 1.5 times the length LP of the first pad pair 61. Become. The same applies to the length of the recess RC2.
  • the length LP of the first pad pair 61 is the total dimension of the first pad pair 61 in the direction in which the first pad 61a and the first pad 61b face each other (the horizontal direction in FIG. 20).
  • the length LR of the recess RC1 is the dimension of the recess RC1 in the above direction. The same applies to the length of the second pad pair 62 and the length of the recess RC2.
  • the concave portions RC1 and RC2 can be reliably arranged in a sufficient range near the first pad pair 61 and the second pad pair 62. This makes it possible to more reliably obtain the effects of the concave portions RC1 and RC2 described above.
  • FIG. 21 is a partial top view illustrating a high-frequency board 301w (wiring board) according to a fourth modification.
  • the first pad pair 61 has a shape characterized by a minimum length LP1 and a maximum length LP2. Within the minimum length LP1, the first pad pair 61 has a substantially constant width. Outside this range, the first pad pair 61 has a tapered shape.
  • the minimum length LP1 is regarded as the length of the first pad pair.
  • the length LR of the concave portion RC1 is equal to or longer than the length of the first pad pair 61, that is, the minimum length LP1. If the length LR is too large, the area in which the first ground pattern 41 is provided is reduced. Therefore, the length LR may be set to be equal to or less than the maximum length LP2 of the first pad pair 61.
  • the length of the recess RC2 is also defined in the same manner as the length LR of the recess RC1.
  • the concave portions RC1 and RC2 can be reliably arranged in a sufficient range near the first pad pair 61 and the second pad pair 62. This makes it possible to more reliably obtain the effects of the concave portions RC1 and RC2 described above.
  • FIG. 22 is a top view schematically showing a configuration of high-frequency package 502 according to the second embodiment.
  • the high-frequency package 502 has a high-frequency board 302 (wiring board) instead of the high-frequency board 301 (FIG. 1: Embodiment 1).
  • the high-frequency board 302 is different from the high-frequency board 301 and is entirely mounted in the cavity CV of the casing 530.
  • the high-frequency board 302 may be used as a mounting area for mounting part or all of the internal circuit 750 (FIG. 1). In that case, part or all of the mounting area 550 may be omitted.
  • casing 530 has external terminals 91 to 94 arranged outside cavity CV.
  • Each of the external terminals 91 to 94 is electrically connected to the external terminals 81 to 84 of the high-frequency board 302.
  • the specific configuration of the external terminals 91 to 94 is arbitrary, and for example, a metal pin penetrating the frame portion 532 is used.
  • the high-frequency board 302 of the present embodiment does not constitute external terminals of a package. Except for this point, almost the same effects as in the first embodiment can be obtained in the present embodiment.

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Abstract

According to the present invention, a second wiring path (52) is separated from a first ground pattern (41) by means of a first wiring path (51), and extends parallel to the first wiring path (51). A second ground pattern (42) is separated from the first wiring path (51) by means of the second wiring path (52). A first pad pair (61) for mounting a capacitor is provided in the middle of the first wiring path (51), and has a width that is greater than the width of the first wiring path (51). A second pad pair (62) for mounting a capacitor is provided in the middle of the second wiring path (52), and has a width that is greater than the width of the second wiring path (52). A ceramic base (10) has: a first recess portion (RC1) provided between the first ground pattern (41) and the first pad pair (61); and a second recess portion (RC2) provided between the second ground pattern (42) and the second pad pair (62).

Description

配線基板、パッケージおよびモジュールWiring boards, packages and modules
 本発明は、配線基板、パッケージおよびモジュールに関するものである。 The present invention relates to a wiring board, a package, and a module.
 国際公開第2017/170389号によれば、高周波モジュールが開示されている。高周波モジュールは、高周波パッケージと、半導体素子と、蓋体とを有している。高周波パッケージは、貫通孔を有する枠体と、貫通孔に取り付けられた高周波基板とを有している。高周波基板は、絶縁基体と、第1線路導体と、第2線路導体と、キャパシタと、第1接合材と、第2接合材とを有している。第1線路導体と第2線路導体との間にキャパシタが設けられることによって、高周波信号の直流電流成分を除去することができる。 高周波 WO 2017/170389 discloses a high frequency module. The high-frequency module has a high-frequency package, a semiconductor element, and a lid. The high-frequency package includes a frame having a through-hole and a high-frequency board attached to the through-hole. The high-frequency substrate has an insulating base, a first line conductor, a second line conductor, a capacitor, a first bonding material, and a second bonding material. By providing a capacitor between the first line conductor and the second line conductor, the DC current component of the high-frequency signal can be removed.
 絶縁基体は、上面に凹部を有している。第1電極パッドは、絶縁基体の上面において凹部の端部に設けられている。第1線路導体は、絶縁基体の上面に、第1電極パッドから延びて設けられている。第2電極パッドは、絶縁基体の上面に、凹部を挟んで第1電極パッドと対向して設けられている。第2線路導体は、絶縁基体の上面に、第2電極パッドから延びて設けられている。キャパシタは凹部と重なっている。第1接合材は、キャパシタと第1電極パッドとを接合している。第2接合材は、キャパシタと第2電極パッドとを接合するとともに、第1接合材と間を空けて設けられている。 The insulating base has a concave portion on the upper surface. The first electrode pad is provided at an end of the recess on the upper surface of the insulating base. The first line conductor is provided on the upper surface of the insulating base so as to extend from the first electrode pad. The second electrode pad is provided on the upper surface of the insulating base so as to face the first electrode pad with the concave portion interposed therebetween. The second line conductor is provided on the upper surface of the insulating base so as to extend from the second electrode pad. The capacitor overlaps the recess. The first bonding material bonds the capacitor and the first electrode pad. The second joining material joins the capacitor and the second electrode pad, and is provided with a space between the first joining material.
 高周波基板に凹部が設けられていることにより、第1接合材および第2接合材の量が多くなってしまったとしても、第1接合材と第2接合材との間隔を凹部によって保持することができる。このことによって、第1接合材と第2接合材とが接触するおそれを低減することができる。さらに、凹部によりキャパシタの電極部の間に空間が設けられるため、キャパシタの電極部の間、第1電極パッドと第2電極パッドとの間、および第1接合材と第2接合材との間のそれぞれに生じる静電容量の影響を小さくすることができ、高周波信号の伝送線路における特性インピーダンスを所望の値に調整することができる。 Even when the amounts of the first bonding material and the second bonding material are increased due to the provision of the concave portion in the high-frequency substrate, the gap between the first bonding material and the second bonding material is maintained by the concave portion. Can be. Thereby, the possibility that the first bonding material and the second bonding material come into contact with each other can be reduced. Further, since a space is provided between the electrode portions of the capacitor by the concave portion, between the electrode portions of the capacitor, between the first electrode pad and the second electrode pad, and between the first bonding material and the second bonding material. Can be reduced, and the characteristic impedance of the transmission line for the high-frequency signal can be adjusted to a desired value.
国際公開第2017/170389号WO 2017/170389
 上記公報に記載の技術によれば、上述したように、キャパシタに重なるように配置された凹部によって、高周波信号の伝送線路における特性インピーダンスを調整することができる。しかしながら、本発明者らの検討によれば、特性インピーダンスの十分なマッチングを上記凹部に主に頼って確保しようとすると、凹部が設けられた箇所での特性インピーダンスの局所的な急変が顕著となる。特性インピーダンスの局所的な急変は、周波数が高いほど、より大きな反射損失につながる。近年、高周波パッケージの帯域をより広げることが求められており、よって、より高い周波数領域においても良好な通過特性を得ることが求められている。 According to the technique described in the above publication, as described above, the characteristic impedance of the transmission line for the high-frequency signal can be adjusted by the concave portion arranged to overlap the capacitor. However, according to the study of the present inventors, if it is attempted to ensure sufficient matching of the characteristic impedance mainly by relying on the concave portion, a local sudden change in the characteristic impedance at a portion where the concave portion is provided becomes remarkable. . Local sudden changes in characteristic impedance result in higher return losses at higher frequencies. In recent years, there has been a demand for broadening the band of a high-frequency package, and thus it has been required to obtain good pass characteristics even in a higher frequency region.
 本発明は以上のような課題を解決するためになされたものであり、その目的は、高周波領域で良好な通過特性を得ることができる、配線基板、パッケージおよびモジュールを提供することである。 The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a wiring board, a package, and a module that can obtain good transmission characteristics in a high-frequency region.
 本発明の配線基板は、セラミック基体と、第1の接地パターンと、第1の配線路と、第2の配線路と、第2の接地パターンと、第1のパッド対と、第2のパッド対とを有している。第1の接地パターンはセラミック基体上に設けられている。第1の配線路は、セラミック基体上に設けられており、第1の接地パターンから離れて配置されており、セラミック基体上を一の方向に延びる部分を有している。第2の配線路は、セラミック基体上に設けられており、セラミック基体上において第1の配線路によって第1の接地パターンから隔てられており、第1の配線路に並んで一の方向に延びる部分を有している。第2の接地パターンは、セラミック基体上に設けられており、セラミック基体上において第2の配線路によって第1の配線路から隔てられており、セラミック基体上において第2の配線路から離れている。第1のパッド対は、キャパシタを実装するためのものであり、第1の配線路の中途に設けられており、第1の配線路の幅よりも大きな幅を有している。第2のパッド対は、キャパシタを実装するためのものであり、第2の配線路の中途に設けられており、第2の配線路の幅よりも大きな幅を有している。第1のパッド対は、一の方向に対向する1対の第1パッドを含む。第2のパッド対は、一の方向に対向する1対の第2パッドを含む。第1のパッド対および第2のパッド対は、一の方向に直交する方向に対向している。セラミック基体は、第1の接地パターンと第1のパッド対との間に設けられた第1の凹部と、第2の接地パターンと第2のパッド対との間に設けられた第2の凹部とを有している。 A wiring board according to the present invention includes a ceramic base, a first ground pattern, a first wiring path, a second wiring path, a second ground pattern, a first pad pair, and a second pad. Have a pair. The first ground pattern is provided on the ceramic base. The first wiring path is provided on the ceramic base, is disposed apart from the first ground pattern, and has a portion extending in one direction on the ceramic base. The second wiring path is provided on the ceramic base, is separated from the first ground pattern by the first wiring path on the ceramic base, and extends in one direction alongside the first wiring path. Has a part. The second ground pattern is provided on the ceramic base, is separated from the first wiring path by the second wiring path on the ceramic base, and is separated from the second wiring path on the ceramic base. . The first pad pair is for mounting a capacitor, is provided in the middle of the first wiring path, and has a width larger than the width of the first wiring path. The second pad pair is for mounting a capacitor, is provided in the middle of the second wiring path, and has a width larger than the width of the second wiring path. The first pad pair includes a pair of first pads opposed in one direction. The second pad pair includes a pair of second pads opposed in one direction. The first pad pair and the second pad pair face each other in a direction orthogonal to one direction. The ceramic base includes a first concave portion provided between the first ground pattern and the first pad pair, and a second concave portion provided between the second ground pattern and the second pad pair. And
 本発明のパッケージは、配線基板と、キャビティを有するケーシングとを含む。配線基板の少なくとも一部はキャビティの内部に位置している。 パ ッ ケ ー ジ The package of the present invention includes a wiring board and a casing having a cavity. At least a part of the wiring board is located inside the cavity.
 本発明のモジュールは、パッケージと、パッケージのキャビティを封止する蓋体と、キャビティ内に実装された集積回路とを有している。第1の配線路および第2の配線路は、集積回路に電気的に接続される差動線路を構成している。 The module of the present invention has a package, a lid for sealing the cavity of the package, and an integrated circuit mounted in the cavity. The first wiring path and the second wiring path form a differential line electrically connected to the integrated circuit.
 本発明によれば、第1のパッド対が設けられた第1の配線路と、第2のパッド対が設けられた第2の配線路とが並んで延びることによって、差動線路が構成される。この差動線路を用いての信号伝送において、本発明者らの検討によれば、セラミック基体に上述した配置で第1および第2の凹部が設けられることによって、高周波領域で良好な通過特性を得ることができる。 According to the present invention, a differential line is formed by extending the first wiring path provided with the first pad pair and the second wiring path provided with the second pad pair side by side. You. In the signal transmission using this differential line, according to the study of the present inventors, by providing the first and second concave portions in the above-described arrangement in the ceramic base, good pass characteristics in a high frequency region are obtained. Obtainable.
 この発明の目的、特徴、局面、および利点は、以下の詳細な説明と添付図面とによって、より明白となる。 The objects, features, aspects, and advantages of the present invention will become more apparent from the following detailed description and the accompanying drawings.
本発明の実施の形態1におけるモジュールの構成を概略的に示す上面図である。FIG. 2 is a top view schematically illustrating a configuration of a module according to Embodiment 1 of the present invention. 本発明の実施の形態1におけるパッケージの構成を概略的に示す上面図である。FIG. 2 is a top view schematically showing a configuration of the package according to the first embodiment of the present invention. 図2の線III-IIIに沿う概略的な部分断面図である。FIG. 3 is a schematic partial sectional view taken along a line III-III in FIG. 2. 本発明の実施の形態1における配線基板の構成を概略的に示す回路図である。FIG. 2 is a circuit diagram schematically showing a configuration of a wiring board according to Embodiment 1 of the present invention. 図4の配線基板の回路の一部を、図3の視野に平行な視野で示す模式図である。FIG. 5 is a schematic diagram showing a part of the circuit of the wiring board in FIG. 4 in a view parallel to the view in FIG. 3. 図4の配線基板の回路の一部を、図3の視野に平行な視野で示す模式図である。FIG. 5 is a schematic diagram showing a part of the circuit of the wiring board in FIG. 4 in a view parallel to the view in FIG. 3. 本発明の実施の形態1における配線基板の表面配線の構成を概略的に示す部分上面図である。FIG. 2 is a partial top view schematically showing a configuration of a surface wiring of the wiring board according to Embodiment 1 of the present invention. 図7の線VIII-VIIIに沿う概略的な部分断面図である。FIG. 8 is a schematic partial sectional view taken along line VIII-VIII in FIG. 7. 第1の比較例の配線基板の表面配線の構成を概略的に示す部分上面図である。FIG. 4 is a partial top view schematically showing a configuration of a surface wiring of a wiring board of a first comparative example. 図9の線X-Xに沿う概略的な部分断面図である。FIG. 10 is a schematic partial sectional view taken along line XX of FIG. 9. 第2の比較例の配線基板の表面配線の構成を概略的に示す部分上面図である。FIG. 9 is a partial top view schematically showing a configuration of a surface wiring of a wiring board of a second comparative example. 図11の線XII-XIIに沿う概略的な部分断面図である。FIG. 12 is a schematic partial sectional view taken along line XII-XII in FIG. 11. 第3の比較例の配線基板の表面配線の構成を概略的に示す部分上面図である。FIG. 13 is a partial top view schematically illustrating a configuration of a surface wiring of a wiring board of a third comparative example. 図13の線XIV-XIVに沿う概略的な部分断面図である。FIG. 14 is a schematic partial cross-sectional view taken along a line XIV-XIV in FIG. 13. 本実施の形態の実施例および第1~第3の比較例の配線基板についての特性インピーダンスのシミュレーション結果を、時間領域反射として示すグラフ図である。FIG. 13 is a graph showing, as time-domain reflection, simulation results of characteristic impedances of the wiring boards of the example of the present embodiment and the first to third comparative examples. 本実施の形態の実施例および第1~第3の比較例の配線基板についての0~75GHzの帯域における反射特性のシミュレーション結果を示すグラフ図である。FIG. 10 is a graph showing simulation results of reflection characteristics in the band of 0 to 75 GHz for the wiring boards of the example of the present embodiment and the first to third comparative examples. 本実施の形態の実施例および第1~第3の比較例の配線基板についての25~75GHzの帯域におけるクロストーク特性のシミュレーション結果を示すグラフ図である。FIG. 14 is a graph showing simulation results of crosstalk characteristics in a band of 25 to 75 GHz for the wiring board of the example of the present embodiment and the first to third comparative examples. 本実施の形態の実施例および第1~第3の比較例の配線基板についての25~75GHzの帯域におけるエネルギー損失の割合のシミュレーション結果を示すグラフ図である。FIG. 10 is a graph showing simulation results of the ratio of energy loss in the band of 25 to 75 GHz for the wiring board of the example of the present embodiment and the first to third comparative examples. 本実施の形態の実施例および第1~第3の比較例の配線基板についての25~75GHzの帯域における通過特性のシミュレーション結果を示すグラフ図である。FIG. 14 is a graph showing simulation results of pass characteristics in the band of 25 to 75 GHz for the wiring board of the example of the present embodiment and the first to third comparative examples. 図7の一の変形例を示す部分上面図である。FIG. 8 is a partial top view showing a modification of FIG. 7. 図7の他の変形例を示す部分上面図である。FIG. 9 is a partial top view showing another modification of FIG. 7. 本発明の実施の形態2におけるパッケージの構成を概略的に示す上面図である。FIG. 11 is a top view schematically showing a configuration of a package according to a second embodiment of the present invention.
 以下、図面に基づいて本発明の実施の形態について説明する。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
 <実施の形態1>
 (構成)
 図1は、本実施の形態1における高周波モジュール701の構成を概略的に示す上面図である。なお蓋体730については、図を見やすくするために、外縁のみが二点鎖線で示されている。図2は、高周波モジュール701を得るために用いられる高周波パッケージ501の構成を概略的に示す上面図である。なお、高周波モジュール701(図1)および高周波パッケージ501(図2)の外部端子は、図示されているものに限定されるわけではなく、例えば、高周波モジュール701(高周波パッケージ501)中へ電源を供給するための電源端子(図示せず)が設けられていてよい。図3は、図2の線III-IIIに沿う概略的な部分断面図である。
<First Embodiment>
(Constitution)
FIG. 1 is a top view schematically showing a configuration of high-frequency module 701 according to the first embodiment. Note that, for the lid 730, only the outer edge is indicated by a two-dot chain line in order to make the drawing easy to see. FIG. 2 is a top view schematically illustrating a configuration of a high-frequency package 501 used to obtain the high-frequency module 701. Note that the external terminals of the high-frequency module 701 (FIG. 1) and the high-frequency package 501 (FIG. 2) are not limited to those illustrated, and for example, power is supplied into the high-frequency module 701 (high-frequency package 501). A power supply terminal (not shown) may be provided. FIG. 3 is a schematic partial sectional view taken along line III-III of FIG.
 高周波モジュール701(図1)は、高周波パッケージ501(図2)と、蓋体730と、内部回路750とを有している。内部回路750はIC(集積回路)751を有している。高周波モジュール701および高周波パッケージ501のそれぞれは高周波モジュールおよび高周波パッケージであり、IC751は高い動作周波数を有していてよく、具体的には55GHz以上の動作周波数を有していてよい。本実施の形態においては、内部回路750はさらに光学部品752を有しており、よって高周波モジュール701および高周波パッケージ501はそれぞれ、光モジュールおよび光パッケージである。光学部品752は、例えば、フォトダイオードである。 The high-frequency module 701 (FIG. 1) includes the high-frequency package 501 (FIG. 2), the lid 730, and the internal circuit 750. The internal circuit 750 has an IC (integrated circuit) 751. Each of the high-frequency module 701 and the high-frequency package 501 is a high-frequency module and a high-frequency package, and the IC 751 may have a high operating frequency, specifically, an operating frequency of 55 GHz or more. In the present embodiment, the internal circuit 750 further has an optical component 752, and thus the high-frequency module 701 and the high-frequency package 501 are an optical module and an optical package, respectively. The optical component 752 is, for example, a photodiode.
 高周波パッケージ501は、高周波基板301(配線基板)と、ケーシング530とを有している。ケーシング530は、底部531と底部531を囲む枠部532とを有することによって、キャビティCVを有している。蓋体730はキャビティCVを封止している。内部回路750はキャビティCV内に実装されている。本実施の形態の高周波パッケージ501においては、高周波モジュール701の外部に配置された光ファイバ(図示せず)からの光を受けるためまたは光ファイバへ光を送るための経路を確保するために、ケ―シング530の枠部532に開口部535が設けられている。開口部535には、光ファイバを固定するための筒状部材が取り付けられていてもよい。筒状部材の内部に透光性材料が取り付けられていてもよい。 The high-frequency package 501 includes the high-frequency board 301 (wiring board) and the casing 530. The casing 530 has a cavity CV by having a bottom 531 and a frame 532 surrounding the bottom 531. The cover 730 seals the cavity CV. The internal circuit 750 is mounted in the cavity CV. In the high-frequency package 501 of the present embodiment, a cable is provided to receive light from an optical fiber (not shown) disposed outside the high-frequency module 701 or to secure a path for transmitting light to the optical fiber. An opening 535 is provided in the frame 532 of the thing 530. A cylindrical member for fixing an optical fiber may be attached to the opening 535. A translucent material may be attached inside the cylindrical member.
 高周波基板301は、キャビティCVの内部に位置する部分と、キャビティCVの外部に位置する部分とを有している。これにより、高周波基板301は、キャビティCVの内部と外部とをつなぐ電気的経路を構成している。この構成を得るために、高周波基板301は、ケーシング530の枠部532に設けられた貫通孔THを貫通している。 (4) The high-frequency substrate 301 has a portion located inside the cavity CV and a portion located outside the cavity CV. Thus, the high-frequency substrate 301 forms an electric path connecting the inside and the outside of the cavity CV. In order to obtain this configuration, the high-frequency board 301 penetrates through holes TH provided in the frame portion 532 of the casing 530.
 高周波基板301は、内部端子71~74と、外部端子81~84とを有している。内部端子71~74はキャビティCVの内部に配置されており、外部端子81~84はキャビティCVの外部に配置されている。なお、図中においては外部端子81~84が模式的にのみ示されているところ、具体的には外部端子81~84は、例えば、突出したリード端子であってよい。 The high-frequency board 301 has internal terminals 71 to 74 and external terminals 81 to 84. The internal terminals 71 to 74 are arranged inside the cavity CV, and the external terminals 81 to 84 are arranged outside the cavity CV. Although the external terminals 81 to 84 are only schematically shown in the drawing, the external terminals 81 to 84 may be, for example, projecting lead terminals.
 図4は、高周波基板301の構成を概略的に示す回路図である。高周波基板301は、少なくとも1つの差動線路を構成しており、本実施の形態においては2つの差動線路CA,CBを構成している。各差動線路に対応して、内部端子71~74および外部端子81~84の1組が設けられている。 FIG. 4 is a circuit diagram schematically showing a configuration of the high-frequency board 301. The high-frequency substrate 301 constitutes at least one differential line, and in this embodiment, constitutes two differential lines CA and CB. One set of internal terminals 71 to 74 and external terminals 81 to 84 is provided corresponding to each differential line.
 内部端子71と外部端子81との間は第1の接地パターン41によって接続されている。同様に、内部端子74と外部端子84との間は、第2の接地パターン42によって接続されている。なお「接地パターン」は、高周波モジュール701が使用される際に、通常、接地電位とされることが想定される導体パターンである。よって高周波基板301において接地パターン間は互いに電気的に短絡されていることが好ましい。 The first ground pattern 41 connects between the internal terminal 71 and the external terminal 81. Similarly, the second ground pattern 42 connects between the internal terminal 74 and the external terminal 84. The “ground pattern” is a conductor pattern that is normally assumed to be at a ground potential when the high-frequency module 701 is used. Therefore, it is preferable that the ground patterns on the high-frequency substrate 301 are electrically short-circuited to each other.
 高周波基板301は、内部端子72と外部端子82との間に、第1の配線路51と、1対の第1パッド61a,61bとを有している。以下において、これら1対の第1パッド61a,61bの総体を、第1のパッド対61とも称する。第1のパッド対61は、第1の配線路51の途中に設けられている。第1のパッド対61は、キャパシタ90を実装するためのものであり、第1の配線路51の中途に設けられている。同様に、高周波基板301は、内部端子73と外部端子83との間に、第2の配線路52と、1対の第2パッド62a,62bとを有している。以下において、これら1対の第2パッド62a,62bの総体を、第2のパッド対62とも称する。第2のパッド対62は、第2の配線路52の途中に設けられている。第2のパッド対62は、キャパシタ90を実装するためのものであり、第2の配線路52の中途に設けられている。 The high-frequency board 301 has the first wiring path 51 and the pair of first pads 61a and 61b between the internal terminal 72 and the external terminal 82. Hereinafter, the whole of the pair of first pads 61a and 61b is also referred to as a first pad pair 61. The first pad pair 61 is provided in the middle of the first wiring path 51. The first pad pair 61 is for mounting the capacitor 90, and is provided in the middle of the first wiring path 51. Similarly, the high-frequency substrate 301 has the second wiring path 52 and a pair of second pads 62a and 62b between the internal terminal 73 and the external terminal 83. Hereinafter, the whole of the pair of second pads 62a and 62b is also referred to as a second pad pair 62. The second pad pair 62 is provided in the middle of the second wiring path 52. The second pad pair 62 is for mounting the capacitor 90 and is provided in the middle of the second wiring path 52.
 第1のパッド対61および第2のパッド対62の具体的な配置については図7を参照して後述するが、第1のパッド対61および第2のパッド対62は、第1の配線路51および第2の配線路52の間でこれらの延在方向に沿って延びる想像線に対して線対称に配置されている。これは以下の理由による。キャパシタ90は、通常、高誘電率を有する部材を有しているため、キャパシタ90内部で信号の位相が変化すると推測される。例えば、第1のパッド対61に実装されているキャパシタ90内部と、それに隣り合う箇所の第2の配線路52とで位相が異なっていて、それらに容量結合が生じると、インピーダンスが設計値からずれる。したがって、第1のパッド対61と第2のパッド対62とが配線路の延在方向において互いにずれて配置されている場合は、インピーダンスが設計値から大きくずれてしまうおそれがある。これに対して、第1のパッド対61および第2のパッド対62が上記線対称性で配置されていれば、すなわち、第1のパッド対61および第2のパッド対62が配線路の延在方向に直交する方向に対向して配置されていれば、インピーダンスが設計値から大きくずれてしまうことが防止される。 The specific arrangement of the first pad pair 61 and the second pad pair 62 will be described later with reference to FIG. 7, but the first pad pair 61 and the second pad pair 62 51 and the second wiring path 52 are arranged symmetrically with respect to an imaginary line extending along the extending direction. This is for the following reason. Since the capacitor 90 usually has a member having a high dielectric constant, it is assumed that the phase of the signal changes inside the capacitor 90. For example, when the phase inside the capacitor 90 mounted on the first pad pair 61 and the phase of the second wiring path 52 adjacent to the capacitor 90 are different from each other and capacitive coupling occurs between them, the impedance is changed from the design value. Shift. Therefore, when the first pad pair 61 and the second pad pair 62 are arranged so as to be shifted from each other in the extending direction of the wiring path, there is a possibility that the impedance is largely shifted from the design value. On the other hand, if the first pad pair 61 and the second pad pair 62 are arranged in line symmetry, that is, if the first pad pair 61 and the second pad pair 62 are extended If they are arranged facing each other in a direction orthogonal to the existing direction, it is possible to prevent the impedance from greatly deviating from the design value.
 第1の配線路51および第2の配線路52は、IC751に電気的に接続される差動線路を構成している。言い換えれば、IC751(図1)の動作時に、第1の配線路51および第2の配線路52には逆位相の信号が伝搬させられる。差動線路にキャパシタ90が設けられることによって、差動線路中における直流成分の流れを阻害することができる。具体的には、IC751中で用いられているバイアス電圧が外部端子82,83に印加されることを、ブロッキングキャパシタとしてのキャパシタ90が防止する。 The first wiring path 51 and the second wiring path 52 constitute a differential line electrically connected to the IC 751. In other words, during the operation of the IC 751 (FIG. 1), signals of opposite phases are propagated through the first wiring path 51 and the second wiring path 52. By providing the capacitor 90 on the differential line, the flow of the DC component in the differential line can be inhibited. Specifically, the capacitor 90 as a blocking capacitor prevents the bias voltage used in the IC 751 from being applied to the external terminals 82 and 83.
 図5は、高周波基板301の回路のうち、内部端子71と外部端子81との間の部分を、図3の視野に平行な視野で示す模式図である。なお、内部端子74と外部端子84との間の部分も同様の構成を有している。図6は、高周波基板301の回路のうち、内部端子72と外部端子82との間の部分を、図3の視野に平行な視野で示す模式図である。なお、内部端子73と外部端子83との間の部分も同様の構成を有している。 FIG. 5 is a schematic diagram showing a portion between the internal terminal 71 and the external terminal 81 in the circuit of the high-frequency board 301 in a view parallel to the view in FIG. The portion between the internal terminal 74 and the external terminal 84 has the same configuration. FIG. 6 is a schematic diagram showing a portion between the internal terminal 72 and the external terminal 82 in the circuit of the high-frequency board 301 in a view parallel to the view of FIG. The portion between the internal terminal 73 and the external terminal 83 has the same configuration.
 高周波基板301中の配線WR(図4に示された回路)は、高周波基板301の表面上に配置された表面配線WRSを有している。さらに、配線WRは、高周波基板301中に配置され、厚み方向に延びる部分を有する内部配線WRBを有していてよい。上述したキャパシタ90は、表面配線WRSへ実装される。言い換えれば、上述した第1のパッド対61および第2のパッド対62は、表面配線WRSに設けられている。以下、表面配線WRSの具体的な構成について詳述する。 (4) The wiring WR (the circuit shown in FIG. 4) in the high-frequency substrate 301 has a surface wiring WRS arranged on the surface of the high-frequency substrate 301. Further, the wiring WR may include an internal wiring WRB which is disposed in the high-frequency substrate 301 and has a portion extending in the thickness direction. The above-described capacitor 90 is mounted on the surface wiring WRS. In other words, the first pad pair 61 and the second pad pair 62 described above are provided on the surface wiring WRS. Hereinafter, a specific configuration of the surface wiring WRS will be described in detail.
 図7は、高周波基板301の表面配線WRS(図5および図6)の構成を概略的に示す部分上面図である。図8は、図7の線VIII-VIIIに沿う概略的な部分断面図である。 FIG. 7 is a partial top view schematically showing the configuration of surface wiring WRS (FIGS. 5 and 6) of high-frequency substrate 301. FIG. 8 is a schematic partial sectional view taken along line VIII-VIII of FIG.
 高周波基板301は、絶縁体からなるセラミック基体10を有している。セラミック基体10上に、第1の接地パターン41と、第1の配線路51と、第2の配線路52と、第2の接地パターン42と、第1パッド61a,61bと、第2パッド62a,62bとが設けられている。第1パッド61aと第1パッド61bとは、一の方向(図7における横方向)に、間隔を介して対向している。この間隔によって第1の配線路51が電気的に分断されている。第2パッド62aと第2パッド62bとは、一の方向(図7における横方向)に、間隔を介して対向している。この間隔によって第2の配線路52が電気的に分断されている。 The high frequency substrate 301 has the ceramic base 10 made of an insulator. On the ceramic base 10, a first ground pattern 41, a first wiring path 51, a second wiring path 52, a second ground pattern 42, first pads 61a, 61b, and a second pad 62a , 62b. The first pad 61a and the first pad 61b face each other in one direction (the horizontal direction in FIG. 7) with an interval therebetween. The first wiring path 51 is electrically separated by this interval. The second pad 62a and the second pad 62b face each other in one direction (the horizontal direction in FIG. 7) with an interval therebetween. The second wiring path 52 is electrically separated by this interval.
 第1の配線路51は、第1の接地パターン41から離れて配置されている。第1の配線路51は、セラミック基体10上を一の方向(図7および図8における横方向)に延びる部分を有している。第2の配線路52は、セラミック基体10上において第1の配線路51によって第1の接地パターン41から隔てられている。第2の配線路52は、第1の配線路51に並んで一の方向(図7および図8における横方向)に延びる部分を有している。第2の接地パターン42は、セラミック基体10上において第2の配線路52によって第1の配線路51から隔てられており、セラミック基体10上において第2の配線路52から離れている。 The first wiring path 51 is arranged apart from the first ground pattern 41. The first wiring path 51 has a portion that extends on the ceramic base 10 in one direction (the horizontal direction in FIGS. 7 and 8). The second wiring path 52 is separated from the first ground pattern 41 by the first wiring path 51 on the ceramic base 10. The second wiring path 52 has a portion extending in one direction (the horizontal direction in FIGS. 7 and 8) alongside the first wiring path 51. The second ground pattern 42 is separated from the first wiring path 51 by a second wiring path 52 on the ceramic base 10 and is separated from the second wiring path 52 on the ceramic base 10.
 なお高周波基板301はさらに第3の接地パターン43を有していてよい。第3の接地パターン43は、セラミック基体10上において、第1の配線路51と第2の配線路52との間に配置されている。第3の接地パターン43は第1の配線路51および第2の配線路52から離れている。図7に示された構成においては、第2の配線路52は第1の配線路51に第3の接地パターン43を介して並んでいる。 The high frequency substrate 301 may further have a third ground pattern 43. The third ground pattern 43 is disposed between the first wiring path 51 and the second wiring path 52 on the ceramic base 10. The third ground pattern 43 is separated from the first wiring path 51 and the second wiring path 52. In the configuration shown in FIG. 7, the second wiring path 52 is arranged on the first wiring path 51 via the third ground pattern 43.
 第1のパッド対61および第2のパッド対62から離れた箇所(図7の視野の外側)において、並走する第1の配線路51および第2の配線路52に曲線部が設けられている場合、この曲線部で両者の信号に位相差が生じる。この位相差が高周波伝送特性へ及ぼす影響を第3の接地パターン43によって抑えることができる。 At a position (outside of the field of view in FIG. 7) apart from the first pad pair 61 and the second pad pair 62, a curved portion is provided in the first wiring path 51 and the second wiring path 52 running in parallel. In this case, there is a phase difference between the two signals at the curved portion. The effect of this phase difference on high-frequency transmission characteristics can be suppressed by the third ground pattern 43.
 図7に示されるように、第3の接地パターン43は第1のパッド対61と第2のパッド対62との間には配置されていない方が望ましい。これにより、本実施の形態による効果が、より大きくなる。 よ う As shown in FIG. 7, it is preferable that the third ground pattern 43 is not arranged between the first pad pair 61 and the second pad pair 62. Thereby, the effect of the present embodiment is further increased.
 第1パッド61a,61bを含む第1のパッド対61は、第1の配線路51の幅よりも大きな幅を有している。第2パッド62a,62bを含む第2のパッド対62は、第2の配線路52の幅よりも大きな幅を有している。ここで幅とは、配線路の延在方向(図7における横方向)に垂直な方向における寸法であり、図7においては縦方向の寸法である。パッド対が配線路の幅よりも大きな幅を有することにより、配線路の幅よりも大きな幅を有するキャパシタ90を容易に実装することができる。例えば、配線路の幅は100μm程度であり、パッド対の幅は300μm程度である。キャパシタ90の実装は、接合材(例えば、はんだ)を用いて行われ得る。 The first pad pair 61 including the first pads 61a and 61b has a width larger than the width of the first wiring path 51. The second pad pair 62 including the second pads 62a and 62b has a width larger than the width of the second wiring path 52. Here, the width is a dimension in a direction perpendicular to the extending direction of the wiring path (horizontal direction in FIG. 7), and is a vertical dimension in FIG. Since the pad pair has a width larger than the width of the wiring path, the capacitor 90 having a width larger than the width of the wiring path can be easily mounted. For example, the width of the wiring path is about 100 μm, and the width of the pad pair is about 300 μm. The mounting of the capacitor 90 can be performed using a bonding material (for example, solder).
 高周波基板301へのキャパシタ実装工程が行われた後においては、高周波基板301は、第1のパッド対61上に実装されたキャパシタ90と、第2のパッド対62上に実装されたキャパシタ90とを有している。逆に、高周波基板301へのキャパシタ実装工程が行われる前においては、高周波基板301は未だキャパシタ90を有していない。 After the step of mounting the capacitors on the high-frequency substrate 301 is performed, the high-frequency substrate 301 includes a capacitor 90 mounted on the first pad pair 61 and a capacitor 90 mounted on the second pad pair 62. have. Conversely, before the step of mounting the capacitor on the high-frequency substrate 301 is performed, the high-frequency substrate 301 does not have the capacitor 90 yet.
 セラミック基体10の表面上には、凹部RC1(第1の凹部)と、凹部RC2(第2の凹部)とが設けられている。凹部RC1は、第1の接地パターン41と、第1のパッド対61との間に配置されている。凹部RC2は、第2の接地パターン42と、第2のパッド対62との間に配置されている。なお本明細書における「凹部」は、その周囲に比して明確に奥まっている領域であり、具体的には、50μm以上の深さを有する領域である。 (4) On the surface of the ceramic base 10, a concave portion RC1 (first concave portion) and a concave portion RC2 (second concave portion) are provided. The concave portion RC1 is arranged between the first ground pattern 41 and the first pad pair 61. The concave portion RC2 is disposed between the second ground pattern 42 and the second pad pair 62. Note that the “recess” in the present specification is a region that is clearly deeper than its periphery, and specifically, a region that has a depth of 50 μm or more.
 高周波基板301は、図8に示されているように、セラミック基体10の内部に、第1の内層接地パターン31と、第2の内層接地パターン32とを有している。第2の内層接地パターン32は、第1の内層接地パターン31に比して深く設けられている。すなわち、第2の内層接地パターン32の深さD2は、第1の内層接地パターン31の深さD1よりも大きい。 (8) As shown in FIG. 8, the high-frequency substrate 301 has a first inner-layer ground pattern 31 and a second inner-layer ground pattern 32 inside the ceramic base 10. The second inner-layer ground pattern 32 is provided deeper than the first inner-layer ground pattern 31. That is, the depth D2 of the second inner-layer ground pattern 32 is greater than the depth D1 of the first inner-layer ground pattern 31.
 第1の内層接地パターン31は、厚み方向(図中、縦方向)において第1の配線路51および第2の配線路52(図8において図示せず)に対向する部分を有しており、かつ、第1のパッド対61および第2のパッド対62(図8において図示せず)の下方に開口部OPを有している。第2の内層接地パターン32は、第1の内層接地パターン31の開口部OPを介して第1のパッド対61および第2のパッド対62(図8において図示せず)に対向する部分を有している。開口部OPを設けることにより、第1のパッド対61および第2のパッド対62の各々と内層接地パターンとの間の距離を、深さD1よりも大きい深さD2に設定することができる。 The first inner-layer ground pattern 31 has a portion facing the first wiring path 51 and the second wiring path 52 (not shown in FIG. 8) in the thickness direction (vertical direction in the figure), Further, an opening OP is provided below the first pad pair 61 and the second pad pair 62 (not shown in FIG. 8). The second inner layer ground pattern 32 has a portion facing the first pad pair 61 and the second pad pair 62 (not shown in FIG. 8) via the opening OP of the first inner layer ground pattern 31. are doing. By providing the opening OP, the distance between each of the first pad pair 61 and the second pad pair 62 and the inner-layer ground pattern can be set to a depth D2 larger than the depth D1.
 第1の接地パターン41および第2の接地パターン42(図7)は、互いに電気的に短絡されている。一般的には、これらは、内部配線WRB(図5)の縦方向部分(スルーホールを通る部分)と横方向部分(内層接地パターン)とを介して互いに電気的に接続されている。ただし変形例として、表面配線WRS(図5)のみが設けられ、内部配線WRBが設けられなくてもよく、その場合、第1の接地パターン41および第2の接地パターン42(図7)は、他の任意の方法によって互いに電気的に短絡されればよい。 The first ground pattern 41 and the second ground pattern 42 (FIG. 7) are electrically short-circuited to each other. Generally, these are electrically connected to each other via a vertical portion (a portion passing through a through hole) and a horizontal portion (an inner layer ground pattern) of internal wiring WRB (FIG. 5). However, as a modification, only the surface wiring WRS (FIG. 5) may be provided, and the internal wiring WRB may not be provided. In this case, the first ground pattern 41 and the second ground pattern 42 (FIG. 7) It may be electrically short-circuited to each other by any other method.
 内層接地パターンは、通常はセラミック基体10の表面に平行なパターンであり、平面レイアウトにおいてセラミック基体10のほぼ全体に配置されたパターン、言い換えればベタパターン、であってよい。この場合、信号を伝送するための、内部端子72と外部端子82とを結ぶ内部配線WRB(図6)を、内層接地パターンで囲むことによって、疑似同軸構造を形成することができる。 The inner-layer ground pattern is usually a pattern parallel to the surface of the ceramic base 10, and may be a pattern arranged over substantially the entire ceramic base 10 in a planar layout, in other words, a solid pattern. In this case, a pseudo coaxial structure can be formed by surrounding the internal wiring WRB (FIG. 6) connecting the internal terminal 72 and the external terminal 82 for transmitting signals with an inner layer ground pattern.
 (比較例)
 次に、高周波基板301(図7および図8)に対する第1~第3の比較例について、以下に説明する。
(Comparative example)
Next, first to third comparative examples with respect to the high-frequency substrate 301 (FIGS. 7 and 8) will be described below.
 図9は、第1の比較例の高周波基板301Aの表面配線WRS(図5および図6参照)の構成を概略的に示す部分上面図である。図10は、図9の線X-Xに沿う概略的な部分断面図である。高周波基板301Aにおいてはセラミック基体10に凹部が設けられていない。これ以外の構成については、高周波基板301(図7および図8)と同じである。 FIG. 9 is a partial top view schematically showing the configuration of the surface wiring WRS (see FIGS. 5 and 6) of the high-frequency substrate 301A of the first comparative example. FIG. 10 is a schematic partial sectional view taken along line XX of FIG. In the high-frequency substrate 301A, no recess is provided in the ceramic base 10. Other configurations are the same as those of the high-frequency substrate 301 (FIGS. 7 and 8).
 図11は、第2の比較例の高周波基板301Bの表面配線WRS(図5および図6参照)の構成を概略的に示す部分上面図である。図12は、図11の線XII-XIIに沿う概略的な部分断面図である。高周波基板301Bにおいてはセラミック基体10は、凹部RC1および凹部RC2(図7および図8)を有しておらず、代わりに凹部RC4(第4の凹部)および凹部RC5(第5の凹部)を有している。凹部RC4は第1パッド61aと第1パッド61bとの間に配置されており、凹部RC5は第2パッド62aと第2パッド62bとの間に配置されている。凹部RC4および凹部RC5は、図11に示されているようにつながっていてよい。変形例として、凹部RC4および凹部RC5は互いに分離されていてもよい。 FIG. 11 is a partial top view schematically showing the configuration of surface wiring WRS (see FIGS. 5 and 6) of high-frequency substrate 301B of the second comparative example. FIG. 12 is a schematic partial sectional view taken along line XII-XII in FIG. In the high-frequency substrate 301B, the ceramic base 10 does not have the recesses RC1 and RC2 (FIGS. 7 and 8), but instead has the recesses RC4 (fourth recess) and the recess RC5 (fifth recess). are doing. The recess RC4 is arranged between the first pad 61a and the first pad 61b, and the recess RC5 is arranged between the second pad 62a and the second pad 62b. The recess RC4 and the recess RC5 may be connected as shown in FIG. As a variant, the recesses RC4 and RC5 may be separated from each other.
 図13は、第3の比較例の高周波基板301Cの表面配線WRS(図5および図6参照)の構成を概略的に示す部分上面図である。図14は、図13の線XIV-XIVに沿う概略的な部分断面図である。高周波基板301Cにおいてはセラミック基体10は、凹部RC1および凹部RC2(図7および図8)を有しておらず、代わりに凹部RC3(第3の凹部)を有している。凹部RC3は、第1のパッド対61と、第2のパッド対62との間に配置されている。 FIG. 13 is a partial top view schematically showing the configuration of surface wiring WRS (see FIGS. 5 and 6) of high-frequency substrate 301C of the third comparative example. FIG. 14 is a schematic partial cross-sectional view taken along line XIV-XIV in FIG. In the high-frequency substrate 301C, the ceramic base 10 does not have the concave portions RC1 and RC2 (FIGS. 7 and 8), but has a concave portion RC3 (third concave portion) instead. The recess RC3 is arranged between the first pad pair 61 and the second pad pair 62.
 次に、図15~図19を参照して、本実施の形態の実施例の高周波基板301と、第1~第3の比較例の高周波基板301A~301Cとの間での、高周波特性のシミュレーション結果の差異について説明する。なお図17~図19においては図を見やすくするために0~25GHzの範囲の図示が省略されているが、この範囲でのシミュレーションも行われており、上記基板間での差異がほとんど見られないことが確認されている。 Next, with reference to FIG. 15 to FIG. 19, simulation of high frequency characteristics between high frequency substrate 301 of the example of the present embodiment and high frequency substrates 301A to 301C of the first to third comparative examples. The difference between the results will be described. 17 to 19, the range of 0 to 25 GHz is omitted for the sake of clarity, but a simulation is also performed in this range, and there is almost no difference between the substrates. That has been confirmed.
 シミュレーションは、キャパシタ90の代用として金属ブロックが実装されたモデルで行われている。また、シミュレーション結果の比較を容易とするために、高周波基板301,301B,301Cにおいてセラミック基体10の表面上に形成される凹部の大きさは、詳しくは図15を参照して後述するように、凹部によって行われる特性インピーダンスの平均的な補正がおおよそ同程度になるように選択されている。 The simulation is performed with a model in which a metal block is mounted as a substitute for the capacitor 90. Further, in order to facilitate comparison of the simulation results, the size of the concave portion formed on the surface of the ceramic substrate 10 in the high- frequency substrates 301, 301B, and 301C is described in detail with reference to FIG. The average correction of the characteristic impedance performed by the recess is selected to be approximately the same.
 具体的には、本シミュレーションは、以下に示される条件で実施されている。なお、配線路の延在方向(例えば図7では横方向)の寸法を長さ、配線路の幅方向(図7では縦方向)の寸法を幅と表記する。高周波基板301および301A~301Cのいずれに関しても、第1の内層接地パターン31および第2の内層接地パターン32の構成が同一条件で設定されている。なおこれらの内層接地パターンはほぼベタパターンとされている。 Specifically, the simulation is performed under the following conditions. The dimension in the extending direction of the wiring path (for example, the horizontal direction in FIG. 7) is referred to as length, and the dimension in the width direction of the wiring path (vertical direction in FIG. 7) is referred to as width. Regarding any of the high- frequency boards 301 and 301A to 301C, the configurations of the first inner-layer ground pattern 31 and the second inner-layer ground pattern 32 are set under the same conditions. These inner-layer ground patterns are almost solid patterns.
 第1の配線路51(第2の配線路52)の幅:0.1mm
 距離D1(図8):0.15mm
 距離D2(図8):0.5mm
 各パッド(矩形)の幅:0.35mm
 各パッド(矩形)の長さ:0.25mm
 パッド対の各々を構成するパッド同士の最短距離:0.3mm
 第1の配線路51および第2の配線路52のそれぞれの中心線の間の距離:0.8mm
 凹部RC1(RC2)(図7)の寸法:幅0.25mm、長さ0.80mm、深さ0.4mm(矩形)
 凹部RC3(図13)の寸法:幅0.35mm、長さ0.80mm、深さ0.2mm(矩形)
 凹部RC4およびRC5(図11)の総体の寸法:幅1.35mm、長さ0.20mm、深さ0.25mm(矩形)
 セラミック基体:アルミナ製(比誘電率8.7)
 配線路および接地パターン:タングステン製(ニッケルおよび金の被膜あり、金が最表層)
 内層接地パターン:タングステン製
 シミュレーションに用いられたソフトウエア:HFSS ver.15 (Ansys社製)
Width of first wiring path 51 (second wiring path 52): 0.1 mm
Distance D1 (FIG. 8): 0.15 mm
Distance D2 (FIG. 8): 0.5 mm
Each pad (rectangular) width: 0.35mm
Length of each pad (rectangle): 0.25mm
Shortest distance between pads constituting each pad pair: 0.3 mm
Distance between respective center lines of first wiring path 51 and second wiring path 52: 0.8 mm
Dimensions of recesses RC1 (RC2) (FIG. 7): width 0.25 mm, length 0.80 mm, depth 0.4 mm (rectangle)
Dimensions of recess RC3 (FIG. 13): width 0.35 mm, length 0.80 mm, depth 0.2 mm (rectangle)
Overall dimensions of recesses RC4 and RC5 (FIG. 11): width 1.35 mm, length 0.20 mm, depth 0.25 mm (rectangular)
Ceramic substrate: made of alumina (dielectric constant: 8.7)
Wiring path and grounding pattern: Tungsten (with nickel and gold coating, gold on outermost layer)
Inner layer ground pattern: made of tungsten Software used for simulation: HFSS ver. 15 (manufactured by Ansys)
 図15は、特性インピーダンスのシミュレーション結果を、周波数67GHzにおける時間領域反射(TDR:Time Domain Reflectometry)として示すグラフ図である。図中、横軸で表わされた時間軸は空間軸とみなすことができ、1対の矢印は、1対の第1パッド61a,61bの位置におおよそ対応している。セラミック基体10に凹部が形成されていない高周波基板301Aにおいては、矢印間での特性インピーダンスの平均値が、大きく低下している。これは第1のパッド対61の存在による容量成分の増大に起因している。一方、高周波基板301,301B,301Cは、セラミック基体10に凹部が形成されていることによって、矢印間での特性インピーダンスの平均値の低下が補正されている。すなわち、特性インピーダンスの平均値が設計値100Ωに近づいている。前述したように、高周波基板301,301B,301Cの凹部の大きさは、この補正の効果が同程度となるように選択されている。高周波基板301,301B,301C間で特性インピーダンスを比較すると、高周波基板301Bにおいては、矢印間での特性インピーダンスの局所的な急変が顕著である。 FIG. 15 is a graph showing the simulation result of the characteristic impedance as time domain reflection (TDR: Time Domain Reflectometry) at a frequency of 67 GHz. In the drawing, the time axis represented by the horizontal axis can be regarded as a space axis, and a pair of arrows roughly corresponds to the positions of the pair of first pads 61a and 61b. In the high-frequency substrate 301A in which no recess is formed in the ceramic base 10, the average value of the characteristic impedance between the arrows is greatly reduced. This is due to an increase in the capacitance component due to the presence of the first pad pair 61. On the other hand, in the high- frequency substrates 301, 301B, and 301C, since the concave portions are formed in the ceramic base 10, a decrease in the average value of the characteristic impedance between the arrows is corrected. That is, the average value of the characteristic impedance approaches the designed value of 100Ω. As described above, the sizes of the concave portions of the high- frequency boards 301, 301B, and 301C are selected so that the effect of this correction is substantially the same. Comparing the characteristic impedances of the high- frequency boards 301, 301B, and 301C, a local sudden change in the characteristic impedance between the arrows is remarkable in the high-frequency boards 301B.
 図16は、反射特性のシミュレーション結果を示すグラフ図である。高周波基板301Bは、40GHzから60GHzまでの広い範囲に渡って、他の配線基板に比して、大きな反射を有している。この理由は、上述した特性インピーダンスの急変に起因していると考えられる。 FIG. 16 is a graph showing simulation results of reflection characteristics. The high-frequency board 301B has a large reflection over a wide range from 40 GHz to 60 GHz as compared with other wiring boards. This reason is considered to be due to the sudden change in the characteristic impedance described above.
 図17は、クロストーク特性のシミュレーション結果を示すグラフ図である。具体的には、図4を参照して、差動線路CAから差動線路CBへの信号エネルギーの漏れの大きさがシミュレーションされている。クロストークが大きいということは、この望ましくない漏れが大きいことを意味する。高周波基板301Cは、40GHz程度以上の帯域のうちの大部分において、最も劣ったクロストーク特性を有している。一方、高周波基板301は、40GHz以上の帯域のうちの大部分において、最も優れたクロストーク特性を有している。 FIG. 17 is a graph showing simulation results of crosstalk characteristics. Specifically, referring to FIG. 4, the magnitude of signal energy leakage from differential line CA to differential line CB is simulated. Large crosstalk means that this undesirable leakage is large. The high-frequency substrate 301C has the poorest crosstalk characteristics in most of the band of about 40 GHz or higher. On the other hand, the high frequency substrate 301 has the most excellent crosstalk characteristics in most of the band of 40 GHz or more.
 図18は、エネルギー損失の割合のシミュレーション結果を示すグラフ図である。ここでいうエネルギー損失とは、回路へ入力した信号エネルギーから、反射による損失(図16参照)と、回路を通過した信号エネルギー(図19参照)とを除くことによって得られる差分である。このようなエネルギー損失は、一般的には、誘電損、導体損、放射損などによるものと考えられる。55GHz未満においては、エネルギー損失特性に大きな差異は見られない。一方、55GHz以上においては高周波基板301が最も優れた特性を有しており、60GHz以上においてその効果はより顕著である。これは、表面波へのモード変換による放射損失(詳しくは後述する)、およびクロストークによる損失(図17)を抑えることができているためと思われる。なお図18の結果から、高周波基板301は、多くの用途において、少なくとも70GHz程度までは使用することができると考えられる。よって高周波基板301は、優れたエネルギー損失特性を、少なくとも55GHz以上70GHz以下の高周波領域において有していると考えられる。なおこのような高周波領域は、特に、光モジュール(光パッケージ)において用いられることが想定され得る。 FIG. 18 is a graph showing a simulation result of an energy loss ratio. The energy loss referred to here is a difference obtained by removing a loss due to reflection (see FIG. 16) and a signal energy passing through the circuit (see FIG. 19) from the signal energy input to the circuit. Such energy loss is generally considered to be due to dielectric loss, conductor loss, radiation loss, and the like. Below 55 GHz, there is no significant difference in energy loss characteristics. On the other hand, at 55 GHz or higher, the high-frequency substrate 301 has the most excellent characteristics, and at 60 GHz or higher, the effect is more remarkable. This is presumably because radiation loss due to mode conversion into a surface wave (described later in detail) and loss due to crosstalk (FIG. 17) can be suppressed. From the results in FIG. 18, it is considered that the high-frequency substrate 301 can be used at least up to about 70 GHz in many applications. Therefore, it is considered that the high-frequency substrate 301 has excellent energy loss characteristics at least in a high-frequency region of 55 GHz or more and 70 GHz or less. In addition, it can be assumed that such a high frequency region is used particularly in an optical module (optical package).
 図19は、通過特性のシミュレーション結果を示すグラフ図である。高周波基板301Bは、40GHzから60GHzまでの広い範囲に渡って、凹部を有しない高周波基板301Aに比して、劣る通過特性を有している。この理由は、前述した特性インピーダンスの局所的な急変に起因していると考えられる。高周波基板301Cは、凹部を有しない高周波基板301Aに類似した通過特性を有している。よって、高周波基板301Cの凹部RC3は、通過特性の観点では、信号の通過帯域を広げる効果を有していないことがわかる。高周波基板301は、高い周波数、特に60GHz以上の周波数、において、他の配線基板に比して、優れた通過特性を有している。これはエネルギー損失が小さいこと(図18)に対応する結果である。 FIG. 19 is a graph showing a simulation result of the passage characteristic. The high frequency substrate 301B has inferior transmission characteristics over a wide range from 40 GHz to 60 GHz as compared with the high frequency substrate 301A having no concave portion. This reason is considered to be due to the above-mentioned sudden change in the characteristic impedance. The high-frequency substrate 301C has a transmission characteristic similar to that of the high-frequency substrate 301A having no concave portion. Therefore, it can be seen that the concave portion RC3 of the high-frequency substrate 301C does not have the effect of widening the signal pass band from the viewpoint of the pass characteristics. The high-frequency substrate 301 has excellent transmission characteristics at a high frequency, particularly at a frequency of 60 GHz or higher, as compared with other wiring substrates. This is a result corresponding to the small energy loss (FIG. 18).
 (効果のまとめ)
 差動線路CA,CB(図4)を用いての信号伝送において、特に図18に示されたシミュレーション結果からわかるように、凹部RC1,RC2が設けられた高周波基板301によって、高周波領域でのエネルギー損失を顕著に抑制することができる。この結果、良好な通過特性(図19参照)を得ることができる。
(Summary of effects)
In the signal transmission using the differential lines CA and CB (FIG. 4), as can be seen from the simulation results particularly shown in FIG. 18, the energy in the high frequency region is provided by the high frequency substrate 301 provided with the concave portions RC1 and RC2. Loss can be significantly suppressed. As a result, good pass characteristics (see FIG. 19) can be obtained.
 なお、図10を参照して、凹部が設けられていない高周波基板301Aにおいても、第1の内層接地パターン31および第2の内層接地パターン32を組み合わせた構成によって、第1のパッド対61および第2のパッド対62が存在することに起因しての特性インピーダンスの局所的低下を、ある程度抑制することができる。仮にこの構成の最適化のみに依存して特性インピーダンスの局所的低下、すなわち設計値100Ωからのずれ、を十分に抑制しようとすると、配線路の幅に比してのパッドの幅の増大に対応する分だけ、深さD2を相応に大きくしなければならない。言い換えれば、第2の内層接地パターン32と、第1のパッド対61および第2のパッド対62(図8において図示せず)の各々との間の距離を、相応に大きくしなければならない。その場合、電磁気学的な現象として、第1パッド61aと第1パッド61bとの間(および、第2パッド62aと第2パッド62bとの間)を正常に伝搬する信号に対応する横電磁界波(TEM波:Transverse Electromagnetic Wave)が、表面波に変換されやすくなる。この変換が増大する結果、表面波の放射による伝搬損失が増大してしまう。本実施の形態によれば、凹部RC1および凹部RC2が、特性インピーダンスの局所的低下を抑制する効果を有する(図15参照)。これにより、深さD2を過度に大きくする必要がない。よって、高周波領域での表面波の放射によるエネルギー損失を顕著に抑制することができる。 Referring to FIG. 10, even in high-frequency substrate 301 </ b> A in which no concave portion is provided, first pad pair 61 and second pad pair 61 are formed by combining first inner layer ground pattern 31 and second inner layer ground pattern 32. The local decrease in the characteristic impedance due to the presence of the two pad pairs 62 can be suppressed to some extent. If the local decrease in the characteristic impedance, that is, the deviation from the design value of 100Ω, is sufficiently suppressed only depending on the optimization of this configuration, the width of the pad becomes larger than the width of the wiring path. The depth D2 must be increased accordingly. In other words, the distance between the second inner layer ground pattern 32 and each of the first pad pair 61 and the second pad pair 62 (not shown in FIG. 8) must be correspondingly large. In this case, as an electromagnetic phenomenon, a transverse electromagnetic field corresponding to a signal that normally propagates between the first pad 61a and the first pad 61b (and between the second pad 62a and the second pad 62b). A wave (TEM wave: Transverse @ Electromagnetic @ Wave) is easily converted to a surface wave. As a result of the increase in the conversion, the propagation loss due to the emission of the surface wave increases. According to the present embodiment, concave portions RC1 and RC2 have an effect of suppressing a local decrease in characteristic impedance (see FIG. 15). Thus, it is not necessary to increase the depth D2 excessively. Therefore, the energy loss due to the emission of the surface wave in the high frequency region can be significantly suppressed.
 差動線路では、第1の配線路を伝送する信号と、第2の配線路を伝送する信号との間の位相差が所定の位相差(逆位相)からずれると、インピーダンスが設計値からずれるおそれがある。よって、配線基板の表面配線の構成はできるだけ対称であることが好ましい。例えば図7では、凹部RC1(第1の凹部)および凹部RC2(第2の凹部)と、第1パッド61aおよび第2パッド62aと、第1パッド61bおよび第2パッド62bと、第1の配線路51および第2の配線路52と、第1の接地パターン41および第2の接地パターン42と、はそれぞれ同じ寸法(凹部の深さ、および配線路等の厚みも含む)を有することが好ましく、かつ、これらは第3の接地パターン43の中心線(もし図7に付されるとすれば、水平方向に延びる中心線)に対して線対称に配置されることが好ましい。第1のパッド対61および第2のパッド対62に実装されるキャパシタ90も、上述した対称性を有することが好ましい。これは、他の比較例および変形例における差動線路についても同様である。 In the differential line, when the phase difference between the signal transmitted through the first wiring path and the signal transmitted through the second wiring path deviates from a predetermined phase difference (opposite phase), the impedance deviates from a design value. There is a risk. Therefore, it is preferable that the configuration of the surface wiring of the wiring board be as symmetrical as possible. For example, in FIG. 7, the concave portion RC1 (first concave portion) and the concave portion RC2 (second concave portion), the first pad 61a and the second pad 62a, the first pad 61b and the second pad 62b, and the first wiring The path 51 and the second wiring path 52 and the first ground pattern 41 and the second ground pattern 42 preferably have the same dimensions (including the depth of the concave portion and the thickness of the wiring path and the like). These are preferably arranged symmetrically with respect to the center line of the third ground pattern 43 (if shown in FIG. 7, the center line extending in the horizontal direction). The capacitors 90 mounted on the first pad pair 61 and the second pad pair 62 also preferably have the above-mentioned symmetry. This is the same for the differential lines in other comparative examples and modified examples.
 (第1の変形例)
 セラミック基体10は、凹部RC1,RC2(図7)に加えて、凹部RC3(図13)を有していてよい。設計上、凹部RC1,RC2の深さには上限がある。具体的には、凹部RC1,RC2の深さは、深さD2(図8)よりも小さくなければならない。これに起因して、第1のパッド対61および第2のパッド対62の近傍での特性インピーダンスの局所的低下を十分には抑制できない場合がある。そのような場合に、凹部RC3をも設けることによって、特性インピーダンスの局所的低下を十分に抑制することができる。これにより、高周波領域でのエネルギー損失を、より抑制することができる。凹部RC3の長さは、第1のパッド対61の長さLP(図20)以上であるのが好ましい。また、凹部RC3の深さは、凹部RC1,RC2の各々の深さよりも小さいことが好ましい。これにより、凹部RC3を設けることで生じる高周波領域でのクロストークによるエネルギー損失を抑えつつ、特性インピーダンスの局所的低下を抑制することができる。
(First Modification)
The ceramic base 10 may have a recess RC3 (FIG. 13) in addition to the recesses RC1 and RC2 (FIG. 7). Due to the design, there is an upper limit to the depth of the concave portions RC1 and RC2. Specifically, the depths of the concave portions RC1 and RC2 must be smaller than the depth D2 (FIG. 8). Due to this, there is a case where the local decrease in the characteristic impedance in the vicinity of the first pad pair 61 and the second pad pair 62 cannot be sufficiently suppressed. In such a case, by providing the concave portion RC3, it is possible to sufficiently suppress the local decrease in the characteristic impedance. Thereby, the energy loss in the high frequency region can be further suppressed. The length of the recess RC3 is preferably equal to or longer than the length LP of the first pad pair 61 (FIG. 20). Further, it is preferable that the depth of the recess RC3 is smaller than the depth of each of the recesses RC1 and RC2. Thereby, it is possible to suppress the local loss of the characteristic impedance while suppressing the energy loss due to the crosstalk in the high frequency region caused by providing the concave portion RC3.
 (第2の変形例)
 セラミック基体10は、凹部RC1および凹部RC2(図7)に加えて、凹部RC4,RC5(図11)を有していてよい。
(Second Modification)
The ceramic base 10 may have concave portions RC4 and RC5 (FIG. 11) in addition to the concave portions RC1 and RC2 (FIG. 7).
 凹部RC4,RC5が設けられることによって、第1パッド61aと第1パッド61bとの間(および、第2パッド62aと第2パッド62bとの間)において、キャパシタ90の実装時に接合材(典型的には、はんだ)が、意図せず第1パッド61aと第1パッド61bとの間(および、第2パッド62aと第2パッド62bとの間)に跨って形成されてしまうことが避けられる。これにより、第1パッド61aと第1パッド61bとの間(および、第2パッド62aと第2パッド62bとの間)での電気的短絡を防止することができる。第1の配線路51(および第2の配線路52)の幅方向において、凹部RC4(およびRC5)の幅は第1パッド61a(および第2パッド62a)の幅以上であることが好ましい。これにより電気的短絡を確実に防止することができる。 By providing the concave portions RC4 and RC5, a bonding material (typical) is provided between the first pad 61a and the first pad 61b (and between the second pad 62a and the second pad 62b) when the capacitor 90 is mounted. Is unintentionally formed between the first pad 61a and the first pad 61b (and between the second pad 62a and the second pad 62b). Thus, an electrical short circuit between the first pad 61a and the first pad 61b (and between the second pad 62a and the second pad 62b) can be prevented. In the width direction of the first wiring path 51 (and the second wiring path 52), the width of the concave portion RC4 (and RC5) is preferably equal to or larger than the width of the first pad 61a (and the second pad 62a). As a result, an electrical short circuit can be reliably prevented.
 凹部RC4,RC5の各々の深さは、凹部RC1,RC2の各々の深さよりも小さいことが好ましく、第1パッド61aと第1パッド61bとの間(および第2パッド62aと第2パッド62bとの間)での電気的短絡を防止できる程度で十分である。これにより、凹部RC4,RC5に起因しての特性インピーダンスの局所的な急変を不必要に招くことが避けられる。 The depth of each of the recesses RC4 and RC5 is preferably smaller than the depth of each of the recesses RC1 and RC2, and is between the first pad 61a and the first pad 61b (and between the second pad 62a and the second pad 62b). ) Is sufficient to prevent an electrical short circuit. Thus, unnecessary abrupt changes in the characteristic impedance caused by the concave portions RC4 and RC5 can be avoided.
 なお、第1および第2の変形例が組み合わされてもよい。すなわち、セラミック基体10は、凹部RC1および凹部RC2(図7)に加えて、凹部RC3~RC5を有していてよい。 Note that the first and second modifications may be combined. That is, the ceramic base 10 may have the concave portions RC3 to RC5 in addition to the concave portions RC1 and RC2 (FIG. 7).
 (第3の変形例)
 図20は、第3の変形例の高周波基板301v(配線基板)を示す部分上面図である。高周波基板301vにおいては、凹部RC1の長さLRは、第1のパッド対61の長さLP以上である。同様に、凹部RC2の長さは第2のパッド対62の長さ以上である。長さLRが大き過ぎると第1の接地パターン41を設ける領域が減ってしまうため、実際の設計では第1のパッド対61の長さLPの1.5倍程度までが長さLRの上限となる。凹部RC2の長さについても同様である。
(Third Modification)
FIG. 20 is a partial top view showing a high-frequency board 301v (wiring board) of the third modification. In the high-frequency substrate 301v, the length LR of the recess RC1 is longer than the length LP of the first pad pair 61. Similarly, the length of the recess RC2 is longer than the length of the second pad pair 62. If the length LR is too large, the area where the first ground pattern 41 is provided is reduced. Therefore, in an actual design, the upper limit of the length LR is up to about 1.5 times the length LP of the first pad pair 61. Become. The same applies to the length of the recess RC2.
 なお第1のパッド対61の長さLPは、第1パッド61aと第1パッド61bとが互いに対向する方向(図20における横方向)における第1のパッド対61の総体の寸法である。また凹部RC1の長さLRは、上記方向における凹部RC1の寸法である。第2のパッド対62の長さ、および凹部RC2の長さについても同様である。 The length LP of the first pad pair 61 is the total dimension of the first pad pair 61 in the direction in which the first pad 61a and the first pad 61b face each other (the horizontal direction in FIG. 20). The length LR of the recess RC1 is the dimension of the recess RC1 in the above direction. The same applies to the length of the second pad pair 62 and the length of the recess RC2.
 本変形例によれば、第1のパッド対61および第2のパッド対62の近傍の十分な範囲に、凹部RC1および凹部RC2を確実に配置することができる。これにより、前述した、凹部RC1および凹部RC2による効果を、より確実に得ることができる。 According to the present modification, the concave portions RC1 and RC2 can be reliably arranged in a sufficient range near the first pad pair 61 and the second pad pair 62. This makes it possible to more reliably obtain the effects of the concave portions RC1 and RC2 described above.
 (第4の変形例)
 図21は、第4の変形例の高周波基板301w(配線基板)を示す部分上面図である。高周波基板301wにおいては、第1のパッド対61は、最小長さLP1および最大長さLP2によって特徴づけられる形状を有している。最小長さLP1の範囲内では、第1のパッド対61は実質的に一定の幅を有している。この範囲の外側において、第1のパッド対61はテーパ形状を有している。
(Fourth modification)
FIG. 21 is a partial top view illustrating a high-frequency board 301w (wiring board) according to a fourth modification. In the high-frequency substrate 301w, the first pad pair 61 has a shape characterized by a minimum length LP1 and a maximum length LP2. Within the minimum length LP1, the first pad pair 61 has a substantially constant width. Outside this range, the first pad pair 61 has a tapered shape.
 本変形例においては、最小長さLP1を第1のパッド対の長さと見なす。上記第3の変形例と同様に本変形例においても、凹部RC1の長さLRは、第1のパッド対61の長さ、すなわち最小長さLP1、以上である。また長さLRが大き過ぎると第1の接地パターン41を設ける領域が減ってしまうため、長さLRは、第1のパッド対61の最大長さLP2以下とされていてよい。なお凹部RC2の長さも、凹部RC1の長さLRと同様に規定される。 に お い て In this modification, the minimum length LP1 is regarded as the length of the first pad pair. In this modification as well as the third modification, the length LR of the concave portion RC1 is equal to or longer than the length of the first pad pair 61, that is, the minimum length LP1. If the length LR is too large, the area in which the first ground pattern 41 is provided is reduced. Therefore, the length LR may be set to be equal to or less than the maximum length LP2 of the first pad pair 61. The length of the recess RC2 is also defined in the same manner as the length LR of the recess RC1.
 本変形例によれば、第1のパッド対61および第2のパッド対62の近傍の十分な範囲に、凹部RC1および凹部RC2を確実に配置することができる。これにより、前述した、凹部RC1および凹部RC2による効果を、より確実に得ることができる。 According to the present modification, the concave portions RC1 and RC2 can be reliably arranged in a sufficient range near the first pad pair 61 and the second pad pair 62. This makes it possible to more reliably obtain the effects of the concave portions RC1 and RC2 described above.
 <実施の形態2>
 図22は、本実施の形態2における高周波パッケージ502の構成を概略的に示す上面図である。高周波パッケージ502は、高周波基板301(図1:実施の形態1)に代わって、高周波基板302(配線基板)を有している。高周波基板302は、高周波基板301と異なり、その全体がケーシング530のキャビティCV内に実装されている。高周波基板302は、内部回路750(図1)の一部または全部を実装するための実装領域として用いられてもよい。その場合、実装領域550の一部または全部が省略され得る。
<Embodiment 2>
FIG. 22 is a top view schematically showing a configuration of high-frequency package 502 according to the second embodiment. The high-frequency package 502 has a high-frequency board 302 (wiring board) instead of the high-frequency board 301 (FIG. 1: Embodiment 1). The high-frequency board 302 is different from the high-frequency board 301 and is entirely mounted in the cavity CV of the casing 530. The high-frequency board 302 may be used as a mounting area for mounting part or all of the internal circuit 750 (FIG. 1). In that case, part or all of the mounting area 550 may be omitted.
 本実施の形態においては、ケーシング530は、キャビティCVの外側に配置された外部端子91~94を有している。外部端子91~94のそれぞれは、高周波基板302の外部端子81~84に電気的に接続されている。外部端子91~94の具体的な構成は任意であり、例えば、枠部532を貫く金属ピンなどが用いられる。 に お い て In the present embodiment, casing 530 has external terminals 91 to 94 arranged outside cavity CV. Each of the external terminals 91 to 94 is electrically connected to the external terminals 81 to 84 of the high-frequency board 302. The specific configuration of the external terminals 91 to 94 is arbitrary, and for example, a metal pin penetrating the frame portion 532 is used.
 なお、上記以外の構成については、上述した実施の形態1の構成とほぼ同じであるため、同一または対応する要素について同一の符号を付し、その説明を繰り返さない。 Since the configuration other than the above is substantially the same as the configuration of the above-described first embodiment, the same or corresponding elements are denoted by the same reference characters, and description thereof will not be repeated.
 本実施の形態の高周波基板302は、高周波基板301(図1:実施の形態1)と異なり、パッケージの外部端子を構成していない。この点を除き、実施の形態1とほぼ同様の効果が本実施の形態によっても得られる。 高周波 Unlike the high-frequency board 301 (FIG. 1: Embodiment 1), the high-frequency board 302 of the present embodiment does not constitute external terminals of a package. Except for this point, almost the same effects as in the first embodiment can be obtained in the present embodiment.
 この発明は詳細に説明されたが、上記した説明は、すべての局面において、例示であって、この発明がそれに限定されるものではない。例示されていない無数の変形例が、この発明の範囲から外れることなく想定され得るものと解される。 Although the present invention has been described in detail, the above description is illustrative in all aspects, and the present invention is not limited thereto. It is understood that innumerable modifications that are not illustrated can be assumed without departing from the scope of the present invention.
 CA,CB 差動線路
 RC1~RC5 第1~第5の凹部
 CV キャビティ
 TH 貫通孔
 OP 開口部
 WR 配線
 WRB 内部配線
 WRS 表面配線
 10 セラミック基体
 31,32 第1および第2の内層接地パターン
 41~43 第1~第3の接地パターン
 51,52 第1および第2の配線路
 61 第1のパッド対
 61a,61b 第1パッド
 62 第2のパッド対
 62a,62b 第2パッド
 71~74 内部端子
 81~84 外部端子
 90 キャパシタ
 301,301A~301C,301v,301w,302 高周波基板(配線基板)
 501,502 高周波パッケージ
 530 ケーシング
 531 底部
 532 枠部
 535 開口部
 550 実装領域
 701 高周波モジュール
 730 蓋体
 750 内部回路
 751 IC(集積回路)
 752 光学部品
CA, CB Differential line RC1 to RC5 First to fifth concave portions CV cavity TH Through hole OP Opening WR Wiring WRB Internal wiring WRS Surface wiring 10 Ceramic base 31, 32 First and second inner layer ground patterns 41 to 43 First to third ground patterns 51, 52 First and second wiring paths 61 First pad pair 61a, 61b First pad 62 Second pad pair 62a, 62b Second pad 71-74 Internal terminal 81- 84 external terminal 90 capacitor 301, 301A to 301C, 301v, 301w, 302 high frequency substrate (wiring substrate)
501, 502 High-frequency package 530 Casing 531 Bottom 532 Frame 535 Opening 550 Mounting area 701 High-frequency module 730 Cover 750 Internal circuit 751 IC (integrated circuit)
752 Optical parts

Claims (12)

  1.  セラミック基体と、
     前記セラミック基体上に設けられた第1の接地パターンと、
     前記セラミック基体上に設けられ、前記第1の接地パターンから離れて配置され、前記セラミック基体上を一の方向に延びる部分を有する第1の配線路と、
     前記セラミック基体上に設けられ、前記セラミック基体上において前記第1の配線路によって前記第1の接地パターンから隔てられ、前記第1の配線路に並んで前記一の方向に延びる部分を有する第2の配線路と、
     前記セラミック基体上に設けられ、前記セラミック基体上において前記第2の配線路によって前記第1の配線路から隔てられ、前記セラミック基体上において前記第2の配線路から離れた第2の接地パターンと、
     前記第1の配線路の中途に設けられ、前記第1の配線路の幅よりも大きな幅を有する、キャパシタを実装するための第1のパッド対と、
     前記第2の配線路の中途に設けられ、前記第2の配線路の幅よりも大きな幅を有する、キャパシタを実装するための第2のパッド対と、
    を備え、
     前記第1のパッド対は、前記一の方向に対向する1対の第1パッドを含み、前記第2のパッド対は、前記一の方向に対向する1対の第2パッドを含み、前記第1のパッド対および前記第2のパッド対は前記一の方向に直交する方向に対向しており、
     前記セラミック基体は、前記第1の接地パターンと前記第1のパッド対との間に設けられた第1の凹部と、前記第2の接地パターンと前記第2のパッド対との間に設けられた第2の凹部と、を有している、
    配線基板。
    A ceramic substrate;
    A first ground pattern provided on the ceramic base;
    A first wiring path which is provided on the ceramic base, is disposed apart from the first ground pattern, and has a portion extending in one direction on the ceramic base;
    A second portion provided on the ceramic base, having a portion on the ceramic base separated from the first ground pattern by the first wiring path and extending in the one direction alongside the first wiring path; Wiring route,
    A second ground pattern provided on the ceramic base, separated from the first wiring path by the second wiring path on the ceramic base, and separated from the second wiring path on the ceramic base; ,
    A first pad pair for mounting a capacitor, provided in the middle of the first wiring path and having a width larger than the width of the first wiring path;
    A second pad pair for mounting a capacitor, provided in the middle of the second wiring path and having a width larger than the width of the second wiring path;
    With
    The first pad pair includes a pair of first pads facing in the one direction, the second pad pair includes a pair of second pads facing in the one direction, The one pad pair and the second pad pair are opposed in a direction orthogonal to the one direction,
    The ceramic base is provided between a first concave portion provided between the first ground pattern and the first pad pair, and is provided between the second ground pattern and the second pad pair. A second concave portion,
    Wiring board.
  2.  前記セラミック基体の内部に設けられ、厚み方向において前記第1の配線路および前記第2の配線路に対向する部分を有し、前記第1のパッド対および前記第2のパッド対の下方に開口部を有する第1の内層接地パターンと、
     前記セラミック基体の内部に前記第1の内層接地パターンに比して深く設けられ、前記第1の内層接地パターンの前記開口部を介して前記第1のパッド対および前記第2のパッド対に対向する部分を有する第2の内層接地パターンと、
    をさらに備える、請求項1に記載の配線基板。
    A portion provided inside the ceramic base, facing the first wiring path and the second wiring path in a thickness direction, and having an opening below the first pad pair and the second pad pair; A first inner-layer ground pattern having a portion;
    The first inner layer ground pattern is provided deeper inside the ceramic base than the first inner layer ground pattern, and is opposed to the first pad pair and the second pad pair via the opening of the first inner layer ground pattern. A second inner layer ground pattern having a portion
    The wiring board according to claim 1, further comprising:
  3.  前記第1のパッド対上に実装されたキャパシタと、前記第2のパッド対上に実装されたキャパシタと、をさらに備える、請求項1または2に記載の配線基板。 3. The wiring board according to claim 1, further comprising: a capacitor mounted on the first pad pair; and a capacitor mounted on the second pad pair. 4.
  4.  前記第1の凹部の長さは前記第1のパッド対の長さ以上であり、前記第2の凹部の長さは前記第2のパッド対の長さ以上である、請求項1から3のいずれか1項に記載の配線基板。 The length of the said 1st recessed part is more than the length of the said 1st pad pair, The length of the said 2nd recessed part is more than the length of the said 2nd pad pair. The wiring board according to claim 1.
  5.  前記セラミック基体は、前記第1のパッド対と前記第2のパッド対との間に設けられた第3の凹部を有している、請求項1から4のいずれか1項に記載の配線基板。 The wiring substrate according to claim 1, wherein the ceramic base has a third recess provided between the first pad pair and the second pad pair. .
  6.  前記第3の凹部の深さは、前記第1の凹部および前記第2の凹部の各々の深さよりも小さい、請求項5に記載の配線基板。 6. The wiring board according to claim 5, wherein the depth of the third recess is smaller than the depth of each of the first recess and the second recess. 7.
  7.  前記セラミック基体は、前記第1パッド間に設けられた第4の凹部と、前記第2パッド間に設けられた第5の凹部と、を有している、請求項1から6のいずれか1項に記載の配線基板。 7. The ceramic substrate according to claim 1, wherein the ceramic base has a fourth recess provided between the first pads and a fifth recess provided between the second pads. The wiring board according to the item.
  8.  前記第4の凹部および前記第5の凹部の各々の深さは、前記第1の凹部および前記第2の凹部の各々の深さよりも小さい、請求項7に記載の配線基板。 8. The wiring board according to claim 7, wherein a depth of each of the fourth recess and the fifth recess is smaller than a depth of each of the first recess and the second recess.
  9.  請求項1から8のいずれか1項に記載の配線基板と、
     キャビティを有するケーシングと、
    を備え、
     前記配線基板の少なくとも一部は前記キャビティの内部に位置している、
    パッケージ。
    A wiring board according to any one of claims 1 to 8,
    A casing having a cavity;
    With
    At least a part of the wiring board is located inside the cavity,
    package.
  10.  前記配線基板は、前記キャビティの外部に位置する部分を有している、請求項9に記載のパッケージ。 The package according to claim 9, wherein the wiring board has a portion located outside the cavity.
  11.  請求項9または10に記載のパッケージと、
     前記パッケージの前記キャビティを封止する蓋体と、
     前記キャビティ内に実装された集積回路と、
    を備え、
     前記第1の配線路および前記第2の配線路は、前記集積回路に電気的に接続される差動線路を構成している、
    モジュール。
    A package according to claim 9 or 10,
    A lid for sealing the cavity of the package;
    An integrated circuit mounted in the cavity;
    With
    The first wiring path and the second wiring path form a differential line electrically connected to the integrated circuit.
    module.
  12.  前記集積回路は55GHz以上の動作周波数を有している、請求項11に記載のモジュール。 The module according to claim 11, wherein the integrated circuit has an operating frequency of 55 GHz or more.
PCT/JP2019/032221 2018-08-21 2019-08-19 Wiring board, package, and module WO2020040072A1 (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023100964A1 (en) * 2021-12-03 2023-06-08 京セラ株式会社 Wiring substrate and electronic device
JP7456516B2 (en) 2020-11-04 2024-03-27 株式会社村田製作所 Multilayer circuit board with signal power separation circuit

Citations (2)

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Publication number Priority date Publication date Assignee Title
JPH10107626A (en) * 1996-09-27 1998-04-24 Matsushita Electric Ind Co Ltd Pll circuit
WO2018074100A1 (en) * 2016-10-21 2018-04-26 京セラ株式会社 High frequency base body, high frequency package, and high frequency module

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012026516A1 (en) * 2010-08-27 2012-03-01 京セラ株式会社 Element-containing package and module provided therewith

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10107626A (en) * 1996-09-27 1998-04-24 Matsushita Electric Ind Co Ltd Pll circuit
WO2018074100A1 (en) * 2016-10-21 2018-04-26 京セラ株式会社 High frequency base body, high frequency package, and high frequency module

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7456516B2 (en) 2020-11-04 2024-03-27 株式会社村田製作所 Multilayer circuit board with signal power separation circuit
WO2023100964A1 (en) * 2021-12-03 2023-06-08 京セラ株式会社 Wiring substrate and electronic device

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JPWO2020040072A1 (en) 2021-06-03
JP7026804B2 (en) 2022-02-28
CN112119489A (en) 2020-12-22

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