WO2020037981A1 - 一种基于双S核的8-bitAES电路 - Google Patents

一种基于双S核的8-bitAES电路 Download PDF

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WO2020037981A1
WO2020037981A1 PCT/CN2019/078238 CN2019078238W WO2020037981A1 WO 2020037981 A1 WO2020037981 A1 WO 2020037981A1 CN 2019078238 W CN2019078238 W CN 2019078238W WO 2020037981 A1 WO2020037981 A1 WO 2020037981A1
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box
bytes
data
key
cycles
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单伟伟
徐嘉铭
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东南大学
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
    • H04L9/0618—Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation
    • H04L9/0631—Substitution permutation network [SPN], i.e. cipher composed of a number of stages or rounds each involving linear and nonlinear transformations, e.g. AES algorithms
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/08—Key distribution or management, e.g. generation, sharing or updating, of cryptographic keys or passwords
    • H04L9/0891—Revocation or update of secret information, e.g. encryption key update or rekeying
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • the invention discloses a high-energy-efficiency 8-bit AES circuit based on dual S cores, and belongs to the technical field of confidential or secure communication devices.
  • IoT Internet of Things
  • SoC System on Chip
  • AES Advanced Encryption Standard
  • Rijndael Rijndael algorithm
  • the traditional 128-bit AES uses a 16-byte 128-bit data path, and 64 routing tracks are used for row shift replacement to achieve single-cycle round delay and 10-cycle iterations.
  • 64 routing tracks are used for row shift replacement to achieve single-cycle round delay and 10-cycle iterations.
  • the large area overhead and energy consumption caused by these parallel operations makes them unsuitable for use in mobile and wearable systems and IoT fields that are constrained by battery power.
  • 8-bit AES Due to the urgent need for data encryption in the field of Internet of Things, and the area and power consumption of 128-bit AES can no longer meet the use of lightweight equipment, 8-bit AES has gradually received attention.
  • 8-bit AES for IoT applications uses an 8-bit data path. Compared with traditional 128-bit AES circuits, it improves energy efficiency by making full use of serial processing and partial parallel processing to reduce circuit area and power consumption.
  • the important module S-box completes the byte substitution conversion function through non-linear changes.
  • the 8-bit AES circuit reduces the number of S-Boxes to only one or two, that is, reduces the power consumption and reduces the area by reducing the combinational logic, but the number of cycles to implement the encryption operation is significantly increased, and the throughput is greatly increased. reduce.
  • the object of the present invention is to address the above-mentioned shortcomings of the background technology, and provide an energy-efficient 8-bit AES circuit based on dual S cores.
  • the operation period of the key expansion module is reasonably divided into S
  • the -Box operation is concentrated in the early processing cycle, making the S-Box core called by the key expansion module idle in the post-processing cycle.
  • the data processing module shares the computing tasks of the called S-Box by calling the idle S-Box core, and performs parallel processing.
  • Data processing and key expansion have achieved an 8-bit AES circuit throughput improvement with a short calculation cycle, which solves the technical problems of traditional 128-bit AES circuit with large power consumption area and long traditional 8-bit AES circuit encryption operation cycle.
  • An 8-bit AES circuit based on dual S cores includes: a data processing module, a key plus module, a control module, and a key plus module;
  • the data processing module calls an S-Box in the first to fourth cycles to check the four bytes of the intermediate data to perform the S-Box operation and complete the cyclic shift operation, and calls two S in the fifth to eleventh cycles.
  • -Box checks the remaining twelve bytes of the intermediate data to perform S-Box operations and completes the cyclic shift operation of the remaining twelve bytes and the column mixed operation of all bytes to generate new intermediate data.
  • the S-Box that is being called by the shared data processing module performs S-Box operations on all bytes and completes the cyclic shift operation. XOR the extended key after the bit to generate a new extended key,
  • a key addition module that performs an exclusive-OR operation on the intermediate data generated by the data processing module and the extended key updated by the key expansion module to generate the next round of intermediate data or ciphertext, and,
  • Control module enabling the data processing module to perform S-Box operation, row shift operation, and column mixed operation on the intermediate data to generate new intermediate data, and enabling the key expansion module to perform S-Box operation and cyclic shift on the extended key Bit operation or XOR operation to update the extended key, enable the key addition module to generate the next round of intermediate data or ciphertext.
  • the affine transformation S-Box core is used instead of the LUT S-Box core to reduce the area.
  • the three paths of the affine transformation S-Box core can be inserted into the D flip-flop. Reduce glitch power consumption to reduce the extra power added by using the affine transform S-Box core.
  • the data processing module integrates S-Box operations, row shift operations, and column mixed operations.
  • the idle S- Box1 performs parallel operations to reduce the number of execution cycles of the data processing module.
  • the shift operation is implemented by register-to-register assignment, reducing intermediate registers. The specific process is:
  • Step 1 When receiving the data processing enable signal sub_start_i from the control module, perform data processing. If it is the first round, the plaintext is directly called; if it is not the first round, the result of the key addition operation is processed.
  • Step 2 In the 1-4th cycle, S-Box operation is performed on the 4th to 15th bytes of data through S-Box2. After the 12th to 14th bytes are completed, they are stored in the intermediate register and the 15th byte is calculated. After completion, it is stored in the original register, which brings a total of 3 bytes of intermediate register area cost;
  • Step 3 In the 5th to 6th cycles, perform S-Box operations on the 11th and 5th bytes through S-Box2. Since S-Box1 is already idle, the 10th and 0th bytes are passed through S-Box1 Perform S-Box operation. These four bytes are directly stored in the original register after the operation is completed, without any area cost. After S-Box operation is completed, the new columns 12-15 are subjected to column mixing operation.
  • Step 4 In the 7th to 8th cycles, perform S-Box operations on the 9th and 6th bytes through S-Box2, and perform S-Box operations on the 8th and 1st bytes through S-Box1.
  • the 8th byte is stored in the intermediate register after the operation is completed, and the 6th and 1st bytes are stored in the original register after the operation is completed, which brings the cost of the two bytes of the intermediate register area; -11 bytes for column mixing operation;
  • Step 5 In the 9th to 10th cycles, perform S-Box operations on the 7th and 3rd bytes through S-Box2, and perform S-Box operations on the 2nd and 4th bytes through S-Box1. Stored in the register, without bringing any area cost; after the S-Box operation is completed, the column mixing operation is performed on the new 4-7 bytes;
  • Step 6 Perform column mixing operation on the new 0th to 3rd bytes in the 11th cycle. At this point, the new 128-bit data after data processing has been completely generated, and a data processing completion signal sub_ready_o is output to the control module.
  • the key expansion module is implemented in a one-hot-shift overall manner using a circular address generator and in the form of a Kano graph instead of the traditional Rcon lookup table. , Reduce the module area; the key expansion module completes the operation in 11 cycles, and completes the S-Box operation of all elements in the last column of the key and the byte rotation of the last column of data in the 1-5 cycle. During the 11 cycle, XOR operation is performed on each column of the extended key after the byte cyclic shift operation and the unexpanded key to obtain the updated extended key.
  • the key expansion module and the data processing module are completely parallel. This reduces the number of cycles and improves the throughput.
  • the specific calculation process is as follows:
  • Step 1 When receiving the key enable signal key_start_i from the control module, perform key expansion. If it is the first round, the original key is directly called; if it is not the first round, the key is expanded;
  • Step 2 The S-Box operation on the last column of data in the matrix is completed in the 1-4th cycle, and the S-Box operation is performed on one of the data in the last column of the matrix in each cycle. At the same time, the S-Box is completed on the 2-5th cycle.
  • the byte of Box operation is byte-shifted;
  • Step 3 In the 5th cycle, update the first column of data for the next round of extended keys
  • Step 4 Update the remaining 12 bytes of the extended key in the 6th to 11th cycles, and update 2 bytes in each cycle;
  • Step 5 In the 11th cycle, a new key after key expansion and a key expansion completion signal key_ready_o are generated.
  • the key expansion module uses a one-hot-shift method to implement a new key expansion module. It is a circular address generator. Consists of 11 registers in series. Only one flip-flop is enabled per clock cycle.
  • the S-Box operation is concentrated in the early processing cycle by reasonably dividing the operation cycle of the key expansion module, so that the S-Box core called by the key expansion module is idle in the post processing cycle.
  • the data processing module shares the computing tasks of the called S-Box by calling the idle S-Box core.
  • the affine transformation S-Box kernel is used to replace the LUT and the S-Box kernel to reduce the area.
  • the way that the three paths of the affine transformation S-Box kernel are inserted into the D trigger can reduce the glitch power consumption and reduce the use of affine transformation -The additional power consumption of the Box core;
  • the one-hot-shift method is used to implement the key expansion module as a whole, which can be implemented after 11 cycles, and the Karnaugh map is used to replace the traditional Rcon lookup table to reduce Area, the first column of data of the next round of expansion keys has been completed in the first 5 cycles, and the remaining 12 expansion keys need only be completed by XOR operation, and the 12 XOR operations are evenly distributed to 6 In this way, the area cost of XOR operation can be minimized, there will be no redundant or idle cells, compared with the need for 16 cycles or even 5n + 1 (where n is the number of rounds).
  • Traditional key expansion module shortening the execution cycle and reducing the circuit area;
  • the data processing module makes full use of the idle time of the key expansion module and does not use the S-Box idle time.
  • the intermediate data is updated in the same time as the key expansion module processing cycle, reducing the number of data processing module execution cycles and improving the throughput rate.
  • the number of registers is reduced from 384 to 168, of which the number of intermediate registers is reduced from 128 to 40. Compared with traditional data processing modules that require 21 cycles, the number of execution cycles is reduced while the circuit area is reduced.
  • FIG. 1 is a structural block diagram of a dual S-core 8-bit AES circuit of the present invention.
  • FIG. 2 is a structural diagram of an S-Box of the present invention.
  • FIG. 3 is a timing diagram of a dual S-core 8-bit AES circuit of the present invention.
  • FIG. 4 is a structural diagram of a key expansion module of the present invention.
  • FIG. 5 is a structural diagram of a data processing module of the present invention.
  • FIG. 6 is a data flow diagram of a dual S-core 8-bit AES circuit of the present invention.
  • the 8-bit AES circuit based on the dual S core designed by the present invention is shown in FIG. 1 and is mainly divided into four modules: a data processing module, a key expansion module, a control module, and a key addition module.
  • the input signal of the circuit is the clock signal clk, the reset signal reset, the start signal start_i, the plaintext data_i, and the key keyi, and the output signals are the completion signal ready_o and the ciphertext data_o.
  • the work of this circuit can be divided into the following steps:
  • Step 1 At the beginning of the circuit startup, the control module performs the encryption operation by monitoring the external encryption enable signal start_i. First, the first round of calculation is performed. The original plaintext data_i and the key key_i are directly input to the key adding module for encryption. Key addition.
  • Step 2 After the key addition operation is completed, the key addition completion signal Addroundkey_ready_o is sent to the control module.
  • Step 3 In the 1-10 cycle, the key expansion and data processing are performed simultaneously.
  • the data processing is divided into three steps, which are S-Box operation, column mixed operation, and row shift transformation (the column mixed operation is not included in the 10th round).
  • S-Box1 is called by the key expansion module in the 1-4 cycle, and is called by the data processing module in the 5-10 cycle; and S-Box2 is always called by the data processing module.
  • Step 4 When the key expansion and data processing are completed, key_ready_o and sub_ready_o signals are sent to the control module; the control module sends a key plus enable signal addroundkey_start_i to perform a new round of key plus function.
  • Step 5 Repeat steps 2-4 for a total of 10 rounds.
  • FIG. 2 is the structure diagram of S-Box.
  • S-Box1 and S-Box2 used by the data processing module and the key expansion module adopt this structure.
  • the S-Box implemented in this way uses affine transformation instead of LUT to reduce Up area.
  • the long-delay path and the short-delay path are balanced in the S-Box.
  • the S-Box contains two short paths and one long path.
  • Reduce glitch power consumption that is, insert a trigger at (1) (2) (3) to reduce glitch power consumption.
  • the critical path of the S-Box includes two GF (24) multiplications. Inserting a trigger at (2) can reduce the critical path delay, thereby increasing the frequency of the overall AES circuit encryption to improve the throughput.
  • FIG. 3 is a timing diagram of the dual S-core 8-bit AES circuit. It is executed in seven steps. A total of T cycles are required to complete the AES encryption operation. The formula is as follows:
  • T T cycle * 10 + T init + T ready
  • T cycle represents the cycle required for each round, and the value is 11, which means that a total of 11 cycles are required to complete an iteration; the data processing module and the key expansion module are executed in parallel, which requires a total of 11 cycles.
  • T init represents the period required for the first round of key addition.
  • the value is 2.
  • T ready represents the period required to generate the encryption completion signal, with a value of 1. It takes 1 cycle to generate the final AES encryption completion signal ready_o when the last round of operation is completed, which is shown in the dark gray area in the lower right corner of Figure 3.
  • Figure 4 shows the key expansion module.
  • the key expansion module is completely parallel to the data processing module. Since one cycle of data processing requires 11 cycles, in the design of the dual S core, the key expansion module is no longer limited to be completed in 5 cycles. Therefore, a new method is adopted here, which is implemented in 11 cycles.
  • the S-Box operation and byte rotation are completed in the 1-5 cycle, and the XOR operation is completed in the 5-11 cycle.
  • the specific operation process is as follows:
  • Step 1 When receiving the key expansion enable signal key_start_i from the control module, perform key expansion. If it is the first round, directly call the original key key_i. Key for expansion;
  • Step 2 The S-Box operation on the last column of data in the key matrix is completed in the 1-4th cycle, and the S-Box operation on one element in the last column of the key matrix is completed in each cycle; Bytes that have completed the S-Box operation are byte-shifted, and each cycle shifts the last column of the current key matrix to the first column;
  • Step 3 In the fifth cycle, the first column data of the key matrix after the S-Box operation in the previous 4 cycles is XORed with the first column data of the original extended key and rcon respectively to update the next round of extended secrets.
  • Step 4 In the 6th to 11th cycles, the next 12 bits of the extended key are bitwise XORed with the original extended key, and the remaining 12 bytes of the extended key are updated. Two updates are performed every period. Bytes.
  • Step 5 In the 11th cycle, the next round of extended keys and the key extension completion signal key_ready_o are generated.
  • This design uses a circular address generator (one-hot-shift) to implement a new key expansion module. It is a circular address generator consisting of 11 serial registers. Only one flip-flop is enabled in each clock cycle. Compared with traditional iterative methods, this implementation has a smaller area.
  • Carnot maps are smaller area and lower power consumption.
  • its execution speed is lower than the look-up table.
  • this module it does not need to consider its execution speed, as long as it can meet the start of each round. Update regularly.
  • Figure 5 is a data processing module.
  • the data processing module optimizes and integrates traditional S-Box operations, column mixed operations, and row shift transformations, and performs column mixed operation of round keys in the order from high to low order.
  • S-Box operation and row shift transformation Through the parallel processing of column mixing operation, S-Box operation and row shift transformation, the overall number of cycles is compressed. Because in the 5-11 cycle, the key expansion module has completed the use of S-Box1, at this time, one more idle S-Box can be called, so a round of data processing only needs 11 cycles to complete.
  • the specific implementation method is discussed below, and the process is as follows:
  • Step 1 When receiving the data processing enable signal sub_start_i from the control module, perform data processing. If it is the first round, it will directly call the plain text. If it is not the first round, it will add the round obtained by adding the previous key. The key is used for data processing.
  • Step 2 In the 1-4th cycle, S-Box operation is performed on the four-byte data of D15, D14, D13, and D12 through S-Box2, which brings the cost of 3 bytes of intermediate register area. Since the data D'14, D'13 and D'12 to be entered in the addresses L2, L5 and L8 after D-, D13, and D12 have not been calculated yet, the address is in a non-idle state. These three sets of values are assigned to three 8-bit intermediate registers (ImmediateReg) of I2, I5, and I8. The data D'15 after the S-Box calculation at D15 enters the original address L15.
  • ImmediateReg 8-bit intermediate registers
  • Step 3 In the 5th to 6th cycles, since S-Box1 is already idle, perform S-Box operations on data D11 and D5 through S-Box2, and perform S-Box operations on data D10 and D0 through S-Box1. Does not bring any area cost; because the data after D-box calculation of D11, D10, D5, and D0 must enter the addresses L11, L14, L13, and L12, and the old data corresponding to these four addresses D15, D14, D13 And D12 have performed S-Box operations, and the calculated values have entered new addresses, so these addresses are idle.
  • the four groups of data D'11, D'10, D'5, and D'0 after S-Box operation are directly assigned to the four 8-bit original registers (DataReg) of L11, L14, L13, and L12;
  • DataReg original registers
  • Step 4 In the 7th to 8th cycles, perform S-Box operations on data D9 and D6 through S-Box2, and perform S-Box operations on data D8 and D1 through S-Box1, bringing two bytes of intermediate registers Area cost; because the data in the addresses L1 and L4 to be entered after the S-Box operation of D9 and D8 has not been converted, these addresses are in a non-idle state, and D'9 and D'8 are assigned to I1 and I4 Two 8-bit intermediate registers (ImmediateReg).
  • Step 5 In the 9th to 10th cycles, perform the S-Box operation on the data D7 and D3 through S-Box2, and perform the S-Box operation on the data D2 and D4 through S-Box1, without any area cost; due to D2
  • the data D'2 and D'4 after the S-Box operation with D4 must enter the addresses L6 and L0.
  • the old data corresponding to these two addresses D6 and D0 have been calculated, and the calculated values have entered the new value. These addresses are in the idle state.
  • the two sets of values D'2 and D'4 are directly assigned to the two 8-bit original registers (DataReg) of L6 and L0.
  • DataReg original registers
  • the data D'7 and D'3 after the S-Box operation are performed by D7 and D3 enter the original addresses L7 and L3.
  • Step 6 When the number of rounds is less than 10, in the eleventh cycle, at this time, all the new data at L0-L3 have been generated. Column mixing operations are performed on the L0, I1, L2, and L3 data, and the result of the operation is passed in. L0-L3 (At this time, both L1 and L2 data have been calculated and are in the idle state). At this point, the new 128-bit data sub_data_o after data processing has been completely generated, and a data processing completion signal sub_ready_o is output to the control module.
  • Figure 6 is a data flow table of a dual S-core 8-bit AES circuit.
  • the newly generated data D'9, D'14, D'8, D'13, and D'12 are located in L1 / L2 / L4 / L5 / L8 in the DataReg. Since these positions are in a non-idle state, the data is transferred to ImmediateReg I1 / I2 / I4 / I5 / I8; secondly, the italics in the table represent S-Box operations performed by S-Box1, and the rest are performed by S-Box2 This operation; in the end, '(M)' represents that after completing the S-Box operation of this cycle, the 4-byte column mixed operation is completed in the next cycle.

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Abstract

本发明公开了一种基于双S核的8-bitAES电路，属于保密或安全通信装置的技术领域。该电路面向IoT应用，与传统128-bit AES电路相比，采用了8比特的数据路径，通过充分利用串行处理和部分并行处理来降低电路面积与功耗，提高能量效率。电路包括：数据处理模块、密钥扩展模块、控制模块、密钥加模块。双S核的设计使数据处理模块和密钥扩展模块可以并行执行，数据处理模块充分利用S核不被密钥扩展模块调用的空闲时间，降低周期数，提高吞吐率。同时，移位操作采用寄存器到寄存器的方式实现，减少了中间寄存器，进一步降低了电路面积。

Description

一种基于双S核的8-bitAES电路 技术领域
本发明公开了一种基于双S核的高能效8-bitAES电路，属于保密或安全通信装置的技术领域。
背景技术
随着物联网(Internet of Things，IoT)技术的迅速发展，市场对物联网芯片的需求也越来越多。就物联网的安全性需求而言，由于存在大量的信息交互，数据安全是物联网中很重要的一个问题。
为了保障信息安全，加密算法被广泛地应用在片上系统(System on a Chip，SoC)中，其中最具代表性的是高级加密算法(Advanced Encryption Standard，AES)。AES算法也称为Rijndael算法是一种对称分组密码算法，数据以128位的块进行加密和解密。
传统128-bit AES采用的是16字节的128位数据路径，64个布线轨道用于行移位置换，以实现单周期轮延迟和10周期的迭代。然而，这些并行操作导致的大面积开销和能量消耗使得它们不适合在受电池电量约束的移动和可穿戴系统以及IoT领域使用。
由于物联网领域对数据加密有迫切需求，同时128-bit AES的面积和功耗已经无法满足轻量级设备的使用，8-bit AES逐渐受到了重视。面向IoT应用的8-bit AES采用了8比特的数据路径，与传统128-bit AES电路相比，通过充分利用串行处理和部分并行处理来降低电路面积与功耗来提高能量效率，其中一个重要的模块S-box通过非线性变化完成字节替代变换功能。数据路径为8-bit的AES电路将S-Box数量减少至只剩一个或者两个，即，通过减少组合逻辑来降低功耗并减小面积，但是实现加密运算的周期明显增多，吞吐率大大降低。
发明内容
本发明的发明目的是针对上述背景技术的不足，提供了一种基于双S核的高能效8-bitAES电路，在双S核的电路架构下，通过合理划分密钥扩展模块的运算周期将S-Box运算集中在前期处理周期，使得密钥扩展模块调用的S-Box核在后期处理周期空闲，数据处理模块通过调用空闲的S-Box核分担已调用S-Box的运算任务，通过并行处理数据处理和密钥扩展，以较短的运算周期实现了8-bitAES电路吞吐率的提高，解决了传统128-bitAES电路功耗面积大、传统8-bitAES电路加密运算周期过长的技术问题。
本发明为实现上述发明目的采用如下技术方案：
一种基于双S核的8-bitAES电路包括：数据处理模块、密钥加模块、控制模块、密钥加模块；
数据处理模块，在第一至第四周期内调用一个S-Box核对中间数据的四个字节进行S-Box运算并完成循环移位运算，在第五至第十一周期内调用两个S-Box核对中间数据的其余十二个字节进行S-Box运算并完成其余十二个字节的循环移位运算以及所有字节的列混合运算，生成新的中间数据，
密钥扩展模块，在第一至第四周期内共享数据处理模块正在调用的S-Box核对所有字节进行S-Box运算并完成循环移位运算，在第五至第十一周期内对移位后的扩展密钥进行异或运算，生成新的扩展密钥，
密钥加模块，对数据处理模块产生的中间数据和密钥扩展模块更新的扩展密钥进行异或运算产生下一轮的中间数据或者密文，及，
控制模块，使能数据处理模块对中间数据进行S-Box运算、行移位运算、列混合运算以生成新的中间数据，使能密钥扩展模块对扩展密钥进行S-Box运算、循环移位运算、异或运算以更新扩展密钥，使能密钥加模块生成下一轮的中间数据或者密文。
。
作为基于双S核的8-bitAES电路的进一步优化方案，用仿射变换S-Box核代替LUT S-Box核，减少面积，同时仿射变换S-Box核三条路径插入D触发器的方式能够减少毛刺功耗，以降低使用仿射变换S-Box核所增加的额外功耗。
作为基于双S核的8-bitAES电路的进一步优化方案，数据处理模块把S-Box运算、行移位运算、列混合运算进行整合，在5-11周期调用密钥扩展完成后空闲的S-Box1进行并行运算，降低数据处理模块执行周期数；移位操作通过寄存器到寄存器的赋值方式实现，减少了中间寄存器，其具体流程为：
步骤一：当收到来自控制模块的数据处理使能信号sub_start_i时，进行数据处理。若为第一轮，则直接调用明文；若非第一轮，则对密钥加运算后的结果进行数据处理；
步骤二：在第1-4个周期，通过S-Box2对第12-15四个字节数据进行S-Box运算，第12-14字节完成运算后存入中间寄存器，第15字节运算完成后存入原始寄存器，总共带来3个字节的中间寄存器面积代价；
步骤三：在第5-6个周期，对第11和第5字节通过S-Box2进行S-Box运算，由于S-Box1已处于空闲状态，对第10和第0字节通过S-Box1进行S-Box运算，这四个字节完成运算后直接存入原始寄存器，未带来任何面积代价；S-Box运算完成后对新的第12-15字节进行列混合运算；
步骤四：在第7-8个周期，对第9和第6字节通过S-Box2进行S-Box运算，对第8和第1字节通过S-Box1进行S-Box运算，第9和第8字节完成运算后存入中间寄存器，第6和第 1字节完成运算后存入原始寄存器，带来两个字节的中间寄存器面积代价；S-Box运算完成后对新的第8-11字节进行列混合运算；
步骤五：在第9-10个周期，对第7和第3字节通过S-Box2进行S-Box运算，对第2和第4字节通过S-Box1进行S-Box运算，运算结果均存入寄存器，未带来任何面积代价；S-Box运算完成后对新的第4-7字节进行列混合运算；
步骤六：在第11周期对新的第0-3字节进行列混合运算，至此，经过数据处理后的新的128位数据已经完全产生，输出数据处理完成信号sub_ready_o至控制模块。
作为基于双S核的8-bitAES电路的进一步优化方案，密钥扩展模块采用循环地址发生器的方式(one-hot-shift)整体实现以及利用卡诺图实现的方式代替Rcon传统查找表的方式，减小模块面积；密钥扩展模块在11个周期完成运算，在1-5周期内完成密钥最后一列所有元素的S-Box运算以及最后一列数据的字节循环移位，在第5-11周期内对经字节循环位移操作后的扩展密钥以及还未进行扩展的密钥的各列数据进行异或运算得到更新后的扩展密钥，密钥扩展模块和数据处理模块完全并行，从而减少周期数，提高吞吐率，其具体运算流程如下：
步骤一：当收到来自控制模块的密钥使能信号key_start_i时，进行密钥扩展。若为第一轮，则直接调用原始密钥；若非第一轮，则进行密钥扩展；
步骤二：第1-4周期完成对矩阵中最后一列数据的S-Box运算，每个周期对矩阵最后一列中的一个数据进行S-Box运算；同时，第2-5周期对已完成S-Box运算的字节进行字节循环移位；
步骤三：第5个周期，更新下一轮扩展密钥的第一列数据；
步骤四：第6-11个周期，更新剩下12个字节的扩展密钥，每个周期更新两个字节；
步骤五：第11个周期，生成经过密钥扩展后的新密钥以及密钥扩展完成信号key_ready_o。
作为基于双S核的8-bitAES电路的进一步优化方案，密钥扩展模块采用循环地址发生器的方式(one-hot-shift)方式实现新的密钥扩展模块，是一种循环地址发生器，由11个串联的寄存器组成，在每个时钟周期，只有一个触发器被使能。
本发明采用上述技术方案，具有以下有益效果：
(1)在双S核的电路架构下，通过合理划分密钥扩展模块的运算周期将S-Box运算集中在前期处理周期，使得密钥扩展模块调用的S-Box核在后期处理周期空闲，数据处理模块通过调用空闲的S-Box核分担已调用S-Box的运算任务，通过完全并行处理数据处理和密钥扩展，减少周期数到113，以较短的运算周期实现了8-bitAES电路吞吐率的提高；
(2)用仿射变换S-Box核代替LUT S-Box核，减少面积，同时仿射变换S-Box核三条路 径插入D触发器的方式能够减少毛刺功耗，以降低使用仿射变换S-Box核所增加的额外功耗；
(3)采用循环地址发生器的方式(one-hot-shift)整体实现密钥扩展模块，经过11个周期即可实现，并利用卡诺图实现的方式代替Rcon传统查找表的方式以减小面积，前5个周期就已经完成了下一轮扩展秘钥的第一列数据，剩下的12个扩展秘钥只需要通过异或运算完成即可，将12个异或运算平均分配到6个周期中，从而可以将进行异或运算的面积代价降到最低，不会有冗余或者空闲的单元，相比于需要16个周期甚至5n+1(其中，n为轮数)个周期实现的传统密钥扩展模块，缩短执行周期且减小电路面积；
(3)数据处理模块充分利用密钥扩展模块不使用S-Box的空闲时间，在与密钥扩展模块处理周期一样的时间内实现中间数据的更新，降低数据处理模块执行周期数，提高吞吐率，同时，寄存器从384个减少到168个，其中，中间寄存器从128个减少到40个，相比于需要21个周期的传统数据处理模块，降低执行周期数的同时降低了电路面积。
附图说明
图1为本发明双S核8-bitAES电路的结构框图。
图2为本发明的S-Box的结构图。
图3为本发明双S核8-bitAES电路时序图。
图4为本发明的密钥扩展模块结构图。
图5位本发明的数据处理模块结构图。
图6位本发明双S核8-bitAES电路的数据流图。
具体实施方式
下面结合附图对发明的技术方案进行详细说明。
本发明设计的基于双S核的8-bitAES电路如图1所示，主要分为四个模块：数据处理模块、密钥扩展模块、控制模块、密钥加模块。电路的输入信号为时钟信号clk、复位信号reset、启动信号start_i、明文data_i、密钥key_i，输出信号为完成信号ready_o、密文data_o，该电路的工作可分为以下几个步骤：
步骤1：在电路启动初始，控制模块通过监测外部加密使能信号start_i来执行加密操作，首先进行第一轮运算，将输入的原始明文data_i和密钥key_i直接输入至密钥加模块，进行密钥加运算。
步骤2：密钥加运算完成之后，发送密钥加已完成信号Addroundkey_ready_o至控制模块。控制模块判断轮数，若轮数<10，控制模块分别发出密钥扩展使能信号key_start_i信号和数据处理使能信号sub_start_i信号给密钥扩展模块和数据处理模块；若轮数＝10，得到最终的密文并产生ready_o信号。
步骤3：在1-10周期，同时执行密钥扩展和数据处理，数据处理分三步，分别是S-Box运算、列混合运算和行移位变换(在第10轮不包含列混合运算)；其中，S-Box1在在1-4周期被密钥扩展模块调用，在5-10周期被数据处理模块调用；而S-Box2一直由数据处理模块调用。
步骤4：当密钥扩展和数据处理均完成时，发出key_ready_o和sub_ready_o信号给控制模块；控制模块发出密钥加使能信号addroundkey_start_i，执行新一轮的密钥加功能。
步骤5：重复步骤2-4，一共10轮。
图2为S-Box的结构图，数据处理模块和密钥扩展模块使用的S-Box1和S-Box2都采用了该结构，这种方式实现的S-Box用仿射变换代替LUT，减小了面积。为了降低功耗，将S-Box中延时长的路径和延时短的路径平衡化处理，S-Box中一共含有两条短路径、一条长路径，通过对这三条路径插入D触发器的方式以减少毛刺功耗，即在(1)(2)(3)处插入触发器以减少毛刺功耗。同时，S-Box的关键路径包括两个GF(24)乘法，在(2)处插入触发器可以减小关键路径延时，从而提高整体AES电路加密的频率以提高吞吐率。
图3为双S核8-bit AES电路时序图，按七个步骤执行，一共需要T个周期完成AES加密运算，公式如下：
T＝T cycle*10+T init+T ready
其中，T cycle代表每轮需要的周期，值为11，表示一共需要11周期完成一轮迭代；数据处理模块和密钥扩展模块并行执行，共需要11个周期。
T init代表第一轮密钥加需要的周期，值为2，步骤1阶段中第一轮密钥加时，需要2个周期完成运算，即图3中左下角浅灰色区域所示。
T ready代表生成加密完成信号需要的周期，值为1，最后一轮完成运算时产生最终AES加密完成信号ready_o需要1个周期，即图3中右下角深灰色区域所示。
故整个单S核的8-bitAES加密运算需要113个周期完成。
图4为密钥扩展模块，密钥扩展模块与数据处理模块完全并行。由于数据处理一轮周期需要11个周期，故在双S核的设计中，不再把密钥扩展模块限制在5个周期内完成。因此，此处采用一种新的方式，11个周期实现。在1-5周期内完成S-Box运算和字节循环移位，在第5-11周期内完成异或运算，其具体运算流程如下：
步骤一：当收到来自控制模块的密钥扩展使能信号key_start_i时，进行密钥扩展，若为第一轮，则直接调用原始密钥key_i，若非第一轮，则对上一轮扩展密钥进行扩展；
步骤二：第1-4周期完成对密钥矩阵中最后一列数据的S-Box运算，每个周期完成密钥 矩阵最后一列中一个元素的S-Box运算；同时，第2-4周期对已完成S-Box运算的字节进行字节循环移位，每个周期将当前密钥矩阵的最后一列移位至第一列；
步骤三：第5个周期，将前4个周期S-Box运算后的密钥矩阵第一列数据分别与原扩展密钥的第一列数据以及rcon进行异或运算，更新下一轮扩展密钥的第一列数据；
步骤四：第6-11个周期，下一轮扩展密钥剩余12个字节与原扩展密钥的按位异或运算，更新剩下12个字节的扩展密钥，每个周期更新两个字节。
步骤五：第11个周期，生成下一轮扩展密钥以及密钥扩展完成信号key_ready_o。
本设计采用循环地址发生器的方式(one-hot-shift)实现新的密钥扩展模块，是一种循环地址发生器，由11个串联的寄存器组成。在每个时钟周期，只有一个触发器被使能。和传统的迭代方式相比，这种实现方式面积更小。
传统方式采用的是查找表的方式来实现。本设计中通过简单的卡诺图优化方法对Rcon进行了优化，具体结果如下式所示：
input＝round[3:0]
output＝rcon[7:0]
Figure PCTCN2019078238-appb-000001
Figure PCTCN2019078238-appb-000002
Figure PCTCN2019078238-appb-000003
Figure PCTCN2019078238-appb-000004
Figure PCTCN2019078238-appb-000005
Figure PCTCN2019078238-appb-000006
Figure PCTCN2019078238-appb-000007
rcon[7]＝round[2]·round[1]·round[0]
采用卡诺图实现所带来的优点是面积更小，功耗更小，当然其执行速度要低于查找表的方式，但是对于该模块，不需要考虑其执行速度，只要能满足每轮开始定期更新就行。
图5为数据处理模块，数据处理模块把传统的S-Box运算、列混合运算和行移位变换进行优化整合，按照从高四位至低四位的顺序进行轮密钥的列混合运算。通过列混合运算、S-Box运算和行移位变换的并行处理交叉进行，压缩整体实现周期数。由于在5-11周期，密钥扩展模块已使用完成S-Box1，此时多一个空闲的S-Box可以调用，故一轮数据处理只需要11个 周期就可以完成。下面讨论其具体执行方式，流程如下：
步骤一：当收到来自控制模块的数据处理使能信号sub_start_i时，进行数据处理，若为第一轮，则直接调用明文，若非第一轮，则对上一轮密钥加运算得到的轮密钥进行数据处理。
步骤二：在第1-4个周期，通过S-Box2对D15、D14、D13和D12四个字节数据进行S-Box运算，带来3个字节的中间寄存器面积代价。由于D14、D13和D12进行S-Box运算后的数据D’14，D’13和D’12要进入的地址L2、L5和L8中的数据还未进行运算，故该地址处于非空闲状态，这三组值赋值到I2、I5和I8三个8bit中间寄存器(ImmediateReg)。D15进行S-Box运算后的数据D’15进入原地址L15。
步骤三：在第5-6个周期，由于S-Box1已处于空闲状态，对数据D11和D5通过S-Box2进行S-Box运算，对数据D10和D0通过S-Box1进行S-Box运算，未带来任何面积代价；由于D11、D10、D5和D0进行S-Box运算后的数据要进入地址L11、L14、L13和L12中，而这四个地址所对应的旧数据D15、D14、D13和D12已进行过S-Box运算，且运算后的值已进入新的地址，故这些地址处于空闲状态。因此，这四组经过S-Box运算后的数据D’11、D’10、D’5和D’0直接赋值到L11、L14、L13和L12四个8bit原寄存器中(DataReg)；同时当轮数小于10时，在第7周期，此时新的位于L12-L15位置的数据已经生成，对L12、L13、L14和L15数据进行列混合运算，运算后的结果传入L12-L15。
步骤四：在第7-8个周期，对数据D9和D6通过S-Box2进行S-Box运算，对数据D8和D1通过S-Box1进行S-Box运算，带来两个字节的中间寄存器面积代价；由于D9和D8进行S-Box运算后的数据要进入的地址L1和L4中的数据还未进行变换，故这些地址处于非空闲状态，将D’9和D’8赋值到I1和I4两个8bit中间寄存器(ImmediateReg)。D6和D1进行S-Box运算后的数据D’6和D’1要进入地址L10和L9中，而这两个地址所对应的数据D10和D9已进行过运算，且运算后的值已进入新的地址，故这些地址处于空闲状态。因此，这两组值D’6和D’1直接赋值到L10和L9两个8bit原寄存器中(DataReg)。同时当轮数小于10时，在第9周期，此时新的位于L8-L11位置的数据已经全部生成，对I8、L9、L10和L11进行列混合运算，运算后的结果传入L8-L11(此时L8的数据已经被运算过，处于空闲状态)。
步骤五：在第9-10个周期，对数据D7和D3通过S-Box2进行S-Box运算，对数据D2和D4通过S-Box1进行S-Box运算，未带来任何面积代价；由于D2和D4进行S-Box运算后的数据D’2和D’4要进入地址L6和L0中，这两个地址所对应的旧数据D6和D0已进行过运算，且运算后的值已进入新的地址，故这些地址处于空闲状态，这两组值D’2和D’4直接赋值到L6和L0两个8bit原寄存器中(DataReg)。D7和D3进行S-Box运算后的数据 D’7和D’3进入原地址L7和L3。同时当轮数小于10时，在第10周期，此时新的位于L4-L7的数据已经全部生成，对I4、I5、L6、L7数据进行列混合运算，运算后的结果传入L4-L7(此时L4和L5数据均已经被运算过，处于空闲状态)。
步骤六：当轮数小于10时，在第11个周期，此时新的位于L0-L3的数据已经全部生成，对L0、I1、L2和L3数据进行列混合运算，运算后的结果传入L0-L3(此时L1和L2数据均已经被运算过，处于空闲状态)。至此，经过数据处理后的新的128位数据sub_data_o已经完全产生，输出数据处理完成信号sub_ready_o至控制模块。
图6为双S核8-bitAES电路的数据流表，新产生的数据D'9、D'14、D'8、D'13和D'12位于DataReg中L1/L2/L4/L5/L8处，由于这些位置处于非空闲状态，数据传入ImmediateReg I1/I2/I4/I5/I8；其次，表中斜体部分代表是通过S-Box1执行S-Box运算的，其它均通过S-Box2执行该运算；最后，'(M)'代表在完成该周期的S-Box运算后，在下一个周期完成4个字节的列混合运算。

Claims (5)

  1. 一种基于双S核的8-bitAES电路，其特征在于，包括：
    数据处理模块，在第一至第四周期内调用一个S-Box核对中间数据的四个字节进行S-Box运算并完成循环移位运算，在第五至第十一周期内调用两个S-Box核对中间数据的其余十二个字节进行S-Box运算并完成其余十二个字节的循环移位运算以及所有字节的列混合运算，生成新的中间数据，
    密钥扩展模块，在第一至第四周期内共享数据处理模块正在调用的S-Box核对所有字节进行S-Box运算并完成循环移位运算，在第五至第十一周期内对移位后的扩展密钥进行异或运算，生成新的扩展密钥，
    密钥加模块，对数据处理模块产生的中间数据和密钥扩展模块更新的扩展密钥进行异或运算产生下一轮的中间数据或者密文，及，
    控制模块，使能数据处理模块对中间数据进行S-Box运算、行移位运算、列混合运算以生成新的中间数据，使能密钥扩展模块对扩展密钥进行S-Box运算、循环移位运算、异或运算以更新扩展密钥，使能密钥加模块生成下一轮的中间数据或者密文。
  2. 根据权利要求1所述基于双S核的8-bitAES电路，其特征在于，所述S-Box核基于仿射变换实现，并在S-Box核的若干路径中插入D触发器。
  3. 根据权利要求1所述基于双S核的8-bit AES电路，其特征在于，所述数据处理模块在接收到控制模块的使能信号后执行如下步骤生成新的中间数据：
    A、在第1至第4周期，调用一个S-Box核对中间数据的第12至第15四个字节进行S-Box运算，将第12至第14字节的S-Box运算结果存入中间寄存器，将第15字节S-Box运算结果存入原始寄存器；
    B、在第5至第6周期，继续调用前4周期使用的S-Box核对中间数据的第11字节和第5字节进行S-Box运算，调用处于空闲状态的另一个S-Box核对中间数据的第10和第0字节进行S-Box运算，将第11字节、第5字节、第10字节、第0字节的S-Box运算结果存入原始寄存器，对移位后中间数据的第12至第15字节进行列混合运算；
    C、在第7至第8周期，继续调用前4周期使用的S-Box核对中间数据的第9字节和第6字节进行S-Box运算，调用处于空闲状态的另一个S-Box核对中间数据的第8和第1字节进行S-Box运算，将第9字节和第8字节的S-Box运算结果存入中间寄存器，将第6字节和第1字节的S-Box运算结果存入原始寄存器，对移位后中间数据的第8至第11字节进行列混合运算；
    D、在第9至第10周期，继续调用前4周期使用的S-Box核对中间数据的第7字节和第3字节进行S-Box运算，调用处于空闲状态的另一个S-Box核对中间数据的第2字节和第4字节进行S-Box运算，将第7字节、第3字节、第2字节、第4字节的S-Box运算结果存入原始寄存器，对移位后中间数据的第4至第7字节进行列混合运算；
    E、在第11周期，对移位后中间数据的第0至第3字节进行列混合运算，输出数据处理完成信号至控制模块。
  4. 根据权利要求1所述基于双S核的8-bit AES电路，其特征在于，所述密钥扩展模块在接收到控制模块的使能信号后执行如下步骤生成新的扩展密钥：
    a、在第1周期，对扩展密钥矩阵中最后一列数据的第二个字节进行S-Box运算；
    b、在第2周期，对扩展密钥矩阵中最后第一列数据的第三个字节进行S-Box运算；
    c、在第3周期，对扩展密钥矩阵中最后一列数据的第四个字节进行S-Box运算；
    d、在第4周期，对扩展密钥矩阵中最后一列数据的第一个字节进行S-Box运算，将当前扩展密钥矩阵中最后一列数据移位至第一列；
    e、在第5周期，将第1至第4周期中得到的第一列数据与原扩展密钥的第一列数据以及rcon进行异或运算生成下一轮扩展密钥的第一列数据；
    f、在第6至第11周期这6个周期内，以每个周期更新两个字节的方式完成下一轮扩展密钥剩余12个字节与原扩展密钥的按位异或运算，第11周期完成异或运算后输出密钥扩展完成信号至控制模块。
  5. 根据权利要4所述基于双S核的8-bitAES电路，其特征在于，所述密钥扩展模块为串联寄存器组成的循环地址发生器，利用卡诺图实现的方式代替Rcon传统查找表方式实现循环地址的触发。
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