WO2007112672A1

WO2007112672A1 - A device for implementing sms4 algorithm

Info

Publication number: WO2007112672A1
Application number: PCT/CN2007/001017
Authority: WO
Inventors: Jiayin Lu; Jun Cao; Xiang Yan; Zhenhai Huang
Original assignee: China Iwncomm Co., Ltd.
Priority date: 2006-03-31
Filing date: 2007-03-29
Publication date: 2007-10-11
Also published as: CN1983925A; CN100525183C

Abstract

A device for implementing SMS4 algorithm includes a device for encrypting/decrypting data circularly, which includes data register, a set of data conversing components, and constant array memory. The data register stores external data and result of the last data conversing.The set of data conversing components includes at least two components in series. The input of data conversing component connects to the output of the data register, and the output of data conversing component connects to the input of data register. The constant array memory stores the constant data array utilized in encrypting and decrypting. The output of the constant array memory connects to the input of each component of the set of data conversing components. The present invention solves problems such as cycling too many times and low efficiency in the prior art. The integrated circuit of present invention can make the integrity of chip signal much better, easier to manufacture the products, and lower producing cost. Interference in the system can also be dropped greatly.

Description

A device for realizing SMS4 encryption and decryption algorithm

This application claims priority to Chinese Patent Application No. 200610042608.6, entitled "A device for implementing SMS4 encryption and decryption algorithm", filed on March 31, 2006, the entire contents of which are incorporated herein by reference. In the application.

Technical field

The present invention relates to the field of information technology, and in particular, to an apparatus for implementing an SMS4 encryption and decryption algorithm. Background technique

The key components that implement the SMS4 encryption and decryption algorithm are the key extension component and the encryption and decryption component. The key extension component and the internal structure and processing of the encryption and decryption component are basically the same. Among them, the encryption and decryption component is mainly composed of three parts, namely, a data registration component, a constant array storage component, and a data conversion component.

The data register component uses a generic trigger for data registration. The data registered by the part does not change in one clock cycle. A general-purpose flip-flop is a data temporary storage device that inputs data at the data input to the output of the flip-flop at the upper or lower edge of the clock, while the data at the output of the flip-flop does not change at other times.

The constant array storage component is a storage component that stores a constant array. The constant array in the prior art is generally a data array having a width of 32 bits and a depth of 32 which has been prepared before the encryption and decryption process. The data of the constant array storage unit is arranged in the order of the address, and can be named as rk0, rkl, ... rk31 _{0. The} data conversion unit is a component that performs data processing according to the cryptographic algorithm. For example, data processing is performed in accordance with the requirements of the national SMS4 cryptographic algorithm, and the data conversion component performs only one synthetic permutation specified by the cryptographic algorithm.

At present, the method of encrypting and decrypting data according to the SMS4 cryptographic algorithm is as follows:

1) input external data into the data registration component;

After the external data is input to the data register unit, the output of the data register unit outputs the data. For example, 128-bit external data is divided into four 32-bit data blocks, which can be named AO, Al, A2, and A3. After the data registration component, the data at the output is still 128 bits, and is divided into four 32-bit data blocks, which are respectively named a0, al, a2, and a3.

2) performing data conversion processing;

The data at the output of the data registration unit is input to the data conversion unit for data conversion processing. For example, the data a0, al, a2, a3 at the output of the data register component are condensed: converted to a conversion component 128bit data C0, Cl, C2, C3.

3) performing data conversion processing again;

The data after the previous data conversion processing is again stored in the data registration unit, and then the data at the output of the data registration unit is again input to the data conversion unit, and the data conversion processing is performed again.

4) Repeat the data conversion process again to obtain the final data processing result.

For 128-bit external data, the data conversion processing must be cyclically processed 30 times, that is, the data conversion processing must be performed 32 times in total to obtain the final data processing result.

In the above prior art, a constant array having a width of 32 bits and a depth of 32 is prepared by the encryption and decryption processing, and an operation of synthesizing the replacement specified by only one cipher algorithm by the data conversion unit is performed, so that the number of cycles of the data conversion processing is large. For example, to encrypt 128-bit data, at least 32 data conversion processing cycles must be run to get the final data processing result.

In addition, the above prior art encryption and decryption efficiency is low. The efficiency of encryption and decryption is the amount of data encrypted and decrypted per unit time. For example, encrypting 128-bit data requires data conversion processing 32 times, which requires 32 clock cycles. Since the clock frequency in the actual application is relatively low, the amount of data encrypted per unit time is small and the efficiency is low. If the encryption and decryption efficiency is specified, the clock frequency needs to be increased, and the clock frequency in practical applications is often difficult to increase, so the actual encryption and decryption efficiency is still low. If the clock frequency is to be increased, the design and implementation of the existing integrated circuit will be difficult; the signal integrity is not good; and the design cost is high. In addition, the integrated circuit designed in the prior art, which is applied to the system, also causes an increase in the cost of the printed circuit board (PCB); difficulty in PCB design, difficulty in product implementation; and large interference in the system, which may affect Normal and efficient operation of other devices and devices.

Summary of the invention

The invention provides a device for realizing the SMS4 encryption and decryption algorithm, which can reduce the number of cycles of data conversion processing and improve the encryption and decryption efficiency.

The technical solution of the present invention is:

A device for implementing an SMS4 encryption and decryption algorithm, comprising:

a cyclic encryption/decryption data processing device comprising a data registering component, a data conversion component group and a constant array storage component;

The data registering component is configured to register external data and a result of a previous data conversion process; the data conversion component group is composed of at least two data conversion components sequentially connected in series, the data The input part of the conversion component is connected to the output end of the data registration component, and the output end of the data conversion component is connected to the input end of the data registration component;

The constant array storage unit is configured to store constant array data used for encryption and decryption processing, and an output end thereof is respectively connected to an input end of each of the data conversion unit groups.

The constant array data satisfies the following conditions:

1) result data obtained by key expansion processing;

2) Arrange in order of address;

3) arranging the width and depth corresponding to the array according to the number of data conversion components in the data conversion component group;

4) The product of width and depth is 1024.

The number of data conversion sections of the data conversion component group in the cyclic encryption/decryption data processing apparatus is a divisor of 32.

The method further includes: a first additional encryption and decryption data processing device, coupled to the input end of the cyclic encryption/decryption data processing device, for supplementing processing data conversion processing that is not completed by the cyclic encryption/decryption data processing device; The first additional encryption and decryption data processing device includes:

a first additional data registration component for registering external data;

The first additional data conversion component group is composed of a data conversion component or two or more serially connected data conversion components, and the first additional data conversion component group input terminal is connected to the output end of the first additional data registration component The output end of the first additional data conversion component group is connected to the input end of the cyclic encryption/decryption data processing device;

The first additional constant array storage unit is configured to store constant array data for use in the encryption and decryption process, and an output end thereof is respectively connected to an input end of each of the data conversion units in the first additional data conversion unit group.

The constant array data stored by the constant array storage unit satisfies the following conditions:

1) result data obtained by key expansion processing;

2) Arrange in order of address;

3) a first product of a constant array data width and a depth of the constant array storage unit in the cyclic encryption/decryption data processing device, and a constant array data width and depth of the first additional constant array storage unit in the first additional encryption/decryption data processing device a product of the second product, the sum of the first product and the second product is 1024; The width of the constant array data in the first additional constant array storage unit is the number of data conversion units in the first additional data conversion unit group multiplied by 32, and the depth of the constant array data in the first additional constant array storage unit is 1.

The method further includes: a second additional encryption and decryption data processing device, coupled to the output end of the cyclic encryption/decryption data processing device, for supplementing processing, the data processing of the cyclic encryption/decryption data processing device is not completed; The second additional encryption and decryption data processing device includes:

a second additional data registering component for registering a result of said cyclic encryption/decryption data processing process; a second additional data conversion component group consisting of a data conversion component or two or more data conversion components sequentially connected in series The second additional data conversion component group input terminal is connected to the second additional data registration component output end, and the second additional data conversion component group output terminal is connected to the second additional data registration component input terminal;

And a second additional constant array storage unit for storing constant array data for use in the encryption and decryption processing, the output ends of which are respectively connected to the input ends of the respective data conversion units in the second additional data conversion unit group.

1) cyclically encrypting and decrypting the constant array data used by the data processing device;

2) Arrange in order of address;

3) a third product of a constant array data width and a depth of the constant array storage unit in the cyclic encryption/decryption data processing device, and a constant array data width and depth of the second additional constant array storage unit in the second additional encryption/decryption data processing device a quad product, the sum of the third product and the fourth product is 1024; the width of the constant array data in the second additional constant array storage unit is the number of data conversion components in the second additional data conversion component group multiplied by 32, The depth of the constant array data in the second additional constant array storage unit is one.

a second additional data registering component for registering a result of the cyclic encryption/decryption data processing process; the second additional data conversion component group being constituted by a data conversion component or by two or more data conversion components sequentially connected in series, The second additional data conversion component group input is terminated to the second additional data a register component output end, the second additional data conversion component group output end is connected to the second additional data register component input end;

The constant array data stored by the first additional constant array storage unit and the second additional constant array storage unit satisfies the following conditions:

1) the first additional constant array storage unit stores result data obtained by key expansion processing; and the second additional constant array storage unit stores result data obtained by key expansion processing;

2) Arrange in order of address;

3) a fifth product of a constant array data width and a depth of the constant array storage unit in the cyclic encryption/decryption data processing device, and a constant array data width and depth of the first additional constant array storage unit in the first additional encryption/decryption data processing device a sixth product, a seventh additional product of a constant array data width and a depth of the second additional constant array storage unit in the second additional encryption/decryption data processing device, wherein the sum of the fifth product, the sixth product, and the seventh product is 1024 The width of the constant array data in the first additional constant array storage unit is the number of data conversion units in the first additional data conversion unit group multiplied by 32, and the depth of the constant array data in the first additional constant array storage unit a width of the constant array data in the second additional constant array storage unit is the number of data conversion components in the second additional data conversion component group multiplied by 32, and the second additional constant array storage component constant array data The depth is 1.

The data registering component is a data temporary storage device that transmits input data to the output terminal at the time of the upper edge or the lower edge of the clock, and the data of the output terminal does not change at other times; the data conversion component group and the first additional data The data conversion unit in the conversion component group and the second additional data conversion component group is a data processing device that performs data processing in accordance with a cryptographic algorithm and performs synthesis replacement as defined by only one cryptographic algorithm in the operation.

The device for realizing the SMS4 encryption and decryption algorithm of the present invention can reduce the number of cycles of data conversion processing by arranging the constant array and setting the corresponding data conversion component. Since the amount of data encrypted and decrypted per unit time is greatly increased, the efficiency of encryption and decryption is improved. For example, encrypting 128-bit data, With four data conversion components, the final data processing result can be output by running only 8 clock cycles. Therefore, in the case of the same clock frequency, the encryption efficiency can be increased by 4 times.

The device for realizing the SMS4 encryption and decryption algorithm of the present invention, in the case that the required encryption and decryption efficiency is satisfied, since the clock frequency is only the original 1/n, the clock frequency only needs the original l/n. For example, to encrypt 128-bit data, if four data conversion components are used, the clock frequency is only 1/4 of the original.

In addition, in the case of the same processing efficiency, the design and implementation of the integrated circuit implementing the inventive scheme are relatively easy; the signal integrity is greatly optimized; and the design cost is reduced. In addition, with the integrated circuit designed by the present invention, the clock frequency is only 1/n, and the clock frequency only needs the original l/n, when the required encryption and decryption efficiency is satisfied. PCB cost is reduced with the same processing efficiency; PCB design and product are easy to implement; interference in the system is reduced, and the impact on the normal and efficient operation of other devices and devices is greatly reduced.

DRAWINGS

1 is a schematic structural diagram of cyclic encryption and decryption data processing according to an embodiment of the present invention;

2 is a schematic structural diagram of data processing of cyclic encryption and decryption according to Embodiment 2 of the present invention;

FIG. 3 is a schematic structural diagram of the process of adding additional encryption and decryption data before the data processing of the cyclic encryption/decryption according to the embodiment of the present invention; FIG.

4 is a schematic structural diagram of processing of adding and decrypting data after cyclic data processing in accordance with an embodiment of the present invention;

FIG. 5 is a schematic structural diagram of the process of adding additional encryption and decryption data before and after the cyclic data is processed and decrypted according to the fifth embodiment of the present invention.

DESCRIPTION OF REFERENCE NUMERALS: 1 data registering component, 2 - data conversion component group, 3 - constant array storage component, 4 - cyclic encryption and decryption data processing device; 21 - first additional data conversion component group, 22 - second additional data Conversion component group; 101 - first additional data registration component, 102 - second additional data registration component; 200 - first data conversion component, 201 - second data conversion component, 202 - third data conversion component, 203 - fourth Data conversion component; 210 - first additional data conversion component, 211 - second additional data conversion component; 220 - third additional data conversion component, 221 - fourth additional data conversion component; 301 - first additional constant array storage component, 302 - a second additional constant array storage component; 501 - a first additional encryption and decryption data processing device, 502 - a second additional encryption and decryption data processing device. detailed description Referring to FIG. 1, a schematic structural diagram of cyclic encryption and decryption data processing according to an embodiment of the present invention is shown. As shown in FIG. 1, it mainly includes: a data registering component 1, a constant array storage component 3, and a data conversion component group 2; wherein:

The data register unit 1 is used to register external data and the result of the last data conversion process, and a general-purpose flip-flop such as a D flip-flop, a JK flip-flop, or the like can be used. This type of general-purpose flip-flop is a data temporary storage device that transfers data at the data input end to the output of the flip-flop at the upper or lower edge of the clock, and the data at the output of the flip-flop does not change at other times. During the same data conversion processing cycle, the data registered by the data registration unit 1 is unchanged.

The data conversion component group 2 is a component that performs data processing in accordance with a cryptographic algorithm. For example, data processing is performed in accordance with the national SMS4 cryptographic algorithm, and the data conversion component group 2 performs only one synthetic interrupt per stipulated by the cryptographic algorithm.

The constant array storage unit 3 is for storing constant array data. The constant array used in the present invention is the result data obtained by the key expansion process, arranged in order of address level, and the width and depth corresponding to the constant array are arranged according to the number of data conversion components in the data conversion component group 2, and the width and the depth are The product is 1024. For example, with four data conversion components, the constant array has a width of 128 bits and a depth of 8. With eight data conversion components, the constant array has a width of 256 bits and a depth of four.

When the number of data conversion units in the data conversion unit group 2 of the present invention is a divisor of 32, it is preferable to use a structure in which only cyclic encryption/decryption data is processed.

Referring to Fig. 2, in the cyclic encryption/decryption data processing of the present invention, the input end of the data registering component 1 is connected to the input terminal of the external data, and the output terminal of the data registering component 1 is connected to the data conversion component group 2, and the output of the constant array storage section 3 The terminals are respectively connected to the respective data conversion sections of the data conversion component group 2, that is, the input ends of the first data conversion component 200, the second data conversion component 201, the third data conversion component 202, and the fourth data conversion component 203. The respective data conversion sections 200 - 203 are sequentially connected in series, and the output thereof is input to the input terminal of the data registration section 1. The data conversion unit group 2 is composed of at least two data conversion units which are sequentially connected in series.

The data conversion unit group 2 takes four data conversion units 200 - 203 as an example, and has a constant array width of 128 bits and a depth of 8, and performs encryption and decryption processing by means of cyclic encryption and decryption data processing. The process is as follows:

1) Prepare a constant array; The constant array is stored in the constant array storage unit 3. If there are four data conversion processing units in the data conversion processing, the constant array has a width of 128 bits and a depth of 8. The 128-bit constant array data is divided into 8 lines corresponding to the depth 8, and each line is named rkO, rkl ₅ ... rk7; the constant array data of 128 bits per line is divided into four 32-bit data. rkO is divided into rk0a, rk0b, rk0c, rkOd; rkl is divided into rkla, rklb, rklc, rkld.

2) inputting external data to the input end of the data storage unit 1;

The external data is 128-bit data, which is divided into four 32-bit data, named A0, Al, A2, and A3. On the upper or lower edge of the clock, the data at the input of the data register unit 1 is transferred to the output of the data register unit 1, and the data register unit 1 outputs 128 bits, which are divided into four pieces of 32-bit data, which are named a0, al, a2, respectively. , a3.

3) Perform the first data conversion process;

In the clock cycle, the data corresponding to the first row of the constant array stored in the constant array storage unit 3 is respectively output to all of the data conversion sections 200 - 203. In the same clock cycle, the data of the output of the data registration unit 1 is input to the first data conversion unit 200 for data conversion processing; the data output by the first data conversion unit 200 is input to the next data conversion unit, that is, the second data conversion unit 201. Data conversion processing; in this manner, until all the data conversion sections, that is, the data conversion sections 200-203, sequentially perform the data conversion processing. details as follows:

The data a0, a1, a2, a3 at the output of the data register unit 1 and the data rkOa output from the constant array storage unit 3 are input to the first data conversion unit 200, and the converted data is still 128 bits, and are named B0, Bl, B2, respectively. , B3;

The data B0, Bl, B2, B3 output by the first data conversion unit 200 and the data rkOb outputted by the constant array storage unit 3 are input to the second data conversion unit 201, and the converted data is still 128 bits, respectively named C0, Cl. , C2, C3;

The data C0, Cl, C2, C3 outputted by the second data conversion unit 201 and the data rkOc outputted by the constant array storage unit 3 are input to the third data conversion unit 202, and the converted data is still 128 bits, respectively named D0, Dl. , D2, D3;

The data D0, D1, D2, D3 output by the third data conversion unit 202 and the data rkOd output from the constant array storage unit 3 are input to the fourth data conversion unit 203, and the converted data is still 128 bits, respectively named E0, El. , E2, E3; E0, El, E2, and E3 are the result data of the first data conversion process.

4) performing data conversion processing again;

At the time when the clock edge arrives, the data E0, El, E2, E3 of the previous data conversion processing are stored in the data registration unit 1; the output data e0, el, e2, e3 of the data registration unit 1 are sequentially input to the data conversion unit. 200 - 203 „ The data rkla, rklb, rklc, rkld corresponding to the next row of the constant array stored in the constant array storage unit 3 are input to the data conversion sections 200 - 203, respectively.

5) Repeat the data conversion process again to obtain the encryption and decryption data processing result. Once again, the data conversion process is performed once, that is, a data conversion processing cycle is completed. The data conversion processing is processed again six times, that is, the number is performed eight times in total, and the data output after the last data conversion processing is the final data processing result.

When two data conversion units are used, the cyclic encryption/decryption data processing performs a total of 16 clock cycles to complete the encryption and decryption processing. When eight data conversion components are used, the cyclic encryption/decryption data processing performs a total of four clock cycles to complete the encryption and decryption process. When sixteen data conversion units are used, the cyclic encryption/decryption data processing performs a total of two clock cycles to complete the encryption and decryption processing.

The additional encryption/decryption data processing is used to supplement the completion of the cyclic encryption/decryption data processing 4, and the data conversion processing is not completed, especially when the number of data conversion components in the data conversion component group 2 is not a divisor of 32, the data can be encrypted and decrypted by cyclic The process 4 performs data conversion processing together with the additional encryption and decryption data processing.

Referring to Fig. 3, the input end of the cyclic encryption/decryption data processing device 4 is connected to the first additional encryption/decryption data processing device 501 for supplementing the data conversion processing that is not completed by the cyclic encryption/decryption data processing device 4. The first additional encryption/decryption data processing device 501 is mainly composed of a first additional data registration unit 101 for registering external data, and the input terminal is connected to the output end of the first additional data registration unit 101, and the output terminal is connected to the cyclic encryption/decryption data processing device 4. The first additional data conversion component group 21 at the input end and the output terminal are connected to the first additional constant array storage component 301 at the input end of the first additional data conversion component group 21. The first additional data conversion component group 21 can be constructed by one, two or more data conversion components which are sequentially connected in series. The outputs of the first additional constant array storage unit 301 are respectively coupled to the input terminals of each of the data conversion units 210, 211, ... in the additional data conversion unit group 21. The constant array stored by the first additional constant array storage unit 301 is a data array that satisfies the following conditions:

1) result data obtained by key expansion processing; 2) Arrange in order of address;

3) a first product of the constant array data width and depth of the constant array storage unit 3 in the cyclic encryption/decryption data processing device 4, and a constant array data width of the first additional constant array storage unit 301 in the first additional encryption/decryption data processing device 501 a second product of the depth, the sum of the first product and the second product is 1024; the width of the constant array data in the first additional constant array storage unit 3Q1 is the data conversion in the first additional data conversion unit group 21 The number of components is multiplied by 32, and the depth of the constant array data in the first additional constant array storage section 301 is 1.

The process of data processing by the first additional encryption/decryption data processing device 501 is as follows:

1) The external data is input to the input terminal of the data register unit 1, and the data of the input terminal of the data register unit 1 is transferred to the output terminal of the data register unit 1 at the upper or lower edge of the clock.

2) In the clock cycle, the data corresponding to the constant array stored in the first additional constant array storage unit 301 is respectively input to all the data conversion units 210, 211 and the like in the first additional encryption/decryption data processing device 501.

3) In the same clock cycle, the data of the output of the data registration unit 1 is input to the first additional data conversion unit 210 for data conversion processing; the data output by the first additional data conversion unit 210 is input to the next data conversion unit, that is, The second additional data conversion unit 211 performs data conversion processing; in this manner, until all the additional data conversion units in the first additional data conversion unit group 21 in the first additional encryption/decryption data processing unit 501 sequentially complete the data conversion processing. The data processing result of the first additional encryption/decryption data processing device 501.

4) The processing result of the first additional encryption/decryption data processing means 501 is used as external data in the cyclic encryption/decryption data processing for completing the cyclic encryption/decryption data processing.

Referring to Fig. 4, a second additional encryption/decryption data processing means 502 is provided at the output of the cyclic encryption/decryption data processing 4 for supplementing the data conversion processing which is not completed by the processing cyclic encryption/decryption data processing apparatus 4. The second additional encryption/decryption data processing means 502 is mainly composed of a second additional data registration means 102 for registering the result of the cyclic encryption/decryption data processing 4, and a second additional data conversion means which is connected to the output of the second additional data registration means 102. The group 22 is configured to be coupled to a second additional constant array storage component 302 at the input of the second additional data conversion component group 22. The second additional data conversion component group 22 may be constituted by one data conversion component or by two or more data conversion components sequentially connected in series. The output of the second additional constant array storage unit 302 and the second additional data conversion unit The inputs of each of the data conversion sections 220, 221, ... in the set 22 are coupled. The constant array stored by the second additional constant array storage unit 302 is a data array that satisfies the following conditions:

1) cyclically encrypting and decrypting the constant array data used by the data processing device 4;

2) Arrange in order of address;

3) a third product of the constant array data width and depth of the constant array storage unit 3 in the cyclic encryption/decryption data processing device 4, and a constant array data width of the second additional constant array storage unit 302 in the second additional encryption/decryption data processing device 502 a fourth product of the depth, the sum of the third product and the fourth product is 1024; the width of the constant array data in the second additional constant array storage unit 302 is the data conversion in the second additional data conversion unit group 22 The number of components is multiplied by 32, and the depth of the constant array data in the second additional constant array storage section 302 is one.

The process of data processing by the second additional encryption/decryption data processing means 502 is similar to that of the first additional encrypted data processing means 501, which performs conversion processing on the data processed by the cyclic encryption/decryption data processing means 4. The data processing result of the second additional encryption/decryption data processing means 502 is the final encryption/decryption data processing result. The data conversion processing means in the first additional encryption/decryption data processing means 501 or the second additional encryption/decryption data processing means 502 may be one, two or more.

The additional encryption/decryption data processing means may be added before or after the cyclic encryption/decryption data processing means 4, or may be added before and after the cyclic encryption/decryption data processing means 4, see Fig. 5. The constant array stored by the first additional constant array storage unit 301 and the second additional constant array storage unit 302 in the structure is a data array that satisfies the following conditions:

1) the first additional constant array storage unit 301 stores result data obtained by key expansion processing; and the second additional constant array storage unit 302 stores result data obtained by key expansion processing;

2) Arrange in order of address;

3) a fifth product of the constant array data width and depth of the constant array storage unit 3 in the cyclic encryption/decryption data processing device 4, and a constant array data width of the first additional constant array storage unit 301 in the first additional encryption/decryption data processing device 501 a sixth product of depth, a seventh product of a constant array data width and a depth of the second additional constant array storage unit 302 in the second additional encryption/decryption data processing device 502, the fifth product, the sixth product, and the seventh product The sum of the three is 1024; the width of the constant array data in the first additional constant array storage unit 301 is the first additional data conversion component group The number of data conversion components in 21 is multiplied by 32, the depth of the constant array data in the first additional constant array storage unit 301 is 1; the width of the constant array data in the second additional constant array storage unit 302 is the second The number of data conversion sections in the additional data conversion component group ² 2 is multiplied by 32, and the depth of the constant array data in the second additional constant array storage section 302 is 1.

The device for realizing the SMS4 encryption and decryption algorithm of the present invention can reduce the number of cycles of data conversion processing by arranging the constant array and setting the corresponding data conversion unit. Since the amount of data added and decrypted per unit time is greatly increased, the efficiency of encryption and decryption is improved. For example, to encrypt 128-bit data, if four data conversion components are used, it is only necessary to cycle through 8 clock cycles to output the final data processing result. Therefore, when the clock frequency is the same, the encryption efficiency can be increased by 4 times.

The device for realizing the SMS4 encryption and decryption algorithm of the present invention, in the case of satisfying the required encryption and decryption efficiency, requires only the original l/n because the clock frequency is only 1/n of the original. For example, to encrypt 128-bit data, if four data conversion components are used, the clock frequency is only 1/4 of the original.

The above embodiments are intended to illustrate and solve the principles of the present invention. It is to be understood that the specific embodiments of the present invention are not limited thereto. Various changes and modifications may be made without departing from the spirit and scope of the invention. Accordingly, the scope of the invention is defined by the claims.

Claims

Rights request

An apparatus for implementing an SMS4 encryption and decryption algorithm, comprising:

a cyclic encryption/decryption data processing device (4) comprising a data registering component (1), a data conversion component group (2) and a constant array storage component (3);

The data registering component (1) is configured to register external data and a result of a previous data conversion process;

The data conversion component group (2) is composed of at least two data conversion components serially connected in series, and the data conversion component input terminal is connected to the output end of the data registration component (1), and the data conversion component output terminal is connected to the data registration. The input of component (1);

The constant array storage unit (3) is configured to store constant array data for encryption and decryption processing, and an output end thereof is respectively connected to an input end of each of the data conversion unit groups (2).

The apparatus for implementing an SMS4 encryption/decryption algorithm according to claim 1, wherein: said constant array data satisfies the following conditions:

1) result data obtained by key expansion processing;

2) Arrange in order of address;

3) arranging the width and depth corresponding to the array according to the number of data conversion components in the data conversion component group (2);

4) The product of width and depth is 1024.

The apparatus for implementing an SMS4 encryption/decryption algorithm according to claim 1 or 2, wherein: the number of data conversion components of the data conversion component group (2) in the cyclic encryption/decryption data processing device (4) It is the approximate number of 32.

The device for implementing the SMS4 encryption and decryption algorithm according to claim 1, further comprising: a first additional encryption and decryption data processing device (501), and the cyclic encryption/decryption data processing device (4) The input end is connected to supplement the data conversion processing of the cyclic encryption/decryption data processing device (4); the first additional encryption/decryption data processing device (501) includes: a first additional data registration unit (101), for registering external data;

The first additional data conversion component group (21) is composed of a data conversion component or two or more data conversion components sequentially connected in series, and the first additional data conversion component group (21) is input to the first terminal. An additional data registering component (101) output, the first additional data conversion component group (21) The output end of the loop access encryption and decryption data processing device (4);

a first additional constant array storage unit (301) for storing constant array data for use in the encryption and decryption process, the output ends of which are respectively associated with the input ends of the respective data conversion components in the first additional data conversion component group (21) Pick up.

The apparatus for implementing the SMS4 encryption and decryption algorithm according to claim 4, characterized in that: the constant array data stored by the constant array storage unit (301) satisfies the following conditions:

1) result data obtained by key expansion processing;

2) Arrange in order of address;

3) a first product of a constant array data width and a depth of the constant array storage unit (3) in the cyclic encryption/decryption data processing device (4), and a first additional constant array storage unit in the first additional encryption/decryption data processing device (501) a second product of a constant array data width and a depth of (301), a sum of the first product and the second product is 1024; a width of the constant array data in the first additional constant array storage unit (301) is a first addition The number of data conversion sections in the data conversion component group (21) is multiplied by 32, and the depth of the constant array data in the first additional constant array storage section (301) is 1.

The apparatus for implementing an SMS4 encryption/decryption algorithm according to claim 1, further comprising: a second additional encryption/decryption data processing device (502), and the cyclic encryption/decryption data processing device (4) And the output of the second encryption and decryption data processing device (502) is:

a second additional data registration unit (102) for registering a result of the cyclic encryption/decryption data processing (4) processing;

The second additional data conversion component group (22) is composed of a data conversion component, or two or more data conversion components sequentially connected in series, and the second additional data conversion component group (22) is terminated at the second input. An output of the additional data registration unit (102), the output of the second additional data conversion unit group (22) is connected to the input end of the second additional data registration unit (102);

a second additional constant array storage unit (302) for storing constant array data for encryption and decryption processing, the output ends of which are respectively associated with the input ends of the data conversion units of the second additional data conversion unit group (22) Pick up.

The apparatus for implementing an SMS4 encryption/decryption algorithm according to claim 6, wherein: the constant array data stored by the constant array storage unit (302) satisfies the following conditions: 1) cyclically encrypting and decrypting the constant array data used by the data processing device (4);

2) Arrange in the order of address high ^ ί;

3) a third product of the constant array data width and depth of the constant array storage unit (3) in the cyclic encryption/decryption data processing device (4), and a second additional constant array storage unit in the second additional encryption/decryption data processing device (502) (302) a constant array data width and a fourth product of the depth, the sum of the third product and the fourth product is 1024; the width of the constant array data in the second additional constant array storage unit (302) is a second addition The number of data conversion sections in the data conversion component group (22) is multiplied by 32, and the depth of the constant array data in the second additional constant array storage section (302) is one.

The device for implementing the SMS4 encryption and decryption algorithm according to claim 4, further comprising: a second additional encryption and decryption data processing device (502), and the cyclic encryption/decryption data processing device (4) And the output of the second encryption and decryption data processing device (502) is:

The second additional data conversion component group (22) is composed of a data conversion component, or two or more data conversion components sequentially connected in series, and the second additional data conversion component group (22) is terminated at the second input. An output of the additional data registering component (102), and an output of the second additional data conversion component group (22) is coupled to the input end of the second additional data register component (102);

9. The apparatus for implementing an SMS4 encryption and decryption algorithm according to claim 8, wherein: said constant array data stored by said first additional constant array storage unit (301) and said second additional constant array storage unit (302) Meet the following pieces:

1) the first additional constant array storage unit (301) stores result data obtained by key expansion processing; and the second additional constant array storage unit (302) stores results obtained by key expansion processing. Data

2) Arrange in order of address;

3) Constant array of constant array storage unit (3) in the cyclic encryption/decryption data processing device (4) a fifth product of the data width and the depth, a sixth product of the constant array data width and the depth of the first additional constant array storage unit (301) in the first additional encryption/decryption data processing device (501), and a second additional encryption and decryption data processing a seventh product of a constant array data width and a depth of the second constant array storage unit (302) in the device (502), wherein the sum of the fifth product, the sixth product, and the seventh product is 1024; The width of the constant array data in an additional constant array storage unit (301) is the number of data conversion units in the first additional data conversion unit group (21) multiplied by 32, the first additional constant array storage unit (301) The depth of the constant array data is 1; the width of the constant array data in the second additional constant array storage unit (302) is the number of data conversion components in the second additional data conversion component group (22) multiplied by 32, The depth of the constant array data in the second additional constant array storage unit (302) is one.

10. The apparatus for implementing an SMS4 encryption/decryption algorithm according to claim 1 or 5 or 7, wherein: said data registering component (1) transmits input data to an output at a time of a clock edge or a lower edge. a data temporary storage device in which the output data does not change at other times; in the data conversion component group (2), the first additional data conversion component group (21), and the second additional data conversion component group (22) The data conversion unit is a data processing device that performs data processing in accordance with a cryptographic algorithm and performs synthesis replacement as defined by only one cryptographic algorithm in the operation.