WO2020034525A1 - 一种阵列基板驱动电路的测试方法及显示面板 - Google Patents

一种阵列基板驱动电路的测试方法及显示面板 Download PDF

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Publication number
WO2020034525A1
WO2020034525A1 PCT/CN2018/122615 CN2018122615W WO2020034525A1 WO 2020034525 A1 WO2020034525 A1 WO 2020034525A1 CN 2018122615 W CN2018122615 W CN 2018122615W WO 2020034525 A1 WO2020034525 A1 WO 2020034525A1
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Prior art keywords
test
signal line
drive signal
terminal
driving
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French (fr)
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宋乔乔
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays

Definitions

  • the present application relates to the field of display technology, and in particular, to a test method for an array substrate driving circuit and a display panel.
  • GOA Gate-driver On Array
  • the inventor of the present application has found in long-term research and development that the implementation of the scanning signal output of the existing GOA products requires multiple sets of signals and circuits to be completed together; because the output of the scanning signals requires multiple sets of GOA signals, the detection process in the array substrate process needs Add multiple test terminals to provide input signals to the display panel for testing; however, as the requirements for products become higher and higher, GOA signals are gradually increasing, which makes the array substrate test need to design multiple sets of test terminals. Pins increase, which greatly increases the cost of the array substrate test fixture.
  • the test of the array substrate requires designing multiple sets of test terminals, and the pins of the machine test fixture increase, which greatly increases the cost of the array substrate test fixture.
  • the main problem solved by this application is to provide a test method and display panel for an array substrate drive circuit, which can complete the test of the drive circuit by using fewer test terminals than the number of drive signal lines, saving test terminals and production costs.
  • the technical solution adopted in the present application is to provide a test method for an array substrate driving circuit.
  • the method includes: connecting one driving signal to one of a plurality of test signal lines drawn from the test terminals of the array substrate. Input signal to the test terminal for testing; disconnect the recently tested test signal cable from the drive signal cable; connect another test signal cable to another drive signal cable and input a signal to the test terminal for testing; return The step of disconnecting the recently tested test signal line from the drive signal line until the test is completed; at least one of the connection structures between the test signal line and the drive signal line is a welded structure, and / or at least There is a blown or cut structure between the test signal line and the driving signal line.
  • another technical solution adopted in the present application is to provide a test method for an array substrate driving circuit, the method comprising: connecting one of a plurality of test signal lines drawn from the test terminals of the array substrate to one Drive the signal line to input signals to the test terminal for testing; disconnect the recently tested test signal line from the drive signal line; connect another test signal line to another drive signal line and input signals to the test terminal for testing ; Return to the step of disconnecting the recently tested test signal line from the drive signal line until the test is completed.
  • a display panel which includes: a substrate, a pixel circuit, a plurality of driving signal lines, and a plurality of test signal lines; the pixel circuit is located in a display area on a side of the substrate; The driving signal line is located on the substrate on the same side as the pixel circuit and extends from the non-display area to the display area on the periphery of the substrate. The driving signal line is connected to the pixel circuit; the test signal line is located on the substrate on the same side as the pixel circuit.
  • the signal line is designed to be connected to a driving signal line to test the pixel circuit;
  • the connection structure between at least one test signal line and the driving signal line is a soldering structure, and / or at least one test signal line and the driving signal There are blown or cut structures between the lines.
  • the beneficial effect of the present application is that the test terminals of the array substrate in the present application are connected to a plurality of test signal lines.
  • one of the plurality of test signal lines connected to the test terminal is connected to a driving signal line, and an external
  • the test probe inputs signals to the test terminals for testing; and then repeats: disconnect the test signal line that has been recently tested from the drive signal line, and connect another test signal line to another drive signal line.
  • the test terminal inputs signals for the test operation until the test is completed; the test of the drive circuit is completed by using fewer test terminals than the number of drive signal lines, saving test terminals and production costs.
  • FIG. 1 is a schematic diagram of a connection between a signal line and a test terminal in the prior art.
  • FIG. 2 is a schematic flowchart of a first embodiment of a test method for an array substrate driving circuit provided by the present application.
  • FIG. 3 is a schematic diagram of a connection between a driving signal line and a test terminal corresponding to step 21 in FIG. 2.
  • FIG. 4 is a schematic diagram of a connection between a driving signal line and a test terminal corresponding to steps 22 and 23 in FIG. 2.
  • FIG. 5 is a schematic flowchart of a second embodiment of a test method for an array substrate driving circuit provided by the present application.
  • FIG. 6 is a schematic diagram of a connection between a driving signal line and a test terminal when a high vertical alignment curing process is performed in a second embodiment of a test method for an array substrate driving circuit provided in the present application.
  • FIG. 7 is a schematic diagram of a connection between a driving signal line and a test terminal after a high vertical alignment curing process is completed in a second embodiment of a test method for an array substrate driving circuit provided in the present application.
  • FIG. 8 is a schematic flowchart of a third embodiment of a test method for an array substrate driving circuit provided by the present application.
  • FIG. 9 is a schematic diagram of a connection between a driving signal line and a test terminal corresponding to step 81 in FIG. 8.
  • FIG. 10 is a timing chart of driving signals in a third embodiment of a test method of an array substrate driving circuit provided by the present application.
  • FIG. 11 is a schematic diagram of a connection between a driving signal line and a test terminal corresponding to steps 82 and 83 in FIG. 8.
  • FIG. 12 is a schematic flowchart of a fourth embodiment of a test method for an array substrate driving circuit provided by the present application.
  • FIG. 13 is a schematic diagram of a connection between a driving signal line and a test terminal corresponding to step 121 in FIG. 12.
  • FIG. 14 is a schematic diagram of a connection between a driving signal line and a test terminal corresponding to steps 122 and 123 in FIG. 12.
  • FIG. 15 is a schematic structural diagram of an embodiment of a display panel provided in the present application.
  • FIG. 16 is another schematic structural diagram of a display panel in an embodiment of a display panel provided by the present application.
  • the signals of the existing product array substrate test mainly include data signals (Blue, Green, and Red), GOA signals, and common signals (ACOM and CFCOM); GOA signals mainly include multiple sets of high-frequency clock signals; VSS It is a low-potential DC signal.
  • LC1 and LC2 are a set of low-frequency AC signals. They are input source signals and realize the output of scanning signals under the action of the GOA circuit. In order to improve the charging capacity of the gate, increase the continuous transmission of the gate.
  • the clock signal gradually increases, from 2CK to 4CK (Clock, clock), 6CK, 8CK, or 12CK, etc., resulting in the number of array substrate test terminals gradually increased; take 6CK as an example, at least 16 test terminals, this requires The number of test fixtures for array substrates has increased, which has greatly increased costs.
  • FIG. 2 is a schematic flowchart of a first embodiment of a test method for an array substrate driving circuit provided by the present application. The method includes:
  • Step 21 One of the plurality of test signal lines 32 drawn from the test terminals 31 of the array substrate is connected to a drive signal line 33, and a signal is input to the test terminals 31 for testing.
  • the driving signal line 33 may be a clock signal line, and the driving circuit may be a GOA circuit 34. As shown in FIG. 3, there are four clock signal lines (CK1, CK2, CK3, and CK4). In order to save the test terminal 31, multiple test signals are provided.
  • the line 32 is connected to the same test terminal 31. When a test is performed, one of the test signal lines 32 is connected to the drive signal line 33 (CK1).
  • the driving signal line 33 is connected to the GOA circuit 34, and the external jig probe 35 is connected to the test terminal 31 to input a desired signal to the GOA circuit 34, so that the output scanning signal in the GOA circuit 34 is used to light up the display panel and pass the analysis A defective position is detected on the screen of the display panel.
  • Step 22 Disconnect the test signal line 32 and the drive signal line 33 that have been recently tested.
  • test signal lines 32 are connected to the same test terminal 31, when testing whether the GOA circuit 34 connected to another drive signal line 33 is working normally, it is necessary to firstly test the test signal line 32 and the drive signal line 33 that have been recently tested. Disconnected to avoid duplicate testing.
  • Step 23 Connect another test signal line 32 to another drive signal line 33, and input a signal to the test terminal 31 for testing.
  • test signal line 32 After the connection between the recently tested test signal line 32 and the drive signal line 33 is disconnected, as shown in FIG. 4, another test signal line 32 is connected to another drive signal line 33 (CK2), and then an external The jig probe 35 inputs a signal to the test terminal 31 for testing.
  • CK2 drive signal line 33
  • Step 24 Return to the step of disconnecting the recently-tested test signal line 32 from the drive signal line 33 until the test is completed.
  • step 22 and step 23 are repeatedly performed until the test is completed.
  • this embodiment provides a test method for an array substrate driving circuit.
  • the test terminal 31 of the array substrate is connected to a plurality of test signal lines 32.
  • the plurality of test signal lines 32 connected to the test terminal 31 are connected.
  • One of them is connected to a driving signal line 33, and an external test probe 35 is used to input a signal to the test terminal 31 for testing; then it is repeatedly executed: the connection between the recently tested test signal line 32 and the driving signal line 33 is disconnected And connect another test signal line 32 to another drive signal line 33, and input a signal to the test terminal 31 to perform a test operation until the test is completed; the drive circuit is completed by using fewer test terminals 31 than the number of the drive signal lines 33 Test, saving test terminal 31 and production cost.
  • FIG. 5 is a schematic flowchart of a second embodiment of a test method for an array substrate driving circuit provided by the present application. The method includes:
  • Step 51 One of the plurality of test signal lines 62 drawn from the test terminal 61 of the array substrate is connected to a driving signal line 63, and a signal is input to the test terminal 61 for testing.
  • Step 52 Disconnect the test signal line 62 and the drive signal line 63 that have been recently tested.
  • Step 53 Connect another test signal line 62 to another drive signal line 63, and input a signal to the test terminal 61 for testing.
  • Step 54 Return to the step of disconnecting the recently-tested test signal line 62 from the drive signal line 63 until the test is completed.
  • Steps 51-54 are similar to steps 11-14 in the first embodiment, and details are not described herein again.
  • the number of test terminals 61 is at least two, and the number of test signal lines 62 is equal to the number of drive signal lines 63.
  • Circuit breakpoints are set on the test signal lines 62, and solder point 64 is preset on the circuit breakpoints, as shown in Figure 6.
  • the test signal line 62 and the driving signal line 63 are connected by the welding point 64 on the breaking point of the welding circuit; the welding point 64 on the breaking point of the laser welding circuit can be used to make the driving signal line 63 and the testing signal line 62 are connected to form a path.
  • Step 55 After the test is completed, one of the plurality of test signal lines 62 drawn from the test terminals 61 of the array substrate is connected to all the drive signal lines 63 to perform a high vertical alignment curing process.
  • one of the plurality of test signal lines 62 drawn from the test terminals 61 of the array substrate is connected to all the drive signal lines 63 to perform high vertical alignment curing (High Vertical Alignment Curing (HVA) process; as shown in FIG. 6, the fourth test signal line 62 is connected to all driving signal lines 63, and the remaining test signal lines 62 are disconnected from the driving signal line 63.
  • HVA High Vertical Alignment Curing
  • Step 56 After the high vertical alignment curing process is completed, the test signal line 62 and the driving signal line 63 are disconnected.
  • the connection between the test signal line 62 and the driving signal line 63 is disconnected, so that the driving signal line can work normally after the display panel is sold.
  • this embodiment provides a method for testing an array substrate driving circuit.
  • a plurality of test signal lines 62 are provided on the test terminal 61 of the array substrate, and a soldering point 64 is provided on the test signal line 62.
  • the test signal line 62 is connected to the driving signal line 63 by welding different welding point positions 64, which improves the utilization rate of the test terminal 61 and saves the test terminal. 61 and production costs.
  • FIG. 8 is a schematic flowchart of a third embodiment of a method for testing an array substrate driving circuit provided by the present application.
  • the method includes:
  • Step 81 Connect the first test signal line from the first test terminal 91 to the first drive signal line, and connect the fourth test signal line from the second test terminal 92 to the fourth drive signal line.
  • the test terminal 91 and the second test terminal 92 input signals for testing.
  • the signal S1 input to the first test terminal 91 and the signal S2 input to the second test terminal 92 have opposite potentials, as shown in FIG. 10.
  • the first test signal line drawn from the first test terminal 91 is connected to the first driving signal line.
  • the fourth test signal line from the two test terminals 92 is connected to the fourth drive signal line.
  • the external fixture probe 93 is used to input signals to the first test terminal 91 and the second test terminal 92 for testing, as shown in FIG. 9. Show.
  • Step 82 Disconnect the first test signal line and the first drive signal line after the test, and disconnect the fourth test signal line and the fourth drive signal line after the test.
  • Step 83 Connect the second test signal line from the first test terminal 91 to the second drive signal line, and connect the fifth test signal line from the second test terminal 92 to the fifth drive signal line.
  • the test terminal 91 and the second test terminal 92 input signals for testing.
  • Step 84 Disconnect the second test signal line and the second drive signal line after the test, and disconnect the fifth test signal line and the fifth drive signal line after the test.
  • Step 85 Repeat the above steps until all the driving signal lines are tested.
  • this embodiment provides a test method for an array substrate driving circuit.
  • the test connected to each test terminal is first performed during the test.
  • One of the signal lines is connected to a driving signal line, and after the test is completed, the connection between the test signal line and the driving signal line is cut off, the test terminals are reused, the utilization rate of the test terminals is improved, and fewer tests are used.
  • the terminal completed the test of the GOA circuit, saving test terminals and production costs.
  • FIG. 12 is a schematic flowchart of a fourth embodiment of a method for testing an array substrate driving circuit provided by the present application. The method includes:
  • Step 121 Connect the first test signal line from the test terminal 131 to the first drive signal line, and connect the first test signal line from the test terminal 131 to the fourth drive signal line through the inverter 132 to the test terminal 131 input signals for testing.
  • the first test signal line drawn from the test terminal 131 is connected to the first drive signal line, and the first test signal line is connected to the fourth drive signal line through the inverter 132, and then the test terminal is connected to the test terminal using an external jig probe 133 131 input signals for testing, as shown in Figure 13.
  • Step 122 Disconnect the tested first test signal line from the first drive signal line, and disconnect the tested first test signal line from the fourth drive signal line.
  • Step 123 Connect the second test signal line from the test terminal 131 to the second drive signal line, and connect the second test signal line from the test terminal 131 to the fifth drive signal line through the inverter 132 to the test terminal. 131 input signals for testing.
  • Step 124 Disconnect the tested second test signal line from the second driving signal line, and disconnect the tested second test signal line from the fifth driving signal line.
  • Step 125 Repeat the above steps until all the driving signal lines are tested.
  • step 121 -124 After completing the GOA circuit test on the second driving signal line and the fifth driving signal line, disconnect the second test signal line from the second driving signal line and the fifth driving signal line respectively; then repeat step 121 -124 until all drive signal lines are tested.
  • this embodiment provides a method for testing an array substrate driving circuit.
  • testing a driving circuit first connect one of the test signal lines connected to the test terminal 131 to a driving signal line.
  • another drive signal line is connected through the inverter, and after the test is completed, the connection between the test signal line and the drive signal line is cut, and the test terminal 131 is reused, which improves the utilization of the test terminal 131 and saves the test. Terminals 131 and production costs.
  • FIG. 15 is a schematic structural diagram of an embodiment of a display panel provided in the present application.
  • the display panel includes a substrate 151, a pixel circuit 152, a plurality of driving signal lines 153, and a plurality of test signal lines 154.
  • the substrate 151 is an array substrate, and the pixel circuit 152 is located on the display area 1511 on the side of the substrate 151; the driving signal line 153 is located on the substrate 151 on the same side as the pixel circuit 151, and extends from the non-display area 1512 to the display area 1511 on the periphery of the substrate 151 The driving signal line 153 is connected to the pixel circuit 152.
  • test signal line 154 is located on the substrate 151 on the same side as the pixel circuit 152, and each test signal line 154 is designed to be connected to a driving signal line 153 to test the pixel circuit 152.
  • connection structure between at least one test signal line 154 and the drive signal line 153 is a welding structure, and / or at least one test signal line 154 and the drive signal line 153 have a blown or cut structure.
  • the display panel also includes two test terminals 155, each test terminal 155 is connected to a plurality of test signal lines 154, each test signal line 154 is connected to a drive signal line 153, and each test terminal 155 is connected to an external fixture (figure (Not shown) is connected to input a signal into the test signal line 154 as shown in FIG. 15.
  • the display panel may also include only one test terminal 155.
  • the test terminal 155 is connected to a plurality of test signal lines 154, and each test signal line 154 is connected to two drive signal lines 153.
  • the test terminal 155 is connected to an external fixture to input signals. Into the test signal line 154, as shown in FIG.
  • At least one test signal line 154 and all the drive signal lines 153 have a blown or cut structure to prevent the test signal lines 154 from connecting all the drive signal lines 153 and short-circuit the drive signal lines 153.
  • the display panel provided in this embodiment can test the pixel circuit 152 by using fewer test 155 terminals, reducing the space occupied by the test terminal 155 on the display panel, and reducing the size of the non-display area 1512.
  • the area is conducive to improving the screen-to-screen ratio of the display panel and can also save the cost of manufacturing the test terminal 155.

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Abstract

一种阵列基板驱动电路的测试方法及显示面板，该方法包括将从阵列基板的测试端子中引出的多条测试信号线中的一条连接一条驱动信号线，对测试端子输入信号以进行测试；断开最近测试完的测试信号线与驱动信号线的连接；将另一条测试信号线连接另一条驱动信号线，对测试端子输入信号以进行测试；返回断开最近测试完的测试信号线与驱动信号线的连接的步骤，直至测试完成。通过上述方式，能够利用少于驱动信号线数量的测试端子完成驱动电路的测试，节省了测试端子和生产成本。

Description

一种阵列基板驱动电路的测试方法及显示面板 技术领域
本申请涉及显示技术领域，具体涉及一种阵列基板驱动电路的测试方法及显示面板。
 背景技术
目前阵列栅极驱动（Gate-driver On Array，GOA）技术已经被广泛用于显示面板中，GOA技术可以节省栅极集成电路的成本，也能够缩减显示面板边框的宽度，对现在流行的窄边框设计非常有利，GOA是未来显示面板设计的一个重要技术。
本申请的发明人在长期研发中发现，现有GOA产品实现扫描信号的输出需要多组信号和电路共同完成；由于扫描信号的输出需要多组GOA信号，从而使得阵列基板制程中的检测制程需要增加多个测试端子来给显示面板提供输入信号以便进行检测；但是随着对产品的要求越来越高，GOA信号逐渐增多，使得阵列基板测试需要设计多组测试端子，机台测试治具的引脚增加，从而大大增加阵列基板测试治具的成本。
 技术问题
阵列基板测试需要设计多组测试端子，机台测试治具的引脚增加，而大大增加阵列基板测试治具的成本。
 技术解决方案
本申请主要解决的问题是提供一种阵列基板驱动电路的测试方法及显示面板，能够利用少于驱动信号线数量的测试端子完成驱动电路的测试，节省了测试端子和生产成本。
为解决上述技术问题，本申请采用的技术方案是提供一种阵列基板驱动电路的测试方法，该方法包括：将从阵列基板的测试端子中引出的多条测试信号线中的一条连接一条驱动信号线，对测试端子输入信号以进行测试；断开最近测试完的测试信号线与驱动信号线的连接；将另一条测试信号线连接另一条驱动信号线，对测试端子输入信号以进行测试；返回断开最近测试完的测试信号线与驱动信号线的连接的步骤，直至测试完成；其中至少有一条所述测试信号线与所述驱动信号线之间的连接结构为焊接结构，和/或至少有一条所述测试信号线与所述驱动信号线之间存在烧断或割断结构。
为解决上述技术问题，本申请采用的另一技术方案是提供一种阵列基板驱动电路的测试方法，该方法包括：将从阵列基板的测试端子中引出的多条测试信号线中的一条连接一条驱动信号线，对测试端子输入信号以进行测试；断开最近测试完的测试信号线与驱动信号线的连接；将另一条测试信号线连接另一条驱动信号线，对测试端子输入信号以进行测试；返回断开最近测试完的测试信号线与驱动信号线的连接的步骤，直至测试完成。
为解决上述技术问题，本申请采用的又一技术方案是提供一种显示面板，该显示面板包括：基板、像素电路、若干驱动信号线和若干测试信号线；像素电路位于基板一侧显示区域；驱动信号线位于与像素电路同侧的基板上，且自基板外围的非显示区域延伸至显示区域，驱动信号线与像素电路连接；测试信号线位于与像素电路同侧的基板上，每条测试信号线被设计为与一条驱动信号线连接以对像素电路进行测试；其中至少有一条测试信号线与驱动信号线之间的连接结构为焊接结构，和/或至少有一条测试信号线与驱动信号线之间存在烧断或割断结构。
 有益效果
通过上述方案，本申请的有益效果是：本申请中阵列基板的测试端子与多条测试信号线连接，首先将与测试端子连接的多条测试信号线中的一条连接一条驱动信号线，利用外部测试探针对测试端子输入信号以进行测试；然后重复执行：将最近测试完的测试信号线与驱动信号线之间的连接断开，并将另一条测试信号线连接另一条驱动信号线，对测试端子输入信号以进行测试的操作，直至测试完成；通过利用少于驱动信号线数量的测试端子完成了驱动电路的测试，节省了测试端子和生产成本。
 附图说明
图1是现有技术中信号线和测试端子的连接示意图。
图2是本申请提供的阵列基板驱动电路的测试方法第一实施例的流程示意图。
图3是图2中步骤21对应的驱动信号线和测试端子的连接示意图。
图4是图2中步骤22和步骤23对应的驱动信号线和测试端子的连接示意图。
图5是本申请提供的阵列基板驱动电路的测试方法第二实施例的流程示意图。
图6是本申请提供的阵列基板驱动电路的测试方法第二实施例中进行高垂直排列固化制程时驱动信号线和测试端子的连接示意图。
图7是本申请提供的阵列基板驱动电路的测试方法第二实施例中高垂直排列固化制程完成后驱动信号线和测试端子的连接示意图。
图8是本申请提供的阵列基板驱动电路的测试方法第三实施例的流程示意图。
图9是图8中步骤81对应的驱动信号线和测试端子的连接示意图。
图10是本申请提供的阵列基板驱动电路的测试方法第三实施例中驱动信号时序图。
图11是图8中步骤82和步骤83对应的驱动信号线和测试端子的连接示意图。
图12是本申请提供的阵列基板驱动电路的测试方法第四实施例的流程示意图。
图13是图12中步骤121对应的驱动信号线和测试端子的连接示意图。
图14是图12中步骤122和步骤123对应的驱动信号线和测试端子的连接示意图。
图15是本申请提供的显示面板的一实施例的结构示意图。
图16是本申请提供的显示面板的一实施例中显示面板的另一结构示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性的劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
如图1所示，现有产品阵列基板测试的信号主要包括数据信号（Blue、Green和Red）、GOA信号和公共信号（ACOM和CFCOM）；GOA信号主要包括多组高频的时钟信号；VSS为低电位的直流信号，LC1和LC2是一组低频交流信号，它们为输入源信号，在GOA电路的作用下实现扫描信号的输出；为了提高栅极的充电能力，增大栅极的续传能力，时钟信号逐渐增加，由2CK变成4CK（Clock，时钟）、6CK、8CK或12CK等，导致阵列基板测试端子的数目逐渐增加；以6CK为例，测试端子至少为16个，这就要求阵列基板的测试治具数目增加，大大增加了成本。
参阅图2和图3，图2是本申请提供的阵列基板驱动电路的测试方法第一实施例的流程示意图，该方法包括：
步骤21：将从阵列基板的测试端子31中引出的多条测试信号线32中的一条连接一条驱动信号线33，对测试端子31输入信号以进行测试。
驱动信号线33可以为时钟信号线，驱动电路可以为GOA电路34；如图3所示，时钟信号线有四条（CK1、CK2、CK3和CK4），为了节省测试端子31，将多条测试信号线32连接在同一测试端子31上，在进行测试时，将测试信号线32中的其中一条与驱动信号线33（CK1）连接。
驱动信号线33连接GOA电路34，外部治具探针35与测试端子31连接以向GOA电路34输入所需信号，使得GOA电路34中的输出扫描信号，以将显示面板点亮，并通过分析显示面板的画面检测出不良位置。
步骤22：断开最近测试完的测试信号线32与驱动信号线33的连接。
由于多条测试信号线32连接在同一测试端子31上，在测试另一条驱动信号线33连接的GOA电路34是否正常工作时，需要先将最近测试完的测试信号线32与驱动信号线33的连接断开，以避免重复测试。
步骤23：将另一条测试信号线32连接另一条驱动信号线33，对测试端子31输入信号以进行测试。
在将最近测试完的测试信号线32与驱动信号线33之间的连接断开之后，如图4所示，将另一条测试信号线32连接另一条驱动信号线33（CK2），然后利用外部治具探针35对测试端子31输入信号以进行测试。
步骤24：返回断开最近测试完的测试信号线32与驱动信号线33的连接的步骤，直至测试完成。
为了完成对所有GOA电路34的测试，重复执行步骤22和步骤23，直至测试完成。
区别于现有技术，本实施例提供了一种阵列基板驱动电路的测试方法，阵列基板的测试端子31与多条测试信号线32连接，首先将与测试端子31连接的多条测试信号线32中的一条连接一条驱动信号线33，利用外部测试探针35对测试端子31输入信号以进行测试；然后重复执行：将最近测试完的测试信号线32与驱动信号线33之间的连接断开，并将另一条测试信号线32连接另一条驱动信号线33，对测试端子31输入信号以进行测试的操作，直至测试完成；通过利用少于驱动信号线33数量的测试端子31完成了驱动电路的测试，节省测试端子31和生产成本。
参阅图5至图7，图5是本申请提供的阵列基板驱动电路的测试方法第二实施例的流程示意图，该方法包括：
步骤51：将从阵列基板的测试端子61中引出的多条测试信号线62中的一条连接一条驱动信号线63，对测试端子61输入信号以进行测试。
步骤52：断开最近测试完的测试信号线62与驱动信号线63的连接。
步骤53：将另一条测试信号线62连接另一条驱动信号线63，对测试端子61输入信号以进行测试。
步骤54：返回断开最近测试完的测试信号线62与驱动信号线63的连接的步骤，直至测试完成。
其中，步骤51-54与第一实施例中步骤11-14类似，在此不再赘述。
测试端子61的数量为至少为2，测试信号线62的数量等于驱动信号线63的数量；测试信号线62上设置有电路断点，电路断点上预设有焊接点位64，如图6所示，通过焊接电路断点上的焊接点位64将测试信号线62和驱动信号线63连接；可以利用激光焊接电路断点上的焊接点位64，以使得驱动信号线63和测试信号线62连接，形成通路。
步骤55：在测试完成后，将从阵列基板的测试端子61中引出的多条测试信号线62中的一条连接全部的驱动信号线63，以进行高垂直排列固化制程。
在完成对GOA电路65的测试后，将从阵列基板的测试端子61中引出的多条测试信号线62中的一条连接全部的驱动信号线63，以进行高垂直排列固化（High Vertical Alignment Curing，HVA）制程；图6所示中将第四条测试信号线62与所有的驱动信号线63进行了连接，剩余的测试信号线62均与驱动信号线63断开。
步骤56：在高垂直排列固化制程完成之后，断开测试信号线62与驱动信号线63的连接。
如图7所示，在完成HVA制程之后，测试信号线62与驱动信号线63的连接被断开，以使得显示面板售出后驱动信号线能正常工作。
区别于现有技术，本实施例提供了一种阵列基板驱动电路的测试方法，通过在阵列基板的测试端子61设置多条测试信号线62，并在测试信号线62上设置焊接点位64，在对不同的驱动信号线63连接的GOA电路65进行测试时，通过焊接不同的焊接点位64使得测试信号线62与驱动信号线63连接，提高了测试端子61的利用率，节省了测试端子61和生产成本。
参阅图8至图11，图8是本申请提供的阵列基板驱动电路的测试方法第三实施例的流程示意图，该方法包括：
步骤81：将第一测试端子91中引出的第一测试信号线连接第一驱动信号线，并将第二测试端子92中引出的第四测试信号线连接第四驱动信号线，分别对第一测试端子91和第二测试端子92输入信号以进行测试。
输入第一测试端子91的信号S1与输入第二测试端子92的信号S2电位相反，如图10所示；第一测试端子91中引出的第一测试信号线与第一驱动信号线连接，第二测试端子92中引出的第四测试信号线与第四驱动信号线连接，分别利用外部治具探针93对第一测试端子91和第二测试端子92输入信号以进行测试，如图9所示。
步骤82：断开测试完的第一测试信号线与第一驱动信号线的连接，并断开测试完的第四测试信号线与第四驱动信号线的连接。
步骤83：将第一测试端子91中引出的第二测试信号线连接第二驱动信号线，并将第二测试端子92中引出的第五测试信号线连接第五驱动信号线，分别对第一测试端子91和第二测试端子92输入信号以进行测试。
在完成对第一驱动信号线和第四驱动信号线连接的GOA电路测试后，将第一测试信号线与第一驱动信号线的连接断开，并将第四测试信号线与第四驱动信号线的连接断开，如图11所示；再将第二测试信号线与第二驱动信号线连接，并将第五测试信号线与第五驱动信号线连接，然后分别输入信号至第一测试端子91和第二测试端子92中。
步骤84：断开测试完的第二测试信号线与第二驱动信号线的连接，并断开测试完的第五测试信号线与第五驱动信号线的连接。
步骤85：重复上述步骤，直至测试完所有驱动信号线。
在完成对第二驱动信号线和第五驱动信号线连接的GOA电路测试后，将第二测试信号线与第二驱动信号线的连接断开，并将第五测试信号线与第五驱动信号线的连接断开；然后重复执行步骤81-84，直至测试完所有驱动信号线。
区别于现有技术，本实施例提供了一种阵列基板驱动电路的测试方法，通过在每个测试端子上连接多条测试信号线，在进行测试时，先将每个测试端子中连接的测试信号线中的一条与一条驱动信号线连接，并在测试完成后，切断测试信号线与驱动信号线之间的连接，实现重复利用测试端子，提高了测试端子的利用率，利用较少的测试端子完成了对GOA电路的测试，节省了测试端子和生产成本。
参阅图12和图14，图12是本申请提供的阵列基板驱动电路的测试方法第四实施例的流程示意图，该方法包括：
步骤121：将测试端子131中引出的第一测试信号线连接第一驱动信号线，并将测试端子131中引出的第一测试信号线通过反相器132连接第四驱动信号线，对测试端子131输入信号以进行测试。
测试端子131中引出的第一测试信号线与第一驱动信号线连接，并将第一测试信号线通过反相器132连接至第四驱动信号线，然后利用外部治具探针133对测试端子131输入信号以进行测试，如图13所示。
步骤122：断开测试完的第一测试信号线与第一驱动信号线的连接，并断开测试完的第一测试信号线与第四驱动信号线的连接。
步骤123：将测试端子131中引出的第二测试信号线连接第二驱动信号线，并将测试端子131中引出的第二测试信号线通过反相器132连接第五驱动信号线，对测试端子131输入信号以进行测试。
在完成对第一驱动信号线和第四驱动信号线连接的GOA电路测试后，分别将第一测试信号线与第一驱动信号线和第四驱动信号线的连接断开，如图14所示；再将第二测试信号线与第二驱动信号线连接，并将第二测试信号线通过反相器132与第五驱动信号线连接，然后利用外部治具探针133输入信号至测试端子131中。
步骤124：断开测试完的第二测试信号线与第二驱动信号线的连接，并断开测试完的第二测试信号线与第五驱动信号线的连接。
步骤125：重复上述步骤，直至测试完所有驱动信号线。
在完成对第二驱动信号线和第五驱动信号线连接的GOA电路测试后，分别将第二测试信号线与第二驱动信号线和第五驱动信号线的连接断开；然后重复执行步骤121-124，直至测试完所有驱动信号线。
区别于现有技术，本实施例提供了一种阵列基板驱动电路的测试方法，在进行驱动电路的测试时，先将测试端子131中连接的测试信号线中的一条与一条驱动信号线连接，同时通过反相器连接另一条驱动信号线，并在测试完成后，切断测试信号线与驱动信号线之间的连接，实现重复利用测试端子131，提高了测试端子131的利用率，节省了测试端子131和生产成本。
参阅图15和图16，图15是本申请提供的显示面板一实施例的结构示意图，该显示面板包括：基板151、像素电路152、若干驱动信号线153以及若干测试信号线154。
基板151为阵列基板，像素电路152位于基板151一侧的显示区域1511；驱动信号线153位于与像素电路151同侧的基板151上，且自基板151外围的非显示区域1512延伸至显示区域1511，驱动信号线153与像素电路152连接。
测试信号线154位于与像素电路152同侧的基板151上，每条测试信号线154被设计为与一条驱动信号线153连接以对像素电路152进行测试。
其中，至少有一条测试信号线154与驱动信号线153之间的连接结构为焊接结构，和/或至少有一条测试信号线154与驱动信号线153之间存在烧断或割断结构。
进一步地，显示面板还包括两个测试端子155，每个测试端子155连接多条测试信号线154，每条测试信号线154连接一条驱动信号线153，每个测试端子155与外部治具（图中未示出）连接以输入信号至测试信号线154中，如图15所示。
此外，显示面板还可仅包括一个测试端子155，测试端子155连接多条测试信号线154，且每条测试信号线154连接两条驱动信号线153，测试端子155与外部治具连接以输入信号至测试信号线154中，如图16所示。
其中，至少有一根测试信号线154与所有驱动信号线153之间均存在烧断或割断结构，以防止测试信号线154将所有驱动信号线153连通，使得驱动信号线153短路。
区别于现有技术，本实施例提供的显示面板，通过利用较少的测试155端子即可实现对像素电路152的测试，减小了测试端子155占用显示面板的空间，缩小非显示区1512的面积，有利于提高显示面板的占屏比，还可以节省制作测试端子155的成本。
以上仅为本申请的实施例，并非因此限制本申请的专利范围，凡是利用本申请说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本申请的专利保护范围内。

Claims (20)

  1. 一种阵列基板驱动电路的测试方法，包括：
    将从阵列基板的测试端子中引出的多条测试信号线中的一条连接一条驱动信号线，对所述测试端子输入信号以进行测试；
    断开最近测试完的所述测试信号线与所述驱动信号线的连接；
    将另一条所述测试信号线连接另一条驱动信号线，对所述测试端子输入信号以进行测试；以及
    返回所述断开最近测试完的所述测试信号线与所述驱动信号线的连接的步骤，直至测试完成；
    其中至少有一条所述测试信号线与所述驱动信号线之间的连接结构为焊接结构，和/或至少有一条所述测试信号线与所述驱动信号线之间存在烧断或割断结构。
  2. 根据权利要求1所述的阵列基板驱动电路的测试方法，其中所述测试端子的数量为至少为2，所述测试信号线的数量等于所述驱动信号线的数量。
  3. 根据权利要求2所述的阵列基板驱动电路的测试方法，还包括：
    将所述第一测试端子中引出的第一测试信号线连接第一驱动信号线，并将所述第二测试端子中引出的第四测试信号线连接第四驱动信号线，分别对所述第一测试端子和所述第二测试端子输入信号以进行测试；
    断开测试完的所述第一测试信号线与所述第一驱动信号线的连接，并断开测试完的所述第四测试信号线与所述第四驱动信号线的连接；
    将所述第一测试端子中引出的第二测试信号线连接第二驱动信号线，并将所述第二测试端子中引出的第五测试信号线连接第五驱动信号线，分别对所述第一测试端子和所述第二测试端子输入信号以进行测试；
    断开测试完的所述第二测试信号线与所述第二驱动信号线的连接，并断开测试完的所述第五测试信号线与所述第五驱动信号线的连接；以及
    重复上述步骤，直至测试完所有驱动信号线。
  4. 根据权利要求3所述的阵列基板驱动电路的测试方法，其中输入所述第一测试端子的信号与输入所述第二测试端子的信号电位相反。
  5. 根据权利要求1所述的阵列基板驱动电路的测试方法，其中所述测试信号线上设置有电路断点，所述电路断点上预设有焊接点位，通过焊接所述电路断点上的所述焊接点位将所述测试信号线和所述驱动信号线连接。
  6. 根据权利要求5所述的阵列基板驱动电路的测试方法，其中利用激光焊接所述焊接点位，以使得所述驱动信号线和所述测试信号线连接。
  7. 根据权利要求1所述的阵列基板驱动电路的测试方法，还包括：
    在测试完成后，将从所述阵列基板的所述测试端子中引出的多条测试信号线中的一条连接全部的所述驱动信号线，以进行高垂直排列固化制程；以及
    在高垂直排列固化制程完成之后，断开所述测试信号线与所述驱动信号线的连接。
  8. 根据权利要求1所述的阵列基板驱动电路的测试方法，还包括：
    将所述测试端子中引出的第一测试信号线连接第一驱动信号线，并将所述测试端子中引出的所述第一测试信号线通过反相器连接第四驱动信号线，对所述测试端子输入信号以进行测试；
    断开测试完的所述第一测试信号线与所述第一驱动信号线的连接，并断开测试完的所述第一测试信号线与所述第四驱动信号线的连接；
    将所述测试端子中引出的第二测试信号线连接第二驱动信号线，并将所述测试端子中引出的所述第二测试信号线通过所述反相器连接第五驱动信号线，对所述测试端子输入信号以进行测试；
    断开测试完的所述第二测试信号线与所述第二驱动信号线的连接，并断开测试完的所述第二测试信号线与所述第五驱动信号线的连接；以及
    重复上述步骤，直至测试完所有驱动信号线。
  9. 一种阵列基板驱动电路的测试方法，包括：
    将从阵列基板的测试端子中引出的多条测试信号线中的一条连接一条驱动信号线，对所述测试端子输入信号以进行测试；
    断开最近测试完的所述测试信号线与所述驱动信号线的连接；
    将另一条所述测试信号线连接另一条驱动信号线，对所述测试端子输入信号以进行测试；
    返回所述断开最近测试完的所述测试信号线与所述驱动信号线的连接的步骤，直至测试完成。
  10. 根据权利要求9所述的阵列基板驱动电路的测试方法，其中所述测试端子的数量为至少为2，所述测试信号线的数量等于所述驱动信号线的数量。
  11. 根据权利要求10所述的阵列基板驱动电路的测试方法，其中还包括：
    将所述第一测试端子中引出的第一测试信号线连接第一驱动信号线，并将所述第二测试端子中引出的第四测试信号线连接第四驱动信号线，分别对所述第一测试端子和所述第二测试端子输入信号以进行测试；
    断开测试完的所述第一测试信号线与所述第一驱动信号线的连接，并断开测试完的所述第四测试信号线与所述第四驱动信号线的连接；
    将所述第一测试端子中引出的第二测试信号线连接第二驱动信号线，并将所述第二测试端子中引出的第五测试信号线连接第五驱动信号线，分别对所述第一测试端子和所述第二测试端子输入信号以进行测试；
    断开测试完的所述第二测试信号线与所述第二驱动信号线的连接，并断开测试完的所述第五测试信号线与所述第五驱动信号线的连接；以及
    重复上述步骤，直至测试完所有驱动信号线。
  12. 根据权利要求11所述的阵列基板驱动电路的测试方法，其中输入所述第一测试端子的信号与输入所述第二测试端子的信号电位相反。
  13. 根据权利要求9所述的阵列基板驱动电路的测试方法，其中所述测试信号线上设置有电路断点，所述电路断点上预设有焊接点位，通过焊接所述电路断点上的所述焊接点位将所述测试信号线和所述驱动信号线连接。
  14. 根据权利要求13所述的阵列基板驱动电路的测试方法，其中利用激光焊接所述焊接点位，以使得所述驱动信号线和所述测试信号线连接。
  15. 根据权利要求9所述的阵列基板驱动电路的测试方法，还包括：
    在测试完成后，将从所述阵列基板的所述测试端子中引出的多条测试信号线中的一条连接全部的所述驱动信号线，以进行高垂直排列固化制程；以及
    在高垂直排列固化制程完成之后，断开所述测试信号线与所述驱动信号线的连接。
  16. 根据权利要求9所述的阵列基板驱动电路的测试方法，其中还包括：
    将所述测试端子中引出的第一测试信号线连接第一驱动信号线，并将所述测试端子中引出的所述第一测试信号线通过反相器连接第四驱动信号线，对所述测试端子输入信号以进行测试；
    断开测试完的所述第一测试信号线与所述第一驱动信号线的连接，并断开测试完的所述第一测试信号线与所述第四驱动信号线的连接；
    将所述测试端子中引出的第二测试信号线连接第二驱动信号线，并将所述测试端子中引出的所述第二测试信号线通过所述反相器连接第五驱动信号线，对所述测试端子输入信号以进行测试；
    断开测试完的所述第二测试信号线与所述第二驱动信号线的连接，并断开测试完的所述第二测试信号线与所述第五驱动信号线的连接；以及
    重复上述步骤，直至测试完所有驱动信号线。
  17. 一种显示面板，包括：
    基板；
    像素电路，位于所述基板一侧显示区域；
    若干驱动信号线，位于与所述像素电路同侧的所述基板上，且自所述基板外围的非显示区域延伸至所述显示区域，与所述像素电路连接；以及
    若干测试信号线，位于与所述像素电路同侧的所述基板上，每条所述测试信号线被设计为与一条所述驱动信号线连接以对所述像素电路进行测试；
    其中至少有一条所述测试信号线与所述驱动信号线之间的连接结构为焊接结构，和/或至少有一条所述测试信号线与所述驱动信号线之间存在烧断或割断结构。
  18. 根据权利要求17所述的显示面板，还包括两个测试端子，所述测试端子连接多条所述测试信号线，每条所述测试信号线连接一条所述驱动信号线，所述测试端子与外部治具连接以输入信号至所述测试信号线中；
    或者，所述显示面板还包括一个测试端子，所述测试端子连接多条所述测试信号线，且每条所述测试信号线连接两条所述驱动信号线，所述测试端子与所述外部治具连接以输入信号至所述测试信号线中；
    其中至少有一根测试信号线与所有所述驱动信号线之间均存在烧断或割断结构。
  19. 根据权利要求17所述的显示面板，其中所述测试信号线上设置有电路断点，所述电路断点上预设有焊接点位，通过焊接所述电路断点上的所述焊接点位将所述测试信号线和所述驱动信号线连接。
  20. 根据权利要求17所述的显示面板，其中所述测试端子的数量少于所述驱动信号线的数量，所述测试信号线的数量等于所述驱动信号线的数量。
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