WO2020028064A1 - On stack overlay improvement for 3d nand - Google Patents

On stack overlay improvement for 3d nand Download PDF

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Publication number
WO2020028064A1
WO2020028064A1 PCT/US2019/042489 US2019042489W WO2020028064A1 WO 2020028064 A1 WO2020028064 A1 WO 2020028064A1 US 2019042489 W US2019042489 W US 2019042489W WO 2020028064 A1 WO2020028064 A1 WO 2020028064A1
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Prior art keywords
containing gas
silicon
flow rate
seem
dilution
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Ceased
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PCT/US2019/042489
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French (fr)
Inventor
Yongjing Lin
Tza-Jing Gung
Masaki Ogata
Yusheng Zhou
Xinhai Han
Deenesh Padhi
Juan Carlos Rocha
Amit Kumar BANSAL
Mukund Srinivasan
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Applied Materials Inc
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Applied Materials Inc
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Priority to CN201980045611.9A priority Critical patent/CN112771645A/en
Priority to JP2021504225A priority patent/JP7461926B2/en
Priority to SG11202010548YA priority patent/SG11202010548YA/en
Priority to KR1020217002183A priority patent/KR102697912B1/en
Publication of WO2020028064A1 publication Critical patent/WO2020028064A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/69215—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
    • H10P14/6328—Deposition from the gas or vapour phase
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70605—Workpiece metrology
    • G03F7/70616—Monitoring the printed patterns
    • G03F7/70633—Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32082—Radio frequency generated discharge
    • H01J37/32174—Circuits specially adapted for controlling the RF discharge
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
    • H10P14/6328—Deposition from the gas or vapour phase
    • H10P14/6334—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H10P14/6336—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/65—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials
    • H10P14/6516—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials
    • H10P14/6529—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials by exposure to a gas or vapour
    • H10P14/6532—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials by exposure to a gas or vapour by exposure to a plasma
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/66—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials
    • H10P14/662—Laminate layers, e.g. stacks of alternating high-k metal oxides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/66—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials
    • H10P14/668—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials
    • H10P14/6681—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials the precursor containing a compound comprising Si
    • H10P14/6682—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
    • H—ELECTRICITY
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/694—Inorganic materials composed of nitrides
    • H10P14/6943—Inorganic materials composed of nitrides containing silicon
    • H10P14/69433—Inorganic materials composed of nitrides containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/04—Apparatus for manufacture or treatment
    • H10P72/0402—Apparatus for fluid treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/90—Thermal treatments, e.g. annealing or sintering
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H10W20/035—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics combinations of barrier, adhesion or liner layers, e.g. multi-layered barrier layers

Definitions

  • Embodiments of the present disclosure generally relate to 3D NAND memory cell manufacturing processes. More particularly, embodiments of the present disclosure relate to apparatuses and methods of manufacturing layer stacks of oxide/nitride (ON) layers with minimized in-plane distortion (IPD) and lithographic overlay errors.
  • ON oxide/nitride
  • IPD in-plane distortion
  • NAND flash memory which is generally found in memory cards, USB flash drives, solid-state drives, and other similar devices for data storage and transfer.
  • NAND flash memory memory cells made from transistors are connected in series and stacked in vertical layers to create densely-packed, high-capacity memory devices. Flash drives generally use less power and are more durable than ordinary hard drives because they do not contain moving parts. As such, there is great interest in increasing the capacity of flash drives.
  • a method of forming a layer stack of oxide/nitride (ON) layers includes transferring a substrate to a process chamber, heating a pedestal retaining the substrate to a deposition temperature, and flowing a first silicon-containing gas at a first silicon-containing gas flow rate, an oxygen-containing gas at an oxygen-containing gas flow rate, and a first dilution gas at a first dilution gas flow rate into the process chamber.
  • a first radio frequency (RF) power is symmetrically applied to the first silicon-containing gas, the oxygen-containing gas, and the first dilution gas to form a first material layer of silicon dioxide (S1O2).
  • the method further includes flowing a second silicon-containing gas at a second silicon- containing gas flow rate, a nitrogen-containing gas at a nitrogen-containing gas flow rate, and a second dilution gas at a second dilution gas flow rate into the process chamber.
  • a second RF power is symmetrically applied to the second silicon-containing gas, the nitrogen-containing gas, and the second dilution gas to form a second material layer of silicon nitride (ShN 4 ).
  • the flowing the first silicon-containing gas, the oxygen- containing gas, and the first dilution gas, the symmetrically applying the first RF power, the flowing the second silicon-containing gas, the nitrogen-containing gas, and the second dilution gas, and the symmetrically applying the second RF power is repeated until a desired number of material layer pairs of the first material layer and the second material layer make up a layer stack.
  • a method of forming a layer stack of oxide/nitride (ON) layers includes transferring a substrate to a first process chamber, heating a first pedestal of the first process chamber retaining the substrate to a deposition temperature, and flowing a first silicon-containing gas at a first silicon- containing gas flow rate, an oxygen-containing gas at an oxygen-containing gas flow rate, and a first dilution gas at a first dilution gas flow rate into the first process chamber.
  • a first radio frequency (RF) power is symmetrically applied to the first silicon- containing gas, the oxygen-containing gas, and the first dilution gas to form a first material layer of silicon dioxide (S1O2).
  • the method further includes flowing a second silicon-containing gas at a second silicon-containing gas flow rate, a nitrogen- containing gas at a nitrogen-containing gas flow rate, and a second dilution gas at a second dilution gas flow rate into the first process chamber.
  • a second RF power is symmetrically applied to the second silicon-containing gas, the nitrogen-containing gas, and the second dilution gas to form a second material layer of silicon nitride (ShN 4 ).
  • the flowing the first silicon-containing gas, the oxygen-containing gas, and the first dilution gas, the symmetrically applying the first RF power, the flowing the second silicon-containing gas, the nitrogen-containing gas, and the second dilution gas, and the symmetrically applying the second RF power is repeated until a first portion of a desired number of material layer pairs of the first material layer and the second material layer make up a layer stack.
  • the method further includes transferring the substrate from the first process chamber to a second process chamber, heating a second pedestal of the second process chamber retaining the substrate to the deposition temperature, and repeating the flowing the first silicon-containing gas, the oxygen- containing gas, and the first dilution gas, the symmetrically applying the first RF power, the flowing the second silicon-containing gas, the nitrogen-containing gas, and the second dilution gas, and the symmetrically applying the second RF power until a second portion of the desired number of the material layer pairs of the first material layer and the second material layer make up a layer stack.
  • a showerhead in yet another embodiment, includes a symmetric radio frequency (RF) circuit disposed in the showerhead connected to a RF power source by a RF feed having a four portions connected to the symmetric RF circuit at 90 degree intervals.
  • RF radio frequency
  • Figure 1 is a schematic cross-sectional view of a memory device according to an embodiment.
  • Figure 2 is a schematic view of a processing system according to an embodiment.
  • Figure 3 is a schematic cross-sectional view of a plasma-enhanced chemical vapor deposition system according to an embodiment.
  • Figure 4 is a top, schematic cross-sectional view of a showerhead of a process chamber according to an embodiment.
  • Figure 5 is a flow diagram of a method of forming a layer stack of ON layers with minimized IPD and improved lithographic overlay according to an embodiment.
  • Figure 6 is a flow diagram of a method of forming a layer stack of ON layers with minimized IPD and improved lithographic overlay according to an embodiment.
  • Embodiments described herein relate to manufacturing layer stacks of oxide/nitride (ON) layers with minimized in-plane distortion (IPD) and lithographic overlay errors.
  • a method of forming a layer stack ON layers includes flowing a first silicon-containing gas, an oxygen-containing gas, and a first dilution gas.
  • a RF power is symmetrically applied to form a first material layer of S1O2.
  • a second silicon-containing gas, a nitrogen-containing gas, and a second dilution gas are flowed.
  • a second RF power is symmetrically applied to form a second material layer of ShN 4.
  • the flowing the first silicon-containing gas, the oxygen-containing gas, and the first dilution gas, the symmetrically applying the first RF power, the flowing the second silicon-containing gas, the nitrogen-containing gas, and the second dilution gas, and the symmetrically applying the second RF power is repeated until a desired number of first material layers and second material layers make up a layer stack.
  • FIG. 1 is a schematic cross-sectional view of a memory device 100 according to embodiments of the present disclosure.
  • the memory device 100 includes a substrate 102 with a plurality of first material layers 104 and a plurality of second material layers 106 thereon.
  • Material layer pairs 108a, 108b, 108c, ... 108n also known as a plurality of material layer pairs 108 of a first material layer of the plurality of first material layers 104 and a second material layer of the plurality of second material layers 106, make up a layer stack 110.
  • each of the first material layers 104 is generally a silicon dioxide layer (O layer) and each of the second material layers 106 is generally a silicon nitride layer (N layer). While Figure 1 depicts the second material layer 106 deposited over the first material layer 104, the deposition order may be reversed such that the first material layer 104 (0 layer) is deposited over the second material layer 106 (N layer).
  • the memory device 100 is a 3D NAND memory cell
  • the memory device 100 further includes a source and a drain (not shown) disposed on opposite ends of a first surface 112 of the substrate 102.
  • each NAND flash cell For use as flash memory, multiple NAND flash cells are generally connected in series with the adjacent cells sharing a source or drain, and each cell is connected to a bitline and a wordline. In operation, each cell can store data, such as a“0” or“1 ,” therein.
  • the methods of manufacturing layer stacks of ON/OP films with minimized IPD and improved lithographic overlay include plasma-enhanced chemical vapor deposition (PECVD) processes, which can be used to form silicon films at relatively low temperatures.
  • PECVD plasma-enhanced chemical vapor deposition
  • the methods can be performed by one or more twin PECVD systems, such as a PRODUCER® plasma enhanced CVD (PECVD) system, available from Applied Materials, Inc. of Santa Clara, Calif.
  • the PECVD systems may be incorporated into a processing system 200, available from Applied Materials, Inc. of Santa Clara, Calif.
  • the processing system described below is an exemplary processing system and other processing systems, including processing systems from other manufacturers, may be used with or modified to accomplish aspects of the present disclosure.
  • the PECVD system below is an exemplary PECVD system and other PECVD systems, including PECVD systems from other manufacturers, may be used with or modified to accomplish aspects of the present disclosure.
  • FIG. 2 is a schematic view of a processing system 200 utilized for methods of manufacturing layer stacks of ON/OP layers with minimized IPD and improved lithographic overlay.
  • a pair of front opening unified pods (FOUPs) 202 supplies substrates that are received by robotic arms 204 and placed into the holding area 206 before being placed into one of the process chambers 214a-214d of PECVD systems 208a, 208b and/or Rapid Thermal Processing (RTP) chambers 210a, 210b.
  • a second robotic arm 212 may be used to transport the substrates from the holding area 206 to the PECVD systems 208a-208d and/or RTP chambers 210a, 210b and back.
  • FIG. 3 is a schematic cross-sectional view of a PECVD system 208a utilized for methods of manufacturing layer stacks of ON/OP layers with minimized IPD and improved lithographic overlay.
  • the PECVD system 208a includes the process chambers 214a, 214b, wherein the process chambers 214a, 214b share resources, for example, such as a shared vacuum pump 304, a first gas source
  • the process chamber 214a e.g., a first process chamber
  • the process chamber 214b e.g., a second process chamber
  • the process chamber 214a and the process chamber 214b are similarly configured.
  • Each process chamber 214a, 214b has a processing volume 307, 308 that includes a pedestal 309, 310 disposed therein to support a substrate 102.
  • the pedestal 309, 310 includes a heating element (not shown) and a mechanism (not shown) that retains the substrate 102 on the pedestal 309, 310, such as an electrostatic chuck, a vacuum chuck, a substrate retaining clamp, or the like.
  • the pedestal 309, 310 is coupled to and movably disposed in the processing volume 307, 308 by a stem 311 , 312 connected to a lift system (not shown) that moves the pedestal 309, 310 between an elevated processing position and a lowered position that facilitates transfer of the substrate 102 to and from the process chamber 214a, 214b through an opening 315, 316.
  • a flow controller 317, 318 such as a mass flow control (MFC) device, is disposed between the first gas source 306 and the process chamber 214a, 214b to control a flow rate of a first process gas from the first gas source 306 to a showerhead 319, 320 used for distributing the first process gas across the processing volume 307, 308.
  • a flow controller 328, 329 is disposed between the second gas source 332 and the process chamber 214a, 214b to control a flow rate of a second process gas from the second gas source 332 to a showerhead 319, 320 used for distributing the second process gas across the processing volume 307, 308.
  • a flow controller 330, 331 is disposed between the third gas source 334 and the process chamber 214a, 214b to control a flow rate of a third process gas from the third gas source 334 to a showerhead 319, 320 used for distributing the third process gas across the processing volume 307, 308.
  • a valve 325, 326 can be disposed between the shared vacuum pump 304 and the process chamber 214a, 214b for controlling the pressure within the processing volume
  • the showerhead 319, 320 includes a symmetric radio frequency (RF) circuit (shown in Figure 4) connected to a RF power source 321 , 322 by a RF feed 323, 324 having a plurality of portions 344, 345 for striking a substantially uniform plasma in the processing volume 307, 308 from the process gas.
  • the pedestal 309, 310 includes a bottom tuner assembly 340, 341.
  • the bottom tuner assembly 340, 341 includes a tuning electrode 313, 314 coupled to a tuning circuit 342, 343.
  • the 343 is utilized to modulate the impedance on the tuning electrode 313, 314 provide further control of the plasma in the processing volume. For example, modulating the impedance of the tuning electrode 313, 314 increases plasma bombardment on the substrate 102.
  • FIG. 4 a cross-sectional top view of the showerhead 319 of the process chambers 214a.
  • the showerhead 319 has a symmetric RF circuit 402 disposed therein coupled to the RF feed 323.
  • the symmetric RF circuit 402 is connected to the symmetric RF circuit 402 so that the supply of RF power to the symmetric RF circuit 402 is symmetric.
  • the RF feed 323 has four portions connected to the symmetric RF circuit 402 at 90 degree intervals.
  • a symmetric supply of RF power to the symmetric RF circuit 402 allows for striking the substantially uniform plasma in the processing volume 307.
  • the symmetric RF circuit 402 is symmetric so the plasma in the processing volume 307 is substantially uniform to reduce IPD of the layer stacks of ON layers.
  • FIG. 5 is a flow diagram of a method 500 of forming a layer stack of ON layers with minimized IPD and improved lithographic overlay.
  • a substrate 102 is transferred to a process chamber 214a of a PECVD system 208a.
  • a second robotic arm 212 transfers the substrate 102 from the holding area 206 of the processing system 200 to a process chamber 214a of the PECVD system 208a.
  • the pedestal 309 is heated to a deposition temperature of about 500 degrees Celsius (°C) to about 600 °C.
  • a first material layer 104 of silicon dioxide (S1O2) is deposited.
  • a first silicon-containing gas at a first silicon-containing gas flow rate, an oxygen- containing gas at an oxygen-containing gas flow rate, and a first dilution gas at a first dilution gas flow rate are delivered to the process chamber 214a.
  • the flow controller 317 disposed between the first gas source 306 and the process chamber 214a controls the first silicon-containing gas flow rate of the first silicon-containing gas provided to showerhead 319 that distributes the first silicon-containing gas across the processing volume 307 of the process chamber 214a.
  • the first silicon-containing gas may include at least one of silane (SiH 4 ), tetraethyl orthosilicate (TEOS), and disilane (S12H6).
  • the flow controller 328 disposed between the second gas source 332 and the process chamber 214a controls the oxygen-containing gas flow rate of the oxygen-containing gas provided to showerhead 319 that distributes the oxygen-containing gas across the processing volume 307 of the process chamber 214a.
  • the oxygen-containing gas may include at least one of nitrous oxide (N2O), oxygen gas (O2), and trioxygen (O3).
  • the flow controller 330 disposed between the third gas source 334 and the process chamber 214a controls the first dilution gas flow rate of the first dilution gas provided to showerhead 319 that distributes the first dilution gas across the processing volume 307 of the process chamber 214a.
  • the first dilution gas may include at least one of nitrogen gas (N2), argon (Ar), and helum (He).
  • N2 nitrogen gas
  • Ar argon
  • He helum
  • the first silicon-containing gas flow rate is about 600 standard cubic centimeters per minute (seem) to about 5000 seem
  • the oxygen-containing gas flow rate is about 500 seem to about 15000 seem
  • the first dilution gas flow rate is about 100 seem to about 20000 seem.
  • a first RF power is applied to the first silicon-containing gas, the oxygen-containing gas, and the first dilution gas.
  • the showerhead 319 having a symmetric RF circuit 402 disposed therein connected to a RF power source 321 by a RF feed 323 having a plurality of portions 344 to allow for a symmetric application of the first RF power.
  • Each portion of the plurality of portions is connected to the symmetric RF circuit 402 so that the supply of RF power to the symmetric RF circuit 402 is symmetric.
  • a symmetric application of the first RF power allows for deposition of the first material layer 104 of S1O2 with improved residual uniformity to minimize IPD and improve lithographic overlay of the layer stack 110 of ON layers.
  • IPD of the layer stack 110 of ON layers is reduced by 10 percent.
  • the first material layer 104 is exposed to a post- deposition treatment process.
  • the flow of the first silicon-containing gas is discontinued, and the flow of the oxygen-containing gas and the flow of the first dilution gas are continued.
  • the flow of the first silicon-containing gas is discontinued, and the flow of the oxygen-containing gas and the flow of the first dilution gas are continued to stabilize the plasma.
  • the tuning circuit 342 of the bottom tuner assembly 340 is utilized to modulate the impedance on the tuning electrode 313 to increase bombardment of the remaining plasma in the processing volume 307 on the substrate 102.
  • Increasing bombardment of the remaining plasma in the processing volume 307 on the substrate 102 reduces the stress non-uniformity of the first material layer 104. Reducing the stress non-uniformity of the first material layer 104 minimizes IPD and improves lithographic overlay of the layer stack 110 of ON layers.
  • a second material layer 106 of silicon nitride (ShN 4 ) is deposited.
  • a second silicon-containing gas at a second silicon- containing gas flow rate, a nitrogen-containing gas at a nitrogen-containing gas flow rate, and a second dilution gas at a first dilution gas flow rate are delivered to the process chamber 214a.
  • the flow controller 317 disposed between the first gas source 306 and the process chamber 214a controls the second silicon-containing gas flow rate of the second silicon-containing gas provided to showerhead 319 that distributes the second silicon-containing gas across the processing volume 307 of the process chamber 214a.
  • the second silicon-containing gas may include at least one of SiH 4 and S12H6.
  • the flow controller 328 disposed between the second gas source 332 and the process chamber 214a controls the nitrogen-containing gas flow rate of the nitrogen-containing gas provided to showerhead 319 that distributes the nitrogen-containing gas across the processing volume 307 of the process chamber 214a.
  • the nitrogen-containing gas may include at least one of ammonia (NH3) and N2.
  • the flow controller 330 disposed between the third gas source 334 and the process chamber 214a controls the second dilution gas flow rate of the second dilution gas provided to showerhead 319 that distributes the second dilution gas across the processing volume 307 of the process chamber 214a.
  • the second dilution gas may include at least one of N2, Ar, and He.
  • the second dilution gas flow rate is selected to improve the residual uniformity of the second material layer 106 of ShN 4 and reduce IPD by 50 percent.
  • the second dilution gas is N2 and the second dilution gas flow rate is greater than about 2000 seem. Increasing the flow of N2 or Ar may improve the plasma uniformity during deposition to reduce IPD.
  • the second silicon-containing gas flow rate is about 30 standard cubic centimeters per minute (seem) to about 300 seem
  • the nitrogen-containing gas flow rate is about 200 seem to about 7000 seem
  • the first dilution gas flow rate is about 500 seem to about 3000 seem.
  • a second RF power is applied to the second silicon-containing gas, the nitrogen-containing gas, and the second dilution gas.
  • the showerhead 319 having the symmetric RF circuit 402 disposed therein is connected to the RF power source 321 by the RF feed 323 to allow for a symmetric application of the second RF power.
  • a symmetric application of the second RF power allows for deposition of the second material layer 106 of ShN 4 with improved residual uniformity to minimize IPD and improve lithographic overlay of the layer stack 110 of ON layers.
  • the second material layer 106 is exposed to a post- deposition treatment process.
  • the flow of the second silicon-containing gas is discontinued, and the flow of the nitrogen-containing gas and the flow of the second dilution gas are continued.
  • the flow of the second silicon-containing gas is discontinued, and the flow of the nitrogen-containing gas and the flow of the second dilution gas are continued to stabilize the plasma.
  • the tuning circuit 342 of the bottom tuner assembly 340 is utilized to modulate the impedance on the tuning electrode 313 to increase bombardment of the remaining plasma in the processing volume 307 on the substrate 102.
  • Increasing bombardment of the remaining plasma in the processing volume 307 on the substrate 102 reduces the stress non-uniformity of the first material layer 104. Reducing the stress non-uniformity of the first material layer 104 minimizes IPD and improves lithographic overlay of the layer stack 110 of ON layers.
  • operation 507 operation 503, optional operation 504, operation 505, and optional operation 506 are repeated until a desired number of material layer pairs 108 of the first material layer 104 of S1O2 and the second material layer 106 of ShN 4 make up a layer stack 110. In one embodiment, 64 material layer pairs 108 make up the layer stack 110.
  • the substrate 102 is transferred to a RTP chamber 210a.
  • the second robotic arm 212 transfers the substrate 102 from the process chamber 214a of the PECVD system 208a to a RTP chamber 210a of the processing system 200.
  • the layer stack 110 is annealed at an annealing temperature greater than about 800 °C.
  • Annealing at the annealing temperature greater than about 800 °C improves the residual uniformity of the layer stack 110 of ON layers by stress relaxation to minimize IPD and improve lithographic overlay.
  • IPD of the layer stack 110 of ON layers is reduced by 50 percent.
  • FIG. 6 is a flow diagram of a method 600 of manufacturing layer stacks of ON layers with minimized IPD and improved lithographic overlay.
  • a substrate 102 is transferred to a process chamber 214a of a PECVD system 208a.
  • the pedestal 309 is heated to a deposition temperature of about 550 °C to about 650 °C.
  • a first material layer 104 of silicon dioxide (S1O2) is deposited.
  • a first silicon-containing gas at a first silicon- containing gas flow rate, an oxygen-containing gas at an oxygen-containing gas flow rate, and a first dilution gas at a first dilution gas flow rate are delivered to the process chamber 214a.
  • a first RF power is applied symmetrically to the first silicon-containing gas, the oxygen-containing gas, and the first dilution gas.
  • a symmetric application of the first RF power allows for deposition of the first material layer 104 of S1O2 with improved residual uniformity to minimize IPD and improve lithographic overlay of the layer stack 110 of ON layers.
  • a second material layer 106 of silicon nitride (ShN 4 ) is deposited.
  • a second silicon-containing gas at a second silicon- containing gas flow rate, a nitrogen-containing gas at a nitrogen-containing gas flow rate, and a second dilution gas at a first dilution gas flow rate are delivered to the process chamber 214a.
  • the second dilution gas flow rate is selected to improve the residual uniformity of the second material layer 106 of ShN 4 and reduce IPD by 50 percent.
  • the second dilution gas is N2 and the second dilution gas flow rate is greater than about 2000 seem.
  • a second RF power is applied symmetrically to the second silicon-containing gas, the nitrogen-containing gas, and the second dilution gas.
  • a symmetric application of the second RF power allows for deposition of the second material layer 106 of ShN 4 with improved residual uniformity to minimize IPD and improve lithographic overlay of the layer stack 110 of ON layers.
  • operation 605 operation 603, depositing the first material layer 104 of S1O2, and operation 604, depositing the second material layer 106 of ShN 4 , are repeated until a first portion of a desired number of material layer pairs 108 of the first material layer 104 of S1O2 and the second material layer 106 of ShN 4 that make up a layer stack 110 is deposited.
  • 64 material layer pairs 108 make up the layer stack 110 and the first portion of the desired number of material layer pairs 108 is 32 material layer pairs 108.
  • the substrate 102 is rotated 180° after half of the first portion of the desired number of material layer pairs 108 is deposited.
  • Rotating the substrate 102 accounts for non-uniformity within the process chamber 214a to reduce the IPD of the layer stack 110.
  • the substrate 102 is transferred to a process chamber 214b of a PECVD system 208a.
  • the second robotic arm 212 transfers the substrate 102 from the process chamber 214a of the PECVD system 208a to the process chamber 214b of a PECVD system 208a.
  • the pedestal 310 is heated to the deposition temperature of about 550 °C to about 650 °C.
  • Transferring the substrate 102 during the method 600 of forming a layer stack of ON layers allows for improved matching of IPD of the layer stack 110 formed on each pedestal of the process chambers 214a-214d for improved lithographic overlay.
  • the IPD of a layer stack 110 of ON layers formed in the process chamber 214a may be different the IPD of a layer stack 110 of ON layers formed in the process chamber 214b.
  • Transferring the substrate 102 during the method 600 of forming a layer stack of ON layers averages the variation of IPD of the process chamber 214a and the process chamber 214b to match the IPD of the layer stack 110 formed in each process chamber.
  • operation 608 operation 603, depositing the first material layer 104 of S1O2, and operation 604, depositing the second material layer 106 of ShN 4 , are repeated until a second portion of a desired number of material layer pairs 108 of the first material layer 104 of SiC ⁇ and the second material layer 106 of ShN 4 that make up a layer stack 110.
  • 64 material layer pairs 108 make up the layer stack 110 and the second portion of the desired number of material layer pairs 108 is 32 material layer pairs 108.
  • the substrate 102 is rotated 180° after half of the second portion of the desired number of material layer pairs 108 is deposited.
  • Rotating the substrate 102 accounts for non-uniformity within the process chamber 214b to reduce the IPD of the layer stack 110.
  • the substrate 102 is transferred to a RTP chamber 210a.
  • the second robotic arm 212 transfers the substrate 102 from the process chamber 214b of the PECVD system 208a to a RTP chamber 210a of the processing system 200.
  • the layer stack 110 is annealed at an annealing temperature greater than about 800 °C. Annealing at the annealing temperature greater than about 800 °C improves the residual uniformity of the layer stack 110 of ON layers by stress relaxation to minimize IPD and improve lithographic overlay. In one embodiment, IPD of the layer stack 110 of ON layers is reduced by 50 percent.
  • the second dilution gas flow rate is selected to improve the residual uniformity of the second material layer of ShN 4 and reduce IPD. Transferring the substrate allows for differences of IPD of the layer stack formed on each pedestal of the process chambers to be eliminated for improved lithographic overlay. Annealing at the annealing temperature greater than about 800 °C improves the residual uniformity of the layer stack of ON layers by stress relaxation to minimize IPD and improve lithographic overlay.

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Abstract

Embodiments described herein relate to manufacturing layer stacks of oxide/nitride (ON) layers with minimized in-plane distortion (IPD) and lithographic overlay errors. A method of forming a layer stack ON layers includes flowing a first silicon-containing gas, an oxygen-containing gas, and a first dilution gas. A RF power is symmetrically applied to form a first material layer of SiO2. A second silicon-containing gas, a nitrogen-containing gas, and a second dilution gas are flowed. A second RF power is symmetrically applied to form a second material layer of Si3N4. The flowing the first silicon-containing gas, the oxygen-containing gas, and the first dilution gas, the symmetrically applying the first RF power, the flowing the second silicon-containing gas, the nitrogen-containing gas, and the second dilution gas, and the symmetrically applying the second RF power is repeated until a desired number of first material layers and second material layers make up a layer stack.

Description

ON STACK OVERLAY IMPROVEMENT FOR 3D NAND
BACKGROUND
Field
[0001] Embodiments of the present disclosure generally relate to 3D NAND memory cell manufacturing processes. More particularly, embodiments of the present disclosure relate to apparatuses and methods of manufacturing layer stacks of oxide/nitride (ON) layers with minimized in-plane distortion (IPD) and lithographic overlay errors.
Description of the Related Art
[0002] Growing demands continue to drive the need for high-capacity, high performance computer memory devices with smaller geometries at lower costs. To this end, components of memory cells are stacked on top of each other to create three- dimensional (3D) memory cells, such as vertical gate 3D memory cells. One such technology is NAND flash memory, which is generally found in memory cards, USB flash drives, solid-state drives, and other similar devices for data storage and transfer. In NAND flash memory, memory cells made from transistors are connected in series and stacked in vertical layers to create densely-packed, high-capacity memory devices. Flash drives generally use less power and are more durable than ordinary hard drives because they do not contain moving parts. As such, there is great interest in increasing the capacity of flash drives.
[0003] As flash technology has progressed, challenges have continued to exist in how to create high-capacity devices on a small scale. One such challenge is that 3D NAND memory cells require 64x or more layer stacks of oxide/nitride (ON) layers that are subject to in-plane distortion (IPD) and lithographic overlay errors. Therefore, there is a need in the art for an apparatus and methods of manufacturing layer stacks of ON layers with minimized IPD and improved lithographic overlay.
SUMMARY
[0004] In one embodiment, a method of forming a layer stack of oxide/nitride (ON) layers is provided. The method includes transferring a substrate to a process chamber, heating a pedestal retaining the substrate to a deposition temperature, and flowing a first silicon-containing gas at a first silicon-containing gas flow rate, an oxygen-containing gas at an oxygen-containing gas flow rate, and a first dilution gas at a first dilution gas flow rate into the process chamber. A first radio frequency (RF) power is symmetrically applied to the first silicon-containing gas, the oxygen-containing gas, and the first dilution gas to form a first material layer of silicon dioxide (S1O2). The method further includes flowing a second silicon-containing gas at a second silicon- containing gas flow rate, a nitrogen-containing gas at a nitrogen-containing gas flow rate, and a second dilution gas at a second dilution gas flow rate into the process chamber. A second RF power is symmetrically applied to the second silicon-containing gas, the nitrogen-containing gas, and the second dilution gas to form a second material layer of silicon nitride (ShN4). The flowing the first silicon-containing gas, the oxygen- containing gas, and the first dilution gas, the symmetrically applying the first RF power, the flowing the second silicon-containing gas, the nitrogen-containing gas, and the second dilution gas, and the symmetrically applying the second RF power is repeated until a desired number of material layer pairs of the first material layer and the second material layer make up a layer stack.
[0005] In another embodiment, a method of forming a layer stack of oxide/nitride (ON) layers is provided. The method includes transferring a substrate to a first process chamber, heating a first pedestal of the first process chamber retaining the substrate to a deposition temperature, and flowing a first silicon-containing gas at a first silicon- containing gas flow rate, an oxygen-containing gas at an oxygen-containing gas flow rate, and a first dilution gas at a first dilution gas flow rate into the first process chamber. A first radio frequency (RF) power is symmetrically applied to the first silicon- containing gas, the oxygen-containing gas, and the first dilution gas to form a first material layer of silicon dioxide (S1O2). The method further includes flowing a second silicon-containing gas at a second silicon-containing gas flow rate, a nitrogen- containing gas at a nitrogen-containing gas flow rate, and a second dilution gas at a second dilution gas flow rate into the first process chamber. A second RF power is symmetrically applied to the second silicon-containing gas, the nitrogen-containing gas, and the second dilution gas to form a second material layer of silicon nitride (ShN4). The flowing the first silicon-containing gas, the oxygen-containing gas, and the first dilution gas, the symmetrically applying the first RF power, the flowing the second silicon-containing gas, the nitrogen-containing gas, and the second dilution gas, and the symmetrically applying the second RF power is repeated until a first portion of a desired number of material layer pairs of the first material layer and the second material layer make up a layer stack. The method further includes transferring the substrate from the first process chamber to a second process chamber, heating a second pedestal of the second process chamber retaining the substrate to the deposition temperature, and repeating the flowing the first silicon-containing gas, the oxygen- containing gas, and the first dilution gas, the symmetrically applying the first RF power, the flowing the second silicon-containing gas, the nitrogen-containing gas, and the second dilution gas, and the symmetrically applying the second RF power until a second portion of the desired number of the material layer pairs of the first material layer and the second material layer make up a layer stack.
[0006] In yet another embodiment, a showerhead is provided. The showerhead includes a symmetric radio frequency (RF) circuit disposed in the showerhead connected to a RF power source by a RF feed having a four portions connected to the symmetric RF circuit at 90 degree intervals.
BRIEF DESCRIPTION OF THE DRAWINGS
[0007] So that the manner in which the above recited features of the present disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only exemplary embodiments and are therefore not to be considered limiting of its scope, as the disclosure may admit to other equally effective embodiments.
[0008] Figure 1 is a schematic cross-sectional view of a memory device according to an embodiment.
[0009] Figure 2 is a schematic view of a processing system according to an embodiment.
[0010] Figure 3 is a schematic cross-sectional view of a plasma-enhanced chemical vapor deposition system according to an embodiment.
[0011] Figure 4 is a top, schematic cross-sectional view of a showerhead of a process chamber according to an embodiment. [0012] Figure 5 is a flow diagram of a method of forming a layer stack of ON layers with minimized IPD and improved lithographic overlay according to an embodiment.
[0013] Figure 6 is a flow diagram of a method of forming a layer stack of ON layers with minimized IPD and improved lithographic overlay according to an embodiment.
[0014] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.
DETAILED DESCRIPTION
[0015] Embodiments described herein relate to manufacturing layer stacks of oxide/nitride (ON) layers with minimized in-plane distortion (IPD) and lithographic overlay errors. A method of forming a layer stack ON layers includes flowing a first silicon-containing gas, an oxygen-containing gas, and a first dilution gas. A RF power is symmetrically applied to form a first material layer of S1O2. A second silicon-containing gas, a nitrogen-containing gas, and a second dilution gas are flowed. A second RF power is symmetrically applied to form a second material layer of ShN4. The flowing the first silicon-containing gas, the oxygen-containing gas, and the first dilution gas, the symmetrically applying the first RF power, the flowing the second silicon-containing gas, the nitrogen-containing gas, and the second dilution gas, and the symmetrically applying the second RF power is repeated until a desired number of first material layers and second material layers make up a layer stack.
[0016] Figure 1 is a schematic cross-sectional view of a memory device 100 according to embodiments of the present disclosure. The memory device 100 includes a substrate 102 with a plurality of first material layers 104 and a plurality of second material layers 106 thereon. Material layer pairs 108a, 108b, 108c, ... 108n, also known as a plurality of material layer pairs 108 of a first material layer of the plurality of first material layers 104 and a second material layer of the plurality of second material layers 106, make up a layer stack 110. In the embodiment of an ON stack memory device, each of the first material layers 104 is generally a silicon dioxide layer (O layer) and each of the second material layers 106 is generally a silicon nitride layer (N layer). While Figure 1 depicts the second material layer 106 deposited over the first material layer 104, the deposition order may be reversed such that the first material layer 104 (0 layer) is deposited over the second material layer 106 (N layer). In an embodiment in which the memory device 100 is a 3D NAND memory cell, the memory device 100 further includes a source and a drain (not shown) disposed on opposite ends of a first surface 112 of the substrate 102. For use as flash memory, multiple NAND flash cells are generally connected in series with the adjacent cells sharing a source or drain, and each cell is connected to a bitline and a wordline. In operation, each cell can store data, such as a“0” or“1 ,” therein.
[0017] The methods of manufacturing layer stacks of ON/OP films with minimized IPD and improved lithographic overlay include plasma-enhanced chemical vapor deposition (PECVD) processes, which can be used to form silicon films at relatively low temperatures. The methods can be performed by one or more twin PECVD systems, such as a PRODUCER® plasma enhanced CVD (PECVD) system, available from Applied Materials, Inc. of Santa Clara, Calif. The PECVD systems may be incorporated into a processing system 200, available from Applied Materials, Inc. of Santa Clara, Calif. It is to be understood that the processing system described below is an exemplary processing system and other processing systems, including processing systems from other manufacturers, may be used with or modified to accomplish aspects of the present disclosure. It is to be understood that the PECVD system below is an exemplary PECVD system and other PECVD systems, including PECVD systems from other manufacturers, may be used with or modified to accomplish aspects of the present disclosure.
[0018] Figure 2 is a schematic view of a processing system 200 utilized for methods of manufacturing layer stacks of ON/OP layers with minimized IPD and improved lithographic overlay. As shown in Figure 2, a pair of front opening unified pods (FOUPs) 202 supplies substrates that are received by robotic arms 204 and placed into the holding area 206 before being placed into one of the process chambers 214a-214d of PECVD systems 208a, 208b and/or Rapid Thermal Processing (RTP) chambers 210a, 210b. A second robotic arm 212 may be used to transport the substrates from the holding area 206 to the PECVD systems 208a-208d and/or RTP chambers 210a, 210b and back. The PECVD systems 208a, 208b are utilized to deposit ON/OP layer stacks and the RTP chambers 210a, 210b are utilized to anneal the ON/OP layer stacks. [0019] Figure 3 is a schematic cross-sectional view of a PECVD system 208a utilized for methods of manufacturing layer stacks of ON/OP layers with minimized IPD and improved lithographic overlay. As shown in Figure 3, the PECVD system 208a includes the process chambers 214a, 214b, wherein the process chambers 214a, 214b share resources, for example, such as a shared vacuum pump 304, a first gas source
306, a second gas source 332, and a third gas source 334. The process chamber 214a (e.g., a first process chamber) and the process chamber 214b (e.g., a second process chamber) are similarly configured.
[0020] Each process chamber 214a, 214b has a processing volume 307, 308 that includes a pedestal 309, 310 disposed therein to support a substrate 102. The pedestal 309, 310 includes a heating element (not shown) and a mechanism (not shown) that retains the substrate 102 on the pedestal 309, 310, such as an electrostatic chuck, a vacuum chuck, a substrate retaining clamp, or the like. The pedestal 309, 310 is coupled to and movably disposed in the processing volume 307, 308 by a stem 311 , 312 connected to a lift system (not shown) that moves the pedestal 309, 310 between an elevated processing position and a lowered position that facilitates transfer of the substrate 102 to and from the process chamber 214a, 214b through an opening 315, 316.
[0021] A flow controller 317, 318, such as a mass flow control (MFC) device, is disposed between the first gas source 306 and the process chamber 214a, 214b to control a flow rate of a first process gas from the first gas source 306 to a showerhead 319, 320 used for distributing the first process gas across the processing volume 307, 308. A flow controller 328, 329 is disposed between the second gas source 332 and the process chamber 214a, 214b to control a flow rate of a second process gas from the second gas source 332 to a showerhead 319, 320 used for distributing the second process gas across the processing volume 307, 308. A flow controller 330, 331 is disposed between the third gas source 334 and the process chamber 214a, 214b to control a flow rate of a third process gas from the third gas source 334 to a showerhead 319, 320 used for distributing the third process gas across the processing volume 307, 308. A valve 325, 326 can be disposed between the shared vacuum pump 304 and the process chamber 214a, 214b for controlling the pressure within the processing volume
307, 308. [0022] The showerhead 319, 320 includes a symmetric radio frequency (RF) circuit (shown in Figure 4) connected to a RF power source 321 , 322 by a RF feed 323, 324 having a plurality of portions 344, 345 for striking a substantially uniform plasma in the processing volume 307, 308 from the process gas. The pedestal 309, 310 includes a bottom tuner assembly 340, 341. The bottom tuner assembly 340, 341 includes a tuning electrode 313, 314 coupled to a tuning circuit 342, 343. The tuning circuit 342,
343 is utilized to modulate the impedance on the tuning electrode 313, 314 provide further control of the plasma in the processing volume. For example, modulating the impedance of the tuning electrode 313, 314 increases plasma bombardment on the substrate 102.
[0023] As shown in Figure 4, a cross-sectional top view of the showerhead 319 of the process chambers 214a. The showerhead 319 has a symmetric RF circuit 402 disposed therein coupled to the RF feed 323. Each portion of the plurality of portions
344 is connected to the symmetric RF circuit 402 so that the supply of RF power to the symmetric RF circuit 402 is symmetric. For example, the RF feed 323 has four portions connected to the symmetric RF circuit 402 at 90 degree intervals. A symmetric supply of RF power to the symmetric RF circuit 402 allows for striking the substantially uniform plasma in the processing volume 307. The symmetric RF circuit 402 is symmetric so the plasma in the processing volume 307 is substantially uniform to reduce IPD of the layer stacks of ON layers.
[0024] Figure 5 is a flow diagram of a method 500 of forming a layer stack of ON layers with minimized IPD and improved lithographic overlay. At operation 501 , a substrate 102 is transferred to a process chamber 214a of a PECVD system 208a. In one embodiment, a second robotic arm 212 transfers the substrate 102 from the holding area 206 of the processing system 200 to a process chamber 214a of the PECVD system 208a. At operation 502, the pedestal 309 is heated to a deposition temperature of about 500 degrees Celsius (°C) to about 600 °C. At operation 503, a first material layer 104 of silicon dioxide (S1O2) is deposited. During operation 503, a first silicon-containing gas at a first silicon-containing gas flow rate, an oxygen- containing gas at an oxygen-containing gas flow rate, and a first dilution gas at a first dilution gas flow rate are delivered to the process chamber 214a. [0025] In one embodiment, the flow controller 317 disposed between the first gas source 306 and the process chamber 214a controls the first silicon-containing gas flow rate of the first silicon-containing gas provided to showerhead 319 that distributes the first silicon-containing gas across the processing volume 307 of the process chamber 214a. The first silicon-containing gas may include at least one of silane (SiH4), tetraethyl orthosilicate (TEOS), and disilane (S12H6). In another embodiment, the flow controller 328 disposed between the second gas source 332 and the process chamber 214a controls the oxygen-containing gas flow rate of the oxygen-containing gas provided to showerhead 319 that distributes the oxygen-containing gas across the processing volume 307 of the process chamber 214a. The oxygen-containing gas may include at least one of nitrous oxide (N2O), oxygen gas (O2), and trioxygen (O3). In yet another embodiment, the flow controller 330 disposed between the third gas source 334 and the process chamber 214a controls the first dilution gas flow rate of the first dilution gas provided to showerhead 319 that distributes the first dilution gas across the processing volume 307 of the process chamber 214a. The first dilution gas may include at least one of nitrogen gas (N2), argon (Ar), and helum (He). In some embodiments, the first silicon-containing gas flow rate is about 600 standard cubic centimeters per minute (seem) to about 5000 seem, the oxygen-containing gas flow rate is about 500 seem to about 15000 seem, and the first dilution gas flow rate is about 100 seem to about 20000 seem.
[0026] During the deposition of the first material layer 104 of S1O2, a first RF power is applied to the first silicon-containing gas, the oxygen-containing gas, and the first dilution gas. In one embodiment, the showerhead 319 having a symmetric RF circuit 402 disposed therein connected to a RF power source 321 by a RF feed 323 having a plurality of portions 344 to allow for a symmetric application of the first RF power. Each portion of the plurality of portions is connected to the symmetric RF circuit 402 so that the supply of RF power to the symmetric RF circuit 402 is symmetric. A symmetric application of the first RF power allows for deposition of the first material layer 104 of S1O2 with improved residual uniformity to minimize IPD and improve lithographic overlay of the layer stack 110 of ON layers. In one embodiment, IPD of the layer stack 110 of ON layers is reduced by 10 percent.
[0027] In one embodiment, the first material layer 104 is exposed to a post- deposition treatment process. At optional operation 504, after the deposition of the first material layer 104 of S1O2, the flow of the first silicon-containing gas is discontinued, and the flow of the oxygen-containing gas and the flow of the first dilution gas are continued. The flow of the first silicon-containing gas is discontinued, and the flow of the oxygen-containing gas and the flow of the first dilution gas are continued to stabilize the plasma. The tuning circuit 342 of the bottom tuner assembly 340 is utilized to modulate the impedance on the tuning electrode 313 to increase bombardment of the remaining plasma in the processing volume 307 on the substrate 102. Increasing bombardment of the remaining plasma in the processing volume 307 on the substrate 102 reduces the stress non-uniformity of the first material layer 104. Reducing the stress non-uniformity of the first material layer 104 minimizes IPD and improves lithographic overlay of the layer stack 110 of ON layers.
[0028] At operation 505, a second material layer 106 of silicon nitride (ShN4) is deposited. During operation 505, a second silicon-containing gas at a second silicon- containing gas flow rate, a nitrogen-containing gas at a nitrogen-containing gas flow rate, and a second dilution gas at a first dilution gas flow rate are delivered to the process chamber 214a.
[0029] In one embodiment, the flow controller 317 disposed between the first gas source 306 and the process chamber 214a controls the second silicon-containing gas flow rate of the second silicon-containing gas provided to showerhead 319 that distributes the second silicon-containing gas across the processing volume 307 of the process chamber 214a. The second silicon-containing gas may include at least one of SiH4 and S12H6. In another embodiment, the flow controller 328 disposed between the second gas source 332 and the process chamber 214a controls the nitrogen-containing gas flow rate of the nitrogen-containing gas provided to showerhead 319 that distributes the nitrogen-containing gas across the processing volume 307 of the process chamber 214a. The nitrogen-containing gas may include at least one of ammonia (NH3) and N2. In yet another embodiment, the flow controller 330 disposed between the third gas source 334 and the process chamber 214a controls the second dilution gas flow rate of the second dilution gas provided to showerhead 319 that distributes the second dilution gas across the processing volume 307 of the process chamber 214a. The second dilution gas may include at least one of N2, Ar, and He. The second dilution gas flow rate is selected to improve the residual uniformity of the second material layer 106 of ShN4 and reduce IPD by 50 percent. In one embodiment, the second dilution gas is N2 and the second dilution gas flow rate is greater than about 2000 seem. Increasing the flow of N2 or Ar may improve the plasma uniformity during deposition to reduce IPD. In some embodiments, the second silicon-containing gas flow rate is about 30 standard cubic centimeters per minute (seem) to about 300 seem, the nitrogen-containing gas flow rate is about 200 seem to about 7000 seem, and the first dilution gas flow rate is about 500 seem to about 3000 seem.
[0030] During the deposition of the second material layer 106 of ShN4, a second RF power is applied to the second silicon-containing gas, the nitrogen-containing gas, and the second dilution gas. In one embodiment, the showerhead 319 having the symmetric RF circuit 402 disposed therein is connected to the RF power source 321 by the RF feed 323 to allow for a symmetric application of the second RF power. A symmetric application of the second RF power allows for deposition of the second material layer 106 of ShN4 with improved residual uniformity to minimize IPD and improve lithographic overlay of the layer stack 110 of ON layers.
[0031] In one embodiment, the second material layer 106 is exposed to a post- deposition treatment process. At optional operation 506, after the deposition of the second material layer 106 of ShN4, the flow of the second silicon-containing gas is discontinued, and the flow of the nitrogen-containing gas and the flow of the second dilution gas are continued. The flow of the second silicon-containing gas is discontinued, and the flow of the nitrogen-containing gas and the flow of the second dilution gas are continued to stabilize the plasma. The tuning circuit 342 of the bottom tuner assembly 340 is utilized to modulate the impedance on the tuning electrode 313 to increase bombardment of the remaining plasma in the processing volume 307 on the substrate 102. Increasing bombardment of the remaining plasma in the processing volume 307 on the substrate 102 reduces the stress non-uniformity of the first material layer 104. Reducing the stress non-uniformity of the first material layer 104 minimizes IPD and improves lithographic overlay of the layer stack 110 of ON layers.
[0032] At operation 507, operation 503, optional operation 504, operation 505, and optional operation 506 are repeated until a desired number of material layer pairs 108 of the first material layer 104 of S1O2 and the second material layer 106 of ShN4 make up a layer stack 110. In one embodiment, 64 material layer pairs 108 make up the layer stack 110. [0033] At operation 508, the substrate 102 is transferred to a RTP chamber 210a. In one embodiment, the second robotic arm 212 transfers the substrate 102 from the process chamber 214a of the PECVD system 208a to a RTP chamber 210a of the processing system 200. At operation 509, the layer stack 110 is annealed at an annealing temperature greater than about 800 °C. Annealing at the annealing temperature greater than about 800 °C improves the residual uniformity of the layer stack 110 of ON layers by stress relaxation to minimize IPD and improve lithographic overlay. In one embodiment, IPD of the layer stack 110 of ON layers is reduced by 50 percent.
[0034] Figure 6 is a flow diagram of a method 600 of manufacturing layer stacks of ON layers with minimized IPD and improved lithographic overlay. At operation 601 a substrate 102 is transferred to a process chamber 214a of a PECVD system 208a. At operation 602, the pedestal 309 is heated to a deposition temperature of about 550 °C to about 650 °C. At operation 603, a first material layer 104 of silicon dioxide (S1O2) is deposited. During operation 603, a first silicon-containing gas at a first silicon- containing gas flow rate, an oxygen-containing gas at an oxygen-containing gas flow rate, and a first dilution gas at a first dilution gas flow rate are delivered to the process chamber 214a. During the deposition of the first material layer 104 of S1O2, a first RF power is applied symmetrically to the first silicon-containing gas, the oxygen-containing gas, and the first dilution gas. A symmetric application of the first RF power allows for deposition of the first material layer 104 of S1O2 with improved residual uniformity to minimize IPD and improve lithographic overlay of the layer stack 110 of ON layers.
[0035] At operation 604, a second material layer 106 of silicon nitride (ShN4) is deposited. During operation 604, a second silicon-containing gas at a second silicon- containing gas flow rate, a nitrogen-containing gas at a nitrogen-containing gas flow rate, and a second dilution gas at a first dilution gas flow rate are delivered to the process chamber 214a. The second dilution gas flow rate is selected to improve the residual uniformity of the second material layer 106 of ShN4 and reduce IPD by 50 percent. In one embodiment, the second dilution gas is N2 and the second dilution gas flow rate is greater than about 2000 seem. During the deposition of the second material layer 106 of ShN4, a second RF power is applied symmetrically to the second silicon-containing gas, the nitrogen-containing gas, and the second dilution gas. A symmetric application of the second RF power allows for deposition of the second material layer 106 of ShN4 with improved residual uniformity to minimize IPD and improve lithographic overlay of the layer stack 110 of ON layers.
[0036] At operation 605, operation 603, depositing the first material layer 104 of S1O2, and operation 604, depositing the second material layer 106 of ShN4, are repeated until a first portion of a desired number of material layer pairs 108 of the first material layer 104 of S1O2 and the second material layer 106 of ShN4 that make up a layer stack 110 is deposited. In one embodiment, 64 material layer pairs 108 make up the layer stack 110 and the first portion of the desired number of material layer pairs 108 is 32 material layer pairs 108. In another embodiment, the substrate 102 is rotated 180° after half of the first portion of the desired number of material layer pairs 108 is deposited. Rotating the substrate 102 accounts for non-uniformity within the process chamber 214a to reduce the IPD of the layer stack 110. At operation 606, the substrate 102 is transferred to a process chamber 214b of a PECVD system 208a. In one embodiment, the second robotic arm 212 transfers the substrate 102 from the process chamber 214a of the PECVD system 208a to the process chamber 214b of a PECVD system 208a.
[0037] At operation 607, the pedestal 310 is heated to the deposition temperature of about 550 °C to about 650 °C. Transferring the substrate 102 during the method 600 of forming a layer stack of ON layers allows for improved matching of IPD of the layer stack 110 formed on each pedestal of the process chambers 214a-214d for improved lithographic overlay. For example, the IPD of a layer stack 110 of ON layers formed in the process chamber 214a may be different the IPD of a layer stack 110 of ON layers formed in the process chamber 214b. Transferring the substrate 102 during the method 600 of forming a layer stack of ON layers averages the variation of IPD of the process chamber 214a and the process chamber 214b to match the IPD of the layer stack 110 formed in each process chamber.
[0038] At operation 608, operation 603, depositing the first material layer 104 of S1O2, and operation 604, depositing the second material layer 106 of ShN4, are repeated until a second portion of a desired number of material layer pairs 108 of the first material layer 104 of SiC^ and the second material layer 106 of ShN4 that make up a layer stack 110. In one embodiment, 64 material layer pairs 108 make up the layer stack 110 and the second portion of the desired number of material layer pairs 108 is 32 material layer pairs 108. In another embodiment, the substrate 102 is rotated 180° after half of the second portion of the desired number of material layer pairs 108 is deposited. Rotating the substrate 102 accounts for non-uniformity within the process chamber 214b to reduce the IPD of the layer stack 110. At operation 609, the substrate 102 is transferred to a RTP chamber 210a. In one embodiment, the second robotic arm 212 transfers the substrate 102 from the process chamber 214b of the PECVD system 208a to a RTP chamber 210a of the processing system 200. At operation 610, the layer stack 110 is annealed at an annealing temperature greater than about 800 °C. Annealing at the annealing temperature greater than about 800 °C improves the residual uniformity of the layer stack 110 of ON layers by stress relaxation to minimize IPD and improve lithographic overlay. In one embodiment, IPD of the layer stack 110 of ON layers is reduced by 50 percent.
[0039] In summation, methods of manufacturing layer stacks of ON layer with minimized IPD and improved lithographic overlay and a showerhead configured to form a substantially uniform plasma are described herein. During the deposition of the first material layer of S1O2 and the second material layer of ShN4 RF power is applied symmetrically by the showerhead to the first silicon-containing gas, the oxygen- containing gas, and the first dilution gas. A symmetric application of the RF power allows for deposition of the first material layer of S1O2 and the second material layer of ShN4 with improved residual uniformity to minimize IPD and improve lithographic overlay of the layer stack of ON layers. The second dilution gas flow rate is selected to improve the residual uniformity of the second material layer of ShN4 and reduce IPD. Transferring the substrate allows for differences of IPD of the layer stack formed on each pedestal of the process chambers to be eliminated for improved lithographic overlay. Annealing at the annealing temperature greater than about 800 °C improves the residual uniformity of the layer stack of ON layers by stress relaxation to minimize IPD and improve lithographic overlay.
While the foregoing is directed to examples of the present disclosure, other and further examples of the disclosure may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.

Claims

What is claimed is:
1. A method of forming a layer stack of oxide/nitride (ON) layers, comprising:
transferring a substrate to a process chamber;
heating a pedestal retaining the substrate to a deposition temperature;
flowing a first silicon-containing gas at a first silicon-containing gas flow rate, an oxygen-containing gas at an oxygen-containing gas flow rate, and a first dilution gas at a first dilution gas flow rate into the process chamber;
symmetrically applying a first radio frequency (RF) power to the first silicon- containing gas, the oxygen-containing gas, and the first dilution gas to form a first material layer of silicon dioxide (S1O2);
flowing a second silicon-containing gas at a second silicon-containing gas flow rate, a nitrogen-containing gas at a nitrogen-containing gas flow rate, and a second dilution gas at a second dilution gas flow rate into the process chamber;
symmetrically applying a second RF power to the second silicon-containing gas, the nitrogen-containing gas, and the second dilution gas to form a second material layer of silicon nitride (ShN4); and
repeating the flowing the first silicon-containing gas, the oxygen-containing gas, and the first dilution gas, the symmetrically applying the first RF power, the flowing the second silicon-containing gas, the nitrogen-containing gas, and the second dilution gas, and the symmetrically applying the second RF power until a desired number of material layer pairs of the first material layer and the second material layer make up a layer stack.
2. The method of claim 1 , further comprising:
transferring the substrate from the process chamber to a Rapid Thermal Processing (RTP) chamber; and
annealing at an annealing temperature greater than about 800 °C.
3. The method of one of claims 1 or 2, wherein the deposition temperature is about 500 degrees (°C) to about 650 °C.
4. The method of one of claims 1 -3, wherein the first silicon-containing gas comprises at least one of silane (SiH4), tetraethyl orthosilicate (TEOS), and disilane (Si2H6), the oxygen-containing gas comprises at least one of nitrous oxide (N2O), oxygen gas (O2), and trioxygen (O3), and the first dilution gas comprises at least one of nitrogen gas (N2), argon (Ar), and helium (He).
5. The method of one of claims 1-4, wherein the second silicon-containing gas comprises at least one of SiH4 and S12H6, the nitrogen-containing gas comprises at least one of ammonia (NH3) and N2, and the second dilution gas comprises at least one of N2, Ar, and He.
6. The method of one of claims 1 -5, wherein the first silicon-containing gas flow rate is about 600 standard cubic centimeters per minute (seem) to about 5000 seem, the oxygen-containing gas flow rate is about 500 seem to about 15000 seem, and the first dilution gas flow rate is about 100 seem to about 20000 seem.
7. The method of one of claims 1-6, wherein the second silicon-containing gas flow rate is about 30 seem to about 300 seem, the nitrogen-containing gas flow rate is about 2000 seem to about 7000 seem, and the second dilution gas flow rate is about 500 seem to about 3000 seem.
8. A method of forming a layer stack of oxide/nitride (ON) layers, comprising:
transferring a substrate to a first process chamber;
heating a first pedestal of the first process chamber retaining the substrate to a deposition temperature;
flowing a first silicon-containing gas at a first silicon-containing gas flow rate, an oxygen-containing gas at an oxygen-containing gas flow rate, and a first dilution gas at a first dilution gas flow rate into the first process chamber;
symmetrically applying a first radio frequency (RF) power to the first silicon- containing gas, the oxygen-containing gas, and the first dilution gas to form a first material layer of silicon dioxide (S1O2);
flowing a second silicon-containing gas at a second silicon-containing gas flow rate, a nitrogen-containing gas at a nitrogen-containing gas flow rate, and a second dilution gas at a second dilution gas flow rate into the first process chamber;
symmetrically applying a second RF power to the second silicon-containing gas, the nitrogen-containing gas, and the second dilution gas to form a second material layer of silicon nitride (ShN4);
repeating the flowing the first silicon-containing gas, the oxygen-containing gas, and the first dilution gas, the symmetrically applying the first RF power, the flowing the second silicon-containing gas, the nitrogen-containing gas, and the second dilution gas, and the symmetrically applying the second RF power until a first portion of a desired number of material layer pairs of the first material layer and the second material layer make up a layer stack;
transferring the substrate from the first process chamber to a second process chamber;
heating a second pedestal of the second process chamber retaining the substrate to the deposition temperature; and
repeating the flowing the first silicon-containing gas, the oxygen-containing gas, and the first dilution gas, the symmetrically applying the first RF power, the flowing the second silicon-containing gas, the nitrogen-containing gas, and the second dilution gas, and the symmetrically applying the second RF power until a second portion of the desired number of the material layer pairs of the first material layer and the second material layer make up the layer stack.
9. The method of claim 8, further comprising:
transferring the substrate from the second process chamber to a Rapid Thermal Processing (RTP) chamber; and
annealing at an annealing temperature greater than about 800 °C.
10. The method of one of claims 10 or 11 , wherein the first silicon-containing gas comprises at least one of silane (SiH4), tetraethyl orthosilicate (TEOS), and disilane (Si2H6), the oxygen-containing gas comprises at least one of nitrous oxide (N2O), oxygen gas (O2), and trioxygen (O3), and the first dilution gas comprises at least one of nitrogen gas (N2), argon (Ar), and helium (Fie).
11. The method of one of claims 8-10, wherein the second silicon-containing gas comprises at least one of SiH4 and Si2H6, the nitrogen-containing gas comprises at least one of ammonia (NFI3) and N2, and the second dilution gas comprises at least one of N2, Ar, and Fie.
12. The method of one of claims 8-11 , wherein the first silicon-containing gas flow rate is about 600 standard cubic centimeters per minute (seem) to about 5000 seem, the oxygen-containing gas flow rate is about 500 seem to about 15000 seem, and the first dilution gas flow rate is about 100 seem to about 20000 seem.
13. The method of one of claims 8-12, wherein the second silicon-containing gas flow rate is about 30 seem to about 300 seem, the nitrogen-containing gas flow rate is about 200 seem to about 7000 seem, and the second dilution gas flow rate is about 500 seem to about 3000 seem.
14. The method of one of claims 8-13, wherein the second dilution gas is N2 and the second dilution gas flow rate is greater than about 2000 seem.
15. A showerhead, comprising:
a symmetric radio frequency (RF) circuit disposed in the showerhead connected to a RF power source by a RF feed having a four portions connected to the symmetric RF circuit at 90 degree intervals.
PCT/US2019/042489 2018-07-31 2019-07-18 On stack overlay improvement for 3d nand Ceased WO2020028064A1 (en)

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JP2021504225A JP7461926B2 (en) 2018-07-31 2019-07-18 Improved ON Stack Overlay for 3D NAND
SG11202010548YA SG11202010548YA (en) 2018-07-31 2019-07-18 On stack overlay improvement for 3d nand
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