WO2020024339A1 - Contrôleur de séquence temporelle et procédé de détection de séquence temporelle pour celui-ci, et affichage à cristaux liquides - Google Patents

Contrôleur de séquence temporelle et procédé de détection de séquence temporelle pour celui-ci, et affichage à cristaux liquides Download PDF

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Publication number
WO2020024339A1
WO2020024339A1 PCT/CN2018/101306 CN2018101306W WO2020024339A1 WO 2020024339 A1 WO2020024339 A1 WO 2020024339A1 CN 2018101306 W CN2018101306 W CN 2018101306W WO 2020024339 A1 WO2020024339 A1 WO 2020024339A1
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WIPO (PCT)
Prior art keywords
timing
real
time
enable signal
data enable
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PCT/CN2018/101306
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English (en)
Chinese (zh)
Inventor
肖光星
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深圳市华星光电技术有限公司
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Publication of WO2020024339A1 publication Critical patent/WO2020024339A1/fr

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays

Definitions

  • the invention belongs to the technical field of timing controllers, and in particular, relates to a timing controller, a timing detection method thereof, and a liquid crystal display.
  • a liquid crystal display is a flat and ultra-thin display device. It consists of a certain number of color or black and white pixels and is placed in front of a light source or reflective surface. Liquid crystal displays have very low power consumption, and have the characteristics of high image quality, small size, and light weight. Therefore, they have become the mainstream of displays. At present, liquid crystal displays are mainly thin film transistor liquid crystal displays, and liquid crystal panels are the main components of liquid crystal displays.
  • the liquid crystal panel generally includes a color filter substrate and a TFT array substrate disposed opposite to each other, and a liquid crystal layer flat between the two substrates.
  • an array substrate row driving (GOA) technology is often used in a liquid crystal display panel.
  • the GOA technology integrates a gate row driving circuit on the array substrate in the array substrate manufacturing process, which can be omitted.
  • the original gate drive IC on the array substrate achieves the purpose of reducing production costs and achieving a narrow frame.
  • the GOA timing may be disordered, causing the GOA disorder in the panel, resulting in overcurrent protection of the level shift device and causing a black screen.
  • the timing of the GOA driving circuit is generated by the timing controller, and the timing controller needs to generate the corresponding GOA timing according to the data enable signal (Data Enable). If the DE timing timing is disordered, it will eventually cause the GOA timing disorder. .
  • an object of the present invention is to provide a timing controller capable of outputting a correct timing of a data enable signal, a timing detection method thereof, and a liquid crystal display.
  • a timing detection method of a timing controller includes the following steps:
  • S2 Acquire real-time parameters corresponding to the actual timing of the data enable signal in the timing controller, and judge the state of the real-time timing of the data enable signal according to the real-time parameters and the configuration parameters;
  • S3 According to the state of the real-time timing of the data enable signal, output the standard timing or real-time timing of the data enable signal.
  • the configuration parameter includes a number of standard high levels corresponding to a standard timing of a data enable signal
  • the step S2 specifically includes:
  • the real-time timing of the data enable signal is normal; if not, the real-time timing of the data enable signal is abnormal.
  • the configuration parameter includes a number of standard low levels corresponding to a standard timing of a data enable signal
  • the step S2 specifically includes:
  • the real-time timing of the data enable signal is normal; if not, the real-time timing of the data enable signal is abnormal.
  • the configuration parameter includes a standard line blanking duration range value corresponding to a standard timing of the data enable signal
  • the step S2 specifically includes:
  • the real-time timing of the data enable signal is normal; if not, the real-time timing of the data enable signal is abnormal.
  • the configuration parameter includes a standard field blanking duration range value corresponding to a standard timing of a data enable signal
  • the step S2 specifically includes:
  • the real-time timing of the data enable signal is normal; if not, the real-time timing of the data enable signal is abnormal.
  • step S3 specifically includes:
  • the real-time timing of the data enable signal is normal, the real-time timing of the data enable signal is directly output.
  • the invention also discloses a timing controller, including:
  • a configuration unit configured to obtain configuration parameters corresponding to a standard timing of a data enable signal
  • a detecting unit configured to obtain a real-time parameter corresponding to the actual timing of the data enable signal, and judge a state of the real-time timing of the data enable signal according to the real-time parameter and the configuration parameter;
  • the processing unit is configured to output a standard timing or a real-time timing of the data enable signal according to a state of the real-time timing of the data enable signal.
  • the configuration parameters include a range value of the number of standard high levels corresponding to the standard timing of the data enable signal, a range value of the number of standard low levels, a range value of the standard line blanking duration, and a standard field cancellation.
  • the real-time parameters include the number of real-time high levels, the number of real-time low levels, the real-time line blanking time, and the real-time field blanking time corresponding to the real-time timing of the data enable signal At least one of.
  • the detection unit includes:
  • Video frame header detection module used to detect whether a frame of video is turned on
  • the detection module is configured to obtain a real-time parameter corresponding to the actual timing of the data enable signal after a frame of the video is turned on, and judge a state of the real-time timing of the data enable signal according to the real-time parameter and the configuration parameter.
  • the invention also discloses a liquid crystal display.
  • the liquid crystal display stores a plurality of instructions, and the plurality of instructions are suitable for being loaded by a processor and executing the following steps:
  • the corresponding timing of the data enable signal is output.
  • a timing controller, a timing detection method and a liquid crystal display disclosed by the present invention detect the real-time timing corresponding to the real-time parameters of the data enable signal before outputting the data enable signal, and determine whether each parameter meets the standard timing If the requirements are not met, the standard is re-generated and output. If the requirements are met, the real-time timing is directly output. This can ensure that the output timing of the data enable signal is normal and thus the GOA circuit timing is normal.
  • FIG. 1 is a flowchart of a timing detection method according to the first embodiment of the present invention
  • FIG. 2 is a timing diagram of a timing controller according to the first embodiment of the present invention.
  • FIG 3 is another timing diagram of the timing controller according to the first embodiment of the present invention.
  • FIG. 4 is a schematic diagram of a timing controller according to a second embodiment of the present invention.
  • FIG. 5 is a schematic diagram of a detection unit according to a second embodiment of the present invention.
  • FIG. 1 shows a flowchart of a timing detection method of a timing controller according to a first embodiment of the present invention.
  • the timing detection method includes steps S1 to S3:
  • Step S1 Acquire a configuration parameter corresponding to the standard timing of the data enable signal.
  • the standard timings of the data enable signals in the displays with different resolutions are different, and the configuration parameters corresponding to the standard timings are different.
  • the configuration parameters include the number of standard high levels and the number of standard low levels corresponding to the standard timing. Number, standard line blanking time range value, and standard field blanking time range value.
  • Step S2 Acquire a real-time parameter corresponding to the actual timing of the data enable signal in the timing controller, and judge the state of the real-time timing of the data enable signal according to the real-time parameter and the configuration parameter.
  • the step S2 includes:
  • Step S201 Detect whether a frame of the video is turned on.
  • the data enable signal is at a low level, that is, DE_VB
  • the data enable signal is at a low level, that is, DE_VB
  • the data enable signal is at a low level, that is, DE_VB
  • the data enable signal is at a low level, that is, DE_VB
  • the video signal is in the vertical valid period, that is, VVD in the timing diagram
  • the DE signal includes a plurality of DE periodic signals, wherein each DE periodic signal includes a plurality of alternating high and low levels.
  • each DE periodic signal includes a plurality of alternating high and low levels.
  • the multiple DE periodic signals mentioned in this embodiment need to be determined according to the specific parameters of the specific display panel. For example, for a 4K display with a resolution of 4800 * 3840, the low-level duration of the DE signal is greater than 4800 DE periodic signals.
  • the total duration of the video is determined, one frame of the video is turned on.
  • Step S202 if yes, calculate the number of real-time high levels corresponding to the real-time timing of the data enable signal.
  • the DE signal in the vertical valid period is detected.
  • the real-time high level number of the DE signal is counted until the entire vertical valid period is detected.
  • Step S203 determine whether the number of real-time high levels is the same as the number of standard high levels
  • Step S204 if yes, judge that the real-time timing of the data enable signal is normal; if not, judge that the real-time timing of the data enable signal is abnormal.
  • step S2 includes:
  • Step S211 It is detected whether a frame of the video is turned on. This step S211 is the same as step S201, and details are not described herein.
  • Step S212 If yes, calculate the number of low-level real-time signals corresponding to the real-time timing of the data enable signal.
  • a DE period signal in a vertical valid period is detected, and when a falling edge of the DE period signal is detected, a real-time low level number of the DE signal is counted until a complete vertical valid period is detected.
  • Step S213 It is determined whether the number of real-time low levels is the same as the number of standard low levels.
  • Step S214 if yes, judge that the real-time timing of the data enable signal is normal; if not, judge that the real-time timing of the data enable signal is abnormal.
  • the step S2 includes:
  • Step S221 It is detected whether a frame of the video is turned on. This step S221 is the same as step S201, and details are not described herein.
  • Step S222 The real-time line blanking duration corresponding to the real-time timing of the data enable signal is detected.
  • Step S223 determine whether the real-time line blanking duration is within the range of the standard line blanking duration
  • Step S224 if yes, judge that the real-time timing of the data enable signal is normal; if not, judge that the real-time timing of the data enable signal is abnormal.
  • the step S2 includes:
  • Step S231 It is detected whether a frame of the video is turned on. This step S231 is the same as step S201, and details are not described herein.
  • Step S232 If yes, the real-time field blanking duration corresponding to the real-time timing of the detection data enable signal.
  • Step S233 Determine whether the real-time field blanking duration is within the range of the standard field blanking duration.
  • Step S234 if yes, judge that the real-time timing of the data enable signal is normal; if not, judge that the real-time timing of the data enable signal is abnormal.
  • the real-time parameters corresponding to the real-time timing of the data enable signal for example, the number of real-time high levels, the number of real-time low levels, the real-time blanking time and the real-time field effect duration, it is determined whether each parameter meets the standard As long as one of the parameters does not meet the requirements of the timing, it indicates that the current timing is abnormal and corresponding processing needs to be taken.
  • Step S3 output the corresponding timing of the data enable signal according to the state of the real-time timing of the data enable signal.
  • step S2 there are two possibilities for the state of the real-time sequence. If the real-time timing is normal, it can be directly output. Correspondingly, the timing controller generates a timing signal required by the GOA circuit according to the real-time timing.
  • the timing controller If the real-time timing is abnormal, use the standard timing generation module to generate the standard timing of the data enable signal, and replace the standard timing with the real-time timing. Accordingly, the timing controller generates the timing required by the GOA circuit according to the standard timing.
  • the standard timing generation module generates a corresponding standard timing according to the specifications of the display. For example, for a 4K display, the standard timing generation module generates a standard timing corresponding to a 4K display.
  • the timing detection method disclosed in the first embodiment of the present invention detects the real-time timing corresponding to the real-time parameters of the data enable signal before outputting the data enable signal, and determines whether each parameter meets the requirements of the standard timing. Generate standards and output, if they meet, directly output the real-time timing, this can ensure that the output timing of the data enable signal is normal, and thus the GOA circuit timing is normal.
  • the timing controller includes a configuration unit 10, a detection unit 20, and a processing unit 30.
  • the configuration unit 10 is configured to obtain a data enable signal from an external microcontroller. Configuration parameters corresponding to standard timing; the detection unit 20 is configured to obtain real-time parameters corresponding to the real-time timing of the data enable signal, and judge the status of the real-time timing of the data enable signal according to the real-time parameters and configuration parameters; the processing unit 30 is configured to The state of the real-time timing of the data enable signal, and the corresponding timing of the output data enable signal.
  • the detection unit 20 includes a video frame header detection module 21 and a detection module 22.
  • Video frame header detection module 21 is used to detect whether a frame of video is turned on; detection module 22 is used to obtain real-time parameters corresponding to the actual timing of the data enable signal after a frame of video is turned on, and according to the real-time parameters and configuration parameters Determine the status of the real-time timing of the data enable signal.
  • the configuration parameters include a range value of the number of standard high levels corresponding to the standard timing of the data enable signal, a range value of the number of standard low levels, a range value of the standard line blanking period, and a range value of the standard field blanking period.
  • At least one of the real-time parameters includes at least one of the number of real-time high levels, the number of real-time low levels, the real-time blanking duration, and the real-time field blanking duration corresponding to the real-time timing of the data enable signal.
  • a plurality of instructions are stored in the liquid crystal display according to the third embodiment of the present invention, and the plurality of instructions are suitable for being loaded by the processor and executing the following steps:
  • the corresponding timing of the data enable signal is output.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
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  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

L'invention concerne un contrôleur de séquence temporelle et un procédé de détection de séquence temporelle pour celui-ci, et un affichage à cristaux liquides. Le procédé de détection de séquence temporelle comprend les étapes suivantes consistant à : acquérir des paramètres de configuration correspondant à une séquence temporelle standard d'un signal d'activation de données (S1) ; acquérir des paramètres en temps réel dans le contrôleur de séquence temporelle qui correspondent à une séquence temporelle réelle du signal d'activation de données, et déterminer l'état de séquence temporelle en temps réel du signal d'activation de données selon les paramètres en temps réel et les paramètres de configuration (S2) ; produire une séquence temporelle correspondante du signal d'activation de données selon l'état de séquence temporelle en temps réel du signal d'activation de données (S3). Des paramètres en temps réel correspondant à une séquence temporelle en temps réel d'un signal d'activation de données sont détectés avant de produire le signal d'activation de données pour déterminer si chaque paramètre est conforme aux critères d'une séquence temporelle standard ; si ce n'est pas le cas, une norme est recréée et fournie ; et si c'est le cas, la séquence temporelle en temps réel est produite directement ; ainsi, il peut être assuré qu'une séquence temporelle de sortie du signal d'activation de données est normale, ce qui assure que la séquence temporelle d'un circuit GOA est normale.
PCT/CN2018/101306 2018-08-01 2018-08-20 Contrôleur de séquence temporelle et procédé de détection de séquence temporelle pour celui-ci, et affichage à cristaux liquides WO2020024339A1 (fr)

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CN201810864145.4 2018-08-01
CN201810864145.4A CN109036309A (zh) 2018-08-01 2018-08-01 时序控制器及其时序检测方法、液晶显示器

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CN111477187B (zh) * 2020-05-08 2022-01-04 Tcl华星光电技术有限公司 时序控制器及其信号校准方法、显示装置
CN111681623B (zh) * 2020-06-09 2022-04-08 Tcl华星光电技术有限公司 时序控制器及其帧间标志的生成方法、显示装置
CN114842787A (zh) * 2022-04-26 2022-08-02 深圳市华星光电半导体显示技术有限公司 显示面板

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CN102376289A (zh) * 2010-08-06 2012-03-14 晨星软件研发(深圳)有限公司 显示时序控制电路及其方法
US20160005345A1 (en) * 2014-07-07 2016-01-07 Rohm Co., Ltd. Noise removal circuit
CN107068092A (zh) * 2017-05-04 2017-08-18 京东方科技集团股份有限公司 一种静电防护方法、装置及液晶显示器
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