WO2020019551A1 - 一种raid卡供电电路 - Google Patents
一种raid卡供电电路 Download PDFInfo
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- WO2020019551A1 WO2020019551A1 PCT/CN2018/112057 CN2018112057W WO2020019551A1 WO 2020019551 A1 WO2020019551 A1 WO 2020019551A1 CN 2018112057 W CN2018112057 W CN 2018112057W WO 2020019551 A1 WO2020019551 A1 WO 2020019551A1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/30—Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations
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- the present application relates to the technical field of RAID (Redundant Arrays of Independent Disks), and more particularly, to a RAID card power supply circuit.
- RAID Redundant Arrays of Independent Disks
- a RAID card is generally used to form multiple disks in the server system by using RAID0, RAID5, etc. to form a disk array to expand the read and write of disk data. Performance and storage capacity.
- a backup battery or a super capacitor module is configured on the RAID card as a power backup unit, so that when the system loses power, the power backup unit can be a RAID card. Power supply, and then save the real-time data of the disk array in time, the circuit for powering the RAID card is shown in Figure 1.
- the prior art circuit for powering a RAID card has the problem that if an overcurrent occurs between the power backup unit and the RAID card, the power backup unit will be damaged.
- the purpose of this application is to provide a RAID card power supply circuit, so as to solve the problem that the circuit for realizing power supply of a RAID card in the prior art may damage the power backup unit if an overcurrent occurs between the power backup unit and the RAID card.
- a RAID card power supply circuit includes a PMOS tube, a current detection unit, and / or an arithmetic unit; the D end of the PMOS tube is connected to the current detection unit, and the S end of the PMOS tube is protected from power failure of the RAID card.
- the power backup unit in the circuit is connected, the G terminal of the PMOS tube is connected to the output terminal of the OR operation unit, and the input terminal of the OR operation unit is respectively connected to the output terminal of the current detection unit and the power failure.
- the output end of the power failure detection unit in the protection circuit is connected, and the current detection unit is disposed between the power backup unit and the RAID card, and is used to supply power to the RAID card in the power backup unit. If it is determined that the line between the power backup unit and the RAID card has an overcurrent, a high level is output to control the PMOS tube to be disconnected.
- an isolation unit having an isolation protection function is further provided between the input terminal of the OR operation unit and the current detection unit.
- the isolation unit includes a first NMOS tube and a second NMOS tube, a D terminal of the first NMOS tube is connected to a power source and a G terminal of the second NMOS tube, and a G terminal of the first NMOS tube is connected An output terminal of the current detection unit, a D terminal of the second NMOS tube are connected to a power source and an input terminal of the OR operation unit, and the S terminal of the first NMOS tube and the second NMOS tube are grounded.
- a first resistor is further provided between the first NMOS tube and the correspondingly connected power source, and a second resistor is further provided between the second NMOS tube and the correspondingly connected power source.
- the current detection unit includes a current detection chip and a third resistor
- the third resistor is disposed between the power backup unit and the RAID card, and the positive end of the acquisition end of the current detection chip and The negative terminal of the acquisition terminal is respectively connected to both ends of the third resistor.
- a fourth resistor is further provided between the positive end of the acquisition end of the current detection chip and the third resistor, and a fourth resistor is further provided between the negative end of the acquisition end of the current detection chip and the third resistor. Fifth resistor.
- the current detection chip is an ADM1276 chip
- a pin SENSE + of the ADM1276 chip is used as the positive terminal of the acquisition terminal
- a pin SENSE- of the ADM1276 chip is used as the negative terminal of the acquisition terminal
- the ADM1276 chip is The pin GATE is used as an output terminal of the current detection unit.
- the OR operation unit includes a first Schottky diode and a second Schottky diode, and a positive terminal of the first Schottky diode is connected to an output terminal of the power-down detection unit, and the first The negative terminal of the Schottky diode is connected to the G terminal of the NMOS transistor, and is connected to the negative terminal of the second Schottky diode in a wired-OR manner.
- the positive terminal of the second Schottky diode is connected to the The D terminal connection of the second PMOS tube is described.
- a power supply circuit for a RAID card includes a PMOS tube, a current detection unit, and / or an arithmetic unit; a D end of the PMOS tube is connected to the current detection unit, and an S end of the PMOS tube is connected to the RAID card.
- the power backup unit in the power-down protection circuit is connected, the G terminal of the PMOS tube is connected to the output terminal of the OR operation unit, and the input terminal of the OR operation unit is respectively connected to the output terminal of the current detection unit and
- the output end of the power failure detection unit in the power failure protection circuit is connected, and the current detection unit is disposed between the power backup unit and the RAID card, and is configured to set the power backup unit to the RAID.
- a high level is output to control the PMOS tube to be disconnected.
- the current detection unit detects an overcurrent between the power backup unit and the RAID card, it outputs a high level, and the high level
- the low level input from the power-down detection unit is high after the OR operation of the operation unit, which controls the PMOS tube to be disconnected; if the current detection unit detects that there is no overcurrent between the backup power unit and the RAID, then Output low level, the low level outputted by the power-down detection unit and the low level output from the OR operation unit to obtain a low level to control the conduction of the PMOS tube; thus, it can be between the power backup unit and the RAID card
- control the PMOS tube to disconnect to cut off the overcurrent line to avoid damage to the backup power unit by the overcurrent.
- the body diode included in the PMOS tube can be used to prevent the backup power unit and the RAID card from being installed, but when the corresponding system is not started, the backup power unit leaks electricity to the RAID card, thereby preventing overcurrent. And anti-leakage dual functions.
- FIG. 1 is a circuit diagram for powering a RAID card in the prior art
- FIG. 2 is a circuit diagram of a RAID card power supply circuit according to an embodiment of the present application.
- FIG. 3 is a circuit diagram of a first part of a RAID card power supply circuit according to an embodiment of the present application
- FIG. 4 is a circuit diagram of a second part of a RAID card power supply circuit according to an embodiment of the present application.
- FIG. 5 is a circuit diagram of a third part of a RAID card power supply circuit according to an embodiment of the present application.
- FIG. 2 shows a RAID card power supply circuit provided by an embodiment of the present application, which includes a PMOS tube (PMOS2 in the figure is the PMOS tube in the present application), a current detection unit, and / or an arithmetic unit; PMOS The D terminal of the tube is connected to the current detection unit, the S terminal of the PMOS tube is connected to the power backup unit in the power-down protection circuit of the RAID card, the G terminal of the PMOS tube is connected to the output terminal of the OR operation unit, or the input of the operation unit Terminals are respectively connected to the output terminal of the current detection unit and the output terminal of the power-down detection unit in the power-down protection circuit.
- PMOS PMOS tube
- the D terminal of the tube is connected to the current detection unit
- the S terminal of the PMOS tube is connected to the power backup unit in the power-down protection circuit of the RAID card
- the G terminal of the PMOS tube is connected to the output terminal of the OR operation unit, or the input of the operation unit Terminals are respectively connected to the
- the current detection unit is disposed between the power backup unit and the RAID card, and is used as a RAID card in the power backup unit. In the process of power supply, if it is determined that the line between the backup power unit and the RAID card has overcurrent, it outputs a high level to control the PMOS tube to be disconnected.
- the output signal of the power failure detection unit is A
- the output signal of the current detection unit is B
- the signal of the G terminal of PMOS2 is Y
- 1 represents a high level
- 0 represents a low level.
- the P12V_IN from the PCIE interface is used to supply power to the RAID card without power failure.
- a value of 0 means power failure, which means that the power supply unit supplies power to the RAID card.
- B means 1 means that the line between the power supply unit and the RAID card is overcurrent.
- B is 0 to indicate that the line between the power backup unit and the RAID card has not overcurrent;
- Y is 1 to indicate that PMOS2 is off, and Y is 0 to indicate that PMOS2 is on; therefore, the logic shown in Table 1 exists in this application relationship:
- PMOS0 is disconnected, PMOS1 is turned on, and the RAID card is powered by the backup power unit.
- the current detection unit detects an overcurrent between the power backup unit and the RAID card, it outputs a high level, the high level output by the current detection unit and the low level output by the power-down detection unit to PMOS2.
- a high level is obtained.
- the G terminal of PMOS2 is input high level, and PMOS2 is disconnected to cut off the overcurrent circuit to prevent the overcurrent from damaging the backup unit. If the current detection unit detects the backup Electrical unit and RAID card If there is no overcurrent between them, a low level is output.
- the low level output by the current detection unit and the low level output by the power-down detection unit to PMOS2 are obtained after the OR operation of the OR unit. Input low level, PMOS2 is turned on, so that the power supply unit supplies power to the RAID card.
- the anode of the body diode included in PMOS2 is connected to the current detection unit, and the cathode is connected to the backup power unit. Therefore, it is possible to avoid the situation that the backup unit and the RAID card are installed, but the corresponding system is not started. The electrical unit will leak to the RAID card through the body diode of the PMOS1, causing it to malfunction.
- the current detection unit when the power backup unit supplies power to the RAID card, if the current detection unit detects an overcurrent between the power backup unit and the RAID card, it outputs a high level, and the high level The low level input from the power-down detection unit is high after the OR operation of the operation unit, which controls the PMOS tube to be disconnected; if the current detection unit detects that there is no overcurrent between the backup power unit and the RAID, then Output low level, the low level outputted by the power-down detection unit and the low level output from the OR operation unit to obtain a low level to control the conduction of the PMOS tube; thus, it can be between the power backup unit and the RAID card
- the overcurrent occurs, control the PMOS tube to disconnect to cut off the overcurrent line to avoid damage to the backup power unit by the overcurrent. Control the PMOS tube to be turned on when there is no overcurrent between the backup power unit and the RAID card, so that the backup power unit Power on the RAID card normally.
- the body diode included in the PMOS tube can be used to prevent the backup power unit and the RAID card from being installed, but when the corresponding system is not started, the backup power unit leaks electricity to the RAID card, thereby preventing overcurrent. And anti-leakage dual functions.
- An embodiment of the present application provides a RAID card power supply circuit, or an isolation unit with an isolation protection function may be provided between the input end of the computing unit and the current detection unit.
- the isolation and protection function of the isolation unit Through the isolation and protection function of the isolation unit, the mutual influence between the current detection unit and the OR operation unit can be avoided, and the normal implementation of the corresponding function is guaranteed.
- the isolation unit may be composed of two inverting units, that is, the isolation unit may include a first NMOS tube and a second NMOS tube.
- the D terminal of the first NMOS tube is connected to a power source and the G terminal of the second NMOS tube.
- the G terminal of the NMOS tube is connected to the output terminal of the current detection unit, the D terminal of the second NMOS tube is connected to the power supply and / or the input terminal of the arithmetic unit, and the S terminals of the first NMOS tube and the second NMOS tube are grounded.
- the specific circuit settings of the isolation unit can be set according to actual needs and are all within the protection scope of this application.
- the circuit composed of the two inverting units described above is used to achieve the isolation protection function. Fewer devices, lower cost, simple circuit and easy implementation.
- a first resistor may be further provided between a first NMOS tube (Negative Channel Metal Oxide Semiconductor) and a correspondingly connected power source,
- a second resistor may also be provided between the second NMOS tube and the correspondingly connected power source.
- a corresponding resistance is set between the first NMOS tube and the correspondingly connected power source, and between the second NMOS tube and the correspondingly connected power source, and the corresponding resistance can be used to play a role of current limiting protection. To avoid damage to the corresponding NMOS tube by the connected power supply.
- the current detection unit may include a current detection chip and a third resistor.
- the third resistor is disposed between the power backup unit and the RAID card, and the positive end of the acquisition end of the current detection chip. And the negative terminal of the acquisition terminal is respectively connected to both ends of the third resistor.
- the essence of data collection in this way is to collect the voltage on both sides of the third resistor, and then compare the difference between the collected voltage on both sides of the third resistor with a preset voltage threshold. If the voltage difference is greater than the voltage threshold, it means that there is overcurrent, otherwise it means that there is no overcurrent, so that under the premise of simple and easy implementation of the circuit, accurate data collection and accurate judgment of whether there is overcurrent can be realized.
- a fourth resistor may be further provided between the positive terminal of the acquisition terminal of the current detection chip and the third resistor, and the negative terminal of the acquisition terminal of the current detection chip and the third resistor may be provided.
- a fifth resistor may also be provided.
- the current detection chip may be an ADM1276 chip, the pin SENSE + of the ADM1276 chip is used as the positive terminal of the acquisition terminal, the pin SENSE- of the ADM1276 chip is used as the negative terminal of the acquisition terminal, and the lead of the ADM1276 chip.
- Pin GATE is used as the output terminal of the current detection unit.
- the chip that implements the current detection unit can be set according to actual needs.
- the ADM1276 chip is selected to implement the overcurrent judgment function.
- the data acquisition is performed through the pin SENSE of the ADM1276 chip.
- the signal output is performed through the pin GATE of the ADM1276 chip.
- the ADM1276 chip itself has the advantages of high accuracy and good real-time performance, so using this chip to implement the overcurrent judgment function also has corresponding advantages.
- a RAID card power supply circuit or an arithmetic unit provided in the embodiment of the present application may include a first Schottky diode and a second Schottky diode, and a positive terminal of the first Schottky diode is connected to an output terminal of the power failure detection unit.
- the negative terminal of the first Schottky diode is connected to the G terminal of the NMOS tube, and is connected to the negative terminal of the second Schottky diode in a wire-or manner, and the positive terminal of the second Schottky diode is connected to the second PMOS tube. D end connection.
- f1 is connected to the backup power unit, b1 is connected to b2, c1 is connected to c2, d1 is connected to d2, e1 is connected to e2;
- ADM1276-3ACPZ chip is a current detection chip, Q10 is the first NMOS tube, Q11 is the second NMOS tube , R10 represents the first resistance, R11 represents the second resistance, R2 represents the third resistance, R85 represents the fourth resistance, R92 represents the fifth resistance, D1 represents the first Schottky diode, D2 represents the second Schottky diode, and others
- the position of the device corresponds to the position described in the description of this application, and the model, value, etc. of each device used in this application can also refer to FIG. 3 to FIG. 5.
- the process of selecting each device in this application can be as follows:
- the anti-overcurrent and leakage switching circuit, power failure detection unit, power backup unit, etc. will be set up to build the power failure protection circuit on the RAID card.
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Abstract
本申请公开了一种RAID卡供电电路，该电路包括PMOS管、电流侦测单元及或运算单元；PMOS管的D端与电流侦测单元连接，PMOS管的S端与RAID卡的掉电保护电路中的备电单元连接，PMOS管的G端与或运算单元的输出端连接，或运算单元的输入端分别与电流侦测单元的输出端及掉电保护电路中的掉电检测单元的输出端连接，电流侦测单元设置于备电单元及RAID卡之间，用于在备电单元为RAID卡供电的过程中，如果判断出备电单元及RAID卡之间的线路发生过流，则输出高电平以控制PMOS管断开。能够避免过流对备电单元的损坏，且能够利用PMOS管中包含的体二极管实现防漏电功能。
Description
本申请要求于2018年07月27日提交中国专利局、申请号为201810843268.X、申请名称为“一种RAID卡供电电路”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
本申请涉及RAID(Redundant Arrays of Independent Disks，磁盘阵列)技术领域，更具体地说，涉及一种RAID卡供电电路。
伴随着互联网的快速发展，云计算技术的不断兴起，网上业务量不断增加，对机房服务器的数据处理能力、存储容量都提出了更高的要求。为了服务器系统扩充更大的存储容量，同时提升数据读写的性能，一般会采用RAID卡将服务器系统中的多块硬盘通过做RAID0、RAID5等方式组成磁盘阵列，以扩充对磁盘数据读写的性能及存储容量。
随着云计算、大数据的发展，各行各业的业务都迁移到互联网云端，一旦出现电网大面积断电，服务器系统上磁盘阵列的实时信息就会丢失，造成磁盘阵列中的实时数据无法恢复。为防止系统磁盘阵列上的实时信息丢失，通常采用掉电保护技术，通过在RAID卡上配置一块备用电池或超级电容模组作为备电单元，使得系统停电时，能够由备电单元为RAID卡供电，进而及时的保存磁盘阵列的实时数据，具体为RAID卡实现供电的电路如图1所示。
在图1所示的电路中，其中，PMOS0及PMOS2均为PMOS管(positive channel Metal Oxide Semiconductor，P沟道金属氧化物半导体场效应管)，正常情况为系统P12V_IN能够正常供电，在正常情况下，掉电检测单元会输出H_GATE＝0，输出L_GATE＝1，由此，PMOS0导通，PMOS1断开，RAID卡由系统P12V_IN供电；当系统P12V_IN掉电时，掉电检测单元会输出H_GATE＝1，输出L_GATE＝0，由此，PMOS0断开，PMOS1导通，RAID卡由备电单元供电。但是，备电单元在进行放电的过程时，若备电单元及RAID卡之间出现过流，会导致备电单元损坏。
综上所述，现有技术用于实现RAID卡供电的电路存在若备电单元及 RAID卡之间出现过流会损坏备电单元的问题。
发明内容
本申请的目的是提供一种RAID卡供电电路，以解决现有技术中用于实现RAID卡供电的电路存在的若备电单元及RAID卡之间出现过流会损坏备电单元的问题。
为了实现上述目的，本申请提供如下技术方案：
一种RAID卡供电电路，包括PMOS管、电流侦测单元及或运算单元；所述PMOS管的D端与所述电流侦测单元连接，所述PMOS管的S端与RAID卡的掉电保护电路中的备电单元连接，所述PMOS管的G端与所述或运算单元的输出端连接，所述或运算单元的输入端分别与所述电流侦测单元的输出端及所述掉电保护电路中的掉电检测单元的输出端连接，所述电流侦测单元设置于所述备电单元及所述RAID卡之间，用于在所述备电单元为所述RAID卡供电的过程中，如果判断出所述备电单元及所述RAID卡之间的线路发生过流，则输出高电平以控制所述PMOS管断开。
优选的，所述或运算单元的输入端与所述电流侦测单元之间还设置有具有隔离保护作用的隔离单元。
优选的，所述隔离单元包括第一NMOS管及第二NMOS管，所述第一NMOS管的D端连接电源及所述第二NMOS管的G端，所述第一NMOS管的G端连接所述电流侦测单元的输出端，所述第二NMOS管的D端连接电源及所述或运算单元的输入端，所述第一NMOS管及所述第二NMOS管的S端均接地。
优选的，所述第一NMOS管与对应连接的电源之间还设置有第一电阻，所述第二NMOS管与对应连接的电源之间还设置有第二电阻。
优选的，所述电流侦测单元包括电流侦测芯片及第三电阻，所述第三电阻设置于所述备电单元及所述RAID卡之间，所述电流侦测芯片的采集端正端及采集端负端分别与所述第三电阻的两端连接。
优选的，所述电流侦测芯片的采集端正端与所述第三电阻之间还设置有第四电阻，所述电流侦测芯片的采集端负端与所述第三电阻之间还设置有第五电阻。
优选的，所述电流侦测芯片为ADM1276芯片，所述ADM1276芯片的引脚SENSE+作为所述采集端正端，所述ADM1276芯片的引脚SENSE-作为所述采集端负端，所述ADM1276芯片的引脚GATE作为所述电流侦测单元的输出端。
优选的，所述或运算单元包括第一肖特基二极管及第二肖特基二极管，所述第一肖特基二极管的正端与所述掉电检测单元的输出端连接，所述第一肖特基二极管的负端与所述NMOS管的G端连接的同时与所述第二肖特基二极管的负端以线或的方式连接，所述第二肖特基二极管的正端与所述第二PMOS管的D端连接。
本申请提供的一种RAID卡供电电路，包括PMOS管、电流侦测单元及或运算单元；所述PMOS管的D端与所述电流侦测单元连接，所述PMOS管的S端与RAID卡的掉电保护电路中的备电单元连接，所述PMOS管的G端与所述或运算单元的输出端连接，所述或运算单元的输入端分别与所述电流侦测单元的输出端及所述掉电保护电路中的掉电检测单元的输出端连接，所述电流侦测单元设置于所述备电单元及所述RAID卡之间，用于在所述备电单元为所述RAID卡供电的过程中，如果判断出所述备电单元及所述RAID卡之间的线路发生过流，则输出高电平以控制所述PMOS管断开。本申请公开的技术方案中，在备电单元为RAID卡供电的过程中，如果电流侦测单元侦测到备电单元与RAID卡之间出现过流，则输出高电平，该高电平与掉电检测单元输的低电平经过或运算单元的或运算后得到高电平，控制PMOS管断开；如果电流侦测单元侦测到备电单元与RAID之间未出现过流，则输出低电平，该低电平与掉电检测单元输出的低电平经过或运算单元的或运算后得到低电平，控制PMOS管导通；由此能够在备电单元与RAID卡之间出现过流时控制PMOS管断开以切断过流线路，避免过流对备电单元的损坏，在备电单元与RAID卡之间未出现过流时控制PMOS管导通，以使得备电单元正常为RAID卡供电。另外，本申请能够利用PMOS管中包含的体二极管防止在备电单元及RAID卡均安装好，但是对应系统未启动的情况下，备电单元漏电给RAID卡的情况发生，从而实现防过流和防漏电的双重功能。
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据提供的附图获得其他的附图。
图1为现有技术中用于实现为RAID卡供电的电路图；
图2为本申请实施例提供的一种RAID卡供电电路的电路图；
图3为本申请实施例提供的一种RAID卡供电电路中第一部分电路图；
图4为本申请实施例提供的一种RAID卡供电电路中第二部分电路图；
图5为本申请实施例提供的一种RAID卡供电电路中第三部分电路图。
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
请参阅图2，其示出了本申请实施例提供的一种RAID卡供电电路，包括PMOS管(图中的PMOS2即为本申请中的PMOS管)、电流侦测单元及或运算单元；PMOS管的D端与电流侦测单元连接，PMOS管的S端与RAID卡的掉电保护电路中的备电单元连接，PMOS管的G端与或运算单元的输出端连接，或运算单元的输入端分别与电流侦测单元的输出端及掉电保护电路中的掉电检测单元的输出端连接，电流侦测单元设置于备电单元及RAID卡之间，用于在备电单元为RAID卡供电的过程中，如果判断出备电单元及RAID卡之间的线路发生过流，则输出高电平以控制PMOS管断开。
其中，假设掉电检测单元输出信号为A，电流侦测单元输出信号为B，PMOS2的G端信号为Y，1表示高电平，0表示低电平，则存在以下表示：A为1表示未掉电、即由PCIE接口过来的P12V_IN为RAID卡供电，A为0表示掉电、即由备电单元为RAID卡供电；B为1表示备电单元及RAID卡之间的线路发生过流，B为0表示备电单元及RAID卡之间的线路未发生过流；Y为1表示PMOS2断开，Y为0表示PMOS2导通；由此，本申请中存在如表1所示的逻辑关系：
表1
| A | B | Y |
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 1 |
具体来说，本申请提供的一种RAID卡的供电电路的工作过程包括：系统P12V_IN正常供电时，掉电检测单元会输出H_GATE＝0，输出L_GATE＝1，由此，PMOS0导通，PMOS1断开，RAID卡由系统P12V_IN供电，此时无论电流侦测单元输出的为何种电平，与掉电检测单元输出给PMOS2的高电平经过或运算单元的或运算后均得到高电平，PMOS2接收到高电平并断开；当系统P12V_IN掉电时，掉电检测单元会输出H_GATE＝1，输出L_GATE＝0，由此，PMOS0断开，PMOS1导通，RAID卡由备电单元供电，此时，如果电流侦测单元侦测到备电单元与RAID卡之间出现过流，则输出高电平，电流侦测单元输出的高电平与掉电检测单元输出给PMOS2的低电平经过或运算单元的或运算后得到高电平，PMOS2的G端输入高电平，PMOS2断开，从而切断过流线路，以避免过流损坏备电单元，如果电流侦测单元侦测到备电单元与RAID卡之间未出现过流，则输出低电平，电流侦测单元输出的低电平与掉电检测单元输出给PMOS2的低电平经过或运算单元的或运算后得到低电平，PMOS2的G端输入低电平，PMOS2导通，以由备电单元给RAID卡供电。另外，PMOS2中包含的体二极管的阳极与电流侦测单元连接，阴极与备电单元连接，由此，能够避免在备电单元及RAID卡均安装好，但是对应系统未启动的情况下，备电单元会经过PMOS1的体二极管(bode diode)漏电到RAID卡，造成其误动等情况出现。
本申请公开的技术方案中，在备电单元为RAID卡供电的过程中，如果电流侦测单元侦测到备电单元与RAID卡之间出现过流，则输出高电平，该高电平与掉电检测单元输的低电平经过或运算单元的或运算后得到高电平，控制PMOS管断开；如果电流侦测单元侦测到备电单元与RAID之间未出现过流，则输出低电平，该低电平与掉电检测单元输出的低电平经过或运算单元的或运 算后得到低电平，控制PMOS管导通；由此能够在备电单元与RAID卡之间出现过流时控制PMOS管断开以切断过流线路，避免过流对备电单元的损坏，在备电单元与RAID卡之间未出现过流时控制PMOS管导通，以使得备电单元正常为RAID卡供电。
另外，本申请能够利用PMOS管中包含的体二极管防止在备电单元及RAID卡均安装好，但是对应系统未启动的情况下，备电单元漏电给RAID卡的情况发生，从而实现防过流和防漏电的双重功能。
本申请实施例提供的一种RAID卡供电电路，或运算单元的输入端与电流侦测单元之间还可以设置有具有隔离保护作用的隔离单元。
通过隔离单元的隔离保护作用，能够避免电流侦测单元与或运算单元之间相互影响，保证了对应功能的正常实现。
具体来说，隔离单元可以由两个反相单元组成，即隔离单元可以包括第一NMOS管及第二NMOS管，第一NMOS管的D端连接电源及第二NMOS管的G端，第一NMOS管的G端连接电流侦测单元的输出端，第二NMOS管的D端连接电源及或运算单元的输入端，第一NMOS管及第二NMOS管的S端均接地。
需要说明的是，隔离单元的具体电路设置可以根据实际需要进行设定，均在本申请的保护范围之内，本实施例中利用上述两个反相单元组成的电路实现隔离保护作用，不仅需要器件较少，成本较低，且电路简单，易于实现。
本申请实施例提供的一种RAID卡供电电路，第一NMOS管(Negative channel Metal Oxide Semiconductor，N沟道金属氧化物半导体场效应管)与对应连接的电源之间还可以设置有第一电阻，第二NMOS管与对应连接的电源之间还可以设置有第二电阻。
需要说明的是，本实施例中在第一NMOS管与对应连接的电源之间、第二NMOS管与对应连接的电源之间均设置对应的电阻，能够利用对应电阻起到限流保护的作用，避免连接的电源对对应NMOS管造成损坏。
本申请实施例提供的一种RAID卡供电电路，电流侦测单元可以包括电流侦测芯片及第三电阻，第三电阻设置于备电单元及RAID卡之间，电流侦测芯片的采集端正端及采集端负端分别与第三电阻的两端连接。
本申请中通过这种方式实现数据采集的实质为采集第三电阻两侧的电压，再将采集到的第三电阻两侧的电压的差值与预先设定的电压阈值比对，如果采集到的电压差值大于电压阈值，则说明存在过流，否则则说明不存在过流，从而在电路简单易实现的前提下，还能够实现数据的准确采集及是否存在过流的准确判断。
本申请实施例提供的一种RAID卡供电电路，电流侦测芯片的采集端正端与第三电阻之间还可以设置有第四电阻，电流侦测芯片的采集端负端与第三电阻之间还可以设置有第五电阻。
通过在采集端正端与第三电阻之间、采集端负端与第三电阻之间均设置对应的电阻，能够减少由于对应线路的差异带来的误差，进而提高电流侦测单元侦测到的数据的精度。
本申请实施例提供的一种RAID卡供电电路，电流侦测芯片可以为ADM1276芯片，ADM1276芯片的引脚SENSE+作为采集端正端，ADM1276芯片的引脚SENSE-作为采集端负端，ADM1276芯片的引脚GATE作为电流侦测单元的输出端。
实现电流侦测单元的芯片可以根据实际需要进行设定，本申请中选取ADM1276芯片实现过流判断功能，通过ADM1276芯片的引脚SENSE实现数据采集，通过ADM1276芯片的引脚GATE实现信号输出，由于ADM1276芯片本身就具有精度高、实时性好等优点，因此采用该芯片实现过流判断功能也具有对应的优点。
本申请实施例提供的一种RAID卡供电电路，或运算单元可以包括第一肖特基二极管及第二肖特基二极管，第一肖特基二极管的正端与掉电检测单元的输出端连接，第一肖特基二极管的负端与NMOS管的G端连接的同时与第二肖特基二极管的负端以线或的方式连接，第二肖特基二极管的正端与第二PMOS管的D端连接。
从而通过这种简便的电路实现或运算单元，不仅能够达到所需的效果，且成本较低。另外需要说明的是，本申请实施例提供的一种RAID卡供电电路的部分电路图可以如图3至图5所示，其中，g1与RAID卡连接，a1与掉电检测单元的输出端连接，f1与备电单元连接，b1与b2连接，c1与c2连接，d1与d2连接，e1与e2连接；ADM1276-3ACPZ芯片为电流侦测芯片，Q10表示 第一NMOS管，Q11表示第二NMOS管，R10表示第一电阻，R11表示第二电阻，R2表示第三电阻，R85表示第四电阻，R92表示第五电阻，D1表示第一肖特基二极管，D2表示第二肖特基二极管，其他器件的位置与本申请说明书中对其描述的位置对应，而本申请中使用的各器件的型号、取值等也可以参见图3至图5。对应的，选取本申请中各器件的过程可以如下：
1)根据系统最大负载电流及电路对PMOS管两端电压值Vgs(th)及PMOS管导通时的阻抗值的Rds(on)的要求，选择合适规格的PMOS管：PMOS0、PMOS1和PMOS2；
2)根据P12V_IN的掉电电压判定的下限值，选择芯片LM393，并利用该芯片搭建好掉电检测单元对应线路；
3)根据掉电RAID卡续航时间要求，确定备电单元的容量规格及充电单元；
4)按照图3所示，将确定好的PMOS0、PMOS1和PMOS2，并根据确定的过流保护点(即电压阈值)的大小，确定电流侦测单元中各电阻的阻值及电流侦测单元对应线路的参数设置，以此搭建好防过流及漏电切换线路；
5)按照图3所示，将搭建好防过流及漏电切换线路、掉电检测单元、备电单元等来搭建RAID卡上掉电保护线路
需要说明的是，本申请实施例提供的上述技术方案中与现有技术中对应技术方案实现原理一致的部分并未详细说明，以免过多赘述。
对所公开的实施例的上述说明，使本领域技术人员能够实现或使用本申请。对这些实施例的多种修改对本领域技术人员来说将是显而易见的，本文中所定义的一般原理可以在不脱离本申请的精神或范围的情况下，在其它实施例中实现。因此，本申请将不会被限制于本文所示的这些实施例，而是要符合与本文所公开的原理和新颖特点相一致的最宽的范围。
Claims (8)
- 一种RAID卡供电电路，其特征在于，包括PMOS管、电流侦测单元及或运算单元；所述PMOS管的D端与所述电流侦测单元连接，所述PMOS管的S端与RAID卡的掉电保护电路中的备电单元连接，所述PMOS管的G端与所述或运算单元的输出端连接，所述或运算单元的输入端分别与所述电流侦测单元的输出端及所述掉电保护电路中的掉电检测单元的输出端连接，所述电流侦测单元设置于所述备电单元及所述RAID卡之间，用于在所述备电单元为所述RAID卡供电的过程中，如果判断出所述备电单元及所述RAID卡之间的线路发生过流，则输出高电平以控制所述PMOS管断开。
- 根据权利要求1所述的电路，其特征在于，所述或运算单元的输入端与所述电流侦测单元之间还设置有具有隔离保护作用的隔离单元。
- 根据权利要求2所述的电路，其特征在于，所述隔离单元包括第一NMOS管及第二NMOS管，所述第一NMOS管的D端连接电源及所述第二NMOS管的G端，所述第一NMOS管的G端连接所述电流侦测单元的输出端，所述第二NMOS管的D端连接电源及所述或运算单元的输入端，所述第一NMOS管及所述第二NMOS管的S端均接地。
- 根据权利要求3所述的方法，其特征在于，所述第一NMOS管与对应连接的电源之间还设置有第一电阻，所述第二NMOS管与对应连接的电源之间还设置有第二电阻。
- 根据权利要求1所述的电路，其特征在于，所述电流侦测单元包括电流侦测芯片及第三电阻，所述第三电阻设置于所述备电单元及所述RAID卡之间，所述电流侦测芯片的采集端正端及采集端负端分别与所述第三电阻的两端连接。
- 根据权利要求5所述的电路，其特征在于，所述电流侦测芯片的采集端正端与所述第三电阻之间还设置有第四电阻，所述电流侦测芯片的采集端负端与所述第三电阻之间还设置有第五电阻。
- 根据权利要求6所述的电路，其特征在于，所述电流侦测芯片为ADM1276芯片，所述ADM1276芯片的引脚SENSE+作为所述采集端正端，所述ADM1276芯片的引脚SENSE-作为所述采集端负端，所述ADM1276芯片的引脚GATE作为所述电流侦测单元的输出端。
- 根据权利要求5所述的电路，其特征在于，所述或运算单元包括第一 肖特基二极管及第二肖特基二极管，所述第一肖特基二极管的正端与所述掉电检测单元的输出端连接，所述第一肖特基二极管的负端与所述NMOS管的G端连接的同时与所述第二肖特基二极管的负端以线或的方式连接，所述第二肖特基二极管的正端与所述第二PMOS管的D端连接。
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