WO2017167112A1 - 备电电路及用电设备 - Google Patents

备电电路及用电设备 Download PDF

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Publication number
WO2017167112A1
WO2017167112A1 PCT/CN2017/077865 CN2017077865W WO2017167112A1 WO 2017167112 A1 WO2017167112 A1 WO 2017167112A1 CN 2017077865 W CN2017077865 W CN 2017077865W WO 2017167112 A1 WO2017167112 A1 WO 2017167112A1
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WO
WIPO (PCT)
Prior art keywords
backup
diode
circuit
electrically connected
branch
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Application number
PCT/CN2017/077865
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English (en)
French (fr)
Inventor
陈冠
余霄
汪德波
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP17773142.9A priority Critical patent/EP3428776B1/en
Publication of WO2017167112A1 publication Critical patent/WO2017167112A1/zh
Priority to US16/146,946 priority patent/US10706942B2/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/30—Power supply circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/30—Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/141—Battery and back-up supplies

Definitions

  • the present invention relates to the field of backup power technologies, and in particular, to a backup power circuit and a power consumption device.
  • SSD Solid-state Drive
  • SSD Solid-state Drive
  • semiconductor solid-state memory technology Compared with traditional mechanical hard disks, it has fast read/write speed, strong shock resistance, large temperature range and volume. Small, light weight and other advantages.
  • the write operation performed by the host device to the SSD is divided into two modes: Write-Through and Write-Back.
  • the write-back mode is faster than the write-through mode, but in the write-back mode, the SSD first writes the data in the buffer of the SSD, and then returns the write success to the host device.
  • the host considers that the SSD has completed the storage of the data. . After that, the SSD's main control chip will scan the data to the SSD's back-end flash memory chip (FLASH). If the SSD disk is powered down, the data in the buffer area will be lost. Therefore, in the SSD design, a backup circuit is generally added.
  • the backup circuit includes a plurality of capacitors connected in parallel.
  • One end of the capacitors is connected between the input end and the output end of the backup circuit, and the other end is grounded. It is used to provide the SSD with the power needed to flush the data in the buffer area to the flash memory chip when the accidental power failure occurs, to avoid the problem of data loss.
  • the capacitors in the backup circuit are connected in parallel with each other. If one of the capacitors is short-circuited, the entire backup circuit will be ineffective, thereby affecting the backup effect of the backup circuit.
  • the embodiment of the invention provides a backup circuit and a power device.
  • the technical solution is as follows:
  • a backup circuit comprising an array of backup branches consisting of N sets of parallel backup branches, N being an integer greater than or equal to 2; each set of the backup branch comprises a capacitor component and a unidirectional conductive component ;
  • the unidirectional conductive elements are electrically connected to the input end of the backup branch array, the output end of the backup branch array, and the capacitor assembly;
  • the unidirectional conductive element is configured to intercept a current path between the N sets of parallel alternate backup branches, and the unidirectional conductive element allows current to flow from the input end of the backup branch array, and the backup power is The output of the road array flows out.
  • the current paths between the capacitor components in the different backup branches are cut off by the unidirectional conductive elements in each of the backup power branch arrays.
  • a short circuit occurs in some of the backup branches, it can ensure that the backup power of the other groups of backup branches is not affected. Ringing, thereby improving the backup effect of the backup branch.
  • the unidirectional conductive element comprises a first diode and a second diode; a cathode of the first diode and a positive polarity of the second diode Connected, the anode of the first diode is electrically connected to the input end of the backup branch array, and the cathode of the second diode is electrically connected to the output end of the backup branch array;
  • the capacitor component includes M capacitors connected in parallel with each other, and one end of each of the capacitors is connected between a cathode of the first diode and a cathode of the second diode, and the other end of each capacitor is grounded, and M is greater than or equal to An integer of 1.
  • the current path between the different backup branches is intercepted by the first diode and the second diode, which is a backup effect when some of the backup branches are short-circuited, and does not affect other backup branches.
  • the capacitance value of each of the capacitors is Cmin, and C min satisfies: C min*M*(Nx)*( Vmax-Vmin) ⁇ Q; wherein x is an integer greater than or equal to 1, Vmax is the maximum discharge voltage of the backup branch array, Vmin is the minimum discharge voltage of the backup branch array, and Q is the storage device The amount of charge required to perform an effective power supply for the preset duration.
  • each of the standby power branches further includes: a resistor; and one end of the resistor and the first diode The negative electrode is electrically connected, and the other end of the resistor is electrically connected to the positive electrode of the second diode; one end of each of the capacitor is connected between the resistor and the positive electrode of the second diode.
  • the resistance R of the resistor is:
  • Vcap is the charging voltage of the N sets of parallel backup branches
  • A0 is the maximum charging current of the standby circuit
  • A1 is the preset current value.
  • the backup circuit further includes a third diode
  • the third diode is in parallel relationship with the backup power branch array, and the anode of the third diode is electrically connected to the input end of the backup power branch array, and the cathode of the third diode is connected to the standby The output ends of the electrical branch array are electrically connected.
  • the backup circuit further includes a constant current source
  • the constant current source includes an input end, an output end and a control end;
  • An input end of the constant current source is electrically connected to an output end of the backup power branch array
  • the output of the constant current source is grounded
  • the control end of the constant current source is electrically connected to the control chip.
  • the M mutually parallel capacitors are electrolytic aluminum capacitors, aggregated At least one of a solid tantalum capacitor, a polymer solid aluminum capacitor, or a ceramic capacitor.
  • an electrical device comprising the backup circuit of the first aspect or any of the possible implementations of the first aspect.
  • the powered device is a storage device.
  • FIG. 1 is a circuit diagram of an electrical device according to an exemplary embodiment of the present invention.
  • FIG. 2 is a schematic diagram of current flow when the backup circuit shown in FIG. 1 is charged
  • FIG. 3 is a schematic diagram of current flow when the backup circuit shown in FIG. 1 is discharged according to the embodiment
  • FIG. 4 is a schematic diagram showing current flow when the backup circuit shown in FIG. 1 is self-tested according to the embodiment.
  • FIG. 1 is a circuit diagram of an electrical device according to an exemplary embodiment of the present invention.
  • the power device includes a backup circuit 110, a control chip 120, a power supply circuit 130, and a function chip 140.
  • the output end of the backup circuit 110 is electrically connected to the input end of the power supply circuit 130 of the electrical device.
  • the input end of the backup circuit 110 is connected to the output end of the power supply circuit 130, and the input end of the power supply circuit 130 is also external.
  • the output of the power source 150 is electrically connected.
  • the powered device can be a storage device such as an SSD or the like.
  • the backup circuit 110 includes N sets of backup branch arrays 111, which are connected in parallel with each other, and N is an integer greater than or equal to 2; each set of the backup branches includes a capacitor component 112a and a unidirectional conductive component 112k
  • the unidirectional conductive element 112k is electrically connected to the input end 114 of the backup branch array, the output end 116 of the backup branch array, and the capacitor component 112a, and the unidirectional conductive element 112k is used to cut off the N
  • the flow flows in from the input 114 of the backup branch array and out of the output 116 of the backup branch array.
  • the unidirectional conductive element 112k includes a first diode 112b and a second diode 112c.
  • Each set of backup branches 112 further includes a resistor 112d.
  • Each capacitor assembly 112a includes M capacitors connected in parallel with each other. And one end of each capacitor is connected between the resistor 112d and the anode of the second diode 112c, and the other end of each capacitor is grounded, and M is an integer greater than or equal to 1.
  • the one end of the resistor 112d is electrically connected to the cathode of the first diode 112b, the other end of the resistor 112d is electrically connected to the anode of the second diode 112c, and the anode and the backup of the first diode 112b are electrically connected.
  • the input end 114 of the branch array 111 is electrically connected, and the cathode of the second diode 112b is electrically connected to the output end 116 of the backup branch array 111.
  • the first diode and the second diode are used to intercept the current path between the N sets of parallel alternate backup branches.
  • the unidirectional conductive element 112k includes a first diode 112b and a second diode 112c as an example.
  • the unidirectional conductive element may also be composed of other components or structures.
  • more diodes may be used in the unidirectional conductive element instead of the first diode 112b and the second diode 112c, or the first diode 112b and the second diode in the unidirectional conductive element
  • the tube 112c can be replaced with other elements having the same function as the diode, such as an ion tube having a unidirectional conductivity, a rectifier, a thyristor, a unidirectional conductive paste, etc., and the composition and structure of the unidirectional conductive element 112k are not in the embodiment of the present invention. Make a limit.
  • the M capacitors connected in parallel may be capacitors with a higher rated voltage such as a common electrolytic aluminum capacitor, a polymer solid tantalum capacitor, a polymer solid aluminum capacitor, and a ceramic capacitor.
  • a common electrolytic aluminum capacitor such as a polymer solid tantalum capacitor, a polymer solid aluminum capacitor, and a ceramic capacitor.
  • the M mutually parallel capacitors required in the present invention are required to have a higher rated voltage and are not intended to limit the range of capacitor selection in the present invention.
  • the control chip 120 is configured to measure the capacitance value of the backup power branch array 111 according to a preset period, determine whether the total capacitance value is less than a first preset threshold, and generate a prompt information indication if the total capacitance value is less than the first preset threshold.
  • the duration of the backup circuit 110 capable of effectively supplying power to the powered device is less than a preset duration.
  • the control chip 120 can send the prompt information to a host device connected to the powered device.
  • the backup circuit 110 further includes a third diode 117a, a fourth diode 117b, and a fifth diode 117c, wherein the anode of the fifth diode 117c is connected to the external power source 150, and the fourth diode
  • the negative electrode of the tube 117b and the negative electrode of the fifth diode 117c are electrically connected to form a top structure for preventing the current flowing from the external power source 150 from entering the backup branch array 111 when the external power source 150 is operating normally, and externally. When the power source 150 is powered down, the current flowing from the backup branch array 111 is prevented from entering the external power source 150.
  • the third diode 117a, the fourth diode 117b, and the fifth diode 117c may have other components or structures, such as the third diode 117a, the fourth diode 117b, and the third
  • the five diodes 117c may each be composed of a plurality of diodes, or the third diode 117a, the fourth diode 117b, and the fifth diode 117c may be replaced by other components having the same function as the diode, for example, having a single Conductive ion tubes, rectifiers, thyristors, and unidirectional conductive pastes.
  • the input terminal 134 of the power supply module 130 is electrically connected to the negative electrode of the fourth diode 117b and the negative electrode of the fifth diode 117c.
  • the power supply module 130 includes a plurality of buck modules 132, each of which corresponds to one or more functional chips 140.
  • the buck module 132 of the power supply module 130 is configured to output different voltage values according to the electrical requirements of its corresponding function chip 140.
  • the voltage values of these outputs may be 1.0V, 1.8V, 3.3V, 5.6V or 6.8V, etc., the above values are only illustrative of the value of the voltage value that the buck module 132 of the power supply module 130 can output, and do not limit the value of the voltage value output by the buck module 132 of the power supply module 130.
  • the backup circuit 110 further includes a boosting module 113 , a buck module 115 , a constant current source 118 , and a current limiting module 119 .
  • the current limiting module 119 includes an input end 119a and an output end 119b.
  • the boosting module 113 includes an input end 113a, an output end 113b and a control end 113c.
  • the buck module 115 includes an input end 115a and an output end 115b.
  • the constant current source 118 includes a current input. Terminal 118a, current output terminal 118b and control terminal 118c.
  • the control chip 120 includes at least a first interface 120a, a second interface 120b, a third interface 120c, a fourth interface 120d, a fifth interface 120e, and a sixth interface 120f.
  • the output end 132a of the buck module 132 of the power supply circuit 130 is electrically connected to the input end 119a of the current limiting module 119.
  • the output end 119b of the current limiting module 119 is electrically connected to the input end 113a of the boosting module 113.
  • the output end 113b of the module 113 is electrically connected to the input end 114 of the backup electric branch array 111 and the positive electrode of the third diode 117a, respectively.
  • the control end 113c of the boosting module 113 and the third interface 120c of the control chip 120 are electrically connected.
  • the input terminals 115a of the buck module 115 are electrically connected to the negative terminal of the third diode 117a and the output end 116 of the backup branch array 111, respectively.
  • the output terminal 115b of the buck module 115 and the fourth diode are respectively connected.
  • the anode of the 117b and the first interface 120a of the control chip 120 are electrically connected, and the current input terminal 118a of the constant current source 118 is electrically connected to the second interface 120b of the control chip 120 and the output 116 of the backup branch array 111, respectively.
  • the current output terminal 118b of the constant current source 118 is grounded, and the control terminal 118c of the constant current source 118 is electrically connected to the fourth interface 120d of the control chip 120.
  • the fifth interface 120e of the control chip 120 and the control terminal 150a of the external power supply are connected. Electrically connected, controlled Sixth interface 120f sheet 120 of the control chip interface 120 of the power supply.
  • the current limiting module 119 is configured to limit the current entering the boosting module 113 to a preset maximum current, that is, limit the current entering the standby circuit 110, and prevent the components from being burnt due to excessive current, thereby being a backup circuit. 110.
  • the boosting module 113, the buck module 115, and the third diode 117a, that is, the fourth diode 117b, provide current limiting protection.
  • the current limiting module 119 can be a current limit module.
  • the boosting module 113 is configured to boost the current entering the boosting module 113, thereby increasing the electrical energy that can be charged by the capacitors in the N sets of parallel-connected backup branches 112. The higher the voltage across the capacitor, the higher the capacitor. The amount of charge is also more).
  • the boost module 113 can be a switching DC boost circuit (Boost) module.
  • Boost switching DC boost circuit
  • the buck module 115 is configured to step down the power stored in the backup branch array 111 and output it to each of the buck modules 132 in the power supply module 130 when the backup circuit 110 supplies power to the electrical device, and then step down each of the buck modules 132.
  • the module 132 is delivered to each of the functional chips 140 after being secondarily stepped down.
  • the buck module 115 can be a buck converter module.
  • the constant current source 118 is used to provide a constant current output path for the output 116 of the backup branch array 111 for the control chip 120 to measure the capacitance value of the backup branch array 111.
  • the control device 120 collects the voltage that is stepped down by the buck module 115 on the output 116 of the backup branch array 111 through the first interface 120a.
  • the first interface 120a may be an analog-to-digital converter in the control chip 120 (Analog) -to-Digital Converter, ADC) interface.
  • the control device 120 detects the voltage on the input of the constant current source 118 through the second interface 120b, which may be another ADC interface in the control chip 120.
  • the control device 120 controls the operation of the boosting module 113 through the third interface 120c, including controlling the opening and closing of the boosting module 113.
  • the third interface may be a general purpose input output (GPIO) in the control chip. .
  • the control device 120 controls the operation of the constant current source 118 through the fourth interface 120d, including controlling the on and off of the constant current source 118, and the fourth interface may be another general purpose input and output interface in the control chip.
  • the control device 120 detects the voltage value provided by the external power source 150 to the powered device through the fifth interface 120e. When the voltage value is less than the preset power supply voltage, the control chip considers that the external power source 150 is in the power-down state, and the fifth interface 120e may be the control.
  • the function chip 140 includes at least a clock, a flash EEPROM (Flash EEPROM or Flash), a double data rate (DDR), and the like.
  • the above functional chip is only a part of a chip that needs to obtain electric energy to work, and other electric energy needs to work in the electric device.
  • the functional chip is also within the protection range of the above functional chip 140.
  • Each functional chip 140 is provided with an output connected to the corresponding buck module 132 according to the difference in its own rated voltage.
  • FIG. 1 is a schematic diagram of current flow when charging a backup circuit according to an embodiment of the invention.
  • the power device is used as a storage device.
  • the storage device When the storage device is working normally, the storage device is first connected to the host device.
  • the host device may be a personal computer, a workstation, a server, or a server cluster.
  • the electronic device that reads and writes the storage device, after the storage device accesses the host device, the storage device obtains the electrical energy through the external power source 150 provided by the host device.
  • the current supplied from the external power source 150 flows into the fifth diode 117c, and flows out in two branches: one falls into the negative pole of the fourth diode 117b and is cut off, no longer flows; the other branch
  • the number of branches corresponding to the number of the respective buck modules 132 in the power supply module 130 respectively flows into the corresponding buck module 132, and the currents flowing into the corresponding buck module 132 are respectively stepped down and converted into output currents of different voltages.
  • each functional chip 140 including the control chip 120 electrically connected thereto. After the control chip 120 obtains the power, it resets and loads the firmware (Firmware, FW). At the same time, each function chip 140 obtains the power to complete the reset operation, and the entire storage device starts normal data reading and writing, and performs data exchange with the host device.
  • the power supply module 130 is electrically connected to the input terminal 119a of the current limiting module 119.
  • the current output from the output terminal 132a of the buck module 132 enters the current limiting module 119, and then flows through the input terminal 113a of the boosting module 113.
  • the module 113, the boosting module 113 is in the on state by default, or the boosting module 130 can also be controlled to be turned on by the control chip 120 through the control terminal 113c. When the boosting module 113 is in the on state, the boosting module 113 flows into the input terminal thereof.
  • the current of 113a is pressurized to raise its voltage to a predetermined value required by the design, which is related to the rated voltage of the capacitor in each set of backup branches 112, optionally taking 70%-80 of the rated voltage.
  • % is a predetermined value Vcap of the design, which may be 17.8V. In the embodiment of the present invention, the value of the 17.8V voltage is only exemplified, and the Vcap is not limited.
  • the Vcap is for each backup battery.
  • the path 112 charges the charging voltage.
  • the current flowing into the boosting module 113 is discharged from the output terminal 113b of the boosting module 113, and is divided into two paths.
  • One input is electrically connected to the input terminal 114 of the backup power branch array 111, and the other is inflow.
  • the positive electrode of the third diode 117a, the current flowing into the input terminal 114 of the backup branch array 111, charges the capacitors in the N sets of backup branches 112.
  • the constant current source 118 is in an inactive state when the open command issued by the control chip 120 via the fourth interface 120d is not obtained, that is, the constant current source 118 is in an open state.
  • the buck module 115 automatically turns on when it enters the normal operating state.
  • the voltage output by the buck module 115 is smaller than the power supply voltage provided by the external power source 150, and is greater than the minimum operating voltage of each of the buck modules 132 in the power supply module 130.
  • the minimum operating voltage may be It is 1V.
  • the value of the voltage Vstangby that the buck module 115 needs to output may be 6.8V, which does not limit the voltage that the buck module 115 needs to output.
  • the voltage output by the buck module 115 is smaller than the power supply voltage provided by the external power source 150. Therefore, the buck module 115 does not pass through the fourth diode 117b to each buck module in the power supply module 130. 132 output current.
  • FIG. 1 is a schematic diagram of current flow when a backup circuit is discharged according to an embodiment of the invention.
  • the buck module 115 electrically connected to the positive electrode of the fourth diode 117b is always in operation, when the voltage at the positive electrode of the fifth diode 117c is lower than the voltage at the positive terminal of the fourth diode 117b. (ie, when the external power source 150 is powered off), the electric energy stored in the backup circuit 110 flows into the respective step-down modules 132 of the power supply module 130 in the form of current through the negative pole of the fourth diode 117b until the backup branch is completed.
  • the voltage across the capacitor in array 111 is lower than the minimum operating voltage of buck module 115 to ensure that the powered device (such as a storage device) can rely on the electrical energy stored in the backup circuit for a period of time.
  • the backup circuit 110 is divided into N sets of backup branches 112 (labeled as "Group 1", “Group 2", ..., “Group N” in FIG. 1), each set
  • the electrical branches 112 each include M capacitors. Assume that one of the capacitors in one of the backup power branches 112 is short-circuited. For example, in FIG.
  • the backup branch where the short-circuited capacitor is located is the Nth group, since the group of M capacitors are connected in parallel, thereby causing the The capacitors on the backup branch are short-circuited, and the backup branch 112 of the Nth group loses stored electrical energy, and due to the presence of the first diode 112b and the second diode 112c, the other backup branches 112 The electric energy cannot enter the backup branch 112 of the Nth group, and therefore, the other groups of the backup branches 112 can provide a backup effect.
  • the first diode 112b can also prevent current from flowing back from the backup branch 112 to the boost module 113 when the external power source 150 is powered down.
  • the resistance value of the resistor 112d is set to be large enough to short a capacitor in the backup group 112 of the Nth group. At this time, the current through the resistor 112d in the backup branch 112 of the Nth group is sufficiently small to minimize the leakage effect of the capacitor short circuit.
  • the resistance of the resistor 112d needs to satisfy: (Vcap/R)*N ⁇ A0-A1, where A0 is the maximum charging current of the standby circuit, and the maximum charging current may be the preset maximum current determined by the current limiting module 119.
  • A1 is a preset current value. Alternatively, A1 may take a value of 10 mA or more.
  • the number of sets of the backup branch is N group
  • the N group backup branch includes a part of redundancy, that is, when the external power source 150 is powered off, only less than N groups are needed.
  • a group of backup power branches works normally, that is, it can support the maximum backup power requirement of the power equipment. That is, the (Nx) group backup branch can be set to support the maximum backup power requirement of the powered device, x is an integer greater than or equal to 1, and x is the number of redundant backup branches, and N is taken.
  • the value should not be too large, generally up to 10.
  • the preferred value scheme does not limit the value of N of the present invention.
  • the maximum backup power requirement of the power device can be supported.
  • the capacitance of each capacitor in the backup circuit is equal, the capacitance value of each capacitor is Cmin.
  • C min satisfies: C min * M * (Nx) * (Vmax - Vmin) ⁇ Q; x is an integer greater than or equal to 1, Vmax is the maximum discharge voltage of the backup branch array, Vmin The minimum discharge voltage of the array of electrical branches, Q is the amount of charge required to perform an effective power supply to the powered device for the predetermined length of time.
  • Vmax may be the above Vcap
  • Vmin may be the above Vstangby.
  • the control device can also detect the magnitude of the capacitance value of the backup branch array 111 by controlling the discharge of the constant current source 118 to implement self-test of the backup circuit.
  • FIG. 1 is a schematic diagram of current flow during self-test of a backup circuit according to an embodiment of the invention.
  • the control chip 120 controls the backup circuit 110 to stop charging when the capacitance value of the backup branch array 111 is charged, and controls the constant current source 118 to discharge with the constant current I0.
  • the control chip 120 can pass through the third interface.
  • the 120c control boost module 113 stops the external output current to stop charging the backup circuit 110.
  • the control chip 120 controls the constant current source 118 to be turned on through the fourth interface 120d, so that the backup circuit 110 passes through the constant current source 118.
  • the branch discharges with a constant current I0.
  • the control chip 120 detects the voltage at the current input terminal 118a of the constant current source 118 through the second interface 120b, due to the constant current source.
  • the current input terminal 118a of the 118 is electrically connected to the output terminal 116 of the backup power branch array 111. That is, the control chip 120 is equivalent to detecting the voltage of the output terminal 116 of the backup power branch array 111 through the second interface 120b.
  • two voltage values that is, a first preset voltage value V1 and a second preset voltage value V2 may be preset, and the control chip 120 measures the voltage of the current input terminal 118a of the constant current source 118 from the first preset voltage.
  • the value V1 falls to the second preset voltage value V2, the time T0, V1 is greater than V2.
  • the values of V1 and V2 can be selected according to the principle of convenient acquisition and reduction of error.
  • the value of V1 may be (Vcap-500mV), and the value of V2 may be (Vcap-1000mV).
  • the value of Vcap is the voltage at the output 116 of the standby power branch array 111 after the charging circuit 110 is completed, that is, the voltage value at the output terminal 113b of the boosting module 113 when the boosting module 113 is turned on.
  • the control chip 120 turns off the constant current source 118 through the fourth interface 120d, so that the constant current source 118 is open, and the control chip 120 turns on the boosting module 113 through the third interface 120c, and controls the boosting module 113 to continue to the standby power supply branch.
  • the road array 111 is charged.
  • the power device completes the measurement of the capacitance value of the backup branch array 111, and the backup circuit 110 returns to the normal standby state.
  • the standby branch 112 is in an effective working state, that is, no short circuit occurs in the M capacitors in the backup branch 112.
  • an auxiliary power branch array consisting of N sets of parallel backup branches is provided in the backup circuit, and the backup branch is measured by the control chip of the electrical equipment.
  • the capacitance value of the array is determined.
  • the capacitance value is less than the first preset threshold. If the capacitance value is less than the first preset threshold, the backup circuit is configured to enable the power supply to be powered for less than the preset duration.
  • a plurality of sets of backup branches are set in the backup circuit, and the capacitance values of the backup branch arrays in the backup circuit are periodically detected. When some of the backup branches are short-circuited, the user can be reminded in time so that The user takes the necessary subsidy measures before the backup circuit is completely disabled, thereby achieving the purpose of improving the power preparation effect of the backup circuit.
  • a person skilled in the art may understand that all or part of the steps of implementing the above embodiments may be completed by hardware, or may be instructed by a program to execute related hardware, and the program may be stored in a computer readable storage medium.
  • the storage medium mentioned may be a read only memory, a magnetic disk or an optical disk or the like.

Abstract

本发明公开了一种备电电路和用电设备，属于备电技术领域。备电电路的输出端和用电设备的供电电路的输入端电性相连，该供电电路的输出端与该用电设备的输入端电性相连，该备电电路的输入端连接于该供电电路的输出端和该用电设备的输入端之间，该备电电路包括由N组相互并联的备电支路组成的备电支路阵列；每组该备电支路包括电容组件和单向导电元件，该单向导电元件用于截断该N组相互并联的备电支路中的电容组件之间的电流通路。通过设置由N组相互并联的备电支路组成的备电支路阵列，当其中部分备电支路中发生短路时，能够保证其它各组备电支路的备电作用不受影响，从而提高备电支路的备电效果。

Description

备电电路及用电设备 技术领域
本发明涉及备电技术领域，特别涉及一种备电电路及用电设备。
背景技术
在存储设备中，SSD(Solid-state Drive，固态硬盘)是一种基于半导体固态存储器技术的新型存储设备，与传统机械硬盘相比，具有读写速度快、抗震能力强、温度范围大、体积小、重量轻等优点。
现有技术中，主机设备向SSD进行的写入操作分为透写(Write-Through)和回写(Write-Back)两种模式。回写模式的速度要快于透写模式，但是在回写模式下SSD先将数据写在SSD的缓存区(buffer)里，随即向主机设备返回写入成功，主机认为SSD已完成数据的存储。之后，SSD的主控芯片将数据下刷到SSD的后端闪存芯片(FLASH)，若此时SSD盘片掉电，则缓存区中的数据就会丢失。因此，在SSD设计中，一般会增加一个备电电路，该备电电路中包含若干个并联的电容器，这若干个电容器的一端连接在备电电路的输入端和输出端之间，另一端接地，用于在意外掉电发生时，为SSD提供将缓存区中的数据下刷到闪存芯片所需的电能，避免发生数据丢失的问题。
但是现有技术存在以下问题：
备电电路中的各个电容器之间互相并联，若其中一个电容发生短路，则整个备电电路就会失效，从而影响备电电路的备电效果。
发明内容
为了提高备电电路的备电效果，本发明实施例提供了一种备电电路及用电设备。所述技术方案如下：
第一方面，提供了一种备电电路，其特征在于，该备电电路的输出端和用电设备的供电电路的输入端电性相连，该备电电路的输入端连接于该供电电路的输出端，该备电电路包括由N组相互并联的备电支路组成的备电支路阵列，N是大于或等于2的整数；每组该备电支路包括电容组件和单向导电元件；
该单向导电元件分别与该备电支路阵列的输入端、该备电支路阵列的输出端以及该电容组件电性相连；
该单向导电元件用于截断该N组相互并联的备电支路之间的电流通路，且该单向导电元件允许电流由该备电支路阵列的输入端流入，并由该备电支路阵列的输出端流出。
通过设置由N组相互并联的备电支路组成的备电支路阵列，各个备电支路阵列中通过单向导电元件截断不同备电支路中的电容组件之间的电流通路，当其中部分备电支路中发生短路时，能够保证其它各组备电支路的备电作用不受影 响，从而提高备电支路的备电效果。
在第一方面的第一种可能实现方式中，该单向导电元件包括第一二极管和第二二极管；该第一二极管的负极与该第二二极管的正极电性相连，该第一二极管的正极与该备电支路阵列的输入端电性相连，该第二二极管的负极与该备电支路阵列的输出端电性相连；该电容组件包括M个相互并联的电容器，且每个该电容器的一端连接于该第一二极管的负极与该第二二极管的正极之间，每个该电容器的另一端接地，M是大于或等于1的整数。
通过第一二极管和第二二极管截断不同备电支路之间的电流通路，是其中部分备电支路发生短路时，不影响其它备电支路的备电效果。
结合第一方面的第一种可能实现方式，在第一方面的第二种可能实现方式中，每个该电容器的电容值为Cmin，且C min满足：C min*M*(N-x)*(Vmax-Vmin)≥Q；其中，x是大于或等于1的整数，Vmax为该备电支路阵列的最大放电电压，Vmin为该备电支路阵列的最小放电电压，Q为对该存储设备进行该预设时长的有效供电所需的电荷量。
结合第一方面的第一种可能实现方式，在第一方面的第三种可能实现方式中，每组该备电支路还包括：电阻器；该电阻器一端与该第一二极管的负极电性相连，该电阻器的另一端与该第二二极管的正极电性相连；每个该电容器的一端连接于该电阻器与该第二二极管的正极之间。
通过在备电支路中设置电阻器，当该备电支路中的电容器发生短路时限制该备电支路中的电流大小，使得其它备电支路能够获得足够的电流进行充电，降低部分备电支路短路对其它备电支路的影响。
结合第一方面的第三种可能实现方式，在第一方面的第四种可能实现方式中，该电阻器的阻值R满足：
(Vcap/R)*N<A0-A1；
其中，Vcap为该N组相互并联的备电支路的充电电压，A0为该备电电路的最大充电电流，A1为预设电流值。
在第一方面的第五种可能实现方式中，该备电电路还包括第三二极管；
该第三二极管与该备电支路阵列为并联关系，该第三二极管的正极与该备电支路阵列的输入端电性相连，该第三二极管的负极与该备电支路阵列的输出端电性相连。
在第一方面的第六种可能实现方式中，该备电电路还包括恒流源；
该恒流源，包括输入端、输出端和一个控制端；
该恒流源的输入端与该备电支路阵列的输出端电性相连；
该恒流源的输出端接地；
该恒流源的控制端与该控制芯片电性相连。
结合第一方面或者第一方面的第一至第六种可能实现方式中的任意一种，在第一方面的第七种可能实现方式中，该M个相互并联的电容器是电解铝电容、聚合物固体钽电容、聚合物固体铝电容或陶瓷电容中的至少一种。
第二方面，提供了一种用电设备，该用电设备包括上述第一方面或者第一方面的任意一种可能实现方式所示的备电电路。
在第二方面的第一种可能实现方式中，该用电设备为存储设备。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图。
图1是本发明一示例性实施例示出的一种用电设备的电路图；
图2是图1对应实施例所示的备电电路充电时的电流流向示意图；
图3是图1对应实施例所示的备电电路放电时的电流流向示意图；
图4是图1对应实施例所示的备电电路自检时的电流流向示意图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚，下面将结合附图对本发明实施方式作进一步地详细描述。
请参考图1，其是本发明一示例性实施例示出的一种用电设备的电路图。该用电设备包括:备电电路110、控制芯片120、供电电路130和功能芯片140。
其中备电电路110的输出端和用电设备的供电电路130的输入端电性相连，该备电电路110的输入端连接于该供电电路130的输出端，供电电路130的输入端还与外部电源150的输出端电性相连。典型的，该用电设备可以是存储设备，比如SSD等。
备电电路110包括N组相互并联的备电支路112组成的备电支路阵列111，N是大于或等于2的整数；每组该备电支路包括电容组件112a和单向导电元件112k，该单向导电元件112k分别与该备电支路阵列的输入端114、该备电支路阵列的输出端116以及该电容组件112a电性相连，该单向导电元件112k用于截断该N组相互并联的备电支路112之间的电流通路，即当某一个备电支路112中的电容组件112a发生短路时，其它备电支路112中的电容组件112a存储的电能无法流通到发生短路的备电支路112中，并且，该单向导电元件112k允许电 流由该备电支路阵列的输入端114流入，并由该备电支路阵列的输出端116流出。
可选的，该单向导电元件112k包括第一二极管112b和第二二极管112c，每组备电支路112还包括电阻器112d，每个电容组件112a包括M个相互并联的电容器，且每个电容器的一端连接于电阻器112d与第二二极管112c的正极之间，每个电容器的另一端接地，M是大于或等于1的整数。
其中，电阻器112d的一端与第一二极管112b的负极电性相连，电阻器112d的另一端与第二二极管112c的正极电性相连，第一二极管112b的正极与备电支路阵列111的输入端114电性相连，第二二极管112b的负极与备电支路阵列111的输出端116电性相连。第一二极管和第二二极管用于截断N组相互并联的备电支路之间的电流通路。
在本发明实施例中，以单向导电元件112k包括第一二极管112b和第二二极管112c为例进行说明，在实际应用中，该单向导电元件还可以由其它元件或者结构，比如，该单向导电元件中可以使用更多的二极管来取代第一二极管112b和第二二极管112c，或者，该单向导电元件中的第一二极管112b和第二二极管112c可以使用其它与二极管功能相同的元件代替，比如具有单向导电性的离子管、整流器、可控硅以及单向导电胶等，本发明实施例对于单向导电元件112k的组成和结构不做限定。
在实际应用中，M个互相并联的电容器可以是普通电解铝电容、聚合物(polymer)固体钽电容、聚合物固体铝电容和陶瓷电容等具有较高额定电压的电容，上述四种电容仅为示例性说明、本发明中所需的M个互相并联的电容器需要具备较高额定电压，并不对本发明中的电容器选择范围构成限定。
控制芯片120，用于按照一预设周期测量备电支路阵列111的电容值，判断总电容值是否小于第一预设阈值，若总电容值小于第一预设阈值，则产生提示信息指示备电电路110能够对用电设备进行有效供电的时长小于预设时长。比如，控制芯片120可以向与用电设备连接的主机设备发送该提示信息。
另外，该备电电路110中还包括第三二极管117a、第四二极管117b和第五二极管117c，其中，第五二极管117c的正极连接外部电源150，第四二极管117b的负极和第五二极管117c的负极电性相连，构成对顶结构，用于在外部电源150正常工作时防止从外部电源150流出的电流进入备电支路阵列111，并在外部电源150掉电时防止从备电支路阵列111流出的电流进入外部电源150。
类似的，上述第三二极管117a、第四二极管117b和第五二极管117c也可以有其它元件或者结构，比如，上述第三二极管117a、第四二极管117b和第五二极管117c分别可以由多个二极管组成，或者，上述第三二极管117a、第四二极管117b和第五二极管117c可以使用其它与二极管功能相同的元件代替，比如具有单向导电性的离子管、整流器、可控硅以及单向导电胶等。
供电模块130的输入端134与第四二极管117b的负极和第五二极管117c的负极电性相连。供电模块130中包含多个降压模块132，每个降压模块132对应为一个或多个功能芯片140供电。供电模块130的降压模块132根据其对应的功能芯片140的电性要求，被设置为输出不同的电压值，比如，这些输出的电压值可以是1.0V、1.8V、3.3V、5.6V或6.8V等等，上述数值仅为示例性说明供电模块130的降压模块132可以输出的电压值的取值，并不对供电模块130的降压模块132输出的电压值数值构成限定。
如图1所示，该备电电路110还包括升压模块113、降压模块115、恒流源118以及限流模块119。限流模块119包括输入端119a和输出端119b，升压模块113包括输入端113a、输出端113b和控制端113c，降压模块115包括输入端115a和输出端115b，恒流源118包括电流输入端118a、电流输出端118b和控制端118c。控制芯片120至少包括:第一接口120a、第二接口120b、第三接口120c、第四接口120d、第五接口120e和第六接口120f。
供电电路130中的一个降压模块132的输出端132a与限流模块119的输入端119a电性相连，限流模块119的输出端119b与升压模块113的输入端113a电性相连，升压模块113的输出端113b分别与备电支路阵列111的输入端114以及第三二极管117a的正极电性相连，升压模块113的控制端113c与控制芯片120的第三接口120c电性相连，降压模块115的输入端115a分别与第三二极管117a的负极以及备电支路阵列111的输出端116电性相连，降压模块115的输出端115b分别与第四二极管117b的正极以及控制芯片120的第一接口120a电性相连电性相连，恒流源118的电流输入端118a分别与控制芯片120的第二接口120b以及备电支路阵列111的输出端116电性相连，恒流源118的电流输出端118b接地，恒流源118的控制端118c与控制芯片120的第四接口120d电性相连，控制芯片120的第五接口120e与外部电源的控制端150a电性相连，控制芯片120的第六接口120f为控制芯片120的供电接口。
限流模块119用于将进入升压模块113的电流限制在预设最大电流以下，即限制了进入备电电路110电流的大小，避免上述元器件由于电流过大而烧毁，从而为备电电路110、升压模块113、降压模块115、第三二极管117a即第四二极管117b提供限流保护。限流模块119可以是一个电流限制电路(Current limit)模块。
升压模块113用于将进入升压模块113中的电流进行升压，从而提高N组互相并联的备电支路112中的电容器可充入的电能(电容器两端电压越高，该电容器中的电荷量也越多)。升压模块113可以是开关直流升压电路(Boost)模块。
降压模块115用于在备电电路110为用电设备供电时，将备电支路阵列111中存储的电能降压后输出给供电模块130中的各个降压模块132，再由各个降压模块132经过二次降压后输送给各个功能芯片140。降压模块115可以是降压式变换电路(Buck)模块。
恒流源118用于为备电支路阵列111的输出端116提供恒定的电流输出通路，以便控制芯片120测量备电支路阵列111的电容值。
控制设备120通过第一接口120a采集备电支路阵列111的输出端116上经过降压模块115降压后的电压，该第一接口120a可以是控制芯片120中的一个模数转换器(Analog-to-Digital Converter，ADC)接口。
控制设备120通过第二接口120b检测恒流源118的输入端上的电压，第二接口120b可以是控制芯片120中的另一个ADC接口。
控制设备120通过第三接口120c来控制升压模块113的运行，包括控制升压模块113的开启和关闭，第三接口可以是控制芯片中的一个通用输入输出接口(General Purpose Input Output，GPIO)。
控制设备120通过第四接口120d来控制恒流源118的运行，包括控制恒流源118的开启和关闭，第四接口可以是控制芯片中的另一个通用输入输出接口。
控制设备120通过第五接口120e来检测外部电源150向用电设备提供的电压值，在电压值小于预设供电电压时，控制芯片认为外部电源150处于掉电状态，第五接口120e可以是控制芯片中的INT接口。
功能芯片140至少包括：时钟芯片(clock)、闪存芯片(Flash EEPROM Memory或Flash)、主存芯片(Double Data Rate，DDR)等等。上述功能芯片仅为举例说明需要获取电能来进行工作的芯片中的一部分，用电设备中其它需要电能工作 的功能芯片也在上述功能芯片140的保护范围之内。每个功能芯片140根据自身工作额定电压的不同，设置连接于相应的降压模块132的输出端。
请参考图1，其示了本发明实施例涉及的一种备电电路充电时的电流流向示意图。如图1所示，以该用电设备为存储设备为例，在存储设备正常工作时，首先，该存储设备接入主机设备中，主机设备可以是个人计算机、工作站、服务器或服务器集群等可对存储设备进行读写操作的电子设备，在该存储设备接入主机设备后，存储设备通过与主机设备提供的外部电源150获得电能。存储设备获得电能之后，外部电源150提供的电流流入第五二极管117c后，分两支流出：一支流入到第四二极管117b的负极而截止，不再流通；另一支分为与供电模块130中的各个降压模块132的数量对应的支路数，分别流入对应的降压模块132，各支流入对应降压模块132的电流经过降压后分别转换成不同电压的输出电流，流向分别与之电性相连的各个功能芯片140(包括控制芯片120)。控制芯片120获得电能后复位，并加载固件(Firmware，FW)，同时各个功能芯片140获得电能完成复位后也开始正常工作，整个存储设备开始正常的数据读写，与主机设备进行数据交换。
与此同时，供电模块130中与限流模块119的输入端119a电性相连降压模块132的输出端132a输出的电流进入限流模块119后，通过升压模块113的输入端113a流入升压模块113，升压模块113默认处于开启状态，或者，升压模块130也可以由控制芯片120通过控制端113c控制开启，当升压模块113处于开启状态时，升压模块113对流入其输入端113a的电流进行加压，使其电压上升到设计要求的预定值，该预定值与每组备电支路112中的电容器的额定电压有关，可选地，取该额定电压的70％-80％为设计要求的预定值Vcap，其取值可以是17.8V，在本发明实施例中，该17.8V电压取值仅作举例说明，不对Vcap形成限定，其中，该Vcap就是对各个备电支路112进行充电时的充电电压。
升压模块113开启之后，流入升压模块113的电流由升压模块113的输出端113b流出后分为两路，一路流入备电支路阵列111的输入端114电性相连，另一支流入第三二极管117a的正极，流入备电支路阵列111的输入端114的电流对N组备电支路112中的电容器进行充电。
需要特别说明的是，恒流源118在没有获得控制芯片120经第四接口120d发出的开启指令时，处于非工作状态，即恒流源118处于开路状态。
随着降压模块115的输入端115a处的电压逐渐升高到降压模块115的最小工作电压，降压模块115进入正常工作状态自动开启。需要特别说明的是，降压模块115输出的电压要小于外部电源150提供的供电电压，并且要大于供电模块130中的各个降压模块132的最小工作电压，可选地，该最小工作电压可以为1V。该降压模块115需要输出的电压Vstangby取值可以是6.8V，该取值并不对该降压模块115需要输出的电压构成限定。由于此时外部电源150正常供电，降压模块115输出的电压小于外部电源150提供的供电电压，因此，降压模块115不会通过第四二极管117b向供电模块130中的各个降压模块132输出电流。
请参考图1，其示了本发明实施例涉及的一种备电电路放电时的电流流向示意图。如图1所示，与第四二极管117b正极电性相连的降压模块115始终处于工作状态，当第五二极管117c正极处的电压低于第四二极管117b正极处的电压(即外部电源150掉电)时，备电电路110中存储的电能即刻通过第四二极管117b的负极以电流的形式流入供电模块130中的各个降压模块132中，直至备电支路阵列111中电容器两端的电压低于降压模块115的最小工作电压，以保证用电设备(比如存储设备)能够依靠备电电路中存储的电能再正常工作一段时间。
在图1中，由于备电电路110分为N组备电支路112(在图1中标注为“第1组”、“第2组”、…、“第N组”)，每组备电支路112均包括M个电容器。假设其中一组备电支路112中某个电容器发生短路，比如，在图1中，短路的电容器所在的备电支路是第N组，由于该组M个电容器是并联连接，因此造成该备电支路上电容器均被短路，第N组的备电支路112丧失了存储的电能，而由于第一二极管112b和第二二极管112c的存在，其它备电支路112中的电能无法进入该第N组的备电支路112，因此，其它各组备电支路112能够起到备电效果。另外，第一二极管112b还可以在外部电源150掉电时，防止电流从备电支路112中倒灌回升压模块113。此外，为了避免某一电容器短路时，大量的电流从短路的电容器中漏掉，电阻器112d的电阻值要设置的足够大，使得在第N组的备电支路112中的某一电容器短路时，通过第N组的备电支路112中的电阻器112d的电流足够小，以尽量减小电容短路的漏电影响。其中，电阻器112d的阻值需满足：(Vcap/R)*N<A0-A1，A0为该备电电路的最大充电电流，该最大充电电流可以是限流模块119决定的预设最大电流，A1为预设电流值，可选地，A1可取10mA以上的值。
需要特别说明的是，本发明中备电支路设计的组数为N组，该N组备电支路中包含一部分的冗余，即在外部电源150掉电时，只需要小于N组的一个组数的备电支路正常工作，即可以支持该用电设备的最大备电需求。即可以设置(N-x)组备电支路正常工作即可支持该用电设备的最大备电需求，x为大于或者等于1的整数，x即为冗余的备电支路数，N的取值不宜过大，一般最大取10。该优选取值方案不对本发明N的取值构成限定。具体的，为了达到(N-x)组备电支路正常工作即可支持该用电设备的最大备电需求的效果，当备电电路中各个电容器的电容相等时，每个电容器的电容值为Cmin，则C min满足：C min*M*(N-x)*(Vmax-Vmin)≥Q；x是大于或等于1的整数，Vmax为所述备电支路阵列的最大放电电压，Vmin所述备电支路阵列的最小放电电压，Q为对所述用电设备进行所述预设时长的有效供电所需的电荷量。其中，Vmax可以是上述Vcap，Vmin可以是上述Vstangby。
在本发明实施例中，控制设备还可以通过控制恒流源118的放电来检测备电支路阵列111的电容值的大小，以实现备电电路的自检。请参考图1，其示了本发明实施例涉及的一种备电电路自检时的电流流向示意图。具体地，控制芯片120在备电支路阵列111的电容值时，控制该备电电路110停止充电，并控制恒流源118以恒定电流I0进行放电，比如，控制芯片120可以通过第三接口120c控制升压模块113停止向外输出电流，以实现停止向备电电路110充电，之后，控制芯片120通过第四接口120d控制恒流源118开启，使得备电电路110通过恒流源118所在支路以恒定电流I0进行放电。
在备电电路110通过恒流源118所在支路以恒定电流I0进行放电的过程中，控制芯片120通过第二接口120b来检测恒流源118的电流输入端118a处的电压，由于恒流源118的电流输入端118a与备电支路阵列111的输出端116电性相连，即控制芯片120相当于通过第二接口120b检测备电支路阵列111的输出端116的电压。本发明实施例可以预先设置两个电压值，即第一预设电压值V1和第二预设电压值V2，控制芯片120测量恒流源118的电流输入端118a的电压从第一预设电压值V1降到第二预设电压值V2耗费的时间T0，V1大于V2，此时备电电路110中，备电支路阵列111的电容值满足：C＝I0T0/(V1-V2)。在实际操作中，V1和V2的数值可根据方便获取和减小误差为原则进行选取。
可选地，V1的值可以为(Vcap-500mV),V2的值可以为(Vcap-1000mV)， Vcap的值为备电电路110充电完成后备电支路阵列111的输出端116处的电压，也就是上述升压模块113开启时，升压模块113的输出端113b处的电压值。测量结束后，控制芯片120通过第四接口120d关闭恒流源118，使得恒流源118开路，并且控制芯片120通过第三接口120c打开升压模块113，控制升压模块113继续向备电支路阵列111充电。此时，该用电设备完成对备电支路阵列111的电容值的测量，备电电路110恢复正常备电状态。
其中，备电支路112处于有效工作状态是指，该备电支路112中M个电容器都没有发生短路。
综上所述，上述实施例提供的用电设备，在备电电路中设置由N组相互并联的备电支路组成的备电支路阵列，通过用电设备的控制芯片测量备电支路阵列的电容值；判断该电容值是否小于第一预设阈值；若该电容值小于该第一预设阈值，则提示该备电电路能够对该用电设备进行有效供电的时长小于预设时长，在备电电路中设置多组备电支路，并定期检测备电电路中的备电支路阵列的电容值，当其中部分备电支路发生短路时，能够及时对用户发出提醒，以便用户在备电电路完全失效之前采取必要的补助措施，从而达到提高备电电路的备电效果的目的。
应当理解的是，在本文中使用的，除非上下文清楚地支持例外情况，单数形式“一个”(“a”、“an”、“the”)旨在也包括复数形式。还应当理解的是，在本文中使用的“和/或”是指包括一个或者一个以上相关联地列出的项目的任意和所有可能组合。
上述本发明实施例序号仅仅为了描述，不代表实施例的优劣。
本领域普通技术人员可以理解实现上述实施例的全部或部分步骤可以通过硬件来完成，也可以通过程序来指令相关的硬件完成，所述的程序可以存储于一种计算机可读存储介质中，上述提到的存储介质可以是只读存储器，磁盘或光盘等。
以上所述仅为本发明的较佳实施例，并不用以限制本发明，凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (10)

  1. 一种备电电路，其特征在于，所述备电电路的输出端和用电设备的供电电路的输入端电性相连，所述备电电路的输入端连接于所述供电电路的输出端，所述备电电路包括由N组相互并联的备电支路组成的备电支路阵列，N是大于或等于2的整数；每组所述备电支路包括电容组件和单向导电元件；
    所述单向导电元件分别与所述备电支路阵列的输入端、所述备电支路阵列的输出端以及所述电容组件电性相连；
    所述单向导电元件用于截断所述N组相互并联的备电支路之间的电流通路，且允许电流由所述备电支路阵列的输入端流入，并由所述备电支路阵列的输出端流出。
  2. 根据权利要求1所述的存储设备，其特征在于，所述单向导电元件包括第一二极管和第二二极管；
    所述第一二极管的负极与所述第二二极管的正极电性相连，所述第一二极管的正极与所述备电支路阵列的输入端电性相连，所述第二二极管的负极与所述备电支路阵列的输出端电性相连；所述电容组件包括M个相互并联的电容器，且每个所述电容器的一端连接于所述第一二极管的负极与所述第二二极管的正极之间，每个所述电容器的另一端接地，M是大于或等于1的整数。
  3. 根据权利要求2任一所述的存储设备，其特征在于，每个所述电容器的电容值为Cmin，且C min满足：C min*M*(N-x)*(Vmax-Vmin)≥Q；
    其中，x是大于或等于1的整数，Vmax为所述备电支路阵列的最大放电电压，Vmin为所述备电支路阵列的最小放电电压，Q为对所述存储设备进行所述预设时长的有效供电所需的电荷量。
  4. 根据权利要求2所述的存储设备，其特征在于，所述每组所述备电支路还包括：电阻器；所述电阻器一端与所述第一二极管的负极电性相连，所述电阻器的另一端与所述第二二极管的正极电性相连；每个所述电容器的一端连接于所述电阻器与所述第二二极管的正极之间。
  5. 根据权利要求4所述的存储设备，其特征在于，所述电阻器的阻值R满足：
    (Vcap/R)*N<A0-A1；
    其中，Vcap为所述N组相互并联的备电支路的充电电压，A0为所述备电电路的最大充电电流，A1为预设电流值。
  6. 根据权利要求1所述的备电电路，其特征在于，所述备电电路还包括第 三二极管；
    所述第三二极管与所述备电支路阵列为并联关系，所述第三二极管的正极与所述备电支路阵列的输入端电性相连，所述第三二极管的负极与所述备电支路阵列的输出端电性相连。
  7. 根据权利要求1所述的备电电路，其特征在于，所述备电电路还包括恒流源；
    所述恒流源，包括输入端、输出端和一个控制端；
    所述恒流源的输入端与所述备电支路阵列的输出端电性相连；
    所述恒流源的输出端接地；
    所述恒流源的控制端与所述控制芯片电性相连。
  8. 根据权利要求1-7任一所述的备电电路，其特征在于，所述M个相互并联的电容器是电解铝电容、聚合物固体钽电容、聚合物固体铝电容或陶瓷电容中的至少一种。
  9. 一种用电设备，其特征在于，所述用电设备包括上述权利要求1至8任一所述的备电电路。
  10. 根据权利要求9所述的用电设备，其特征在于，所述用电设备为存储设备。
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