WO2020015123A1 - 一种用于动态随机存取存储器使用raid做纠错校验的方法 - Google Patents

一种用于动态随机存取存储器使用raid做纠错校验的方法 Download PDF

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WO2020015123A1
WO2020015123A1 PCT/CN2018/105854 CN2018105854W WO2020015123A1 WO 2020015123 A1 WO2020015123 A1 WO 2020015123A1 CN 2018105854 W CN2018105854 W CN 2018105854W WO 2020015123 A1 WO2020015123 A1 WO 2020015123A1
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memory
data
control unit
memory control
random
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PCT/CN2018/105854
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French (fr)
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陈育鸣
李庭育
洪振洲
魏智汎
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江苏华存电子科技有限公司
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Publication of WO2020015123A1 publication Critical patent/WO2020015123A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1044—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices with specific ECC/EDC distribution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1076—Parity data used in redundant arrays of independent storages, e.g. in RAID systems

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  • the invention relates to the technical field of a method for achieving error correction check by using an exclusive-OR operation of a random memory, and in particular to a method for dynamic random access memory using RAID for error correction check.
  • Dynamic memory enables users to specify the amount of RAM used by the virtual operating system startup and maximize the system memory available to the platform.
  • the current memory control systems mostly use random data protection with Hamming code.
  • the ratio of the data bit width to the parity bit width is roughly 2: 1/4: 1/8: 1/16: 1/32: 1.
  • the check digit using the current Hamming code method will consume a large amount of memory space. Therefore, an improved technology is urgently needed to solve the existing problems in the existing technology. The problem.
  • the purpose of the present invention is to provide a method for dynamic random access memory using RAID for error correction check.
  • the use of XOR operation to improve the traditional use of Hamming codes requires a large amount of additional storage space, or causes a large amount of block data. Waste of necessary memory storage space.
  • the invention uses XOR operation to protect a large amount of block data.
  • the advantage is that the protection of block data is relatively simple compared with other algebraic algorithms ECC. Compared with the traditional random memory protection method, for a large number of block data Doing data protection saves the space requirement of a large number of parity bits, while still retaining the ability of data error correction, and at the same time can save a lot of waste of memory space to solve the problems raised in the above background technology.
  • a method for dynamic random access memory using RAID for error correction check including the following steps:
  • Step 1 The internal random memory control unit of the main control does not configure additional check digit storage memory components, but embeds or arranges the check digits together into the storage space of the common data memory components;
  • Step 2 The parity bit controlled by the random memory control unit is generated and written into the random memory
  • Step 3 The random memory control unit inside the main control generates a check bit for checking by performing an exclusive-OR operation on the data in the memory control physical layer;
  • Step 4 The random memory control unit controls and reads data from the random memory. When reading, the user data and parity bit data are read at the same time, and the user data verification operation is performed in the verification module.
  • the main control in step 1 includes a memory control unit and a memory control physical layer.
  • the memory control unit is provided with a writing unit and a reading unit, and the writing unit generates data to be transmitted to the memory control physical layer, and the reading unit reads data from the memory control physical layer.
  • FIG. 1 is a schematic diagram of a random memory control unit inside the main control that is not configured with an additional parity storage memory component.
  • FIG. 2 is a schematic diagram of a process of generating and writing a parity bit controlled by a random memory control unit without a dedicated parity bit storage component configured.
  • FIG. 3 is a schematic diagram of a process of reading data and verifying data from a random memory controlled by a random memory control unit without a dedicated parity storage component configured.
  • FIG. 4 is a schematic diagram of an XOR operation operation of generating and reading a check bit.
  • FIG. 5 is a schematic diagram of a structure of a random memory control unit inside the main control.
  • FIG. 6 is a schematic diagram of configuring an additional parity storage memory component for the random memory control unit inside the main control.
  • FIG. 7 is a flow chart illustrating the process of generating and writing the parity bit controlled by the random memory control unit by configuring a dedicated parity bit storage component.
  • FIG. 8 is a schematic diagram of a process for configuring a dedicated parity bit storage component and reading and verifying data from the random memory controlled by the random memory control unit.
  • the present invention provides a technical solution: a method for dynamic random access memory using RAID for error correction checking, including the following steps:
  • Step 1 The internal random memory control unit of the main control does not configure additional check digit storage memory components, but embeds or arranges the check digits together into the storage space of the common data memory components;
  • Step 2 The parity bit controlled by the random memory control unit is generated and written into the random memory
  • Step 3 The random memory control unit inside the main control generates a check bit for checking by performing an exclusive-OR operation on the data in the memory control physical layer;
  • Step 4 The random memory control unit controls and reads data from the random memory. When reading, the user data and parity bit data are read at the same time, and the user data verification operation is performed in the verification module.
  • the main control internally includes a memory control unit and a memory control physical layer.
  • the memory control unit is provided with a writing unit and a reading unit.
  • the writing unit generates data and transmits it to the memory control physical layer.
  • the unit reads data from the memory control physical layer.
  • the internal random memory control unit of the main control is configured with an additional parity bit storage memory component.
  • the parity bit controlled by the random memory control unit is generated and written into random memory. Control the reading of data and verification from random memory. This method will take a lot of check digits, which will consume a lot of memory space.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Detection And Correction Of Errors (AREA)

Abstract

一种用于动态随机存取存储器使用RAID做纠错校验的方法，包括以下步骤：主控内部的随机内存控制单元，不配置额外的校验位储存用内存组件，随机内存控制单元所控制的校验位产生及写入随机内存；主控内部的随机内存控制单元在内存控制物理层通过对数据做异或运算产生校验用的校验位；随机内存控制单元控制并从随机内存中读出资料，使用异或运算对大量块状数据做数据保护，其优点是对于块数据的保护与其他代数算法ECC比较起来控制逻辑设计相对简单，与传统随机内存保护方式相比，对于大量块状数据做数据保护更是省去大量校验位的空间需求，同时仍保有数据纠错的能力，并可以节省大量的内存空间。

Description

一种用于动态随机存取存储器使用RAID做纠错校验的方法 技术领域
本发明涉及随机内存使用异或运算达成纠错校验的方法技术领域，具体为一种用于动态随机存取存储器使用RAID做纠错校验的方法。
背景技术
动态内存(Dynamic Memory)，使用户能够指定虚拟操作系统启动的RAM容量，并将平台可用的系统内存最大化。
现行内存控制系统多以汉明码方式做随机数据保护，其数据位宽与校验位宽的比例大致为2:1/4:1/8:1/16:1/32:1。但对于块数据的保护(512B/1KB/2KB/4KB…)，使用现行汉明码方式的校验位会消耗大量的内存空间，因此，亟待一种改进的技术来解决现有技术中所存在的这一问题。
发明内容
本发明的目的在于提供一种用于动态随机存取存储器使用RAID做纠错校验的方法，使用异或运算以改善传统使用汉明码需要大量额外储存空间，或是对于大量块状数据造成不必要的内存储存空间浪费。本发明使用异或运算对于大量块状数据做数据保护，其优点是对于块数据的保护与其他代数算法ECC比较起来控制逻辑设计相对简单，与传统随机内存保护方式相比，对于大量块状数据做数据保护更是省去大量校验位的空间需求，同时仍保有数据纠错的能力，同时可以节省大量的内存空间浪费，以解决上述背景技术中提出的问题。
为实现上述目的，本发明提供如下技术方案：一种用于动态随机存取存储器使用RAID做纠错校验的方法，包括以下步骤：
步骤一：主控内部的随机内存控制单元，不配置额外的校验位储存用内存组件，而将校验位一同内嵌或编排储存至普通数据用内存组件的储存空间；
步骤二：随机内存控制单元所控制的校验位产生与写入随机内存；
步骤三：主控内部的随机内存控制单元在内存控制物理层通过对数据数据做异或运算产生校验用的校验位；
步骤四：随机内存控制单元所控制并从随机内存中读出资料，读取时，同时读出用户数据与校验位数据，于校验模块内进行用户数据校验运算。
优选的，步骤一中的主控内部包括内存控制单元及内存控制物理层。
优选的，内存控制单元内部设置有写入单元和读取单元，所述写入单元产生数据传输至内存控制物理层内，再由读取单元从内存控制物理层内读出资料。
与现有技术相比，本发明的有益效果是：
使用异或运算对于大量块状数据做数据保护，其优点是对于块数据的保护与其他代数算法ECC比较起来控制逻辑设计相对简单，与传统随机内存保护方式相比，对于大量块状数据做数据保护更是省去大量校验位的空间需求，同时仍保有数据纠错的能力，同时可以节省大 量的内存空间浪费。
附图说明
图1为主控内部的随机内存控制单元不配置额外的校验位储存用内存组件的示意图。
图2为无配置专用校验位储存组件，随机内存控制单元所控制的校验位产生与写入随机内存的流程示意图。
图3为无配置专用校验位储存组件，随机内存控制单元所控制从随机内存读出资料与校验的流程示意图。
图4为校验位产生与读取校验单元的异或运算操作流程示意图。
图5为主控内部的随机内存控制单元结构示意图。
图6为主控内部的随机内存控制单元配置额外的校验位储存用内存组件的示意图。
图7为配置专用校验位储存组件，随机内存控制单元所控制的校验位产生与写入随机内存的流程示意图。
图8为配置专用校验位储存组件，随机内存控制单元所控制从随机内存读出资料与校验的流程示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参阅图1-4，本发明提供一种技术方案：一种用于动态随机存取存储器使用RAID做纠错校验的方法，包括以下步骤：
步骤一：主控内部的随机内存控制单元，不配置额外的校验位储存用内存组件，而将校验位一同内嵌或编排储存至普通数据用内存组件的储存空间；
步骤二：随机内存控制单元所控制的校验位产生与写入随机内存；
步骤三：主控内部的随机内存控制单元在内存控制物理层通过对数据数据做异或运算产生校验用的校验位；
步骤四：随机内存控制单元所控制并从随机内存中读出资料，读取时，同时读出用户数据与校验位数据，于校验模块内进行用户数据校验运算。
如图5所示，主控内部包括内存控制单元及内存控制物理层，内存控制单元内部设置有写入单元和读取单元，写入单元产生数据传输至内存控制物理层内，再由读取单元从内存控制物理层内读出资料。
如图6-8所示，主控内部的随机内存控制单元，配置额外的校验位储存用内存组件，随机内存控制单元所控制的校验位产生与写入随机内存，随机内存控制单元所控制从随机内存读出资料与校验，该方法将占用大量的校验位，校验位会消耗大量的内存空间。
尽管已经示出和描述了本发明的实施例，对于本领域的普通技术人员而言，可以理解在不脱离本发明的原理和精神的情况下可以对这些实施例进行多种变化、修改、替换和变型，本发明的范围由所附权 利要求及其等同物限定。

Claims (3)

  1. 一种用于动态随机存取存储器使用RAID做纠错校验的方法，其特征在于：包括以下步骤：
    步骤一：主控内部的随机内存控制单元，不配置额外的校验位储存用内存组件，而将校验位一同内嵌或编排储存至普通数据用内存组件的储存空间；
    步骤二：随机内存控制单元所控制的校验位产生与写入随机内存；
    步骤三：主控内部的随机内存控制单元在内存控制物理层通过对数据数据做异或运算产生校验用的校验位；
    步骤四：随机内存控制单元所控制并从随机内存中读出资料，读取时，同时读出用户数据与校验位数据，于校验模块内进行用户数据校验运算。
  2. 根据权利要求1所述的一种用于动态随机存取存储器使用RAID做纠错校验的方法，其特征在于：所述步骤一中的主控内部包括内存控制单元及内存控制物理层。
  3. 根据权利要求2所述的一种用于动态随机存取存储器使用RAID做纠错校验的方法，其特征在于：所述内存控制单元内部设置有写入单元和读取单元，所述写入单元产生数据传输至内存控制物理层内，再由读取单元从内存控制物理层内读出资料。
PCT/CN2018/105854 2018-07-20 2018-09-14 一种用于动态随机存取存储器使用raid做纠错校验的方法 WO2020015123A1 (zh)

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