WO2020013409A1

WO2020013409A1 - Liquid crystal display device

Info

Publication number: WO2020013409A1
Application number: PCT/KR2019/000013
Authority: WO
Inventors: 방정석; 김강우; 배광수; 오민정; 이보람; 조영제
Original assignee: 삼성디스플레이 주식회사
Priority date: 2018-07-11
Filing date: 2019-01-02
Publication date: 2020-01-16
Also published as: KR20200007108A

Abstract

A liquid crystal display device comprises: a first pixel row and a second pixel row; a first data line and a second data line which extend in a first direction; and a plurality of TFTs, wherein the first pixel row and the second pixel row extend in a second direction, the first pixel row comprises a first pixel electrode and a third pixel electrode arranged to be adjacent to the first pixel electrode, the second pixel row comprises a second pixel electrode and a fourth pixel electrode arranged to be adjacent to the second pixel electrode, the plurality of TFTs comprise a first TFT having one end connected to the first pixel electrode, a second TFT having one end connected to the second pixel electrode, a third TFT having one end connected to the third pixel electrode, and a fourth TFT having one end connected to the fourth pixel electrode, the first data line crosses the first pixel electrode and extends along the boundary between the second pixel electrode and the fourth pixel electrode, the second data line extends along the boundary between the first pixel electrode and the third pixel electrode and crosses the fourth pixel electrode, the first data line is connected to the other end of the second TFT, and the second data line is connected to the other end of the third TFT.

Description

Liquid crystal display

The present invention relates to a liquid crystal display device.

The importance of the display device is increasing with the development of multimedia. In response to this, various types of display devices such as liquid crystal displays (LCDs) and organic light emitting displays (OLEDs) are used.

Among the display devices, the liquid crystal display is one of the most widely used flat panel display devices. The liquid crystal display includes two substrates on which electric field generating electrodes such as a pixel electrode and a common electrode are formed, and a liquid crystal layer interposed therebetween. An electric field is generated by applying a voltage to the electrode, thereby determining an orientation of liquid crystal molecules of the liquid crystal layer and controlling an polarization of incident light to display an image.

SUMMARY OF THE INVENTION An object of the present invention is to provide a liquid crystal display device capable of performing high resolution driving and having a low aperture ratio loss.

The objects of the present invention are not limited to the above-mentioned technical problem, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

According to one or more exemplary embodiments, a liquid crystal display includes: a first pixel row; A second pixel row adjacent to the first pixel row; First and second data lines extending in a first direction; And a plurality of thin film transistors, wherein the first pixel row and the second pixel row each extend in a second direction crossing the first direction, wherein the first pixel row is adjacent to the first pixel electrode. A third pixel electrode disposed, wherein the second pixel row includes a second pixel electrode and a fourth pixel electrode disposed adjacent thereto, and each of the plurality of thin film transistors has one end connected to the first pixel electrode A thin film transistor, a second thin film transistor whose one end is connected to the second pixel electrode, a third thin film transistor whose one end is connected to the third pixel electrode, and a fourth thin film transistor whose one end is connected to the fourth pixel electrode, A first data line crosses the first pixel electrode, extends along a boundary between the second pixel electrode and the fourth pixel electrode, and the second data line is connected to the first pixel electrode. Extends along a boundary of the third pixel electrode, crosses the fourth pixel electrode, the first data line is connected to the other end of the second thin film transistor, and the second data line is connected to the third thin film transistor. Connected to the other end.

The first data line may be electrically separated from the first thin film transistor, and the second data line may be electrically separated from the fourth thin film transistor.

The first pixel electrode, the second pixel electrode, the third pixel electrode, and the fourth pixel electrode each include a plurality of domains, wherein the first data line and the second data line each cross each other. The domain boundary of the first pixel electrode and the fourth pixel electrode may overlap.

The width of each of the plurality of domains may be the same.

The first pixel electrode may include at least one stem electrode and a plurality of branch electrodes extending from the stem electrode.

The stem electrode and the first data line may overlap.

The thickness of the branch electrode may be the same for each domain.

The liquid crystal display may extend in the second direction, and include a first scan line disposed on one side of the first pixel row and a second scan line disposed along one side of the second pixel row. The semiconductor device may further include a scan line, wherein the first scan line is connected to a gate electrode of the first thin film transistor and a gate electrode of the third thin film transistor, and the second scan line is a gate electrode of the second thin film transistor and the second scan line. The first scan line and the second scan line may be connected to the gate electrode of the fourth thin film transistor, and may transmit the same scan signal.

The liquid crystal display may further include a third data line extending in the first direction, crossing the third pixel electrode, and electrically connected to the fourth thin film transistor.

An interval between the second data line and the first data line may be equal to an interval between the second data line and the third data line.

The first data line may include a first bypass portion that does not short with the first thin film transistor, and the second data line may include a second bypass portion that does not short with the fourth thin film transistor.

The direction in which the first bypass part is bent and the direction in which the second bypass part is bent may be different from each other.

According to another exemplary embodiment of the present invention, there is provided a liquid crystal display device including: a first pixel; A second pixel disposed adjacent to the first pixel in a first direction; A first data line providing a first data signal to the first pixel and extending in the first direction; A second data line providing a second data signal to the second pixel and extending in the first direction; A first scan line configured to provide a first scan signal to the first pixel and extend in a second direction crossing the first direction; And a second scan line that provides a second scan signal to the second pixel and extends in the second direction, wherein the first scan line and the second scan line are electrically connected to each other. The second pixels are arranged to be shifted in the second direction.

The first data line may overlap one edge of the first pixel, cross the second pixel, and the second data line may cross the first pixel, and overlap the other edge of the second pixel. have.

Each of the first pixel and the second pixel includes a stem electrode formed in the first direction, the first data line overlaps the stem electrode of the second pixel, and the second data line is the first pixel. It may overlap with the stem electrode of.

The liquid crystal display may further include a third pixel adjacent to the first pixel in the first direction and adjacent to the second pixel in the second direction.

The first pixel, the second pixel, and the third pixel may be arranged in a delta manner.

The liquid crystal display may further include a third data line that provides a third data signal to the third pixel and extends in the first direction.

The first data line overlaps one side etch of the first pixel, the third data line overlaps the other edge of the first pixel, and the second data line includes the first data line and the third data. It can be placed between the lines.

Specific details of other embodiments are included in the detailed description and the drawings.

According to embodiments of the present invention, the liquid crystal display may perform high resolution driving while minimizing the reduction of the aperture ratio.

The effects according to the present invention are not limited by the contents exemplified above, and more various effects are included in the present specification.

1 is a block diagram schematically illustrating a liquid crystal display according to an exemplary embodiment.

FIG. 2 is an equivalent circuit diagram of the first to fourth pixel units illustrated in FIG. 1.

FIG. 3 is a layout diagram illustrating first to fourth pixel units illustrated in FIG. 1.

4 is a diagram illustrating in detail the first pixel unit illustrated in FIG. 3.

FIG. 5 is a diagram illustrating a gate conductor included in the first pixel unit illustrated in FIG. 4.

FIG. 6 is a diagram illustrating a data conductor included in the first pixel unit illustrated in FIG. 4.

FIG. 7 illustrates a transparent conductor included in the first pixel unit illustrated in FIG. 4.

FIG. 8 is a cross-sectional view taken along the line I1-I1 'of FIG. 4.

FIG. 9 is a cross-sectional view taken along the line I 2 -I 2 ′ shown in FIG. 4.

10 is a layout diagram illustrating first to fourth pixel units of a liquid crystal display according to another exemplary embodiment.

11 is a layout diagram illustrating first to fourth pixel units of a liquid crystal display according to another exemplary embodiment.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention, and the general knowledge in the technical field to which the present invention belongs. It is provided to fully convey the scope of the invention to those skilled in the art, and the present invention is defined only by the scope of the claims.

When elements or layers are referred to as "on" or "on" of another element or layer, intervening other elements or layers as well as intervening another layer or element in between. It includes everything. On the other hand, when a device is referred to as "directly on" or "directly on" indicates that no device or layer is intervened in the middle.

The same reference numerals are used for the same or similar parts throughout the specification.

Hereinafter, embodiments will be described with reference to the drawings.

Referring to FIG. 1, the liquid crystal display device 1 may include a display unit 110, a scan driver 120, a data driver 130, and a timing controller 140.

The display unit 110 is defined as an area for displaying an image. The display unit 110 may include a plurality of pixel units including the first to fourth pixel units PX1 to PX4. Each pixel portion PX1 to PX4 may be arranged in a triangular (or delta) manner. The arrangement structure of each pixel portion PX1 to PX4 will be described later in detail.

Each of the plurality of pixel parts may be one of the first to nth scan lines SL1 to SLn, where n is a natural number of two or more, and one of the first to mth data lines DL1 to DLm, where m is a natural number of two or more. Can be electrically connected. The first to nth scan lines SL1 to SLn may extend in the first direction d1. In addition, the first to m th data lines DL1 to DLm may extend in the second direction d2. The first direction d1 may cross the second direction d2 in one embodiment. Referring to FIG. 1, the first direction d1 is illustrated in the row direction, and the second direction d2 is illustrated in the column direction. Meanwhile, two adjacent scan lines among the first to nth scan lines SL1 to SLn may be electrically connected to each other. For example, the first scan line SL1 may be electrically connected to the second scan line SL2. This will be described in more detail with reference to FIG. 2.

The scan driver 120 may generate first to nth scan signals S1 to Sn based on the first control signal CONT1 provided from the timing controller 140. The scan driver 120 may provide the generated first to nth scan signals S1 to Sn to the plurality of pixel units disposed in the display unit 110 through the first to nth scan lines SL1 to SLn. have. The scan driver 120 may be formed through a plurality of switching elements in one embodiment, or may be an integrated circuit in another embodiment.

The data driver 130 may receive the second control signal CONT2 and the image data DATA from the timing controller 140. The data driver 130 may generate the first to m th data signals D1 to Dm based on the second control signal CONT2 and the image data DATA. The data driver 130 may provide the generated first to m th data signals D1 to Dm to the plurality of pixel units disposed in the display unit 110 through the first to m th data lines DL1 to DLm. have. The data driver 130 may include, for example, a shift register, a latch, a digital-to-analog converter, and the like.

The timing controller 140 may receive an image signal RGB and a control signal CS from the outside. The timing controller 140 processes the image signal RGB and the control signal CS to suit the operating conditions of the display unit 110, thereby processing the image data DATA, the first control signal CONT1, and the second control signal ( CONT2) can be generated. In an embodiment, the timing controller 140 may generate the first control signal CONT1 and the second control signal CONT2 suitable for the 120HZ driving scheme.

The image signal RGB may include a plurality of grayscale data to be provided to the display unit 110. In addition, the control signal CS may include, for example, a horizontal synchronization signal, a vertical synchronization signal, a main clock signal, and the like. The horizontal synchronizing signal indicates the time taken to display one line of the display unit 110. The vertical synchronization signal represents a time taken to display an image of one frame. The main clock signal is a signal in which the timing controller 140 is synchronized with each of the scan driver 120 and the data driver 130, and becomes a reference for generating various signals.

Hereinafter, the plurality of pixel units disposed on the display unit 110 will be described in more detail with reference to the first to fourth pixel units PX1 to PX4.

FIG. 2 is an equivalent circuit diagram of the first to fourth pixel units illustrated in FIG. 1. FIG. 3 is a layout diagram illustrating first to fourth pixel units illustrated in FIG. 1.

2 and 3, the liquid crystal display device 1 includes a first pixel portion PX1 and a third pixel portion PX3, and includes a first pixel row extending in a first direction d1, and The second pixel row is disposed adjacent to the first pixel row in the second direction d2 and includes the second pixel portion PX2 and the fourth pixel portion PX4 and extends in the first direction d1. It may include. The pixel portion included in the first pixel row and the pixel portion included in the second pixel row may be alternately disposed. For example, the second pixel portion PX2 is adjacent to the first pixel portion PX1 in the second direction d2 and extends in the second direction d2 along one edge of the first pixel portion PX1. The first virtual line may be disposed to cross the second pixel portion PX2. The fourth pixel portion PX4 adjacent to the second pixel portion PX2 in the first direction d1 is adjacent to the first pixel portion PX1 in the second direction d2. A second virtual line extending in the second direction d2 along the other edge may be disposed to cross the fourth pixel portion PX4. Therefore, the pixel column extending in the second direction d2 may extend in a zigzag. Accordingly, the third virtual line extending in the second direction d2 and being the center line of the first virtual line and the second virtual line extends along the other edge of the second pixel portion PX2 and one edge of the fourth pixel portion PX4. Can be.

The first to fourth pixel units PX1 to PX4 may receive different data signals from different data lines, that is, each of the first to fourth data lines DL1 to DL4. Meanwhile, scan signals may be provided from the same scan line between pixel units disposed in the same row. That is, the first pixel portion PX1 and the third pixel portion PX3 may receive the first scan signal S1 from the first scan line SL1, and the second pixel portion PX2 and the fourth pixel. The unit PX4 may receive the second scan signal S2 from the second scan line SL2.

Here, the first scan line SL1 and the second scan line SL2 are electrically connected to each other through the first node N1. That is, the first scan signal S1 provided from the first scan line SL1 and the second scan signal S2 provided from the second scan line SL2 may be the same signal. The position of the first node N1 is not particularly limited and may be disposed in a non-display area in which an image is not displayed. Meanwhile, the first scan line SL1 and the second scan line SL2 are not electrically connected only to the first node N1. That is, the number of nodes connected to the first scan line SL1 and the second scan line SL2 may be plural.

Each of the first to fourth pixel units PX1 to PX4 may include a switching element, a pixel electrode, a liquid crystal capacitor, and a storage capacitor. This will be described in more detail with reference to the first pixel unit PX1.

The first pixel portion PX1 may include a first switching element TR1, a first pixel electrode PE1, a first liquid crystal capacitor Clc1, and a first storage capacitor Cst1.

In an embodiment, the first switching element TR1 may be a thin film transistor having an input electrode, an output electrode, and a control electrode. Hereinafter, the input electrode will be represented as a source electrode, the output electrode as a drain electrode, and the control electrode as a gate electrode.

The first switching element TR1 is the first gate electrode GE1 electrically connected to the first scan line SL1, the first source electrode SE1 and first electrically connected to the first data line DL1. It may include a first drain electrode DE1 electrically connected to the pixel electrode PE1. Here, the first drain electrode DE1 of the first switching element TR1 may be electrically connected to the first pixel electrode PE1 through the first contact hole CNT1. The first switching element TR1 performs a switching operation based on the first scan signal S1 provided from the first scan line SL1, and thus receives the first data signal D1 provided from the first data line DL1. ) May be provided to the first pixel electrode PE1.

The first liquid crystal capacitor Clc1 is formed between the first pixel electrode PE1 and the common electrode (“CE” of FIG. 8) provided with the common voltage Vcom. The first storage capacitor Cst1 is formed between the first pixel electrode PE1 and the first storage line RL1 provided with the storage voltage Vst and between the first pixel electrode PE1 and the second storage line RL2. do. The relationship between the shape of the first pixel electrode PE1 and another configuration will be described later.

Hereinafter, driving of the liquid crystal display device 1 according to the exemplary embodiment of the present invention will be described with reference to the first pixel portion PX1 and the second pixel portion PX2.

The first switching element TR1 performs a switching operation based on the first scan signal S1. In addition, the second switching element TR2 performs a switching operation based on the second scan signal S2. However, as described above, the first scan line SL1 and the second scan line SL2 are electrically connected to each other. That is, the first scan signal S1 and the second scan signal S2 are substantially the same signal.

Accordingly, the first switching element TR1 and the second switching element TR2 perform the same switching operation with each other. However, since the first switching element TR1 is electrically connected to the first data line DL1, the second switching element TR2 is electrically connected to the second data line DL2, and thus, the first pixel electrode ( Different data signals may be provided to each of the PE1 and the second pixel electrode PE2. That is, the first pixel electrode PE1 and the second pixel electrode PE2 may receive different data signals at the same time. That is, since the time in which the scan signals are sequentially provided from the first scan line SL1 to the nth scan line SLn can be reduced by half, the gate delay can be reduced. Through this, the liquid crystal display device 1 according to the exemplary embodiment of the present invention may be applied to a high resolution product requiring high frequency driving.

Hereinafter, an arrangement structure between adjacent data lines will be described. For convenience of description, the description will be made based on the first to third data lines DL1 to DL3.

The first data line DL1 may extend along the second direction d2 at one edge of the first pixel portion PX1 and may cross the second pixel portion PX2. In detail, the first data line DL1 extends along the second direction d2 at one edge of the first pixel portion PX1, and the extended first data line DL1 extends through the second pixel portion ( It may further extend in the second direction d2 to overlap the vertical stem of the pixel electrode of PX2. Expressed as “nested” in this specification, unless otherwise defined, the two configurations are in the thickness direction of the liquid crystal display device 1 (eg, in a direction perpendicular to the surface of the first substrate 210 in FIG. 8). It means to overlap. The stem of the pixel electrode will be described later in detail. The first data line DL1 may include a bypass area in order to prevent a short from the second pixel portion PX2 to the second drain electrode extension DEP2. The bypass area will be described later along with the description of the second data line DL2. The first data line DL1 may be linear except for the bypass area. However, each data line DL1 may not include a bypass area.

The second data line DL2 may cross the first pixel portion PX1 and extend in the second direction d2. The second data line DL2 overlaps the vertical stem portion ('PE1a2' in FIG. 7) of the first pixel portion PX1, similar to the first data line DL1 passing through the second pixel portion PX2. It may extend in the second direction d2. The second data line DL2 may include a first bypass region ('BP1' in FIG. 6 and the same below) and a second bypass region ('BP2 in FIG. 6) in order to prevent a short with the first drain electrode extension DEP1. ', The same below). The first drain electrode extension part DEP1 may be disposed between the first bypass region BP1 and the second bypass region BP1. It may have a shape that is bent in each bypass region BP1 and BP2 of the second data line DL2. In an embodiment, the second data line DL2 has a shape in which the angle bent in the first bypass area BP1 is obtuse, and the region BP2 bent in the second bypass area has a right angle. The shape bent in each bypass area BP1 or BP2 may be various. The second data line DL2 extending across the first pixel portion PX1 further extends along the second direction d2 at one side edge of the second pixel portion PX2.

The third data line DL3 may extend along the second direction d2 at the other edge of the first pixel portion PX1 and the one edge of the third pixel portion PX3. Here, the other edge of the first pixel portion PX1 and the one edge of the third pixel portion PX3 may be in contact with each other. The third data line DL3 may be a wiring for providing a data signal to the third pixel portion PX3. The third data line DL3 may extend in the second direction d2 along a boundary line to overlap the edge of the first pixel portion PX1 and the edge of the third pixel portion PX3. The extended third data line DL3 is adjacent to the third pixel portion PX3 in the second direction d2 and has a fourth pixel portion PX4 disposed to overlap a portion of the third pixel portion PX3. It may further extend in the second direction d2 to cross. The third data line DL3 may overlap the vertical stem portion of the fourth pixel portion PX4.

Through the arrangement of the data lines DL1 to DL3 described above, the liquid crystal display device 1 according to the exemplary embodiment of the present invention can secure a wide aperture ratio.

Next, with reference to FIGS. 4 to 9, the arrangement of the arrangements of the liquid crystal display device 1 according to the exemplary embodiment of the present invention will be described. For convenience of explanation, the description will be made based on the first pixel unit PX1.

4 is a diagram illustrating in detail the first pixel unit illustrated in FIG. 3. FIG. 5 is a diagram illustrating a gate conductor included in the first pixel unit illustrated in FIG. 4. FIG. 6 is a diagram illustrating a data conductor included in the first pixel unit illustrated in FIG. 4. FIG. 7 illustrates a transparent conductor included in the first pixel unit illustrated in FIG. 4. FIG. 8 is a cross-sectional view taken along the line I1-I1 'of FIG. 4. FIG. 9 is a cross-sectional view taken along the line I 2 -I 2 ′ shown in FIG. 4.

The first display panel 200 is disposed to face the second display panel 300. The liquid crystal layer 400 is interposed between the first display panel 200 and the second display panel 300. The liquid crystal layer 400 may include a plurality of liquid crystal molecules 410. In some embodiments, the first display panel 200 may be bonded to the second display panel 300 through sealing.

The first display panel 200 will be described.

In an embodiment, the first substrate 210 may be a transparent insulating substrate. Herein, the transparent insulating substrate may include a glass material, a quartz material, or a transparent plastic material. In another embodiment, the first substrate 210 may be a flexible substrate, or may have a shape in which a plurality of films and the like are stacked.

The gate conductor GW may be disposed on the first substrate 210. The gate conductor GW includes a plurality of scan lines including the first scan line SL1, a plurality of gate electrodes including the first gate electrode GE1, and a plurality of storage electrodes including the storage line RL. It may include. Although not shown, the gate conductor GW is electrically connected to each of the scan lines SL1 to SLn, and a plurality of repair lines for performing a normal switching operation when the scan lines SL1 to SLn are disconnected. It may further include.

The first scan line SL1 extends in the first direction d1 and is directly connected to the gate electrode GE1.

The first pixel portion PX1 may include a storage line RL. Each storage line RL1 may be disposed on the same layer as the plurality of scan lines including the first scan line SL1. In an embodiment, the storage line RL may be arranged to surround at least a portion of the first pixel electrode PE1. For example, the storage line RL may be arranged to surround the left side, the right side, and the lower side of the first pixel electrode PE1 in the drawing. However, the storage line RL is shown in the drawing and is not limited in shape.

The storage line RL may overlap at least part of the first pixel electrode PE1. As the first pixel electrode PE1 and the storage line RL overlap, the first storage capacitor Cst1 described above may be formed.

The gate conductor GW includes aluminum (Al), copper (Cu), molybdenum (Mo), chromium (Cr), titanium (Ti), tungsten (W), molybdenum tungsten (MoW), molybdenum (MoTi), It may be formed of a single film, a double film composed of at least two, or a triple film composed of three, selected from conductive metals including copper / mortitanium (Cu / MoTi). A plurality of storage lines including a plurality of scan lines including a first scan line SL1 included in the gate conductor GW, a plurality of gate electrodes including a first gate electrode GE1, and a storage line RL. The electrodes may be simultaneously formed through the same mask process.

The gate insulating layer 220 may be disposed on the gate conductor GW. The gate insulating layer 220 may be formed of silicon nitride, silicon oxide, or the like in one embodiment. The gate insulating layer 220 may have a multilayer structure including at least two insulating layers having different physical properties.

The data conductor DW may be disposed on the gate insulating layer 220. The data conductor DW includes a plurality of data lines including a first data line DL1, a second data line DL1, and a third data line DL3, and a plurality of data lines including a first source electrode SE1. The semiconductor layer 230 may include a source electrode, a plurality of drain electrodes including the first drain electrode DE1, and a first semiconductor pattern 230a.

The semiconductor layer 230 may be disposed on the gate insulating layer 220. In some embodiments, the semiconductor layer 230 may be formed of amorphous silicon, polycrystalline silicon, or the like. In another embodiment, the semiconductor layer 230 may include an oxide semiconductor. When the semiconductor layer 230 includes an oxide semiconductor, the semiconductor layer 230 may include IGZO (In-Ga-Zinc-Oxide), ZnO, ZnO ₂ , CdO, SrO, SrO ₂ , CaO, CaO ₂ , MgO, MgO ₂ , InO, In ₂ O ₂ , GaO, Ga ₂ O, Ga ₂ O ₃ , SnO, SnO ₂ , GeO, GeO ₂ , PbO, Pb ₂ O ₃ , Pb ₃ O ₄ , TiO, TiO ₂ , Ti ₂ O ₃ , and one selected from an oxide semiconductor including Ti ₃ O ₅ .

The first semiconductor pattern 230a of the semiconductor layer 230 may form a channel region of the first switching element TR1.

The data conductor DW may further include an ohmic contact layer 240. The ohmic contact layer 240 may be disposed on the semiconductor layer 230. The ohmic contact layer 240 may be made of a material such as n + hydrogenated amorphous silicon doped with a high concentration of n-type impurities such as phosphorus, or may be made of silicide. However, the ohmic contact layer 240 may be omitted if the semiconductor layer 230 is made of an oxide semiconductor. Hereinafter, it will be described as including the ohmic contact layer 240.

The first data line DL1, the first source electrode SE1, and the first drain electrode DE1 may be disposed on the gate insulating layer 220 and the ohmic contact layer 240. The first source electrode SE1 may be branched from the first data line DL1 so that at least a portion of the first source electrode SE1 overlaps the first gate electrode GE1. The first drain electrode DE1 may overlap the first gate electrode GE1 and may be disposed to be spaced apart from the first source electrode SE1 by a predetermined distance. The first drain electrode DE1 may further include a first drain electrode extension DEP1. The first drain electrode extension DEP1 may overlap the storage line RL and the first contact hole CNT1.

The second data line DL2 and the third data line DL3 may be disposed on the gate insulating layer 220 and the ohmic contact layer 240 similarly to the first data line DL1. As described above, the second data line DL2 may include the first bypass region BP1 and the second bypass region BP2 so as not to be shorted with the first drain electrode extension DEP1. The first and second bypass regions BP1 and BP2 may be disposed at positions overlapping the first pixel electrode PE1, which will be described later, but is not limited thereto.

The distance l1 of the second data line DL2 and the first data line DL1, the second data line DL2, and the third data line DL3 in the region overlapping the first pixel electrode PE1. The distance l2 may be the same.

In the drawing, the shape of the first source electrode SE1 is U, and the first drain electrode DE1 is illustrated as being surrounded by the first source electrode SE1, but is not limited thereto. The first source electrode SE1, the first drain electrode DE1, the first semiconductor pattern 230a, and the first gate electrode GE1 form the aforementioned first switching element TR1.

The data conductor (DW) includes aluminum (Al), copper (Cu), molybdenum (Mo), chromium (Cr), titanium (Ti), tungsten (W), molybdenum (MoW), molybdenum (MoTi), It may be formed of a single film, a double film composed of at least two, or a triple film composed of three, selected from conductive metals including copper / mortitanium (Cu / MoTi). However, the present invention is not limited thereto and may be made of various metals or conductors. In one embodiment, the data conductors DW may be simultaneously formed through the same mask process.

The first passivation layer 250 may be disposed on the data conductor DW. The first passivation layer 250 may include an opening that exposes at least a portion of the first drain electrode extension part DEP1. In some embodiments, the first passivation layer 250 may be formed of an inorganic insulator such as silicon nitride and silicon oxide. The first passivation layer 250 may prevent the pigment of the organic insulating layer 260, which will be described later, from flowing into the first semiconductor pattern 230a.

The color filter CF may be disposed on the first passivation layer 250. The color filter CF overlaps the opening of the first passivation layer 250 and includes an opening that exposes at least a portion of the first drain electrode extension part DEP1.

The light passing through the color filter CF may display one of primary colors such as three primary colors of red, green, and blue. However, the display color of the light passing through the color filter CF is not limited to the primary color, and any one of cyan, magenta, yellow, and white colors is displayed. You may. For example, the color filter CF is a material that displays different colors for each of the adjacent pixel parts (eg, the first pixel part PX1 and the third pixel part PX3) in the first direction d1. The pixel portion (for example, the first pixel portion PX1 and the second pixel portion PX2) adjacent to each other in the second direction d2 may be formed of a material displaying the same color. . However, the present invention is not limited thereto and may be formed of a material displaying different colors for each of the adjacent pixel units regardless of the direction. 8 and 9 illustrate that the color filter CF is disposed on the first display panel 200. Alternatively, the color filter CF may be disposed on the second display panel 300.

The organic insulating layer 260 may be disposed on the first passivation layer 250 and the color filter CF. The organic insulating layer 260 overlaps the opening of the first passivation layer 250 and includes an opening that exposes at least a portion of the first drain electrode extension part DEP1. The organic insulating layer 260 has excellent planarization characteristics and may include an organic material having photosensitivity. The organic insulating layer 260 may be omitted.

The second passivation layer 270 may be disposed on the organic insulating layer 260. For example, the second passivation layer 270 may be formed of an inorganic insulator such as silicon nitride and silicon oxide. The second passivation film 270 may be omitted.

An opening of the first passivation layer 250, an opening of the color filter CF, an opening of the organic insulating layer 260, and an opening of the second passivation layer 270 may form a first contact hole CNT1.

The transparent conductor TE may be disposed on the second passivation layer 270. The transparent conductor TE may include a transparent conductive material. Here, the transparent conductive material may include polycrystalline, monocrystalline, or amorphous indium tin oxide (ITO). The transparent conductor TE may include a plurality of pixel electrodes including the first pixel electrode PE1 and a shielding electrode Scom. The first pixel electrode PE1 and the shielding electrode Scom are disposed on the same layer, and are physically and electrically insulated from each other.

The shielding electrode Scom may have a shape extending generally in the first direction d1. The shielding electrode Scom may include a plurality of vertical stems extending from the stem extending in the first direction d1 in the fourth direction d4. In an exemplary embodiment, the horizontal line of the shielding electrode Scom may overlap at least a portion of the plurality of scan lines including the first scan line SL1, but is not limited thereto. In addition, the vertical stem of the shielding electrode Scom may overlap at least a portion of the plurality of data lines. In addition, the shielding electrode Scom may overlap the plurality of storage electrodes. For example, the shielding electrode Scom may overlap the first region G1 and the second region G2 of the storage line RL. Can be. In one embodiment, the voltage provided to the shielding electrode Scom may have the same voltage level as the common voltage (“Vcom” of FIG. 2) provided to the common electrode CE. In another embodiment, the shielding electrode Scom may be directly provided with the common voltage Vcom.

The first pixel electrode PE1 may be in direct contact with the first drain electrode extension DEP1 exposed through the first contact hole CNT1. In addition, the first pixel electrode PE1 overlaps the common electrode CE. Accordingly, the first liquid crystal capacitor Clc1 (see FIG. 2) may be formed between the first pixel electrode PE1 and the common electrode CE that overlap each other.

Hereinafter, the shape of the first pixel electrode PE1 will be described in more detail.

First, the stem part and the branch part of the first pixel electrode PE1 will be described.

The first pixel electrode PE1 extends in the first stem portion PE1a1 and the second direction d2 extending in the first direction d1, and crosses the first stem portion PE1a1 and crosses the second stem d2. Is physically connected to the second stem part PE1a2, the first stem part PE1a1, and the second stem part PE1a2 extending to the end of the branch parts PE1b1 to PE1b4, which will be described later. The edge stem PE1a3 and the stem parts PE1a1 to PE1a3 may be physically spaced apart from each other and may include a connection stem part PE1a4 including the first connection part PE1c. In the drawing, the first stem part PE1a1 may be a horizontal stem part, and the second stem part 2PE1a2 may be a vertical stem part.

The first connection part PE1c is defined as an area overlapping the first contact hole CNT1. Therefore, the first connection part PE1c of the first pixel electrode PE1 may be directly connected to the exposed first drain electrode extension part DEP1.

In an embodiment, the first stem portion may define a domain divided into a second direction d2 and a fourth direction d4 on the drawing based on the first stem portion PE1a1. In addition, a domain divided into a first direction d1 and a third direction d3 may be defined based on the second stem part PE1a2. The domain is described in detail below.

The second stem portion of the first pixel electrode PE1 may overlap the second data line DL2, and the vertical stem portion of the second pixel electrode PE2 overlaps the first data line DL1. Can be.

The plurality of branches may extend from the first stem part PE1a1 and the second stem part PE1a2. The first branch portion PE1b1 extending generally in the fifth direction d5, the second branch portion PE1b2 generally extending in the sixth direction d6, and the seventh direction d7. The third branch part PE1b3 extending in the first direction and the fourth branch part PE1b4 extending generally in the eighth direction d8 are included.

The first branch part PE1b1 extends in the fifth direction d5 from the first stem part PE1a1 and the second stem part PE1a2 and is physically connected to the edge stem part PE1a3. The second branch part PE1b2 extends from the first stem part PE1a1 and the second stem part PE1a2 in the sixth direction d6 and is physically connected to the edge stem part PE1a3. The third branch part PE1b3 extends from the first stem part PE1a1 and the second stem part PE1a2 in the seventh direction d7, and partly is physically connected to the edge stem part PE1a3, and the other part. May be physically connected to the connection stem part PE1a4. The edge stem part PE1a3 may extend from the first stem part PE1a1 and the second stem part PE1a2, but may include a part whose end is not physically connected to any stem part. The fourth branch part PE1b4 extends in the eighth direction d8 from the first stem part PE1a1 and the second stem part PE1a2, and at least a part of the fourth branch part PE1b4 is an edge stem part PE1a3. ) Is physically connected, and the remaining part may not be physically connected to any of the edge stems PE1a3.

All the stem parts and the branch parts of the first pixel electrode PE1 are electrically connected to each other, and therefore, each stem part and each branch part may have the same potential.

Next, the domain region of the first pixel electrode PE1 will be described.

The first pixel electrode PE1 may include four domains based on the first stem part PE1a1 and the second stem part PE1a2. For example, the first domain region DM1 may have a region extending in the fourth direction d4 from the first stem portion PE1a1 and a region extending in the first direction d1 from the second stem portion PE1a2. It may be defined as an overlapping area. The second domain region DM2 is a region where the region extending in the fourth direction d4 from the first stem portion PE1a1 and the region extending in the third direction d3 from the second stem portion PE1a2 overlap each other. Can be defined. The third domain region DM3 is a region where the region extending in the second direction d2 from the first stem portion PE1a1 and the region extending in the third direction d3 from the second stem portion PE1a2 overlap each other. Can be defined. The fourth domain region DM4 is a region where the region extending in the second direction d2 from the first stem portion PE1a1 and the region extending in the first direction d1 from the second stem portion PE1a2 overlap each other. Can be defined.

Here, the first domain area DM1 may include the first branch part PE1b1, the second domain area DM2 may include the second branch part PE1b2, and the third domain area DM3. ) May include a third branch portion PE1b3, and the fourth domain region DM4 may include a fourth branch portion PE1b3.

The widths of the domains extending in the first direction d1 and the third direction d3 based on the second stem portion PE1a2 may be the same. For example, the widths of the first domain area DM1 and the second domain area DM2 may be the same, and the widths of the third domain area DM3 and the fourth domain area DM4 may be the same. However, the present invention is not limited thereto, and the width of each domain may be different. For example, the width of the first domain area DM1 may be larger than the width of the second domain area DM2.

When the electric field is formed, the plurality of liquid crystal molecules 410 disposed in the first domain region DM1 may be generally aligned in the fifth direction d5 or the seventh direction d7. Similarly, the plurality of liquid crystal molecules 410 disposed in the second domain region DM2 may be generally aligned in the sixth direction d6 or the seventh direction d7 when an electric field is formed. When the electric field is formed, the plurality of liquid crystal molecules 410 disposed in the third domain region DM3 may be generally aligned in the seventh direction d7 or the fifth direction d5. When the electric field is formed, the plurality of liquid crystal molecules 410 disposed in the fourth domain region DM4 may be generally aligned in the eighth direction d8 or the sixth direction d6. In one embodiment, the alignment direction of the liquid crystals in each domain area DM1 to DM4 may be different. For this reason, the liquid crystal display device 1 may provide a screen having a wide viewing angle.

The first alignment layer (not shown) may be disposed on the transparent conductor TE. The first alignment layer may induce an initial alignment of the plurality of liquid crystal molecules 410 in the liquid crystal layer 400. In some embodiments, the first alignment layer may include a polymer organic material having an imide group in a repeating unit of a main chain.

Each branch may have a constant thickness W in each of the domain areas DM1 to DM4. It may also include spaces between adjacent branches. The thickness SP of the space between adjacent branches in each domain region may be constant. Therefore, the ratio W / SP of the thickness W of the branch to the thickness SP of the space between adjacent branches in each domain region may be constant. In an embodiment, the ratio W / SP of the thickness W of the branch to the thickness SP of the space between adjacent branches in the first to fourth domain regions DM1 to DM4 may be the same, but is not limited thereto. It doesn't happen.

Next, the second display panel 300 will be described.

The second substrate 310 is disposed to face the first substrate 210. The second substrate 310 may be formed of transparent glass, plastic, or the like, and may be formed of the same material as the first substrate 210 in one embodiment.

The black matrix BM may be disposed on the second substrate 310. The black matrix BM may be disposed along the first direction d1 in the inactive region. Here, the inactive region may be a region that does not include branch portions of the pixel electrode as a boundary between adjacent pixel portions in the second direction d2. That is, the black matrix BM may extend in the first direction d1 and may be disposed to overlap the plurality of scan lines SL1 to SLn.

The black matrix BM may block light from being transmitted to the inactive region. The material of the black matrix BM is not particularly limited as long as it can block light. The black matrix BM may be formed of, for example, a photosensitive composition, an organic material, or a metallic material. In one embodiment, the photosensitive composition may include a binder resin, a polymerizable monomer, a polymerizable oligomer, a pigment, a dispersant, and the like. The metallic material may include chromium or the like.

Meanwhile, in the present exemplary embodiment, the black matrix extending in the second direction d2 between pixel portions adjacent to the first direction d1 (eg, between the first pixel portion PX1 and the third pixel portion PX3). (BM) may not be arranged. By adjusting the distance between adjacent pixel portions in the first direction d1, the liquid crystal alignment may be adjusted so that light does not pass between adjacent pixel portions in the first direction d1 without the black matrix BM, and the shielding electrode Scom may be used. The liquid crystal alignment can be adjusted to prevent light from passing through.

The planarization layer 320 may be disposed on the black matrix BM. The planarization layer 320 may provide flatness with respect to the common electrode CE. The material of the planarization layer 320 is not particularly limited and may include an organic material or an inorganic material in one embodiment.

The common electrode CE may be disposed on the planarization layer 320. At least a portion of the common electrode CE may overlap the first pixel electrode PE1. The common electrode CE may be formed in a plate shape in one embodiment. However, the present invention is not limited thereto, and the common electrode CE may include a plurality of slits. The common electrode CE may be formed of a transparent conductive material such as ITO and IZO, or a reflective metal such as aluminum, silver, chromium, or an alloy thereof.

Although not illustrated, a second alignment layer may be disposed on the common electrode CE. The second alignment layer may induce an initial alignment of the plurality of liquid crystal molecules 410 in the liquid crystal layer 400. In some embodiments, the second alignment layer may be formed of the same material as the first alignment layer.

Next, the liquid crystal layer 400 will be described.

The liquid crystal layer 400 includes a plurality of liquid crystal molecules 410. The plurality of liquid crystal molecules 410 may be vertically aligned in an initial alignment state with negative dielectric anisotropy in one embodiment. The plurality of liquid crystal molecules 410 may have a predetermined pretilt angle in the initial alignment state. Initial alignment of the plurality of liquid crystal molecules 410 may be induced by the first and second alignment layers described above. When the electric field is formed between the first display panel 200 and the second display panel 300, the plurality of liquid crystal molecules 410 may change the polarization state of the light passing through the liquid crystal layer by tilting or rotating in a specific direction.

That is, the liquid crystal display device 1 according to an exemplary embodiment of the present invention electrically connects two neighboring scan lines to each other to drive a high resolution driving signal at the same time to the pixel electrodes connected to the two scan lines. The data line may be disposed so as to overlap the stem portion and the shielding electrode of the pixel electrode, thereby reducing the area of the dark portion to improve the aperture ratio.

Hereinafter, a liquid crystal display according to another exemplary embodiment of the present invention will be described. However, descriptions overlapping with those described in FIGS. 1 to 9 will be omitted. In addition, the same reference numerals will be used for the same configuration as the configuration described with reference to FIGS. 1 to 9.

The liquid crystal display device 2 according to the present embodiment differs from the embodiment of FIG. 3 in that the number of stems and the number of domain regions are different. Each pixel unit PX1_1 to PX4_1 may include two domain regions. In addition, the shape of the branch portion of the inter-pixel domain region adjacent in the second direction d2 may be different. For convenience of explanation, the first pixel unit PX1_1 and the second pixel unit PX2_1 will be described as an example.

The first pixel portion PX1_1 may include a vertical stem PE1a2 extending in the second direction d2 and dividing the first pixel electrode PE1_1 into two. The first pixel electrode PE1_1 is a right region of the vertical stem portion in the drawing, and is a left region of the first domain region DM1_1 including the branch portion extending in the fifth direction d5 and the vertical stem portion PE1a2 in the drawing. The second domain region DM2_1 may include a branch portion extending in the sixth direction d6.

Like the first pixel unit PX1_1, the second pixel unit PX2_1 may include a vertical stem PE2a2 extending in the second direction d2 and dividing the second pixel electrode PE2_1 into two. The second pixel electrode PE2_1 is a right region of the vertical stem portion PE2a2 in the drawing and generally includes the first domain region DM1_2 including the branch portion extending in the eighth direction d8 and the vertical stem portion PE2a2 in the drawing. It may include a second domain region DM1_2 that is a left region and includes a branch portion extending in the seventh direction d7.

When the electric field is formed, the plurality of liquid crystal molecules 410 disposed in the first domain region DM1_1 of the first pixel portion PX1_1 are generally aligned in a seventh direction d7 opposite to the fifth direction d5. Can be. Similarly, the plurality of liquid crystal molecules 410 disposed in the second domain region DM2_1 of the first pixel portion PX1_1 generally have a seventh direction d7 facing the sixth direction d6 when an electric field is formed. Can be oriented.

When the electric field is formed, the plurality of liquid crystal molecules 410 disposed in the first domain region DM1_2 of the second pixel portion PX2_1 are generally aligned in a sixth direction d6 opposite to the eighth direction d8. Can be. Similarly, when the electric field is formed, the plurality of liquid crystal molecules 410 disposed in the second domain region DM2_2 may be aligned in a fifth direction d5 that is generally opposed to the seventh direction d7.

Meanwhile, in the liquid crystal display device 2 according to the present exemplary embodiment, the horizontal stem portion ('first stem portion PE1a1 of FIG. 7) may be omitted from each pixel portion PX1_1 to PX4_1.

Since the alignment directions of the liquid crystals are different in each of the domain regions DM1_1 and DM2_1 of the first pixel unit PX1_1 and each of the domain regions DM1_2 and DM2_2 of the second pixel unit PX2_1, the liquid crystal display device 2 may It is possible to provide a screen with a wide viewing angle.

The liquid crystal display device 3 according to the present exemplary embodiment differs from the embodiment of FIG. 3 in that the ratio of the thickness of the branch to the thickness of the space between adjacent branches is not the same in each domain area. For convenience of explanation, the first pixel unit PX1_2 and the second pixel unit PX2_2 will be described as an example.

The first pixel portion PX1_2 may include a first domain region DM1 and a fourth domain region DM4 disposed on the right side of the drawing based on the second stem portion PE1a2, and are disposed on the left side. It may include a second domain area DM2 and a third domain area DM3.

The ratio W1 / S2 of the thickness W1 of the branch to the thickness SP1 of the space between adjacent branches in the first domain area DM1 and the fourth domain area DM4 is W2 / S2. The ratio of the thickness W2 of the branch to the thickness SP2 of the space between adjacent branches in the domain area DM3 may be different. In an embodiment, the ratio W1 / SP1 of the thickness W1 of the branch to the thickness SP1 of the space between the adjacent branches in the first domain area DM1 and the fourth domain area DM4 is equal to the second domain area (D1). In the DM2 and the third domain region DM3, the ratio W2 may be greater than the ratio W2 of the thickness W2 of the space between the adjacent branches between the branches SP2, but is not limited thereto. In another embodiment, the ratio of the thickness of the branch to the thickness of the space between adjacent branches between each of the domains DM1 to DM4 may be all different, and the space between adjacent branches in the first domain region DM1 and the second domain region DM2. The ratio of the thickness of the branch to the thickness of may be formed to be greater than the ratio of the thickness of the branch to the thickness of the space between adjacent branches in the third domain area DM3 and the fourth domain area DM4 (W2 / SP2).

Like the first pixel unit PX1_2, the second pixel unit PX2_2 may include a first domain region DM1 and a fourth domain region DM4 disposed on the right side of the drawing on the basis of the second stem portion. The second domain area DM2 and the third domain area DM3 disposed on the left side may be included. The ratio W1 / SP1 of the thickness W1 of the branch to the thickness SP1 of the space between adjacent branches in the first domain area DM1 and the fourth domain area DM4 in the first pixel portion PX1_2 is equal to the second. In the exemplary embodiment, when formed in the domain region DM2 and the third domain region DM3 to be greater than the ratio W2 / SP2 of the thickness W2 of the branch to the thickness SP2 of the space between the adjacent branches, the second pixel. In the part PX2_2, the ratio W1 / SP1 of the thickness W1 of the branch to the thickness SP1 of the space between adjacent branches in the first domain area DM1 and the fourth domain area DM4 is equal to the second domain area ( It may be formed to be smaller than the ratio W2 / SP2 of the thickness W2 of the branch to the thickness SP2 of the space between adjacent branches in the DM2) and the third domain region DM3.

Although described above with reference to the embodiments of the present invention, which is merely an example and not limiting the present invention, those skilled in the art to which the present invention pertains without departing from the essential characteristics of the embodiments of the present invention. It will be appreciated that various modifications and applications are not possible. For example, each component specifically shown in the embodiment of the present invention may be modified. And differences relating to such modifications and applications will have to be construed as being included in the scope of the invention defined in the appended claims.

Claims

First pixel row;

A second pixel row adjacent to the first pixel row;

First and second data lines extending in a first direction; And

Including a plurality of thin film transistor,

The first pixel row and the second pixel row each extend in a second direction crossing the first direction,

The first pixel row includes a first pixel electrode and a third pixel electrode disposed adjacent thereto;

The second pixel row includes a second pixel electrode and a fourth pixel electrode disposed adjacent thereto;

The plurality of thin film transistors may include a first thin film transistor having one end connected to the first pixel electrode;

A second thin film transistor having one end connected to the second pixel electrode,

A third thin film transistor having one end connected to the third pixel electrode, and

One end includes a fourth thin film transistor connected to the fourth pixel electrode,

The first data line crosses the first pixel electrode and extends along a boundary between the second pixel electrode and the fourth pixel electrode;

The second data line extends along a boundary between the first pixel electrode and the third pixel electrode and crosses the fourth pixel electrode;

The first data line is connected to the other end of the second thin film transistor,

And the second data line is connected to the other end of the third thin film transistor.
According to claim 1,

The first data line is electrically separated from the first thin film transistor, and the second data line is electrically separated from the fourth thin film transistor.
According to claim 1,

The first pixel electrode, the second pixel electrode, the third pixel electrode, and the fourth pixel electrode each include a plurality of domains, and the first data line and the second data line respectively cross each other. The liquid crystal display device overlapping a domain boundary between the first pixel electrode and the fourth pixel electrode.
The method of claim 3,

The width of each of the plurality of domains is the same as each other.
The method of claim 3,

The first pixel electrode includes at least one stem electrode and a plurality of branch electrodes extending from the stem electrode.
The method of claim 5,

The liquid crystal display device wherein the stem electrode and the first data line overlap.
The method of claim 5,

The liquid crystal display of which the thickness of the branch electrode is the same for each domain.
According to claim 1,

And a first scan line extending along the second direction and disposed on one side of the first pixel row, and a second scan line extending along the second direction and disposed on one side of the second pixel row. But

The first scan line is connected to a gate electrode of the first thin film transistor and a gate electrode of the third thin film transistor,

The second scan line is connected to a gate electrode of the second thin film transistor and a gate electrode of the fourth thin film transistor,

The first scan line and the second scan line transmit the same scan signal.
According to claim 1,

And a third data line extending in the first direction and crossing the third pixel electrode and electrically connected to the fourth thin film transistor.
The method of claim 9,

And an interval between the second data line and the first data line is equal to an interval between the second data line and the third data line.
According to claim 1,

The first data line includes a first bypass portion that does not short with the first thin film transistor,

And the second data line includes a second bypass portion to prevent the second data line from being shorted with the fourth thin film transistor.
The method of claim 11, wherein

And a direction in which the first bypass portion is bent and a direction in which the second bypass portion is bent.
A first pixel;

A second pixel disposed adjacent to the first pixel in a first direction;

A first data line providing a first data signal to the first pixel and extending in the first direction;

A second data line providing a second data signal to the second pixel and extending in the first direction;

A first scan line configured to provide a first scan signal to the first pixel and extend in a second direction crossing the first direction; And

A second scan line configured to provide a second scan signal to the second pixel and extend in the second direction,

The first scan line and the second scan line are electrically connected;

The first pixel and the second pixel are arranged to be shifted in the second direction.
The method of claim 13,

The first data line overlaps one edge of the first pixel and crosses the second pixel;

The second data line crosses the first pixel and overlaps the other edge of the second pixel.
The method of claim 14,

The first pixel and the second pixel each include a stem electrode formed in the first direction,

The first data line overlaps the stem electrode of the second pixel, and the second data line overlaps the stem electrode of the first pixel.
The method of claim 13,

And a third pixel adjacent to the first pixel in the first direction and adjacent to the second pixel in the second direction.
The method of claim 16,

The first pixel, the second pixel, and the third pixel are arranged in a delta manner.
The method of claim 16,

And a third data line providing a third data signal to the third pixel and extending in the first direction.
The method of claim 18,

The first data line overlaps an edge of one side of the first pixel,

The third data line overlaps the other edge of the first pixel,

And the second data line is disposed between the first data line and the third data line.
The method of claim 19,

And an interval between the second data line and the first data line is equal to an interval between the second data line and the third data line.