WO2020009296A1

WO2020009296A1 - Liquid crystal display device

Info

Publication number: WO2020009296A1
Application number: PCT/KR2018/016719
Authority: WO
Inventors: 방정석; 배광수; 오민정; 이보람; 조영제
Original assignee: 삼성디스플레이 주식회사
Priority date: 2018-07-03
Filing date: 2018-12-27
Publication date: 2020-01-09
Also published as: KR20200004481A

Abstract

A liquid crystal display device comprises: an insulating substrate comprising a pixel area comprising a first active area, a second active area, and a non-active area arranged between the first active area and the second active area; a first scan line arranged on the insulating substrate so as to overlap the non-active area; a first thin-film transistor which is a thin-film transistor comprising a control electrode, a first electrode, and a second electrode, the control electrode being connected to the first scan line; and a first pixel electrode arranged in the pixel area and electrically connected to the second electrode of the thin-film transistor. The first scan line extends in a first direction. The first active area, the non-active area, and the second active area are arranged in a second direction intersecting with the first direction. The first pixel electrode comprises: a first sub-pixel electrode portion arranged in the first active area; a second sub-pixel electrode portion arranged in the second active area; and a connecting electrode portion arranged in the non-active area so as to connect the first sub-pixel electrode portion and the second sub-pixel electrode portion.

Description

Liquid crystal display

The present invention relates to a liquid crystal display device.

The importance of the display device is increasing with the development of multimedia. In response to this, various types of display devices such as liquid crystal displays (LCDs) and organic light emitting displays (OLEDs) are used.

Among the display devices, the liquid crystal display is one of the most widely used flat panel display devices. The liquid crystal display includes two substrates on which electric field generating electrodes such as a pixel electrode and a common electrode are formed, and a liquid crystal layer interposed therebetween. An electric field is generated by applying a voltage to the electrode, thereby determining an orientation of liquid crystal molecules of the liquid crystal layer and controlling an polarization of incident light to display an image.

SUMMARY OF THE INVENTION An object of the present invention is to provide a liquid crystal display device capable of performing high resolution driving and having a low aperture ratio loss.

The objects of the present invention are not limited to the above-mentioned technical problem, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

According to an exemplary embodiment of the present invention, a liquid crystal display device includes a pixel including a first active region, a second active region, and an inactive region disposed between the first active region and the second active region. An insulating substrate comprising a region; A first scan line disposed on the insulating substrate and overlapping the inactive region; A thin film transistor including a control electrode, a first electrode, and a second electrode, the thin film transistor having the control electrode connected to the first scan line; And a first pixel electrode disposed in the pixel region and electrically connected to the second electrode of the thin film transistor, wherein the first scan line extends in a first direction, the first active region, the inactive region, and The second active region may be arranged along a second direction crossing the first direction, and the first pixel electrode may include a first subpixel electrode portion disposed in the first active region and a second disposed in the second active region. And a second subpixel electrode part and a connection electrode part disposed in the inactive region and connecting the first subpixel electrode part and the second subpixel electrode part.

The liquid crystal display may further include a first data line extending in a second direction and crossing the first active region, the inactive region, and the second active region and connected to the first electrode of the thin film transistor. have.

The first pixel electrode and the second electrode are disposed on different layers with an insulating film interposed therebetween, and the connection electrode part of the first pixel electrode is electrically connected to the second electrode through a contact hole passing through the insulating film. It may include a contact portion.

The pixel area may include a first edge and a second edge extending along the second direction and facing each other, wherein the first subpixel electrode part is disposed at the first edge and extends in the second direction. An electrode, wherein the second subpixel electrode part includes a second stem electrode disposed at the first edge and extending in the second direction, and the connection electrode part is connected to the first stem electrode of the first subpixel electrode part; The second subpixel electrode may be disposed between the second stem electrodes to connect them.

The width of the first direction of the contact portion of the connection electrode part may be greater than the width of the first direction of the first stem electrode and the second stem electrode.

The contact portion of the connection electrode portion may be positioned at a central portion equidistant from the first edge and the second edge.

The first subpixel electrode unit may further include a third stem electrode disposed inside the first edge, extending in the second direction, and overlapping the first data line.

The first subpixel electrode part may further include a fourth stem electrode extending in the first direction and connecting the first stem electrode of the first subpixel electrode part to the third stem electrode of the first subpixel electrode part. have.

The second subpixel electrode part may further include a second stem electrode disposed inside the first edge, extending in the second direction, and overlapping the data line.

The liquid crystal display may further include a second data line extending in a second direction and crossing the first active region, the inactive region, and the second active region and spaced apart from the first data line. .

The first subpixel electrode part is disposed inward of the first edge, extends in the second direction, and overlaps the first data line with a third stem electrode, and a plurality of branches extending from the third stem electrode. An electrode may be further included, and some of the branch electrodes may overlap at least a portion of the second data line.

The first subpixel electrode part, the second subpixel electrode part, and the connection electrode part may be all disposed on the same layer.

A second data line extending in the second direction and crossing the first active region, the inactive region, and the second active region and spaced apart from the first data line; A second scan line extending in the first direction; A second pixel electrode crossing the second scan line; A control electrode connected to the second scan line; An electrode connected to the second data line; And a second thin film transistor having another electrode connected to the second pixel electrode, wherein the first thin film transistor and the second thin film transistor may simultaneously perform a switching operation.

The first scan line and the second scan line may be electrically connected to each other.

And a second switching element having a control electrode connected to the second scan line, one electrode connected to the second data line, and another electrode connected to the second pixel electrode.

The liquid crystal display may further include a first storage line disposed on the same layer as the first scan line and surrounding a portion of the first active area.

At least a portion of the first subpixel electrode part may overlap the first storage line.

The liquid crystal display further includes a second storage line disposed on the same layer as the first scan line and surrounding a portion of the second active area, wherein the first storage line and the second storage line are spaced apart from each other. Can be deployed.

The liquid crystal display further includes a second data line extending in a second direction and crossing the first active region, the inactive region, and the second active region and spaced apart from a first data line. At least one of the first data line and the second data line may include a bent region.

At least a portion of the bent region may overlap the first subpixel electrode part.

Specific details of other embodiments are included in the detailed description and the drawings.

According to embodiments of the present invention, it is possible to perform high resolution driving while minimizing the reduction of the aperture ratio.

The effects according to the present invention are not limited by the contents exemplified above, and more various effects are included in the present specification.

1 is a block diagram schematically illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 2 is an equivalent circuit diagram of the first to fourth pixel units illustrated in FIG. 1.

FIG. 3 is a layout diagram illustrating first to fourth pixel units illustrated in FIG. 1.

4 is a diagram illustrating in detail the first pixel unit illustrated in FIG. 3.

FIG. 5 is a diagram illustrating a gate conductor included in the first pixel unit illustrated in FIG. 4.

FIG. 6 is a diagram illustrating a data conductor included in the first pixel unit illustrated in FIG. 4.

FIG. 7 illustrates a transparent conductor included in the first pixel unit illustrated in FIG. 4.

FIG. 8 is a cross-sectional view taken along the line I1-I1 'of FIG. 4.

FIG. 9 is a cross-sectional view taken along lines I2-I2 'and I3-I3' shown in FIG.

FIG. 10 is a cross-sectional view taken along the line I4-I4 'of FIG. 4.

FIG. 11 is a diagram illustrating a data conductor of the first pixel portion illustrated in FIG. 6 and a transparent conductor of the first pixel portion illustrated in FIG. 7.

12 is a layout diagram illustrating one pixel unit of a liquid crystal display according to another exemplary embodiment.

13 is a layout diagram illustrating one pixel unit of a liquid crystal display according to another exemplary embodiment.

14 is a layout diagram illustrating one pixel unit of a liquid crystal display according to another exemplary embodiment.

15 is a layout diagram illustrating one pixel unit of a liquid crystal display according to another exemplary embodiment.

16 is a layout diagram illustrating one pixel unit of a liquid crystal display according to another exemplary embodiment.

17 is an equivalent circuit diagram of a liquid crystal display according to another exemplary embodiment of the present invention.

18 is a layout diagram illustrating first to fourth pixel units in the configuration of the liquid crystal display according to the equivalent circuit diagram of FIG. 17.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention, and the general knowledge in the art to which the present invention pertains. It is provided to fully convey the scope of the invention to those skilled in the art, and the present invention is defined only by the scope of the claims.

When elements or layers are referred to as "on" or "on" of another element or layer, intervening other elements or layers as well as intervening another layer or element in between. It includes everything. On the other hand, when a device is referred to as "directly on" or "directly on" indicates that no device or layer is intervened in the middle.

Although the first, second, etc. are used to describe various components, these components are of course not limited by these terms. These terms are only used to distinguish one component from another. Therefore, of course, the first component mentioned below may be a second component within the technical spirit of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In addition, the terms "comprise" or "have" are intended to indicate that there is a feature, number, step, operation, component, part, or combination thereof described on the specification, one or more other features or numbers, It does not preclude the possibility of the presence or addition of steps, actions, components, parts or combinations thereof.

The same reference numerals are used for the same or similar parts throughout the specification.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

Referring to FIG. 1, a liquid crystal display according to an exemplary embodiment may include a display unit 110, a scan driver 120, a data driver 130, and a timing controller 140.

The display unit 110 is defined as an area for displaying an image. The display unit 110 may include a plurality of pixel units including the first to fourth pixel units PX1 to PX4. Each of the plurality of pixel parts may be one of the first to nth scan lines SL1 to SLn, where n is a natural number of two or more, and one of the first to mth data lines DL1 to DLm, where m is a natural number of two or more. Can be electrically connected. The first to nth scan lines SL1 to SLn may extend in the first direction d1. In addition, the first to m th data lines DL1 to DLm may extend in the second direction d2. The first direction d1 may cross the second direction d2 in one embodiment. Referring to FIG. 1, the first direction d1 is illustrated in the row direction, and the second direction d2 is illustrated in the column direction. Meanwhile, two adjacent scan lines among the first to nth scan lines SL1 to SLn may be electrically connected to each other. For example, the first scan line SL1 may be electrically connected to the second scan line SL2. This will be described in more detail with reference to FIG. 2.

The scan driver 120 may generate first to nth scan signals S1 to Sn based on the first control signal CONT1 provided from the timing controller 140. The scan driver 120 may provide the generated first to nth scan signals S1 to Sn to the plurality of pixel units disposed in the display unit 110 through the first to nth scan lines SL1 to SLn. have. The scan driver 120 may be formed through a plurality of switching elements in one embodiment, or may be an integrated circuit in another embodiment.

The data driver 130 may receive the second control signal CONT2 and the image data DATA from the timing controller 140. The data driver 130 may generate the first to m th data signals D1 to Dm based on the second control signal CONT2 and the image data DATA. The data driver 130 may provide the generated first to m th data signals D1 to Dm to the plurality of pixel units disposed in the display unit 110 through the first to m th data lines DL1 to DLm. have. The data driver 130 may include, for example, a shift register, a latch, a digital-to-analog converter, and the like.

The timing controller 140 may receive an image signal RGB and a control signal CS from the outside. The timing controller 140 processes the image signal RGB and the control signal CS to suit the operating conditions of the display unit 110, thereby processing the image data DATA, the first control signal CONT1, and the second control signal ( CONT2) can be generated. In an embodiment, the timing controller 140 may generate the first control signal CONT1 and the second control signal CONT2 suitable for the 120HZ driving scheme.

The image signal RGB may include a plurality of grayscale data to be provided to the display unit 110. In addition, the control signal CS may include, for example, a horizontal synchronization signal, a vertical synchronization signal, a main clock signal, and the like. The horizontal synchronizing signal indicates the time taken to display one line of the display unit 110. The vertical synchronization signal represents a time taken to display an image of one frame. The main clock signal is a signal in which the timing controller 140 is synchronized with each of the scan driver 120 and the data driver 130, and becomes a reference for generating various signals.

Hereinafter, the plurality of pixel units disposed on the display unit 110 will be described in more detail with reference to the first to fourth pixel units PX1 to PX4.

FIG. 2 is an equivalent circuit diagram of the first to fourth pixel units illustrated in FIG. 1. FIG. 3 is a layout diagram illustrating first to fourth pixel units illustrated in FIG. 1. 4 is a diagram illustrating in detail the first pixel unit illustrated in FIG. 3.

2 to 4, the first pixel portion PX1 and the second pixel portion PX2 may be adjacent to each other along the second direction d2. In addition, the third pixel portion PX3 and the fourth pixel portion PX4 may also be adjacent to each other along the second direction d2. The first to fourth pixel units PX1 to PX4 may receive different data signals from different data lines, that is, each of the first to fourth data lines DL1 to DL4. Meanwhile, scan signals may be provided from the same scan line between pixel units disposed in the same row. That is, the first pixel portion PX1 and the third pixel portion PX3 may receive the first scan signal S1 from the first scan line SL1, and the second pixel portion PX2 and the fourth pixel. The unit PX4 may receive the second scan signal S2 from the second scan line SL2.

Here, the first scan line SL1 and the second scan line SL2 are electrically connected to each other through the first node N1. That is, the first scan signal S1 provided from the first scan line SL1 and the second scan signal S2 provided from the second scan line SL2 may be the same signal. The position of the first node N1 is not particularly limited and may be disposed in a non-display area in which an image is not displayed. Meanwhile, the first scan line SL1 and the second scan line SL2 are not electrically connected only to the first node N1. That is, the number of nodes connected to the first scan line SL1 and the second scan line SL2 may be plural.

Each of the first to fourth pixel units PX1 to PX4 may include a switching element, a pixel electrode, a liquid crystal capacitor, and a storage capacitor. This will be described in more detail with reference to the first pixel unit PX1.

The first pixel portion PX1 may include a first switching element TR1, a first pixel electrode PE1, a first liquid crystal capacitor Clc1, and a first storage capacitor Cst1.

In an embodiment, the first switching element TR1 may be a thin film transistor having an input electrode, an output electrode, and a control electrode. Hereinafter, the input electrode will be represented as a source electrode, the output electrode as a drain electrode, and the control electrode as a gate electrode.

The first switching element TR1 is the first gate electrode GE1 electrically connected to the first scan line SL1, the first source electrode SE1 and first electrically connected to the first data line DL1. It may include a first drain electrode DE1 electrically connected to the pixel electrode PE1. Here, the first drain electrode DE1 of the first switching element TR1 may be electrically connected to the first pixel electrode PE1 through the first contact hole CNT1. The first contact hole CNT may be located equidistantly from the first data line DL1 and the second data line DL2. In addition, the first contact hole CNT may be located closer to the first active area AA1 of the second active area AA2. The first active area AA1 and the second active area AA2 will be described later. The first switching element TR1 performs a switching operation based on the first scan signal S1 provided from the first scan line SL1, and thus receives the first data signal D1 provided from the first data line DL1. ) May be provided to the first pixel electrode PE1.

The first liquid crystal capacitor Clc1 is formed between the first pixel electrode PE1 and the common electrode (see FIG. 8) provided with the common voltage Vcom. The first storage capacitor Cst1 is formed between the first pixel electrode PE1 and the first storage line RL1 provided with the storage voltage Vcst, and between the first pixel electrode PE1 and the second storage line RL2. do. The relationship between the shape of the first pixel electrode PE1 and another configuration will be described later.

Hereinafter, driving of the liquid crystal display according to the exemplary embodiment of the present invention will be described with reference to the first pixel unit PX1 and the second pixel unit PX2.

The first switching element TR1 performs a switching operation based on the first scan signal S1. In addition, the second switching element TR2 performs a switching operation based on the second scan signal S2. However, as described above, the first scan line SL1 and the second scan line SL2 are electrically connected to each other. That is, the first scan signal S1 and the second scan signal S2 are substantially the same signal.

Accordingly, the first switching element TR1 and the second switching element TR2 perform the same switching operation with each other. However, since the first switching element TR1 is electrically connected to the first data line DL1, the second switching element TR2 is electrically connected to the second data line DL2, and thus, the first pixel electrode ( Different data signals may be provided to each of the PE1 and the second pixel electrode PE2. That is, the first pixel electrode PE1 and the second pixel electrode PE2 may receive different data signals at the same time. As a result, the liquid crystal display according to the exemplary embodiment may be applied to a high resolution product requiring high frequency driving.

Next, with reference to FIGS. 4 to 10, the arrangement relationship of the components of the liquid crystal display according to the exemplary embodiment will be described. For convenience of explanation, the description will be made based on the first pixel unit PX1.

FIG. 5 is a diagram illustrating a gate conductor included in the first pixel unit illustrated in FIG. 4. FIG. 6 is a diagram illustrating a data conductor included in the first pixel unit illustrated in FIG. 4. FIG. 7 illustrates a transparent conductor included in the first pixel unit illustrated in FIG. 4. FIG. 8 is a cross-sectional view taken along the line I1-I1 'of FIG. 4. FIG. 9 is a cross-sectional view taken along lines I2-I2 'and I3-I3' shown in FIG. FIG. 10 is a cross-sectional view taken along the line I4-I4 'of FIG. 4.

The first display panel 200 is disposed to face the second display panel 300. The liquid crystal layer 400 is interposed between the first display panel 200 and the second display panel 300. The liquid crystal layer 400 may include a plurality of liquid crystal molecules 410. In some embodiments, the first display panel 200 may be bonded to the second display panel 300 through sealing.

The first display panel 200 will be described.

In an embodiment, the first substrate 210 may be a transparent insulating substrate. Herein, the transparent insulating substrate may include a glass material, a quartz material, or a transparent plastic material. In another embodiment, the first substrate 210 may be a flexible substrate, or may have a shape in which a plurality of films and the like are stacked.

The gate conductor GW may be disposed on the first substrate 210. The gate conductor GW may include a plurality of scan lines including the first scan line SL1, a plurality of gate electrodes including the first gate electrode GE1, and one or more storage lines RL1 and RL2. have. In addition, the gate conductor GW may further include a plurality of repair lines including the first repair line RPL1.

The first scan line SL1 extends in the first direction d1 and is directly connected to the gate electrode GE1. The first repair line RPL1 may extend along the first direction d1 and may be spaced apart from the first scan line SL1. The first repair line RPL1 may be electrically connected to the first scan line SL1. In an embodiment, the first repair line RPL1 is directly connected to the first gate electrode GE1 and the gate electrode disposed in the same row as the first gate electrode GE1, so that the first repair line RPL1 is connected to the first scan line SL1. Can be electrically connected. The first repair line RPL1 may also receive the same scan signal as the first scan line SL1. Accordingly, even when the first scan line SL1 is disconnected, the first switching element TR1 may normally perform a switching operation. Meanwhile, the first repair line RPL1 may be omitted. In addition, the positions of the first repair line RPL1 and the first scan line SL1 may be changed.

A portion of the first pixel electrode PE1 may be disposed to overlap the first scan line SL1. The expression "overlapping" in this specification means that two configurations overlap in the thickness direction of the liquid crystal display device (the direction perpendicular to the surface of the first substrate in the drawing) unless otherwise defined.

The first pixel portion PX1 may include at least one storage line RL1 and RL2. Each storage line RL1 and RL2 may be disposed on the same layer as the plurality of scan lines including the first scan line SL1. Each of the storage lines RL1 and RL2 may be disposed to surround one region of the first pixel electrode PE1. For example, the first storage line RL1 is disposed to surround a portion of the first pixel electrode PE1 that corresponds to the first active region AA1, and the second storage line RL2 is formed of the first pixel electrode ( The PE1 may be disposed to surround a portion corresponding to the second active region AA2. The first active area AA1 and the second active area AA2 will be described later. However, each of the storage lines RL1 and RL2 is illustrated in FIG. 5 and is not limited in shape.

Each storage line RL1 and RL2 may overlap at least a portion of the first pixel electrode PE1. As the first pixel electrode PE1 and each of the storage lines RL1 and RL2 overlap each other, the first storage capacitor Cst1 described above may be formed.

The gate conductor GW includes aluminum (Al), copper (Cu), molybdenum (Mo), chromium (Cr), titanium (Ti), tungsten (W), molybdenum tungsten (MoW), molybdenum (MoTi), It may be formed of a single film, a double film composed of at least two, or a triple film composed of three, selected from conductive metals including copper / mortitanium (Cu / MoTi). A plurality of scan lines including the first scan line SL1 included in the gate conductor GW, a plurality of gate electrodes including the first gate electrode GE1, a storage line RL, and a first repair line The plurality of repair lines including RPL1) may be simultaneously formed through the same mask process.

The gate insulating layer 220 may be disposed on the gate conductor GW. The gate insulating layer 220 may be formed of silicon nitride, silicon oxide, or the like in one embodiment. The gate insulating layer 220 may have a multilayer structure including at least two insulating layers having different physical properties.

The data conductor DW may be disposed on the gate insulating layer 220. The data conductor DW includes a plurality of data lines including the first data line DL1, a plurality of source electrodes including the first source electrode SE1, and a plurality of drains including the first drain electrode DE1. It may include a semiconductor layer 230 having an electrode and the first semiconductor pattern 230a.

The semiconductor layer 230 may be disposed on the gate insulating layer 220. The semiconductor layer 230 may be formed of, for example, amorphous silicon, polycrystalline silicon, or the like. In another embodiment, the semiconductor layer 230 may include an oxide semiconductor. When the semiconductor layer 230 includes an oxide semiconductor, the semiconductor layer 230 may include IGZO (In-Ga-Zinc-Oxide), ZnO, ZnO ₂ , CdO, SrO, SrO ₂ , CaO, CaO ₂ , MgO, MgO ₂ , InO, In ₂ O ₂ , GaO, Ga ₂ O, Ga ₂ O ₃ , SnO, SnO ₂ , GeO, GeO ₂ , PbO, Pb ₂ O ₃ , Pb ₃ O ₄ , TiO, TiO ₂ , Ti ₂ O ₃ , and one selected from an oxide semiconductor including Ti ₃ O ₅ .

The first semiconductor pattern 230a of the semiconductor layer 230 may form a channel region of the first switching element TR1.

The data conductor DW may further include an ohmic contact layer 240. The ohmic contact layer 240 may be disposed on the semiconductor layer 230. The ohmic contact layer 240 may be made of a material such as n + hydrogenated amorphous silicon doped with a high concentration of n-type impurities such as phosphorus, or may be made of silicide. However, the ohmic contact layer 240 may be omitted if the semiconductor layer 230 is made of an oxide semiconductor. Hereinafter, it will be described as including the ohmic contact layer 240.

The first data line DL1, the first source electrode SE1, and the first drain electrode DE1 may be disposed on the gate insulating layer 220 and the ohmic contact layer 240. The first source electrode SE1 may be branched from the first data line DL1 so that at least a portion of the first source electrode SE1 overlaps the first gate electrode GE1. The first drain electrode DE1 may overlap the first gate electrode GE1 and may be disposed to be spaced apart from the first source electrode SE1 by a predetermined distance. The first drain electrode DE1 may further include a first drain electrode extension DEP1. The first drain electrode extension DEP1 may overlap the storage line RL and the first contact hole CNT1.

3, 4, and 6, the shape of the first source electrode SE1 is U, and the first drain electrode DE1 is surrounded by the first source electrode SE1, but is not limited thereto. . The first source electrode SE1, the first drain electrode DE1, the first semiconductor pattern 230a, and the first gate electrode GE1 form the aforementioned first switching element TR1.

The first data line DL1 may include the first bent region BP1 in order to prevent a short with the first drain electrode extension DEP1. In addition, the second data line DL2 may include a second bent region BP2 to prevent a short from the first drain electrode extension DEP1. The first and second bent regions BP1 and BP2 may be disposed at positions overlapping the first pixel electrode PE1, which will be described later. However, the present disclosure is not limited thereto, and the curved regions BP1 and BP2 may be omitted or disposed so as not to overlap the first pixel electrode PE1 in the inactive region NAA. Here, the inactive area NAA will be described later.

The data conductor (DW) includes aluminum (Al), copper (Cu), molybdenum (Mo), chromium (Cr), titanium (Ti), tungsten (W), molybdenum (MoW), molybdenum (MoTi), It may be formed of a single film, a double film composed of at least two, or a triple film composed of three, selected from conductive metals including copper / mortitanium (Cu / MoTi). However, the present invention is not limited thereto and may be made of various metals or conductors. In one embodiment, the data conductors DW may be simultaneously formed through the same mask process.

The first passivation layer 250 may be disposed on the data conductor DW. The first passivation layer 250 may include an opening that exposes at least a portion of the first drain electrode extension part DEP1. In some embodiments, the first passivation layer 250 may be formed of an inorganic insulator such as silicon nitride and silicon oxide. The first passivation layer 250 may prevent the pigment of the organic insulating layer 260, which will be described later, from flowing into the first semiconductor pattern 230a.

The color filter CF may be disposed on the first passivation layer 250. The color filter CF overlaps the opening of the first passivation layer 250 and includes an opening that exposes at least a portion of the first drain electrode extension part DEP1.

The light passing through the color filter CF may display one of primary colors such as three primary colors of red, green, and blue. However, the display color of the light passing through the color filter is not limited to the primary color, and any one of cyan, magenta, yellow, and white series colors may be displayed. . For example, the color filter CF may be formed of a material displaying different colors for each of the adjacent pixel parts in the first direction d1, and the pixel parts adjacent to the second direction d2 may display the same color. It may be formed of a material. However, the present invention is not limited thereto and may be formed of a material displaying different colors for each of the adjacent pixel units regardless of the direction. 8 to 10 illustrate that the color filter CF is disposed on the first display panel 200. Alternatively, the color filter CF may be disposed on the second display panel 300.

The organic insulating layer 260 may be disposed on the first passivation layer 250 and the color filter CF. The organic insulating layer 260 overlaps the opening of the first passivation layer 250 and includes an opening that exposes at least a portion of the first drain electrode extension part DEP1. The organic insulating layer 260 has excellent planarization characteristics and may include an organic material having photosensitivity. The organic insulating layer 260 may be omitted.

The second passivation layer 270 may be disposed on the organic insulating layer 260. For example, the second passivation layer 270 may be formed of an inorganic insulator such as silicon nitride and silicon oxide. The second passivation film 270 may be omitted.

An opening of the first passivation layer 250, an opening of the color filter CF, an opening of the organic insulating layer 260, and an opening of the second passivation layer 270 may form a first contact hole CNT1.

The transparent conductor TE may be disposed on the second passivation layer 270. The transparent conductor TE may include a transparent conductive material. Here, the transparent conductive material may include polycrystalline, monocrystalline, or amorphous indium tin oxide (ITO). The transparent conductor TE may include a plurality of pixel electrodes including the first pixel electrode PE1.

The first pixel electrode PE1 may be in direct contact with the first drain electrode extension DEP1 exposed through the first contact hole CNT1. In addition, the first pixel electrode PE1 overlaps the common electrode CE. Accordingly, the first liquid crystal capacitor Clc1 (see FIG. 2) may be formed between the first pixel electrode PE1 and the common electrode CE that overlap each other.

Hereinafter, the shape of the first pixel electrode PE1 will be described in more detail.

The first pixel electrode PE1 includes the first active region AA1 and the fifth branch PE1b5 to the eighth branch, which are defined as regions in which the first branch portions PE1b1 to fourth branch PE1b4 extend. The PE1b8 may include a second active region AA2 defined as an extended region, and an inactive region NAA defined between the first active region AA1 and the second active region AA2. In example embodiments, the first pixel electrode may include the first stem parts PE1a1 to fifth stem parts PE1a5 and the first branch parts PE1b1 to fourth branch parts PE1b4 in the first active region AA1. It may include the sixth stem portion PE1a6 to the tenth stem portion PE1a10 and the fifth branch portion PE1b5 to the eighth branch portion PE1b8 in the second active region AA2. The first connection part PE1c of the pixel electrode may be included in the non-active area NAA. Each stem portion, each branch portion, and the first connection portion PE1c of the first pixel electrode PE1 will be described later.

Hereinafter, the first active region AA1 of the first pixel electrode PE1 will be described.

The first pixel electrode PE1 has a first stem portion PE1a1 extending in the first direction d1 and a second stem portion PE1a2 extending in the first direction and spaced apart from the first stem portion PE1a1. , The third stem portion PE1a3 extending in the second direction d2 and the fourth stem portion PE1a4 extending in the second direction d2 and spaced apart from the third stem portion PE1a3. 5 stems (PE1a5) may be included. The fourth stem part PE1a4 is disposed to overlap the second data line DL2 between the third stem part PE1a3 and the fifth stem part PE1a5, and includes the third to fifth stem parts PE1a3, PE1a4, and the like. PE1a5) may be disposed spaced apart from each other.

That is, the first stem part PE1a1 and the second stem part PE1a2 are horizontal stem parts extending in the horizontal direction with reference to FIG. 7, and the third stem part PE1a3, the fourth stem part PE1a4, and the first stem part PE1a2 and the second stem part PE1a2. 5 stem part PE1a5 is a vertical stem part extended in a longitudinal direction. The first stem part PE1a1 to the fifth stem part PE1a5 are electrically connected to each other. In an embodiment, the third stem part PE1a3, the fourth stem part PE1a4, and the fifth stem part PE1a5 may be electrically connected to each other through the first stem part PE1a1, and the first stem part ( The PE1a1 and the second stem part PE1a2 may be electrically connected to each other through the fourth stem part PE1a4. Meanwhile, one side and the other side of the first stem part PE1a1 and the second stem part PE1a2 may be at least one of the first region G1 and the second region G2 of the first storage line RL1. Some may overlap. The fourth stem PE1a4 may overlap the first data line DL1. In addition, the third stem PE1a3 may be disposed to overlap the first region G1 of the first storage line RL1, and the fifth stem PE1a5 is the second of the first storage line RL1. It may be disposed to overlap with the area G2.

The fourth stem PE1a4 may be disposed to overlap the second data line DL2. For example, the fourth stem PE1a4 may extend in the second direction d2 like the second data line DL2 and may be disposed to overlap the second data line DL2. In an embodiment, as illustrated in FIGS. 9 and 10, the fourth stem portion PE1a4 overlaps the second data line DL2, and the center of the fourth stem portion PE1a4 and the second data line DL2. ) May be arranged such that the centers are spaced apart without overlapping. By disposing the center of the fourth stem portion PE1a4 and the second data line DL2 so that the center thereof is not overlapped with each other, the viewing angle of the liquid crystal display may be improved. However, the present disclosure is not limited thereto, and in another embodiment, the center of the fourth stem portion PE1a4 and the second data line DL2 may be disposed to overlap each other.

The first pixel electrode PE1 may include a plurality of first branch parts PE1b1, a plurality of second branch parts PE1b2, a plurality of third branch parts PE1b3, and a plurality of fourth branch parts PE1b4. Can be.

The plurality of first branch parts PE1b1 and the plurality of second branch parts PE1b2 are defined as branch parts extending from the first stem part PE1a2. More specifically, the plurality of first branch parts PE1b1 are disposed on one side of the first stem part PE1a1, and the direction in which the second stem part PE1a2 is disposed (usually, the fourth direction d4). It is defined as the branch extending to.

The plurality of second branch parts PE1b2 are disposed on the other side of the second stem part PE1a2, and are defined as branch parts extending in the direction in which the scan line SL1 is disposed (usually, the second direction d2). . That is, the extending directions of the plurality of first branch parts PE1b1 may be symmetrical with respect to the extending direction of the plurality of second branch parts PE1b2 and the plurality of first stem parts PE1a1. Here, at least some of the plurality of first branch parts PE1b1 and the plurality of second branch parts PE1b2 may at least partially overlap the first data line DL1. In addition, at least a portion of the plurality of first branch parts PE1b1 and the plurality of second branch parts PE1b2 may be, for example, a first area G1 and a second area G2 of the first storage line RL. Can be overlapped with

The plurality of third branch parts PE1b3 and the plurality of fourth branch parts PE1b4 are defined as branch parts extending from the first stem part PE1a1. The plurality of third branch parts PE1b3 are disposed on one side of the fourth stem part PE1a4, and are branch parts extending in the direction in which the third stem part PE1a3 is disposed (usually, the third direction d3). Is defined.

The plurality of fourth branch parts PE1b4 are disposed on the other side of the fourth stem part PE1a4, and are branch parts extending in the direction in which the fifth stem part PE1a5 is disposed (usually, the first direction d1). Is defined. Here, at least some of the plurality of third branch parts PE1b3 may overlap at least part of the first data line DL2.

Hereinafter, the inactive region AA2 of the first pixel electrode PE1 will be described.

The non-active area of the first pixel electrode PE1 may be an area between the first active area AA2 and the second active area AA2 described later. The first pixel electrode PE1 may include the first scan line SL1, the first repair line RPL1, and the black matrix BM in the inactive region NAA.

The first pixel electrode PE1 may further include a first connection part PE1c in the non-active area NAA. The first connection part PE1c extends from the plurality of fifth stem parts PE1a5 and is defined as an area overlapping the first contact hole CNT1. Therefore, the first connection part PE1c of the first pixel electrode PE1 may be directly connected to the exposed first drain electrode extension part DEP1. In an embodiment, the first connection part PE1c of the first pixel electrode PE1 may overlap at least one of the first data line DL1 and the second data line DL2. Meanwhile, in the drawing, the first connection part PE1c is illustrated as being connected to the fifth stem part PE1a5, but the present invention is not limited thereto, and the plurality of second branch parts PE1b2, the plurality of fourth branch parts PE1b4, and the first connection part PE1c are connected to the fifth stem part PE1a5. It may be connected to at least one of the first stem portion PE1a1 and the fourth stem portion PE1a4.

Hereinafter, the second active region AA2 of the first pixel electrode PE1 will be described.

The first pixel electrode PE1 is the sixth stem part PE1a6 extending in the first direction d1, and the seventh stem part PE1a7 extending in the first direction and spaced apart from the sixth stem part PE1a6. , The eighth stem part PE1a8 extending in the second direction d2 and the ninth stem part PE1a9 extending in the second direction d2 and spaced apart from the eighth stem part PE1a8 and the tenth row It may include a base PE1a10. The ninth stem part PE1a9 is disposed to overlap the first data line DL1 between the eighth stem part PE1a8 and the tenth stem part PE1a10, and includes the eighth to tenth stem parts PE1a8, PE1a9, PE1a10 may be disposed spaced apart from each other.

That is, the sixth stem part PE1a6 and the seventh stem part PE1a7 are horizontal stem parts extending in the horizontal direction with reference to FIG. 7, and the eighth stem part PE1a8, the ninth stem part PE1a9, and the seventh stem part PE1a9 and the seventh stem part PE1a9. 10 stem part PE1a10 is a vertical stem part extended in a longitudinal direction. The sixth stem part PE1a6 to the tenth stem part PE1a10 are electrically connected to each other. In an embodiment, the eighth stem part PE1a8, the ninth stem part PE1a9, and the tenth stem part PE1a10 may be electrically connected to each other through the sixth stem part PE1a6, and the sixth stem part ( The PE1a6 and the seventh stem part PE1a7 may be electrically connected to each other through the ninth stem part PE1a9. Meanwhile, one side and the other side of the sixth stem part PE1a6 and the seventh stem part PE1a7 may be at least one of the first region G3 and the second region G4 of the second storage line RL. Some may overlap. The eighth stem portion PE1a8 may overlap at least a portion of the first region G3 of the second storage line RL2, and the tenth stem portion PE1a10 may have a second region G4 of the second storage line. And at least some may overlap. In addition, the seventh stem part PE1a7 may overlap the third region G5 of the second storage line RL2.

The ninth stem portion PE1a9 may be disposed to overlap the first data line DL1. For example, the ninth stem portion PE1a9 may extend in the second direction d2 like the first data line DL1, but may overlap the first data line DL1. In an embodiment, as shown in FIG. 10, the ninth stem portion PE1a9 overlaps the first data line DL1, and the center and the first data line DL1 of the ninth stem portion PE1a9 are cross-sectionally formed. The centers may be disposed to be spaced apart from each other without overlapping, but are not limited thereto as described above in the first active region AA1. In another embodiment, the center of the ninth stem portion PE1a9 and the first data line DL1 may be disposed to overlap the center.

The first pixel electrode PE1 may include a plurality of fifth branches PE1b5, a plurality of sixth branches PE1b6, a plurality of seventh branches PE1b7, and a plurality of eighth branches PE1b8. Can be.

The plurality of fifth branches PE1b5 and the plurality of sixth branches PE1b6 are defined as branch portions extending from the sixth stem portion PE1a6. More specifically, the plurality of fifth branch parts PE1b5 are disposed on one side of the sixth stem part PE1a6, and the direction in which the seventh stem part PE1a7 is disposed (usually, the second direction d2). It is defined as the branch extending to.

The sixth branch parts PE1b6 are defined as branch parts that are disposed on the other side of the sixth stem part PE1a6 and extend in the direction in which the scan line SL is disposed (usually, the fourth direction d4). . That is, the extending directions of the plurality of fifth branch parts PE1b5 may be symmetrical with respect to the extending direction of the plurality of sixth branch parts PE1b6 and the plurality of sixth stem parts PE1a6. Here, at least some of the plurality of fifth branches PE1b5 and the plurality of sixth branches may overlap at least partially with the second data line DL2. In addition, at least a portion of the plurality of fifth branches PE1b5 and the sixth branches PE1b6 may be, for example, a first region G3 and a second region G4 of the second storage line RL2. Can be overlapped with

The plurality of seventh branch parts PE1b7 and the plurality of eighth branch parts PE1b8 are defined as branch parts extending from the ninth stem part PE1a9. The plurality of seventh branch parts PE1b7 are disposed on one side of the ninth stem part PE1a9, and are branch parts extending in the direction in which the tenth stem part PE1a10 is disposed (usually, the first direction d1). Is defined.

The plurality of eighth branch parts PE1b8 are disposed on the other side of the ninth stem part PE1a9 and are branch parts extending in the direction in which the eighth stem part PE1a8 is disposed (usually, the third direction d3). Is defined. Here, at least some of the seventh branch parts PE1b7 may at least partially overlap the second data line DL2.

The tenth stem part PE1a10 may be electrically connected to the first connection part PE1c of the non-active area NAA. Meanwhile, although the first connection part PE1c is illustrated as being connected to the tenth stem part PE1a10 in the drawings, the first connection part PE1c is not limited thereto, and the plurality of seventh branch parts PE1b7, the plurality of eighth branch parts PE1b8, and the eighth branch part PE1b8 are respectively. It may be connected to at least one of the eight stem part PE1a8 and the ninth stem part PE1a9.

The fifth stem portion PE1a5 and the tenth stem portion PE1a10 may be electrically connected to each other through the first opening portion. Therefore, all of the first stem parts PE1a1_ to 10th stem parts PE1a10 and the plurality of first branch parts PE1ba to eighth branch parts PE1b8 may be electrically connected.

Although the fourth stem portion PE1a4 overlaps the second data line RL2 and the ninth stem portion PE1a9 overlaps the first data line RL1, the present invention is not limited thereto. In another embodiment, the fourth stem portion PE1a4 may overlap the first data line RL1, and the ninth stem portion PE1a9 may overlap the second data line RL2. Both the fourth stem PE1a4 and the ninth stem PE1a9 may overlap the first data line RL1 and the second data line RL2.

As described above, the second data line DL2 may overlap the fourth stem PE1a4 of the first pixel electrode PE1 in the first active region AA1, and the first data line DL1 may be overlapped. The second active region AA2 may overlap the ninth stem portion PE1a9 of the first pixel electrode PE1. As a result, the dark area by the first data line DL1 and the second data line DL2 may be minimized in the opening region (the region through which light is transmitted) of the first pixel portion PX1. In addition, as the area of the dark portion is minimized, the aperture ratio can be improved.

Meanwhile, an area overlapping with the first pixel electrode PE1 of the first data line DL1 in the first active region AA1 and an area overlapping with the first pixel electrode PE1 of the second data line DL2. May be disposed between the first region G1 and the second region G2 of the first storage line RL1. That is, the distance l1 between the first data line DL1 and the first area G1 of the first storage line RL is the second area of the second data line DL2 and the first storage line RL. It may be substantially equal to the distance l2 between (G2).

Similarly, an area overlapping the first pixel electrode PE1 of the first data line DL1 in the second active area AA2 and an area overlapping the first pixel electrode PE1 of the second data line DL2. May be disposed between the first region G3 and the second region G4 of the second storage line RL2. That is, the distance l1 between the first data line DL1 and the first area G3 of the second storage line RL2 is the third area of the second data line DL2 and the second storage line RL2. It may be substantially equal to the distance l2 between (G2).

Hereinafter, the domain region of the first pixel electrode PE1 will be described in more detail with reference to FIG. 11.

Referring to FIG. 11, in some embodiments, the first pixel electrode PE1 may include a plurality of domain regions in the first active region AA1. For example, the first pixel electrode PE1 may include first to fourth domain regions DM1 to DM4 in the first active region AA1.

In the first active area AA1, the first domain area DM1 may be defined as an area in which one side of the first stem part PE1a1 and one side of the fourth stem part PE1a4 overlap each other. For example, the first domain region DM1 extends in the fourth direction d4 in the first stem portion PE1a1 and extends in the third direction d3 in the fourth stem portion PE1a4 in the drawing. The region may be an overlapping region.

The second domain area DM2 may be defined as an area in which the other side of the first stem part PE1a1 and one side of the fourth stem part PE1a4 overlap. For example, the second domain area DM2 extends in the second direction d2 in the first stem part PE1a1 and extends in the third direction d3 in the fourth stem part PE1a4 in the drawing. The region may be an overlapping region.

The third domain area DM3 may be defined as an area in which the other side of the first stem part PE1a1 and the other side of the fourth stem part PE1a4 overlap. For example, the third domain area DM3 extends in the second direction d2 in the first stem part PE1a1 and extends in the first direction d1 in the fourth stem part PE1a4 in the drawing. The region may be an overlapping region.

The fourth domain area DM4 may be defined as an area in which one side of the first stem part PE1a1 and the other side of the fourth stem part PE1a4 overlap. For example, the fourth domain region DM4 extends in the fourth direction d4 in the first stem portion PE1a1 and extends in the first direction d1 in the fourth stem portion PE1a4 in the drawing. The region may be an overlapping region.

In the drawing, the first domain area DM1 and the second domain area DM2 may be areas extending in the third direction d3 based on the second data line DL2, and the third domain area DM3 and The fourth domain area DM4 may be an area extending in the first direction d1 based on the second data line DL2. That is, boundaries between the first domain area DM1, the second domain area DM2, the third domain area DM3, and the fourth domain area DM4 may overlap the second data line DL2.

When the electric field is formed, the plurality of liquid crystal molecules disposed in the first domain region DM1 and the second domain region DM2 may be aligned in a first direction d1 that is generally opposed to the third direction d3. . In contrast, the plurality of liquid crystal molecules disposed in the third domain area DM3 and the fourth domain area DM4 may be generally aligned in the third direction d3 when an electric field is formed.

Similarly, the first pixel electrode PE1 may include a plurality of domain regions in the second active region AA2. For example, the first pixel electrode PE1 may include fifth to eighth domain regions DM5 to DM8 in the second active region AA2.

In the second active region AA2, the fifth domain region DM5 may be defined as a region where one side of the sixth stem portion PE1a6 and one side of the ninth stem portion PE1a9 overlap each other. For example, the fifth domain region DM5 extends in the fourth direction d4 in the sixth stem part PE1a6 and extends in the third direction d3 in the ninth stem part PE1a9 in the drawing. The region may be an overlapping region.

The sixth domain area DM6 may be defined as an area in which the other side of the sixth stem part PE1a6 and one side of the ninth stem part PE1a9 overlap. For example, the sixth domain region DM6 extends in the second direction d2 in the sixth stem part PE1a6 and extends in the third direction d3 in the ninth stem part PE1a9 in the drawing. The region may be an overlapping region.

The seventh domain area DM7 may be defined as an area in which the other side of the sixth stem part PE1a6 and the other side of the ninth stem part PE1a9 overlap each other. For example, the seventh domain region DM7 extends in the second direction d2 in the sixth stem part PE1a6 and extends in the first direction d1 in the ninth stem part PE1a9 in the drawing. The region may be an overlapping region.

The eighth domain area DM8 may be defined as an area in which one side of the sixth stem part PE1a6 and the other side of the ninth stem part PE1a9 overlap each other. For example, the eighth domain area DM8 extends in the fourth direction d4 in the sixth stem part PE1a6 and extends in the first direction d1 in the ninth stem part PE1a9 in the drawing. The region may be an overlapping region.

In the drawing, the fifth domain area DM5 and the sixth domain area DM6 may be areas extending in the third direction d3 based on the first data line DL1, and the seventh domain area DM7 and The eighth domain area DM8 may be an area extending in the first direction d1 based on the second data line DL2. That is, boundaries between the fifth domain area DM5 and the sixth domain area DM6, the seventh domain area DM7, and the eighth domain area DM8 may overlap the second data line DL2.

The plurality of liquid crystal molecules disposed in the fifth domain region DM5 and the sixth domain region DM6 may be generally aligned in the first direction d1 when an electric field is formed. In contrast, the plurality of liquid crystal molecules disposed in the seventh and eighth domain regions DM7 and DM8 may be aligned in the third direction d3 when an electric field is formed.

In the first pixel electrode PE1, an area of a domain region in which the liquid crystal molecules are aligned in the first direction d1 may be substantially the same as an area of the domain region in which the liquid crystal molecules are aligned in the third direction d3. have. That is, the sum of the area of the first domain area DM1, the area of the second domain area DM2, the area of the fifth domain area DM5, and the area of the sixth domain area DM6 is the third domain area DM3. ), The area of the fourth domain area DM4, the area of the seventh domain area DM7, and the area of the eighth domain area DM8 may be equal to the sum of the area.

Referring back to FIGS. 3 to 11, the first alignment layer (not shown) may be disposed on the transparent conductor TE. The first alignment layer may induce an initial alignment of the plurality of liquid crystal molecules in the liquid crystal layer 400. In some embodiments, the first alignment layer may include a polymer organic material having an imide group in a repeating unit of a main chain.

Next, the second display panel 300 will be described.

The second substrate 310 is disposed to face the first substrate 210. The second substrate 310 may be formed of transparent glass, plastic, or the like, and may be formed of the same material as the first substrate 210 in one embodiment.

The black matrix BM may be disposed on the second substrate 310. The black matrix BM may be disposed along the first direction in the inactive region NAA. That is, the black matrix may extend in the first direction d1 and be disposed to overlap the plurality of scan lines SL1 to SLn.

The black matrix BM may block light from being transmitted to the inactive region NAA. The material of the black matrix BM is not particularly limited as long as it can block light. The black matrix BM may be formed of, for example, a photosensitive composition, an organic material, or a metallic material. In one embodiment, the photosensitive composition may include a binder resin, a polymerizable monomer, a polymerizable oligomer, a pigment, a dispersant, and the like. The metallic material may include chromium or the like.

In the present exemplary embodiment, a black matrix BM extending in the first direction between pixel portions adjacent to the second direction d2 (eg, between the first pixel portion PX1 and the second pixel portion PX2) is formed. May not be deployed. By adjusting the shortness between adjacent pixel parts in the second direction d2, the liquid crystal alignment may be adjusted so that light does not pass between adjacent pixel parts in the second direction d2 without the black matrix BM. However, the present invention is not limited thereto, and the black matrix extending in the first direction between pixel portions adjacent to each other in the second direction d2 (eg, between the first pixel portion PX1 and the second pixel portion PX2) BM) may be arranged.

The planarization layer 320 may be disposed on the black matrix BM. The planarization layer 320 may provide flatness with respect to the common electrode CE. The material of the planarization layer 320 is not particularly limited and may include an organic material or an inorganic material in one embodiment.

The common electrode CE may be disposed on the planarization layer 320. At least a portion of the common electrode CE may overlap the first pixel electrode PE1. The common electrode CE may be formed in a plate shape in one embodiment. However, the present invention is not limited thereto, and the common electrode CE may include a plurality of slits. The common electrode CE may be formed of a transparent conductive material such as ITO and IZO, or a reflective metal such as aluminum, silver, chromium, or an alloy thereof.

Although not illustrated, a second alignment layer may be disposed on the common electrode CE. The second alignment layer may induce an initial alignment of the plurality of liquid crystal molecules in the liquid crystal layer 400. In some embodiments, the second alignment layer may be formed of the same material as the first alignment layer.

Next, the liquid crystal layer 400 will be described.

The liquid crystal layer 400 includes a plurality of liquid crystal molecules. The plurality of liquid crystal molecules may be vertically aligned in an initial alignment state with negative dielectric anisotropy in one embodiment. The plurality of liquid crystal molecules may have a predetermined pretilt angle in the initial alignment state. Initial alignment of the plurality of liquid crystal molecules may be induced by the first and second alignment layers described above. When the electric field is formed between the first display panel 200 and the second display panel 300, the plurality of liquid crystal molecules may change the polarization state of light passing through the liquid crystal layer by tilting or rotating in a specific direction.

That is, the liquid crystal display according to the exemplary embodiment of the present invention may simultaneously provide data signals to pixel electrodes connected to the two scan lines by electrically connecting two neighboring scan lines to each other for high resolution driving. In addition, by dividing one pixel electrode into two active regions, the area of the dark portion can be reduced to improve the aperture ratio.

In addition, the present embodiment overlaps the data line (eg, the second data line D2) with the stem portion (eg, the fourth stem portion PE1a4) of the pixel portion, thereby reducing the area of the dark portion caused by the data line to reduce the aperture ratio. It can be further improved.

Next, a liquid crystal display according to another exemplary embodiment of the present invention will be described. However, descriptions overlapping with those described in FIGS. 1 to 11 will be omitted. In addition, the same reference numerals will be used for the same configuration as the configuration described with reference to FIGS. 1 to 11.

In the liquid crystal display illustrated in FIG. 12, in contrast to the liquid crystal display illustrated in FIG. 3, the fourth stem portion PE1a4 and the ninth stem portion PE1a9 are arranged in the first data line DL1 in the first pixel portion PX1_1. Alternatively, there is a difference in that it is disposed between the first data line DL1 and the second data line DL2 without overlapping the second data line DL2.

In the liquid crystal display according to the present exemplary embodiment, the same effect as the exemplary embodiment of FIGS. 3 to 11 can be obtained by dividing one pixel electrode into two active regions to improve the aperture ratio by reducing the dark area.

In the liquid crystal display illustrated in FIG. 13, the first pixel portion PX1_2 includes two domains in the first active region AA1 and the second active region AA2, respectively, compared to the liquid crystal display illustrated in FIG. 12. There is a difference in that.

In the first active region AA1, the first pixel electrode may include at least one vertical stem portion and at least one horizontal stem portion. In addition, the first pixel electrode may include a plurality of branch portions extending from the vertical stem in the first direction d1 and the third direction d3. For example, the first pixel electrode extends in the second direction d2 in the first active region AA1 and is spaced apart from each other, and includes a first stem portion PE1a1_2, a second stem portion PE1a2_2, and a third stem portion ( PE1a3_2). The second stem part PE1a2_2 may be disposed between the first stem part PE1a1_2 and the third stem part PE1a3_2. The first pixel portion PX1_2 may include a fourth stem portion PE1a4_2 extending in the third direction d3 in the first active region AA1. The first stem part PE1a1_2 to the third stem part PE1a3_2 may be electrically connected through the fourth stem part PE1a4_2.

The second stem portion PE1a2_2 may not be overlapped with the first data line DL1 and the second data line DL2, and may be disposed between the first data line DL1 and the second data line DL2.

Each stem portion and each branch portion included in the first active region AA1 may be symmetrical with respect to each stem portion and branch portion included in the second active region AA2 and the inactive region NAA. For example, the first pixel portion PX1_2 extends in the second direction d2 in the second active region AA2 and is spaced apart from each other, the fifth stem portion PE1a5_2, the sixth stem portion PE1a6_2, and the seventh. It may include a stem (PE1a7_2). The sixth stem part PE1a6_2 may be disposed between the fifth stem part PE1a5_2 and the seventh stem part PE1a7_2. The first pixel portion PX1_2 may include an eighth stem portion PE1a8_2 extending in the third direction d3 in the second active region AA2. The fifth stem parts PE1a5_2 to the seventh stem parts PE1a7_2 may be electrically connected through the eighth stem part PE1a8_2.

The first pixel portion PX1_2 may further include a first connection portion PE1c_2 in the non-active area NAA. The third stem portion PE1a3 and the seventh stem portion PE1a7 may be electrically connected to each other through the first connection portion PE1c_2.

The first pixel area PX1_2 is a first domain area DM1_2 and a first active area defined as an area extending from the first active area AA1 in the third direction d3 based on the second stem part PE1a2_2. The second domain region DM2_2 defined as the region extending in the first direction d1 based on the second stem portion PE1a2_2 in the region AA1, and the sixth stem portion PE1a6 in the second active region AA2. ) In the third domain region DM3_2 and the second active region AA2 defined as the region extending in the third direction d3 in the first direction d1 based on the sixth stem part PE1a6_2. It may include a fourth domain region DM4_2 defined as an extended region.

In the first pixel portion PX1_2, the area of the domain region region for aligning the liquid crystal molecules in the first direction d1 is generally larger than that of the domain region region for aligning the liquid crystal molecules in the third direction d3. It can be made to be the same as in the liquid crystal display device of 3. For example, the sum of the area of the first domain area DM1_2 and the area of the fourth domain area DM4_2 is substantially equal to the sum of the area of the second domain area DM2_2 and the area of the third domain area DM3_2. May be the same.

In the liquid crystal display shown in FIG. 14, in contrast to the liquid crystal display shown in FIG. 13, one of the vertical stems in each of the active regions has a first data line DL1 and a second data line. There is a difference in overlapping with one of DL2).

For example, the second stem portion PE1a2_2 may be disposed to overlap the second data line DL2 in the first active region AA1, and the fifth stem portion PE1a5_2 may be disposed in the second active region AA2. May overlap the first data line DL1. The second stem part PE1a2_2 may be disposed to overlap the first data line DL1, and the fifth stem part PE1a5_2 may be disposed to overlap the second data line DL2. have.

In the liquid crystal display according to the present exemplary embodiment, by dividing one pixel electrode into two active regions, the aperture area is reduced to improve the aperture ratio, and the data line is overlapped with the stem portion of the pixel portion, thereby reducing the aperture area by the data line. In the further improvement, the same effect as the embodiment of FIGS. 3 to 11 can be obtained.

In the liquid crystal display illustrated in FIG. 15, the first pixel portion PX1_4 includes four domains in the first active region AA1 and the second active region AA2 in comparison to the liquid crystal display illustrated in FIG. 13. The difference is that the two domains are included.

In the first pixel portion PX1_4, the area of the domain region for aligning the liquid crystal molecules in the first direction d1 is generally larger than the area of the domain region for aligning the liquid crystal molecules in the third direction d3. It can be made the same as a liquid crystal display device.

In the drawing, the first pixel portion PX1_4 is illustrated as including four domains in the first active region AA1 and two domains in the second active region AA2, but is not limited thereto. For example, in another embodiment, the first pixel part PX1_4 is not limited to the number of domains included in the first active area AA1 and the second active area AA2, but is included in the first active area AA1. The number of the plurality of domains and the number of wholesalers included in the second active area AA2 may be the same or different.

In the liquid crystal display illustrated in FIG. 16, the first pixel portion PX1_5 has a ratio of the thicknesses of the plurality of branches and the intervals between the branches in the first active region AA1. The space W / S differs in that the ratio (W / S) of the thicknesses of the plurality of branches and the distance between the branches is different in the second active region AA2.

The thickness of the branch may be defined as a thickness in a direction orthogonal to the direction in which the branch extends from the stem. The spacing of the branches can be defined as the vertical distance between the closest branches. The thickness of the branches may be formed in the range of 2.0μm to 4.0μm, the interval of the branches may be formed in the range of 2.5μm to 4.0.

The thickness and spacing of the branches in the same active area may be constant. For example, in one embodiment, the thickness W1 of the branch in the first active region AA1 is 3.3 μm, the interval S1 of the branch is 2.7 μm, and the thickness of the branch in the second active region AA2. W2 may be 2.4 μm, and the interval S2 of the branches may be 3.6 μm. In the above embodiment, the ratio (W / S) of the thicknesses of the plurality of branches and the spacing of each branch is 3.3 / 2.7 (W1 / S1) in the first active region AA1 and 2.4 / 3.6 in the second active region AA2. (W2 / S2) can be different.

The first pixel portion PX1_5 has a ratio W1 / S1 of the thicknesses of the plurality of branches in the first active region AA1 and the interval between the branches, and the thicknesses of the plurality of branches in the second active region AA2 and the branches. By varying the ratio of the intervals (W2 / S2) it may include both a high-level voltage region and a high-level voltage region.

17 is an equivalent circuit diagram illustrating a liquid crystal display according to another exemplary embodiment, and FIG. 18 is a layout diagram illustrating first to fourth pixel units in the configuration of the liquid crystal display according to the equivalent circuit diagram of FIG. 17.

17 and 18, the third switching element TR3 ′ included in the third pixel unit PX3 ′ may have a fourth data line DL4 compared to the liquid crystal display shown in FIG. 2. There is a difference in that the fourth switching element TR4 ', which is electrically connected and included in the fourth pixel unit PX4', is connected to the third data line DL3.

That is, in the liquid crystal display shown in FIG. 18, like the liquid crystal display of FIGS. 2 and 3, pixel units arranged in the same column are alternately arranged, but different from pixel units arranged in adjacent columns.

Although described above with reference to the embodiments of the present invention, which is merely an example and not limiting the present invention, those skilled in the art to which the present invention pertains without departing from the essential characteristics of the embodiments of the present invention. It will be appreciated that various modifications and applications are not possible. For example, each component specifically shown in the embodiment of the present invention may be modified. And differences relating to such modifications and applications will have to be construed as being included in the scope of the invention defined in the appended claims.

Claims

An insulating substrate including a pixel region including a first active region, a second active region, and an inactive region disposed between the first active region and the second active region;

A first scan line disposed on the insulating substrate and overlapping the inactive region;

A thin film transistor including a control electrode, a first electrode, and a second electrode, the thin film transistor having the control electrode connected to the first scan line; And

A first pixel electrode disposed in the pixel region and electrically connected to the second electrode of the thin film transistor,

The first scan line extends in a first direction,

The first active region, the inactive region and the second active region are arranged along a second direction crossing the first direction,

The first pixel electrode may include a first subpixel electrode part disposed in the first active region,

A second subpixel electrode portion disposed in the second active region, and

And a connection electrode part disposed in the inactive region and connecting the first subpixel electrode part and the second subpixel electrode part.
According to claim 1,

And a first data line extending in the second direction and crossing the first active region, the inactive region, and the second active region and connected to the first electrode of the thin film transistor.
The method of claim 2,

The first pixel electrode and the second electrode are disposed in different layers with an insulating film interposed therebetween,

The connection electrode part of the first pixel electrode includes a contact part electrically connected to the second electrode through a contact hole passing through the insulating layer.
The method of claim 3, wherein

The pixel area includes first and second edges extending along the second direction and facing each other.

The first subpixel electrode part includes a first stem electrode disposed at the first edge and extending in the second direction.

The second subpixel electrode part includes a second stem electrode disposed at the first edge and extending in the second direction.

And the connection electrode part is disposed between the first stem electrode of the first subpixel electrode part and the second stem electrode of the second subpixel electrode part to connect them.
The method of claim 4, wherein

The width of the first direction of the contact portion of the connection electrode portion is greater than the width of the first direction of the first stem electrode and the second stem electrode.
The method of claim 4, wherein

And the contact portion of the connection electrode portion is positioned at a central portion equidistant from the first edge and the second edge.
The method of claim 4, wherein

The first subpixel electrode unit further includes a third stem electrode disposed inside the first edge, extending in the second direction, and overlapping the first data line.
The method of claim 7, wherein

The liquid crystal further includes a fourth stem electrode extending in the first direction and connecting the first stem electrode of the first subpixel electrode part to the third stem electrode of the first subpixel electrode part. Display device.
The method of claim 7, wherein

The second subpixel electrode part further includes a second stem electrode disposed inward of the first edge, extending in the second direction, and overlapping the data line.
The method of claim 4, wherein

And a second data line extending in the second direction and crossing the first active area, the inactive area, and the second active area and spaced apart from the first data line.
The method of claim 10,

A third stem electrode disposed inside the first subpixel electrode, extending in the second direction, and overlapping the first data line; and

Further comprising a plurality of branch electrodes extending from the third stem electrode,

Some of the plurality of branch electrodes overlap at least a portion of the second data line.
According to claim 1,

The first subpixel electrode part, the second subpixel electrode part, and the connection electrode part are all disposed on the same layer.
According to claim 1,

A second data line extending in the second direction and crossing the first active region, the inactive region, and the second active region and spaced apart from the first data line;

A second scan line extending in the first direction;

A second pixel electrode crossing the second scan line;

A control electrode connected to the second scan line;

An electrode connected to the second data line; And

Further comprising a second thin film transistor having another electrode connected to the second pixel electrode,

And the first thin film transistor and the second thin film transistor simultaneously perform a switching operation.
The method of claim 13,

The first scan line and the second scan line are electrically connected to each other.
The method of claim 13,

And a second switching element having a control electrode connected to the second scan line, one electrode connected to the second data line, and another electrode connected to the second pixel electrode.
According to claim 1,

And a first storage line disposed on the same layer as the first scan line and surrounding a portion of the first active area.
The method of claim 16,

At least a portion of the first subpixel electrode part overlaps the first storage line.
The method of claim 16,

A second storage line disposed on the same layer as the first scan line and surrounding a portion of the second active area,

The first storage line and the second storage line are spaced apart from each other.
According to claim 1,

And a second data line extending in the second direction and crossing the first active region, the inactive region, and the second active region and spaced apart from the first data line.

And at least one of the first data line and the second data line includes a curved area.
The method of claim 19,

The bent region overlaps at least a portion of the first subpixel electrode part.